Index: lib/Target/Mips/InstPrinter/MipsInstPrinter.cpp
===================================================================
--- lib/Target/Mips/InstPrinter/MipsInstPrinter.cpp
+++ lib/Target/Mips/InstPrinter/MipsInstPrinter.cpp
@@ -86,6 +86,10 @@
     O << "\t.set\tpush\n";
     O << "\t.set\tmips32r2\n";
     break;
+  case Mips::RDHWR_MM:
+    O << "\t.set\tpush\n";
+    O << "\t.set\tmicromips\n";
+    break;
   case Mips::Save16:
     O << "\tsave\t";
     printSaveRestore(MI, O);
@@ -118,6 +122,7 @@
     break;
   case Mips::RDHWR:
   case Mips::RDHWR64:
+  case Mips::RDHWR_MM:
     O << "\n\t.set\tpop";
   }
 }
Index: lib/Target/Mips/MicroMipsInstrFormats.td
===================================================================
--- lib/Target/Mips/MicroMipsInstrFormats.td
+++ lib/Target/Mips/MicroMipsInstrFormats.td
@@ -803,3 +803,27 @@
   let Inst{15-6}  = op;
   let Inst{5-0}   = 0x3c;
 }
+
+class SDBBP_FM_MM : MMArch {
+  bits<10> code_;
+
+  bits<32> Inst;
+
+  let Inst{31-26} = 0x0;
+  let Inst{25-16} = code_;
+  let Inst{15-6}  = 0x36d;
+  let Inst{5-0}   = 0x3c;
+}
+
+class RDHWR_FM_MM {
+  bits<5> rt;
+  bits<5> rd;
+
+  bits<32> Inst;
+
+  let Inst{31-26} = 0x0;
+  let Inst{25-21} = rt;
+  let Inst{20-16} = rd;
+  let Inst{15-6}  = 0x1ac;
+  let Inst{5-0}   = 0x3c;
+}
Index: lib/Target/Mips/MicroMipsInstrInfo.td
===================================================================
--- lib/Target/Mips/MicroMipsInstrInfo.td
+++ lib/Target/Mips/MicroMipsInstrInfo.td
@@ -563,6 +563,9 @@
   def TLBR_MM : MMRel, TLB<"tlbr">, COP0_TLB_FM_MM<0x4d>;
   def TLBWI_MM : MMRel, TLB<"tlbwi">, COP0_TLB_FM_MM<0x8d>;
   def TLBWR_MM : MMRel, TLB<"tlbwr">, COP0_TLB_FM_MM<0xcd>;
+
+  def SDBBP_MM : MMRel, SYS_FT<"sdbbp">, SDBBP_FM_MM;
+  def RDHWR_MM : ReadHardware<GPR32Opnd, HWRegsOpnd>, RDHWR_FM_MM;
 }
 
 //===----------------------------------------------------------------------===//
Index: lib/Target/Mips/MipsInstrInfo.td
===================================================================
--- lib/Target/Mips/MipsInstrInfo.td
+++ lib/Target/Mips/MipsInstrInfo.td
@@ -1171,7 +1171,7 @@
 def BREAK : MMRel, BRK_FT<"break">, BRK_FM<0xd>;
 def SYSCALL : MMRel, SYS_FT<"syscall">, SYS_FM<0xc>;
 def TRAP : TrapBase<BREAK>;
-def SDBBP : SYS_FT<"sdbbp">, SDBBP_FM, ISA_MIPS32_NOT_32R6_64R6;
+def SDBBP : MMRel, SYS_FT<"sdbbp">, SDBBP_FM, ISA_MIPS32_NOT_32R6_64R6;
 
 def ERET : MMRel, ER_FT<"eret">, ER_FM<0x18>, INSN_MIPS3_32;
 def DERET : MMRel, ER_FT<"deret">, ER_FM<0x1f>, ISA_MIPS32;
@@ -1351,8 +1351,9 @@
 def PseudoUDIV : MultDivPseudo<UDIV, ACC64, GPR32Opnd, MipsDivRemU, II_DIVU,
                                0, 1, 1>, ISA_MIPS1_NOT_32R6_64R6;
 
+let AdditionalPredicates = [HasStdEnc, NotInMicroMips] in {
 def RDHWR : ReadHardware<GPR32Opnd, HWRegsOpnd>, RDHWR_FM;
-
+}
 def EXT : MMRel, ExtBase<"ext", GPR32Opnd, uimm5, MipsExt>, EXT_FM<0>;
 def INS : MMRel, InsBase<"ins", GPR32Opnd, uimm5, MipsIns>, EXT_FM<4>;
 
Index: lib/Target/Mips/MipsSEISelDAGToDAG.cpp
===================================================================
--- lib/Target/Mips/MipsSEISelDAGToDAG.cpp
+++ lib/Target/Mips/MipsSEISelDAGToDAG.cpp
@@ -786,7 +786,7 @@
     unsigned RdhwrOpc, DestReg;
 
     if (PtrVT == MVT::i32) {
-      RdhwrOpc = Mips::RDHWR;
+      RdhwrOpc = Subtarget->inMicroMipsMode() ? Mips::RDHWR_MM : Mips::RDHWR;
       DestReg = Mips::V1;
     } else {
       RdhwrOpc = Mips::RDHWR64;
Index: test/CodeGen/Mips/micromips-rdhwr-directives.ll
===================================================================
--- /dev/null
+++ test/CodeGen/Mips/micromips-rdhwr-directives.ll
@@ -0,0 +1,16 @@
+; RUN: llc -march=mipsel -mcpu=mips32 -relocation-model=static < %s \
+; RUN:   -mattr=+micromips | FileCheck %s
+
+@a = external thread_local global i32
+
+define i32 @foo() nounwind readonly {
+entry:
+; CHECK: .set  push
+; CHECK: .set  micromips
+; CHECK: rdhwr
+; CHECK: .set  pop
+
+  %0 = load i32* @a, align 4
+  ret i32 %0
+}
+
Index: test/MC/Mips/micromips-control-instructions.s
===================================================================
--- test/MC/Mips/micromips-control-instructions.s
+++ test/MC/Mips/micromips-control-instructions.s
@@ -14,6 +14,11 @@
 # CHECK-EL:    ssnop                      # encoding: [0x00,0x00,0x40,0x00]
 # CHECK-EL:    ehb                        # encoding: [0x00,0x00,0xc0,0x00]
 # CHECK-EL:    pause                      # encoding: [0x00,0x00,0x40,0x01]
+# CHECK-EL:    sdbbp                      # encoding: [0x00,0x00,0x7c,0xdb]
+# CHECK-EL:   .set push
+# CHECK-EL:   .set micromips
+# CHECK-EL:   rdhwr $5, $29
+# CHECK-EL:   .set pop                    # encoding: [0xbd,0x00,0x3c,0x6b]
 # CHECK-EL:    tlbp                       # encoding: [0x01,0x00,0x7c,0x03]
 # CHECK-EL:    tlbr                       # encoding: [0x01,0x00,0x7c,0x13]
 # CHECK-EL:    tlbwi                      # encoding: [0x01,0x00,0x7c,0x23]
@@ -41,6 +46,11 @@
 # CHECK-EB:   ssnop                       # encoding: [0x00,0x00,0x00,0x40]
 # CHECK-EB:   ehb                         # encoding: [0x00,0x00,0x00,0xc0]
 # CHECK-EB:   pause                       # encoding: [0x00,0x00,0x01,0x40]
+# CHECK-EB:   sdbbp                       # encoding: [0x00,0x00,0xdb,0x7c]
+# CHECK-EB:   .set push
+# CHECK-EB:   .set micromips
+# CHECK-EB:   rdhwr $5, $29
+# CHECK-EB:   .set pop                    # encoding: [0x00,0xbd,0x6b,0x3c]
 # CHECK-EB:   tlbp                        # encoding: [0x00,0x01,0x03,0x7c]
 # CHECK-EB:   tlbr                        # encoding: [0x00,0x01,0x13,0x7c]
 # CHECK-EB:   tlbwi                       # encoding: [0x00,0x01,0x23,0x7c]
@@ -66,6 +76,8 @@
     ssnop
     ehb
     pause
+    sdbbp
+    rdhwr $5, $29
     tlbp
     tlbr
     tlbwi