Index: src/Unwind/UnwindRegistersRestore.S
===================================================================
--- src/Unwind/UnwindRegistersRestore.S
+++ src/Unwind/UnwindRegistersRestore.S
@@ -347,7 +347,11 @@
   @ these registers implies they are, actually, available on the target, so
   @ it's ok to execute.
   @ So, generate the instruction using the corresponding coprocessor mnemonic.
-  ldc p11, cr0, [r0], {#0x20}  @ fldmiad r0, {d0-d15}
+#if __ARM_ARCH < 7
+  ldc p11, cr0, [r0], {0x20}  @ fldmiad r0, {d0-d15}
+#else
+  vldmia r0, {d0-d15}
+#endif
   mov pc, lr
 
 @
@@ -358,7 +362,11 @@
 @
   .p2align 2
 DEFINE_LIBUNWIND_PRIVATE_FUNCTION(_ZN9libunwind13Registers_arm19restoreVFPWithFLDMXEPy)
-  ldc p11, cr0, [r0], {#0x21}  @ fldmiax r0, {d0-d15}
+#if __ARM_ARCH < 7
+  ldc p11, cr0, [r0], {0x21}  @ fldmiax r0, {d0-d15}
+#else
+  vldmia r0, {d0-d15} @ fldmiax is deprecated in ARMv7+ and now behaves like vldmia
+#endif
   mov pc, lr
 
 @
@@ -369,7 +377,11 @@
 @
   .p2align 2
 DEFINE_LIBUNWIND_PRIVATE_FUNCTION(_ZN9libunwind13Registers_arm12restoreVFPv3EPy)
-  ldcl p11, cr0, [r0], {#0x20}  @ vldm r0, {d16-d31}
+#if __ARM_ARCH < 7
+  ldcl p11, cr0, [r0], {0x20}  @ vldm r0, {d16-d31}
+#else
+  vldmia r0, {d16-d31}
+#endif
   mov pc, lr
 
 @
Index: src/Unwind/UnwindRegistersSave.S
===================================================================
--- src/Unwind/UnwindRegistersSave.S
+++ src/Unwind/UnwindRegistersSave.S
@@ -318,7 +318,11 @@
 @
   .p2align 2
 DEFINE_LIBUNWIND_PRIVATE_FUNCTION(_ZN9libunwind13Registers_arm16saveVFPWithFSTMDEPy)
-  stc p11, cr0, [r0], {#0x20}  @ fstmiad r0, {d0-d15}
+#if __ARM_ARCH < 7
+  stc p11, cr0, [r0], {0x20}  @ fstmiad r0, {d0-d15}
+#else
+  vstmia r0, {d0-d15}
+#endif
   mov pc, lr
 
 @
@@ -329,7 +333,11 @@
 @
   .p2align 2
 DEFINE_LIBUNWIND_PRIVATE_FUNCTION(_ZN9libunwind13Registers_arm16saveVFPWithFSTMXEPy)
-  stc p11, cr0, [r0], {#0x21}  @ fstmiax r0, {d0-d15}
+#if __ARM_ARCH < 7
+  stc p11, cr0, [r0], {0x21}  @ fstmiax r0, {d0-d15}
+#else
+  vstmia r0, {d0-d15} @ fstmiax is deprecated in ARMv7+ and now behaves like vstmia
+#endif
   mov pc, lr
 
 @
@@ -347,7 +355,11 @@
   @ these registers implies they are, actually, available on the target, so
   @ it's ok to execute.
   @ So, generate the instructions using the corresponding coprocessor mnemonic.
-  stcl p11, cr0, [r0], {#0x20}  @ vldm r0, {d16-d31}
+#if __ARM_ARCH < 7
+  stcl p11, cr0, [r0], {0x20}  @ vldm r0, {d16-d31}
+#else
+  vstmia r0, {d16-d31}
+#endif
   mov pc, lr
 
 @