Index: tools/llvm-mctoll/ARM/ARMEliminatePrologEpilog.h =================================================================== --- /dev/null +++ tools/llvm-mctoll/ARM/ARMEliminatePrologEpilog.h @@ -0,0 +1,42 @@ +//===--- ARMEliminatePrologEpilog.h - Binary raiser utility llvm-mctoll ---===// +// +// The LLVM Compiler Infrastructure +// +// This file is distributed under the University of Illinois Open Source +// License. See LICENSE.TXT for details. +// +//===----------------------------------------------------------------------===// +// +// This file contains the declaration of ARMEliminatePrologEpilog class for +// use by llvm-mctoll. +// +//===----------------------------------------------------------------------===// + +#ifndef LLVM_TOOLS_LLVM_MCTOLL_ARM_ARMELIMINATEPROLOGEPILOG_H +#define LLVM_TOOLS_LLVM_MCTOLL_ARM_ARMELIMINATEPROLOGEPILOG_H + +#include "ARMRaiserBase.h" + +using namespace llvm; + +class ARMEliminatePrologEpilog : public ARMRaiserBase { +public: + static char ID; + + ARMEliminatePrologEpilog(ModuleRaiser &mr); + ~ARMEliminatePrologEpilog(); + void init(MachineFunction *mf = nullptr, Function *rf = nullptr) override; + bool eliminate(); + bool runOnMachineFunction(MachineFunction &mf) override; + +private: + bool checkRegister(unsigned Reg, std::vector &instrs) const; + bool eliminateProlog(MachineFunction &mf) const; + bool eliminateEpilog(MachineFunction &mf) const; + /// Analyze stack size base on moving sp. + void analyzeStackSize(MachineFunction &mf); + /// Analyze frame adjustment base on the offset between fp and base sp. + void analyzeFrameAdjustment(MachineFunction &mf); +}; + +#endif // LLVM_TOOLS_LLVM_MCTOLL_ARM_ARMELIMINATEPROLOGEPILOG_H Index: tools/llvm-mctoll/ARM/ARMEliminatePrologEpilog.cpp =================================================================== --- /dev/null +++ tools/llvm-mctoll/ARM/ARMEliminatePrologEpilog.cpp @@ -0,0 +1,361 @@ +//===- ARMEliminatePrologEpilog.cpp - Binary raiser utility llvm-mctoll -===// +// +// The LLVM Compiler Infrastructure +// +// This file is distributed under the University of Illinois Open Source +// License. See LICENSE.TXT for details. +// +//===----------------------------------------------------------------------===// +// +// This file contains the implementation of ARMEliminatePrologEpilog class +// for use by llvm-mctoll. +// +//===----------------------------------------------------------------------===/ + +#include "ARMEliminatePrologEpilog.h" +#include "ARMSubtarget.h" + +using namespace llvm; + +char ARMEliminatePrologEpilog::ID = 0; + +ARMEliminatePrologEpilog::ARMEliminatePrologEpilog(ModuleRaiser &mr) + : ARMRaiserBase(ID, mr) {} + +ARMEliminatePrologEpilog::~ARMEliminatePrologEpilog() {} + +void ARMEliminatePrologEpilog::init(MachineFunction *mf, Function *rf) { + ARMRaiserBase::init(mf, rf); +} + +// Return true if an operand in the instrs vector matches the passed register +// number, otherwise false. +bool ARMEliminatePrologEpilog::checkRegister( + unsigned Reg, std::vector &instrs) const { + std::vector::iterator it = instrs.begin(); + for (; it < instrs.end(); ++it) { + MachineInstr *mi = *it; + if (mi->mayStore()) { + for (unsigned i = 0; i < mi->getNumOperands(); i++) { + MachineOperand MO = mi->getOperand(i); + + // Compare the register number. + if (MO.isReg() && MO.getReg() == Reg) + return true; + } + } + } + return false; +} + +// Raise the function prolog. +// +// Look for the following instructions and eliminate them: +// str fp, [sp, #-4]! +// add fp, sp, #0 +// +// sub sp, fp, #0 +// ldr fp, [sp], #4 +// AND +// push {r11,lr} +// add r11, sp, #4 +// +// sub sp, r11, #4 +// pop {r11, pc} +// AND +// stmdb r13!, {r0-r3} +// stmdb r13!, {r4-r12,r13,r14} +// +// ldmia r13, {r4-r11, r13, r15} +// AND +// mov r12, r13 +// stmdb r13!, {r0-r3} +// stmdb r13!, {r4-r12, r14} +// sub r11, r12, #16 +// +// ldmdb r13, {r4-r11, r13, r15} +bool ARMEliminatePrologEpilog::eliminateProlog(MachineFunction &MF) const { + std::vector prologInstrs; + MachineBasicBlock &frontMBB = MF.front(); + + const ARMSubtarget &STI = MF.getSubtarget(); + const ARMBaseRegisterInfo *RegInfo = STI.getRegisterInfo(); + unsigned FramePtr = RegInfo->getFrameRegister(MF); + + for (MachineBasicBlock::iterator frontMBBIter = frontMBB.begin(); + frontMBBIter != frontMBB.end(); frontMBBIter++) { + MachineInstr &curMachInstr = (*frontMBBIter); + + // Push the MOVr instruction + if (curMachInstr.getOpcode() == ARM::MOVr) { + if ((curMachInstr.getOperand(1).isReg() && + curMachInstr.getOperand(1).getReg() == FramePtr)) + prologInstrs.push_back(&curMachInstr); + } + + // Push the STORE instruction + if (curMachInstr.mayStore()) { + MachineOperand storeOperand = curMachInstr.getOperand(0); + if (storeOperand.isReg() && storeOperand.getReg() == FramePtr) { + prologInstrs.push_back(&curMachInstr); + } + } + + // Push the ADDri instruction + if (curMachInstr.getOpcode() == ARM::ADDri && + curMachInstr.getOperand(1).getReg() == FramePtr) { + prologInstrs.push_back(&curMachInstr); + } + + // Push the SUBri instruction + if (curMachInstr.getOpcode() == ARM::SUBri && + curMachInstr.getOperand(0).getReg() == FramePtr && + curMachInstr.getOperand(1).getReg() == FramePtr) { + prologInstrs.push_back(&curMachInstr); + } + + // Push sub r11, r12, #16 + if (curMachInstr.getOpcode() == ARM::SUBri && + curMachInstr.getOperand(0).getReg() == ARM::R11 && + curMachInstr.getOperand(1).getReg() == ARM::R12) { + prologInstrs.push_back(&curMachInstr); + } + } + + // Create the stack frame + const TargetRegisterInfo *TRI = MF.getRegInfo().getTargetRegisterInfo(); + const MCPhysReg *CSRegs = TRI->getCalleeSavedRegs(&MF); + + std::vector CSI; + for (unsigned i = 0; CSRegs[i]; ++i) { + unsigned Reg = CSRegs[i]; + + // Save register. + if (checkRegister(Reg, prologInstrs)) { + CSI.push_back(CalleeSavedInfo(Reg)); + } + } + + const TargetFrameLowering *TFI = MF.getSubtarget().getFrameLowering(); + MachineFrameInfo &MFI = MF.getFrameInfo(); + if (!TFI->assignCalleeSavedSpillSlots(MF, RegInfo, CSI)) { + // If target doesn't implement this, use generic code. + if (CSI.empty()) + return true; // Early exit if no callee saved registers are modified! + + unsigned NumFixedSpillSlots; + const TargetFrameLowering::SpillSlot *FixedSpillSlots = + TFI->getCalleeSavedSpillSlots(NumFixedSpillSlots); + + // Allocate stack slots for the registers that need to be saved and restored + unsigned Offset = 0; + for (auto &CS : CSI) { + unsigned Reg = CS.getReg(); + const TargetRegisterClass *RC = RegInfo->getMinimalPhysRegClass(Reg); + + int FrameIdx; + if (RegInfo->hasReservedSpillSlot(MF, Reg, FrameIdx)) { + CS.setFrameIdx(FrameIdx); + continue; + } + + // Check if this physreg must be spilled to a particular stack slot for + // this target + const TargetFrameLowering::SpillSlot *FixedSlot = FixedSpillSlots; + while (FixedSlot != FixedSpillSlots + NumFixedSpillSlots && + FixedSlot->Reg != Reg) + ++FixedSlot; + + unsigned Size = RegInfo->getSpillSize(*RC); + if (FixedSlot == FixedSpillSlots + NumFixedSpillSlots) { + // Nope, just spill it anywhere convenient. + unsigned Align = RegInfo->getSpillAlignment(*RC); + unsigned StackAlign = TFI->getStackAlignment(); + + // The alignment is the minimum of the desired alignment of the + // TargetRegisterClass and the stack alignment, whichever is smaller. + Align = std::min(Align, StackAlign); + FrameIdx = MFI.CreateStackObject(Size, Align, true); + Offset += Size; + + // Set the object offset + MFI.setObjectOffset(FrameIdx, MFI.getObjectOffset(FrameIdx) - Offset); + } else { + // Spill to the stack. + FrameIdx = MFI.CreateFixedSpillStackObject(Size, FixedSlot->Offset); + } + + // Set the frame index + CS.setFrameIdx(FrameIdx); + } + MFI.setCalleeSavedInfo(CSI); + } + + // Eliminate the instructions identified in function prologue + unsigned int delInstSz = prologInstrs.size(); + for (unsigned int i = 0; i < delInstSz; i++) { + frontMBB.erase(prologInstrs[i]); + } + + return true; +} + +bool ARMEliminatePrologEpilog::eliminateEpilog(MachineFunction &MF) const { + const ARMSubtarget &STI = MF.getSubtarget(); + const ARMBaseRegisterInfo *RegInfo = STI.getRegisterInfo(); + const ARMBaseInstrInfo *TII = STI.getInstrInfo(); + unsigned FramePtr = RegInfo->getFrameRegister(MF); + + for (MachineBasicBlock &MBB : MF) { + std::vector epilogInstrs; + // MBBI may be invalidated by the raising operation. + for (MachineBasicBlock::iterator backMBBIter = MBB.begin(); + backMBBIter != MBB.end(); backMBBIter++) { + MachineInstr &curMachInstr = (*backMBBIter); + + // Push the LOAD instruction + if (curMachInstr.mayLoad()) { + MachineOperand loadOperand = curMachInstr.getOperand(0); + if (loadOperand.isReg() && loadOperand.getReg() == FramePtr) { + // If the register list of current POP includes PC register, + // it should be replaced with return instead of removed. + if (curMachInstr.findRegisterUseOperandIdx(ARM::PC) != -1) { + MachineInstrBuilder mib = + BuildMI(MBB, &curMachInstr, DebugLoc(), TII->get(ARM::BX_RET)); + int cpsridx = curMachInstr.findRegisterUseOperandIdx(ARM::CPSR); + if (cpsridx == -1) { + mib.addImm(14); + } else { + mib.add(curMachInstr.getOperand(cpsridx - 1)) + .add(curMachInstr.getOperand(cpsridx)); + } + mib.add(curMachInstr.getOperand( + curMachInstr.getNumExplicitOperands() - 1)); + } + epilogInstrs.push_back(&curMachInstr); + } + } + + // Push the LDR instruction + if (curMachInstr.getOpcode() == ARM::LDR_POST_IMM && + curMachInstr.getOperand(1).getReg() == FramePtr) { + epilogInstrs.push_back(&curMachInstr); + } + + // Push the STR instruction + if (curMachInstr.getOpcode() == ARM::STR_PRE_IMM && + curMachInstr.getOperand(0).getReg() == FramePtr) { + epilogInstrs.push_back(&curMachInstr); + } + + // Push the ADDri instruction + if (curMachInstr.getOpcode() == ARM::ADDri && + curMachInstr.getOperand(0).isReg()) { + if (curMachInstr.getOperand(0).getReg() == FramePtr) { + epilogInstrs.push_back(&curMachInstr); + } + } + + // Push the SUBri instruction + if (curMachInstr.getOpcode() == ARM::SUBri && + curMachInstr.getOperand(0).getReg() == FramePtr) { + epilogInstrs.push_back(&curMachInstr); + } + + if (curMachInstr.getOpcode() == ARM::MOVr) { + if (curMachInstr.getOperand(1).isReg() && + curMachInstr.getOperand(1).getReg() == ARM::R11 && + curMachInstr.getOperand(0).isReg() && + curMachInstr.getOperand(0).getReg() == FramePtr) + epilogInstrs.push_back(&curMachInstr); + } + } + + // Eliminate the instructions identified in function epilogue + unsigned int delInstSz = epilogInstrs.size(); + for (unsigned int i = 0; i < delInstSz; i++) { + MBB.erase(epilogInstrs[i]); + } + } + + return true; +} + +/// Analyze stack size base on moving sp. +/// Patterns like: +/// sub sp, sp, #28 +void ARMEliminatePrologEpilog::analyzeStackSize(MachineFunction &mf) { + if (mf.size() < 1) + return; + + const MachineBasicBlock &mbb = mf.front(); + + for (const MachineInstr &mi : mbb.instrs()) { + if (mi.getOpcode() == ARM::SUBri && mi.getNumOperands() >= 3 && + mi.getOperand(0).isReg() && mi.getOperand(0).getReg() == ARM::SP && + mi.getOperand(1).isReg() && mi.getOperand(1).getReg() == ARM::SP && + mi.getOperand(2).isImm() && mi.getOperand(2).getImm() > 0) { + mf.getFrameInfo().setStackSize(mi.getOperand(2).getImm()); + break; + } + } +} +/// Analyze frame adjustment base on the offset between fp and base sp. +/// Patterns like: +/// add fp, sp, #8 +void ARMEliminatePrologEpilog::analyzeFrameAdjustment(MachineFunction &mf) { + if (mf.size() < 1) + return; + + const MachineBasicBlock &mbb = mf.front(); + + for (const MachineInstr &mi : mbb.instrs()) { + if (mi.getOpcode() == ARM::ADDri && mi.getNumOperands() >= 3 && + mi.getOperand(0).isReg() && mi.getOperand(0).getReg() == ARM::R11 && + mi.getOperand(1).isReg() && mi.getOperand(1).getReg() == ARM::SP && + mi.getOperand(2).isImm() && mi.getOperand(2).getImm() > 0) { + mf.getFrameInfo().setOffsetAdjustment(mi.getOperand(2).getImm()); + break; + } + } +} + +bool ARMEliminatePrologEpilog::eliminate() { + if (PrintPass) + dbgs() << "ARMEliminatePrologEpilog start.\n"; + + analyzeStackSize(*MF); + analyzeFrameAdjustment(*MF); + bool success = eliminateProlog(*MF); + + if (success) { + success = eliminateEpilog(*MF); + } + + // For debugging. + if (PrintPass) { + MF->dump(); + getCRF()->dump(); + } + + if (PrintPass) + dbgs() << "ARMEliminatePrologEpilog end.\n"; + return !success; +} + +bool ARMEliminatePrologEpilog::runOnMachineFunction(MachineFunction &mf) { + bool rtn = false; + init(); + rtn = eliminate(); + return rtn; +} + +#ifdef __cplusplus +extern "C" { +#endif +FunctionPass *InitializeARMEliminatePrologEpilog(ModuleRaiser &mr) { + return new ARMEliminatePrologEpilog(mr); +} +#ifdef __cplusplus +} +#endif Index: tools/llvm-mctoll/ARM/ARMFunctionPrototype.h =================================================================== --- /dev/null +++ tools/llvm-mctoll/ARM/ARMFunctionPrototype.h @@ -0,0 +1,47 @@ +//===- ARMFunctionPrototype.h -----------------------------------*- C++ -*-===// +// +// The LLVM Compiler Infrastructure +// +// This file is distributed under the University of Illinois Open Source +// License. See LICENSE.TXT for details. +// +//===----------------------------------------------------------------------===// +// +// This file contains the declaration of ARMFunctionPrototype class for +// use by llvm-mctoll. +// +//===----------------------------------------------------------------------===// + +#ifndef LLVM_TOOLS_LLVM_MCTOLL_ARM_ARMFUNCTIONPROTOTYPE_H +#define LLVM_TOOLS_LLVM_MCTOLL_ARM_ARMFUNCTIONPROTOTYPE_H + +#include "llvm/CodeGen/MachineFunction.h" +#include "llvm/CodeGen/MachineFunctionPass.h" + +using namespace llvm; + +class ARMFunctionPrototype : public MachineFunctionPass { +public: + static char ID; + + ARMFunctionPrototype(); + virtual ~ARMFunctionPrototype(); + + Function *discover(MachineFunction &mf); + bool runOnMachineFunction(MachineFunction &mf); + +private: + bool PrintPass; + + /// Check the first reference of the reg is USE. + bool isUsedRegiser(unsigned reg, const MachineBasicBlock &mbb); + /// Check the first reference of the reg is DEF. + bool isDefinedRegiser(unsigned reg, const MachineBasicBlock &mbb); + /// Get all arguments types of current MachineFunction. + void genParameterTypes(std::vector ¶mTypes, + const MachineFunction &mf, LLVMContext &ctx); + /// Get return type of current MachineFunction. + Type *genReturnType(const MachineFunction &mf, LLVMContext &ctx); +}; + +#endif // LLVM_TOOLS_LLVM_MCTOLL_ARM_ARMFUNCTIONPROTOTYPE_H Index: tools/llvm-mctoll/ARM/ARMFunctionPrototype.cpp =================================================================== --- /dev/null +++ tools/llvm-mctoll/ARM/ARMFunctionPrototype.cpp @@ -0,0 +1,224 @@ +//===- ARMFunctionPrototype.h -----------------------------------*- C++ -*-===// +// +// The LLVM Compiler Infrastructure +// +// This file is distributed under the University of Illinois Open Source +// License. See LICENSE.TXT for details. +// +//===----------------------------------------------------------------------===// +// +// This file contains the implementation of ARMFunctionPrototype class +// for use by llvm-mctoll. +// +//===----------------------------------------------------------------------===// + +#include "ARMFunctionPrototype.h" +#include "ARMSubtarget.h" +#include "llvm/CodeGen/MachineModuleInfo.h" + +using namespace llvm; + +char ARMFunctionPrototype::ID = 0; + +ARMFunctionPrototype::ARMFunctionPrototype() : MachineFunctionPass(ID) { + PrintPass = + (cl::getRegisteredOptions()["print-after-all"]->getNumOccurrences() > 0); +} + +ARMFunctionPrototype::~ARMFunctionPrototype() {} + +/// Check the first reference of the reg is USE. +bool ARMFunctionPrototype::isUsedRegiser(unsigned reg, + const MachineBasicBlock &mbb) { + for (MachineBasicBlock::const_iterator ii = mbb.begin(), ie = mbb.end(); + ii != ie; ++ii) { + const MachineInstr &mi = *ii; + for (MachineInstr::const_mop_iterator oi = mi.operands_begin(), + oe = mi.operands_end(); + oi != oe; oi++) { + const MachineOperand &mo = *oi; + if (mo.isReg() && (mo.getReg() == reg)) + return mo.isUse(); + } + } + + return false; +} + +/// Check the first reference of the reg is DEF. +void ARMFunctionPrototype::genParameterTypes(std::vector ¶mTypes, + const MachineFunction &mf, + LLVMContext &ctx) { + assert(!mf.empty() && "The function body is empty!!!"); + + const MachineBasicBlock &fmbb = mf.front(); + // TODO: Need to track register liveness on CFG. + + DenseMap tarr; + int maxidx = -1; // When the maxidx is -1, means there is no argument. + + // The first function argument is from R0. + if (isUsedRegiser(ARM::R0, fmbb)) { + maxidx = 0; + tarr[maxidx] = Type::getInt32Ty(ctx); + } + + // The second function argument is from R1. + if (isUsedRegiser(ARM::R1, fmbb)) { + maxidx = 1; + tarr[maxidx] = Type::getInt32Ty(ctx); + } + + // The third function argument is from R2. + if (isUsedRegiser(ARM::R2, fmbb)) { + maxidx = 2; + tarr[maxidx] = Type::getInt32Ty(ctx); + } + + // The fourth function argument is from R3. + if (isUsedRegiser(ARM::R3, fmbb)) { + maxidx = 3; + tarr[maxidx] = Type::getInt32Ty(ctx); + } + + // The rest of function arguments are from stack. + for (MachineFunction::const_iterator mbbi = mf.begin(), mbbe = mf.end(); + mbbi != mbbe; ++mbbi) { + const MachineBasicBlock &mbb = *mbbi; + + for (MachineBasicBlock::const_iterator mii = mbb.begin(), mie = mbb.end(); + mii != mie; ++mii) { + const MachineInstr &mi = *mii; + + // Match pattern like ldr r1, [fp, #8]. + if (mi.getOpcode() == ARM::LDRi12 && mi.getNumOperands() > 2) { + const MachineOperand &mo = mi.getOperand(1); + const MachineOperand &mc = mi.getOperand(2); + if (mo.isReg() && mo.getReg() == ARM::R11 && mc.isImm()) { + + // TODO: Need to check the imm is larger than 0 and it is align + // by 4(32 bit). + int imm = mc.getImm(); + if (imm >= 0) { + + // The start index of arguments on stack. If the library was + // compiled by clang, it starts from 2. If the library was compiled + // by GNU cross compiler, it starts from 1. + // FIXME: For now, we only treat that the library was complied by + // clang. We will enable the 'if condition' after we are able to + // identify the library was compiled by which compiler. + int idxoff = 2; + if (true /* clang */) + idxoff = 2; + else /* gnu */ + idxoff = 1; + + int idx = imm / 4 - idxoff + 4; // Plus 4 is to guarantee the first + // stack argument index is after all + // of register arguments' indices. + if (maxidx < idx) + maxidx = idx; + tarr[idx] = Type::getInt32Ty(ctx); + } + } + } + } + } + + for (int i = 0; i <= maxidx; ++i) { + if (tarr[i] == nullptr) + paramTypes.push_back(Type::getInt32Ty(ctx)); + else + paramTypes.push_back(tarr[i]); + } +} + +/// Get all arguments types of current MachineFunction. +bool ARMFunctionPrototype::isDefinedRegiser(unsigned reg, + const MachineBasicBlock &mbb) { + + for (MachineBasicBlock::const_reverse_iterator ii = mbb.rbegin(), + ie = mbb.rend(); + ii != ie; ++ii) { + const MachineInstr &mi = *ii; + for (MachineInstr::const_mop_iterator oi = mi.operands_begin(), + oe = mi.operands_end(); + oi != oe; oi++) { + const MachineOperand &mo = *oi; + if (mo.isReg() && (mo.getReg() == reg)) { + // The return register must not be tied to another register. + // If it was, it should not be return register. + if (mo.isTied()) + return false; + + return mo.isDef(); + } + } + } + + return false; +} + +/// Get return type of current MachineFunction. +Type *ARMFunctionPrototype::genReturnType(const MachineFunction &mf, + LLVMContext &ctx) { + // TODO: Need to track register liveness on CFG. + Type *retTy; + + retTy = Type::getVoidTy(ctx); + for (const MachineBasicBlock &mbb : mf) { + if (mbb.succ_empty()) { + if (isDefinedRegiser(ARM::R0, mbb)) { + // TODO: Need to identify data type, int, long, float or double. + retTy = Type::getInt32Ty(ctx); + break; + } + } + } + + return retTy; +} + +Function *ARMFunctionPrototype::discover(MachineFunction &mf) { + if (PrintPass) + dbgs() << "ARMFunctionPrototype start.\n"; + + Function &fn = const_cast(mf.getFunction()); + LLVMContext &ctx = fn.getContext(); + + std::vector paramTys; + genParameterTypes(paramTys, mf, ctx); + Type *retTy = genReturnType(mf, ctx); + FunctionType *fnTy = FunctionType::get(retTy, paramTys, false); + + MachineModuleInfo &mmi = mf.getMMI(); + Module *mdl = const_cast(mmi.getModule()); + mdl->getFunctionList().remove(&fn); + Function *pnfn = + Function::Create(fnTy, GlobalValue::ExternalLinkage, fn.getName(), mdl); + + if (PrintPass) { + mf.dump(); + pnfn->dump(); + } + + if (PrintPass) + dbgs() << "ARMFunctionPrototype end.\n"; + + return pnfn; +} + +bool ARMFunctionPrototype::runOnMachineFunction(MachineFunction &mf) { + discover(mf); + return true; +} + +#ifdef __cplusplus +extern "C" { +#endif +MachineFunctionPass *InitializeARMFunctionPrototype() { + return new ARMFunctionPrototype(); +} +#ifdef __cplusplus +} +#endif Index: tools/llvm-mctoll/ARM/ARMMachineInstructionRaiser.h =================================================================== --- /dev/null +++ tools/llvm-mctoll/ARM/ARMMachineInstructionRaiser.h @@ -0,0 +1,39 @@ +//===-- ARMMachineInstructionRaiser.h - Binary raiser utility llvm-mctoll -===// +// +// The LLVM Compiler Infrastructure +// +// This file is distributed under the University of Illinois Open Source +// License. See LICENSE.TXT for details. +// +//===----------------------------------------------------------------------===// +// +// This file contains the declaration of ARMMachineInstructionRaiser +// class for use by llvm-mctoll. +// +//===----------------------------------------------------------------------===// + +#ifndef LLVM_TOOLS_LLVM_MCTOLL_ARM_ARMMACHINEINSTRUCTIONRAISER_H +#define LLVM_TOOLS_LLVM_MCTOLL_ARM_ARMMACHINEINSTRUCTIONRAISER_H + +#include "MachineInstructionRaiser.h" + +class ARMMachineInstructionRaiser : public MachineInstructionRaiser { +public: + ARMMachineInstructionRaiser() = delete; + ARMMachineInstructionRaiser(MachineFunction &machFunc, Module &m, + const ModuleRaiser *mr, MCInstRaiser *mcir); + bool raise(); + FunctionType *getRaisedFunctionPrototype(); + int getArgumentNumber(unsigned int); + Value *getRegValue(unsigned); + bool buildFuncArgTypeVector(const std::set &, + std::vector &); + +private: + bool raiseMachineFunction(); + // Commonly used LLVM data structures during this phase + MachineRegisterInfo &machRegInfo; + + Module &M; +}; +#endif // LLVM_TOOLS_LLVM_MCTOLL_ARM_ARMMACHINEINSTRUCTIONRAISER_H Index: tools/llvm-mctoll/ARM/ARMMachineInstructionRaiser.cpp =================================================================== --- /dev/null +++ tools/llvm-mctoll/ARM/ARMMachineInstructionRaiser.cpp @@ -0,0 +1,86 @@ +//===-- ARMEliminatePrologEpilog.cpp - Binary raiser utility llvm-mctoll --===// +// +// The LLVM Compiler Infrastructure +// +// This file is distributed under the University of Illinois Open Source +// License. See LICENSE.TXT for details. +// +//===----------------------------------------------------------------------===// +// +// This file contains the implementation of ARMMachineInstructionRaiser class +// for use by llvm-mctoll. +// +//===----------------------------------------------------------------------===// + +#include "ARMMachineInstructionRaiser.h" +#include "ARMEliminatePrologEpilog.h" +#include "ARMFunctionPrototype.h" + +using namespace llvm; + +ARMMachineInstructionRaiser::ARMMachineInstructionRaiser( + MachineFunction &machFunc, Module &m, const ModuleRaiser *mr, + MCInstRaiser *mcir) + : MachineInstructionRaiser(machFunc, m, mr, mcir), + machRegInfo(MF.getRegInfo()), M(m) {} + +bool ARMMachineInstructionRaiser::raiseMachineFunction() { + ModuleRaiser &rmr = const_cast(*MR); + + ARMEliminatePrologEpilog epe(rmr); + epe.init(&MF, raisedFunction); + epe.eliminate(); + + return true; +} + +bool ARMMachineInstructionRaiser::raise() { + raiseMachineFunction(); + + return true; +} + +int ARMMachineInstructionRaiser::getArgumentNumber(unsigned int PReg) { + // NYI + assert(false && + "Unimplemented ARMMachineInstructionRaiser::getArgumentNumber()"); + return -1; +} + +bool ARMMachineInstructionRaiser::buildFuncArgTypeVector( + const std::set &PhysRegs, std::vector &ArgTyVec) { + // NYI + assert(false && + "Unimplemented ARMMachineInstructionRaiser::buildFuncArgTypeVector()"); + return false; +} + +Value *ARMMachineInstructionRaiser::getRegValue(unsigned PReg) { + assert(false && "Unimplemented ARMMachineInstructionRaiser::getRegValue()"); + return nullptr; +} + +FunctionType *ARMMachineInstructionRaiser::getRaisedFunctionPrototype() { + ARMFunctionPrototype AFP; + raisedFunction = AFP.discover(MF); + + Function *ori = const_cast(&MF.getFunction()); + // Insert the map of raised function to tempFunctionPointer. + const_cast(MR)->insertPlaceholderRaisedFunctionMap( + raisedFunction, ori); + + return raisedFunction->getFunctionType(); +} + +#ifdef __cplusplus +extern "C" { +#endif +MachineInstructionRaiser * +InitializeARMMachineInstructionRaiser(MachineFunction &machFunc, Module &m, + const ModuleRaiser *mr, + MCInstRaiser *mcir) { + return new ARMMachineInstructionRaiser(machFunc, m, mr, mcir); +} +#ifdef __cplusplus +} +#endif Index: tools/llvm-mctoll/ARM/ARMRaiserBase.h =================================================================== --- /dev/null +++ tools/llvm-mctoll/ARM/ARMRaiserBase.h @@ -0,0 +1,57 @@ +//===- ARMRaiserBase.h ------------------------------------------*- C++ -*-===// +// +// The LLVM Compiler Infrastructure +// +// This file is distributed under the University of Illinois Open Source +// License. See LICENSE.TXT for details. +// +//===----------------------------------------------------------------------===// +// +// This file contains the declaration of the ARMRaiserBase class. This class +// is a base class of other ARM raisers, it supports some basic utilities for +// sub ARM raisers. +// +//===----------------------------------------------------------------------===// + +#ifndef LLVM_TOOLS_LLVM_MCTOLL_ARM_ARMRAISERBASE_H +#define LLVM_TOOLS_LLVM_MCTOLL_ARM_ARMRAISERBASE_H + +#include "ModuleRaiser.h" +#include "llvm/CodeGen/MachineFunction.h" +#include "llvm/Pass.h" + +using namespace llvm; + +class ARMRaiserBase : public FunctionPass { +protected: + ARMRaiserBase() = delete; + ARMRaiserBase(char &PassID, ModuleRaiser &mr) : FunctionPass(PassID), MR(mr) { + PrintPass = + (cl::getRegisteredOptions()["print-after-all"]->getNumOccurrences() > + 0); + } + ~ARMRaiserBase() override {} + virtual void init(MachineFunction *mf = nullptr, Function *rf = nullptr) { + if (mf) + MF = mf; + if (rf) + RF = rf; + } + virtual bool runOnMachineFunction(MachineFunction &mf) { return false; } + bool runOnFunction(Function &f) override { + RF = &f; + MF = MR.getMachineFunction(&f); + return runOnMachineFunction(*MF); + } + + /// Get current raised llvm::Function. + Function *getCRF() { return RF; } + + bool PrintPass; + ModuleRaiser &MR; + /// Current raised llvm::Function. + Function *RF; + MachineFunction *MF; +}; + +#endif // LLVM_TOOLS_LLVM_MCTOLL_ARM_ARMRAISERBASE_H Index: tools/llvm-mctoll/ARM/CMakeLists.txt =================================================================== --- /dev/null +++ tools/llvm-mctoll/ARM/CMakeLists.txt @@ -0,0 +1,18 @@ +include_directories( + ${LLVM_MAIN_SRC_DIR}/lib/Target/ARM + ${LLVM_BINARY_DIR}/lib/Target/ARM + ${CMAKE_CURRENT_SOURCE_DIR}/.. +) + +if(NOT LLVM_MCTOLL_BUILT_STANDALONE) + set(LLVM_MCTOLL_DEPS intrinsics_gen ARMCommonTableGen) +endif() + +add_llvm_library(ARMRaiser + ARMFunctionPrototype.cpp + ARMEliminatePrologEpilog.cpp + ARMMachineInstructionRaiser.cpp + + DEPENDS + ${LLVM_MCTOLL_DEPS} + ) Index: tools/llvm-mctoll/CMakeLists.txt =================================================================== --- /dev/null +++ tools/llvm-mctoll/CMakeLists.txt @@ -0,0 +1,117 @@ +# Check if llvm-mctoll is built as a standalone project. +if( CMAKE_SOURCE_DIR STREQUAL CMAKE_CURRENT_SOURCE_DIR ) + project(BinaryRaiser) + cmake_minimum_required(VERSION 3.4.3) + + set(LLVM_MCTOLL_BUILT_STANDALONE TRUE) + + find_program(LLVM_CONFIG_PATH "llvm-config" DOC "Path to llvm-config binary") + if(NOT LLVM_CONFIG_PATH) + message(FATAL_ERROR "llvm-config not found: specify LLVM_CONFIG_PATH") + endif() + + execute_process(COMMAND "${LLVM_CONFIG_PATH}" + "--assertion-mode" + "--obj-root" + "--bindir" + "--src-root" + "--cmakedir" + "--cxxflags" + RESULT_VARIABLE HAD_ERROR + OUTPUT_VARIABLE LLVM_CONFIG_OUTPUT + OUTPUT_STRIP_TRAILING_WHITESPACE) + if(HAD_ERROR) + message(FATAL_ERROR "llvm-config failed with status ${HAD_ERROR}") + endif() + + string(REGEX REPLACE "[ \t]*[\r\n]+[ \t]*" ";" LLVM_CONFIG_OUTPUT "${LLVM_CONFIG_OUTPUT}") + + list(GET LLVM_CONFIG_OUTPUT 0 ENABLE_ASSERTIONS) + list(GET LLVM_CONFIG_OUTPUT 1 OBJ_ROOT) + list(GET LLVM_CONFIG_OUTPUT 2 TOOLS_BINARY_DIR) + list(GET LLVM_CONFIG_OUTPUT 3 MAIN_SRC_DIR) + list(GET LLVM_CONFIG_OUTPUT 4 LLVM_CMAKE_PATH) + list(GET LLVM_CONFIG_OUTPUT 5 LLVM_CXX_FLAGS) + + if(NOT MSVC_IDE) + set(LLVM_ENABLE_ASSERTIONS ${ENABLE_ASSERTIONS} + CACHE BOOL "Enable assertions") + # Assertions should follow llvm-config's. + mark_as_advanced(LLVM_ENABLE_ASSERTIONS) + endif() + + set(LLVM_OBJ_ROOT ${OBJ_ROOT} CACHE PATH "Path to LLVM build tree") + set(LLVM_MAIN_SRC_DIR ${MAIN_SRC_DIR} CACHE PATH "Path to LLVM source tree") + set(CMAKE_CXX_FLAGS "${CMAKE_CXX_FLAGS} ${LLVM_CXX_FLAGS}") + set(LLVM_TOOLS_BINARY_DIR ${TOOLS_BINARY_DIR} CACHE PATH "Path to llvm/bin") + set(LLVM_EXTERNAL_LIT ${LLVM_TOOLS_BINARY_DIR}/llvm-lit CACHE PATH "Path to llvm-lit") + + file(TO_CMAKE_PATH ${LLVM_OBJ_ROOT} LLVM_BINARY_DIR) + + if(NOT EXISTS "${LLVM_CMAKE_PATH}/LLVMConfig.cmake") + message(FATAL_ERROR "LLVMConfig.cmake not found") + endif() + include("${LLVM_CMAKE_PATH}/LLVMConfig.cmake") + list(APPEND CMAKE_MODULE_PATH "${LLVM_CMAKE_PATH}") + + # They are used as destination of target generators. + set(LLVM_RUNTIME_OUTPUT_INTDIR ${CMAKE_BINARY_DIR}/${CMAKE_CFG_INTDIR}/bin) + + option(LLVM_ENABLE_WARNINGS "Enable compiler warnings." ON) + + include (AddLLVM) + include_directories(${LLVM_INCLUDE_DIRS}) + + include(CheckLibraryExists) + check_library_exists(xar xar_open "" HAVE_LIBXAR) + if(HAVE_LIBXAR) + set(XAR_LIB xar) + endif() + +endif() + +set(LLVM_MCTOLL_SOURCE_DIR ${CMAKE_CURRENT_SOURCE_DIR}) +set(LLVM_MCTOLL_BINARY_DIR ${CMAKE_CURRENT_BINARY_DIR}) + +llvm_map_components_to_libnames(llvm_libs + ${LLVM_TARGETS_TO_BUILD} + DebugInfoDWARF + DebugInfoPDB + Symbolize +) + +set(LLVM_MCTOLL_LIB_DEPS ${llvm_libs}) + +if(LLVM_TARGETS_TO_BUILD MATCHES "X86") + add_subdirectory(X86) + list(APPEND LLVM_MCTOLL_LIB_DEPS X86Raiser) +endif() + +if(LLVM_TARGETS_TO_BUILD MATCHES "ARM") + add_subdirectory(ARM) + list(APPEND LLVM_MCTOLL_LIB_DEPS ARMRaiser) +endif() + +add_subdirectory(test) + +add_llvm_tool(llvm-mctoll + llvm-mctoll.cpp + COFFDump.cpp + ELFDump.cpp + ExternalFunctions.cpp + MachODump.cpp + WasmDump.cpp + MachineFunctionRaiser.cpp + MCInstOrData.cpp + MCInstRaiser.cpp + EmitRaisedOutputPass.cpp +) + +# Link against LLVM libraries and target-specific Raiser libraries +target_link_libraries(llvm-mctoll PRIVATE ${LLVM_MCTOLL_LIB_DEPS}) + +if(HAVE_LIBXAR) + message(STATUS "Linking xar") + target_link_libraries(llvm-mctoll PRIVATE ${XAR_LIB}) +endif() + Index: tools/llvm-mctoll/COFFDump.cpp =================================================================== --- /dev/null +++ tools/llvm-mctoll/COFFDump.cpp @@ -0,0 +1,728 @@ +//===-- COFFDump.cpp - COFF-specific dumper ---------------------*- C++ -*-===// +// +// The LLVM Compiler Infrastructure +// +// This file is distributed under the University of Illinois Open Source +// License. See LICENSE.TXT for details. +// +//===----------------------------------------------------------------------===// +/// +/// \file +/// \brief This file implements the COFF-specific dumper for llvm-objdump. +/// It outputs the Win64 EH data structures as plain text. +/// The encoding of the unwind codes is described in MSDN: +/// http://msdn.microsoft.com/en-us/library/ck9asaa9.aspx +/// +//===----------------------------------------------------------------------===// + +#include "llvm-mctoll.h" +#include "llvm/Object/COFF.h" +#include "llvm/Object/COFFImportFile.h" +#include "llvm/Object/ObjectFile.h" +#include "llvm/Support/Format.h" +#include "llvm/Support/SourceMgr.h" +#include "llvm/Support/Win64EH.h" +#include "llvm/Support/raw_ostream.h" +#include +#include +#include + +using namespace llvm; +using namespace object; +using namespace llvm::Win64EH; + +// Returns the name of the unwind code. +static StringRef getUnwindCodeTypeName(uint8_t Code) { + switch (Code) { + default: + llvm_unreachable("Invalid unwind code"); + case UOP_PushNonVol: + return "UOP_PushNonVol"; + case UOP_AllocLarge: + return "UOP_AllocLarge"; + case UOP_AllocSmall: + return "UOP_AllocSmall"; + case UOP_SetFPReg: + return "UOP_SetFPReg"; + case UOP_SaveNonVol: + return "UOP_SaveNonVol"; + case UOP_SaveNonVolBig: + return "UOP_SaveNonVolBig"; + case UOP_SaveXMM128: + return "UOP_SaveXMM128"; + case UOP_SaveXMM128Big: + return "UOP_SaveXMM128Big"; + case UOP_PushMachFrame: + return "UOP_PushMachFrame"; + } +} + +// Returns the name of a referenced register. +static StringRef getUnwindRegisterName(uint8_t Reg) { + switch (Reg) { + default: + llvm_unreachable("Invalid register"); + case 0: + return "RAX"; + case 1: + return "RCX"; + case 2: + return "RDX"; + case 3: + return "RBX"; + case 4: + return "RSP"; + case 5: + return "RBP"; + case 6: + return "RSI"; + case 7: + return "RDI"; + case 8: + return "R8"; + case 9: + return "R9"; + case 10: + return "R10"; + case 11: + return "R11"; + case 12: + return "R12"; + case 13: + return "R13"; + case 14: + return "R14"; + case 15: + return "R15"; + } +} + +// Calculates the number of array slots required for the unwind code. +static unsigned getNumUsedSlots(const UnwindCode &UnwindCode) { + switch (UnwindCode.getUnwindOp()) { + default: + llvm_unreachable("Invalid unwind code"); + case UOP_PushNonVol: + case UOP_AllocSmall: + case UOP_SetFPReg: + case UOP_PushMachFrame: + return 1; + case UOP_SaveNonVol: + case UOP_SaveXMM128: + return 2; + case UOP_SaveNonVolBig: + case UOP_SaveXMM128Big: + return 3; + case UOP_AllocLarge: + return (UnwindCode.getOpInfo() == 0) ? 2 : 3; + } +} + +// Prints one unwind code. Because an unwind code can occupy up to 3 slots in +// the unwind codes array, this function requires that the correct number of +// slots is provided. +static void printUnwindCode(ArrayRef UCs) { + assert(UCs.size() >= getNumUsedSlots(UCs[0])); + outs() << format(" 0x%02x: ", unsigned(UCs[0].u.CodeOffset)) + << getUnwindCodeTypeName(UCs[0].getUnwindOp()); + switch (UCs[0].getUnwindOp()) { + case UOP_PushNonVol: + outs() << " " << getUnwindRegisterName(UCs[0].getOpInfo()); + break; + case UOP_AllocLarge: + if (UCs[0].getOpInfo() == 0) { + outs() << " " << UCs[1].FrameOffset; + } else { + outs() << " " + << UCs[1].FrameOffset + + (static_cast(UCs[2].FrameOffset) << 16); + } + break; + case UOP_AllocSmall: + outs() << " " << ((UCs[0].getOpInfo() + 1) * 8); + break; + case UOP_SetFPReg: + outs() << " "; + break; + case UOP_SaveNonVol: + outs() << " " << getUnwindRegisterName(UCs[0].getOpInfo()) + << format(" [0x%04x]", 8 * UCs[1].FrameOffset); + break; + case UOP_SaveNonVolBig: + outs() << " " << getUnwindRegisterName(UCs[0].getOpInfo()) + << format(" [0x%08x]", + UCs[1].FrameOffset + + (static_cast(UCs[2].FrameOffset) << 16)); + break; + case UOP_SaveXMM128: + outs() << " XMM" << static_cast(UCs[0].getOpInfo()) + << format(" [0x%04x]", 16 * UCs[1].FrameOffset); + break; + case UOP_SaveXMM128Big: + outs() << " XMM" << UCs[0].getOpInfo() + << format(" [0x%08x]", + UCs[1].FrameOffset + + (static_cast(UCs[2].FrameOffset) << 16)); + break; + case UOP_PushMachFrame: + outs() << " " << (UCs[0].getOpInfo() ? "w/o" : "w") << " error code"; + break; + } + outs() << "\n"; +} + +static void printAllUnwindCodes(ArrayRef UCs) { + for (const UnwindCode *I = UCs.begin(), *E = UCs.end(); I < E;) { + unsigned UsedSlots = getNumUsedSlots(*I); + if (UsedSlots > UCs.size()) { + outs() << "Unwind data corrupted: Encountered unwind op " + << getUnwindCodeTypeName((*I).getUnwindOp()) << " which requires " + << UsedSlots << " slots, but only " << UCs.size() + << " remaining in buffer"; + return; + } + printUnwindCode(makeArrayRef(I, E)); + I += UsedSlots; + } +} + +// Given a symbol sym this functions returns the address and section of it. +static std::error_code +resolveSectionAndAddress(const COFFObjectFile *Obj, const SymbolRef &Sym, + const coff_section *&ResolvedSection, + uint64_t &ResolvedAddr) { + Expected ResolvedAddrOrErr = Sym.getAddress(); + if (!ResolvedAddrOrErr) + return errorToErrorCode(ResolvedAddrOrErr.takeError()); + ResolvedAddr = *ResolvedAddrOrErr; + Expected Iter = Sym.getSection(); + if (!Iter) + return errorToErrorCode(Iter.takeError()); + ResolvedSection = Obj->getCOFFSection(**Iter); + return std::error_code(); +} + +// Given a vector of relocations for a section and an offset into this section +// the function returns the symbol used for the relocation at the offset. +static std::error_code resolveSymbol(const std::vector &Rels, + uint64_t Offset, SymbolRef &Sym) { + for (auto &R : Rels) { + uint64_t Ofs = R.getOffset(); + if (Ofs == Offset) { + Sym = *R.getSymbol(); + return std::error_code(); + } + } + return object_error::parse_failed; +} + +// Given a vector of relocations for a section and an offset into this section +// the function resolves the symbol used for the relocation at the offset and +// returns the section content and the address inside the content pointed to +// by the symbol. +static std::error_code +getSectionContents(const COFFObjectFile *Obj, + const std::vector &Rels, uint64_t Offset, + ArrayRef &Contents, uint64_t &Addr) { + SymbolRef Sym; + if (std::error_code EC = resolveSymbol(Rels, Offset, Sym)) + return EC; + const coff_section *Section; + if (std::error_code EC = resolveSectionAndAddress(Obj, Sym, Section, Addr)) + return EC; + if (std::error_code EC = Obj->getSectionContents(Section, Contents)) + return EC; + return std::error_code(); +} + +// Given a vector of relocations for a section and an offset into this section +// the function returns the name of the symbol used for the relocation at the +// offset. +static std::error_code resolveSymbolName(const std::vector &Rels, + uint64_t Offset, StringRef &Name) { + SymbolRef Sym; + if (std::error_code EC = resolveSymbol(Rels, Offset, Sym)) + return EC; + Expected NameOrErr = Sym.getName(); + if (!NameOrErr) + return errorToErrorCode(NameOrErr.takeError()); + Name = *NameOrErr; + return std::error_code(); +} + +static void printCOFFSymbolAddress(llvm::raw_ostream &Out, + const std::vector &Rels, + uint64_t Offset, uint32_t Disp) { + StringRef Sym; + if (!resolveSymbolName(Rels, Offset, Sym)) { + Out << Sym; + if (Disp > 0) + Out << format(" + 0x%04x", Disp); + } else { + Out << format("0x%04x", Disp); + } +} + +static void printSEHTable(const COFFObjectFile *Obj, uint32_t TableVA, + int Count) { + if (Count == 0) + return; + + const pe32_header *PE32Header; + error(Obj->getPE32Header(PE32Header)); + uint32_t ImageBase = PE32Header->ImageBase; + uintptr_t IntPtr = 0; + error(Obj->getVaPtr(TableVA, IntPtr)); + const support::ulittle32_t *P = (const support::ulittle32_t *)IntPtr; + outs() << "SEH Table:"; + for (int I = 0; I < Count; ++I) + outs() << format(" 0x%x", P[I] + ImageBase); + outs() << "\n\n"; +} + +template +static void printTLSDirectoryT(const coff_tls_directory *TLSDir) { + size_t FormatWidth = sizeof(T) * 2; + outs() << "TLS directory:" + << "\n StartAddressOfRawData: " + << format_hex(TLSDir->StartAddressOfRawData, FormatWidth) + << "\n EndAddressOfRawData: " + << format_hex(TLSDir->EndAddressOfRawData, FormatWidth) + << "\n AddressOfIndex: " + << format_hex(TLSDir->AddressOfIndex, FormatWidth) + << "\n AddressOfCallBacks: " + << format_hex(TLSDir->AddressOfCallBacks, FormatWidth) + << "\n SizeOfZeroFill: " << TLSDir->SizeOfZeroFill + << "\n Characteristics: " << TLSDir->Characteristics + << "\n Alignment: " << TLSDir->getAlignment() << "\n\n"; +} + +static void printTLSDirectory(const COFFObjectFile *Obj) { + const pe32_header *PE32Header; + error(Obj->getPE32Header(PE32Header)); + + const pe32plus_header *PE32PlusHeader; + error(Obj->getPE32PlusHeader(PE32PlusHeader)); + + // Skip if it's not executable. + if (!PE32Header && !PE32PlusHeader) + return; + + const data_directory *DataDir; + error(Obj->getDataDirectory(COFF::TLS_TABLE, DataDir)); + uintptr_t IntPtr = 0; + if (DataDir->RelativeVirtualAddress == 0) + return; + error(Obj->getRvaPtr(DataDir->RelativeVirtualAddress, IntPtr)); + + if (PE32Header) { + auto *TLSDir = reinterpret_cast(IntPtr); + printTLSDirectoryT(TLSDir); + } else { + auto *TLSDir = reinterpret_cast(IntPtr); + printTLSDirectoryT(TLSDir); + } + + outs() << "\n"; +} + +static void printLoadConfiguration(const COFFObjectFile *Obj) { + // Skip if it's not executable. + const pe32_header *PE32Header; + error(Obj->getPE32Header(PE32Header)); + if (!PE32Header) + return; + + // Currently only x86 is supported + if (Obj->getMachine() != COFF::IMAGE_FILE_MACHINE_I386) + return; + + const data_directory *DataDir; + error(Obj->getDataDirectory(COFF::LOAD_CONFIG_TABLE, DataDir)); + uintptr_t IntPtr = 0; + if (DataDir->RelativeVirtualAddress == 0) + return; + error(Obj->getRvaPtr(DataDir->RelativeVirtualAddress, IntPtr)); + + auto *LoadConf = reinterpret_cast(IntPtr); + outs() << "Load configuration:" + << "\n Timestamp: " << LoadConf->TimeDateStamp + << "\n Major Version: " << LoadConf->MajorVersion + << "\n Minor Version: " << LoadConf->MinorVersion + << "\n GlobalFlags Clear: " << LoadConf->GlobalFlagsClear + << "\n GlobalFlags Set: " << LoadConf->GlobalFlagsSet + << "\n Critical Section Default Timeout: " + << LoadConf->CriticalSectionDefaultTimeout + << "\n Decommit Free Block Threshold: " + << LoadConf->DeCommitFreeBlockThreshold + << "\n Decommit Total Free Threshold: " + << LoadConf->DeCommitTotalFreeThreshold + << "\n Lock Prefix Table: " << LoadConf->LockPrefixTable + << "\n Maximum Allocation Size: " << LoadConf->MaximumAllocationSize + << "\n Virtual Memory Threshold: " << LoadConf->VirtualMemoryThreshold + << "\n Process Affinity Mask: " << LoadConf->ProcessAffinityMask + << "\n Process Heap Flags: " << LoadConf->ProcessHeapFlags + << "\n CSD Version: " << LoadConf->CSDVersion + << "\n Security Cookie: " << LoadConf->SecurityCookie + << "\n SEH Table: " << LoadConf->SEHandlerTable + << "\n SEH Count: " << LoadConf->SEHandlerCount << "\n\n"; + printSEHTable(Obj, LoadConf->SEHandlerTable, LoadConf->SEHandlerCount); + outs() << "\n"; +} + +// Prints import tables. The import table is a table containing the list of +// DLL name and symbol names which will be linked by the loader. +static void printImportTables(const COFFObjectFile *Obj) { + import_directory_iterator I = Obj->import_directory_begin(); + import_directory_iterator E = Obj->import_directory_end(); + if (I == E) + return; + outs() << "The Import Tables:\n"; + for (const ImportDirectoryEntryRef &DirRef : Obj->import_directories()) { + const coff_import_directory_table_entry *Dir; + StringRef Name; + if (DirRef.getImportTableEntry(Dir)) + return; + if (DirRef.getName(Name)) + return; + + outs() << format(" lookup %08x time %08x fwd %08x name %08x addr %08x\n\n", + static_cast(Dir->ImportLookupTableRVA), + static_cast(Dir->TimeDateStamp), + static_cast(Dir->ForwarderChain), + static_cast(Dir->NameRVA), + static_cast(Dir->ImportAddressTableRVA)); + outs() << " DLL Name: " << Name << "\n"; + outs() << " Hint/Ord Name\n"; + for (const ImportedSymbolRef &Entry : DirRef.imported_symbols()) { + bool IsOrdinal; + if (Entry.isOrdinal(IsOrdinal)) + return; + if (IsOrdinal) { + uint16_t Ordinal; + if (Entry.getOrdinal(Ordinal)) + return; + outs() << format(" % 6d\n", Ordinal); + continue; + } + uint32_t HintNameRVA; + if (Entry.getHintNameRVA(HintNameRVA)) + return; + uint16_t Hint; + StringRef Name; + if (Obj->getHintName(HintNameRVA, Hint, Name)) + return; + outs() << format(" % 6d ", Hint) << Name << "\n"; + } + outs() << "\n"; + } +} + +// Prints export tables. The export table is a table containing the list of +// exported symbol from the DLL. +static void printExportTable(const COFFObjectFile *Obj) { + outs() << "Export Table:\n"; + export_directory_iterator I = Obj->export_directory_begin(); + export_directory_iterator E = Obj->export_directory_end(); + if (I == E) + return; + StringRef DllName; + uint32_t OrdinalBase; + if (I->getDllName(DllName)) + return; + if (I->getOrdinalBase(OrdinalBase)) + return; + outs() << " DLL name: " << DllName << "\n"; + outs() << " Ordinal base: " << OrdinalBase << "\n"; + outs() << " Ordinal RVA Name\n"; + for (; I != E; I = ++I) { + uint32_t Ordinal; + if (I->getOrdinal(Ordinal)) + return; + uint32_t RVA; + if (I->getExportRVA(RVA)) + return; + bool IsForwarder; + if (I->isForwarder(IsForwarder)) + return; + + if (IsForwarder) { + // Export table entries can be used to re-export symbols that + // this COFF file is imported from some DLLs. This is rare. + // In most cases IsForwarder is false. + outs() << format(" % 4d ", Ordinal); + } else { + outs() << format(" % 4d %# 8x", Ordinal, RVA); + } + + StringRef Name; + if (I->getSymbolName(Name)) + continue; + if (!Name.empty()) + outs() << " " << Name; + if (IsForwarder) { + StringRef S; + if (I->getForwardTo(S)) + return; + outs() << " (forwarded to " << S << ")"; + } + outs() << "\n"; + } +} + +// Given the COFF object file, this function returns the relocations for .pdata +// and the pointer to "runtime function" structs. +static bool getPDataSection(const COFFObjectFile *Obj, + std::vector &Rels, + const RuntimeFunction *&RFStart, int &NumRFs) { + for (const SectionRef &Section : Obj->sections()) { + StringRef Name; + error(Section.getName(Name)); + if (Name != ".pdata") + continue; + + const coff_section *Pdata = Obj->getCOFFSection(Section); + for (const RelocationRef &Reloc : Section.relocations()) + Rels.push_back(Reloc); + + // Sort relocations by address. + std::sort(Rels.begin(), Rels.end(), RelocAddressLess); + + ArrayRef Contents; + error(Obj->getSectionContents(Pdata, Contents)); + if (Contents.empty()) + continue; + + RFStart = reinterpret_cast(Contents.data()); + NumRFs = Contents.size() / sizeof(RuntimeFunction); + return true; + } + return false; +} + +static void printWin64EHUnwindInfo(const Win64EH::UnwindInfo *UI) { + // The casts to int are required in order to output the value as number. + // Without the casts the value would be interpreted as char data (which + // results in garbage output). + outs() << " Version: " << static_cast(UI->getVersion()) << "\n"; + outs() << " Flags: " << static_cast(UI->getFlags()); + if (UI->getFlags()) { + if (UI->getFlags() & UNW_ExceptionHandler) + outs() << " UNW_ExceptionHandler"; + if (UI->getFlags() & UNW_TerminateHandler) + outs() << " UNW_TerminateHandler"; + if (UI->getFlags() & UNW_ChainInfo) + outs() << " UNW_ChainInfo"; + } + outs() << "\n"; + outs() << " Size of prolog: " << static_cast(UI->PrologSize) << "\n"; + outs() << " Number of Codes: " << static_cast(UI->NumCodes) << "\n"; + // Maybe this should move to output of UOP_SetFPReg? + if (UI->getFrameRegister()) { + outs() << " Frame register: " + << getUnwindRegisterName(UI->getFrameRegister()) << "\n"; + outs() << " Frame offset: " << 16 * UI->getFrameOffset() << "\n"; + } else { + outs() << " No frame pointer used\n"; + } + if (UI->getFlags() & (UNW_ExceptionHandler | UNW_TerminateHandler)) { + // FIXME: Output exception handler data + } else if (UI->getFlags() & UNW_ChainInfo) { + // FIXME: Output chained unwind info + } + + if (UI->NumCodes) + outs() << " Unwind Codes:\n"; + + printAllUnwindCodes(makeArrayRef(&UI->UnwindCodes[0], UI->NumCodes)); + + outs() << "\n"; + outs().flush(); +} + +/// Prints out the given RuntimeFunction struct for x64, assuming that Obj is +/// pointing to an executable file. +static void printRuntimeFunction(const COFFObjectFile *Obj, + const RuntimeFunction &RF) { + if (!RF.StartAddress) + return; + outs() << "Function Table:\n" + << format(" Start Address: 0x%04x\n", + static_cast(RF.StartAddress)) + << format(" End Address: 0x%04x\n", + static_cast(RF.EndAddress)) + << format(" Unwind Info Address: 0x%04x\n", + static_cast(RF.UnwindInfoOffset)); + uintptr_t addr; + if (Obj->getRvaPtr(RF.UnwindInfoOffset, addr)) + return; + printWin64EHUnwindInfo(reinterpret_cast(addr)); +} + +/// Prints out the given RuntimeFunction struct for x64, assuming that Obj is +/// pointing to an object file. Unlike executable, fields in RuntimeFunction +/// struct are filled with zeros, but instead there are relocations pointing to +/// them so that the linker will fill targets' RVAs to the fields at link +/// time. This function interprets the relocations to find the data to be used +/// in the resulting executable. +static void printRuntimeFunctionRels(const COFFObjectFile *Obj, + const RuntimeFunction &RF, + uint64_t SectionOffset, + const std::vector &Rels) { + outs() << "Function Table:\n"; + outs() << " Start Address: "; + printCOFFSymbolAddress(outs(), Rels, + SectionOffset + + /*offsetof(RuntimeFunction, StartAddress)*/ 0, + RF.StartAddress); + outs() << "\n"; + + outs() << " End Address: "; + printCOFFSymbolAddress(outs(), Rels, + SectionOffset + + /*offsetof(RuntimeFunction, EndAddress)*/ 4, + RF.EndAddress); + outs() << "\n"; + + outs() << " Unwind Info Address: "; + printCOFFSymbolAddress(outs(), Rels, + SectionOffset + + /*offsetof(RuntimeFunction, UnwindInfoOffset)*/ 8, + RF.UnwindInfoOffset); + outs() << "\n"; + + ArrayRef XContents; + uint64_t UnwindInfoOffset = 0; + error( + getSectionContents(Obj, Rels, + SectionOffset + + /*offsetof(RuntimeFunction, UnwindInfoOffset)*/ 8, + XContents, UnwindInfoOffset)); + if (XContents.empty()) + return; + + UnwindInfoOffset += RF.UnwindInfoOffset; + if (UnwindInfoOffset > XContents.size()) + return; + + auto *UI = reinterpret_cast(XContents.data() + + UnwindInfoOffset); + printWin64EHUnwindInfo(UI); +} + +void llvm::printCOFFUnwindInfo(const COFFObjectFile *Obj) { + if (Obj->getMachine() != COFF::IMAGE_FILE_MACHINE_AMD64) { + errs() << "Unsupported image machine type " + "(currently only AMD64 is supported).\n"; + return; + } + + std::vector Rels; + const RuntimeFunction *RFStart; + int NumRFs; + if (!getPDataSection(Obj, Rels, RFStart, NumRFs)) + return; + ArrayRef RFs(RFStart, NumRFs); + + bool IsExecutable = Rels.empty(); + if (IsExecutable) { + for (const RuntimeFunction &RF : RFs) + printRuntimeFunction(Obj, RF); + return; + } + + for (const RuntimeFunction &RF : RFs) { + uint64_t SectionOffset = + std::distance(RFs.begin(), &RF) * sizeof(RuntimeFunction); + printRuntimeFunctionRels(Obj, RF, SectionOffset, Rels); + } +} + +void llvm::printCOFFFileHeader(const object::ObjectFile *Obj) { + const COFFObjectFile *file = dyn_cast(Obj); + printTLSDirectory(file); + printLoadConfiguration(file); + printImportTables(file); + printExportTable(file); +} + +void llvm::printCOFFSymbolTable(const object::COFFImportFile *i) { + unsigned Index = 0; + bool IsCode = i->getCOFFImportHeader()->getType() == COFF::IMPORT_CODE; + + for (const object::BasicSymbolRef &Sym : i->symbols()) { + std::string Name; + raw_string_ostream NS(Name); + + Sym.printName(NS); + NS.flush(); + + outs() << "[" << format("%2d", Index) << "]" + << "(sec " << format("%2d", 0) << ")" + << "(fl 0x00)" // Flag bits, which COFF doesn't have. + << "(ty " << format("%3x", (IsCode && Index) ? 32 : 0) << ")" + << "(scl " << format("%3x", 0) << ") " + << "(nx " << 0 << ") " + << "0x" << format("%08x", 0) << " " << Name << '\n'; + + ++Index; + } +} + +void llvm::printCOFFSymbolTable(const COFFObjectFile *coff) { + for (unsigned SI = 0, SE = coff->getNumberOfSymbols(); SI != SE; ++SI) { + Expected Symbol = coff->getSymbol(SI); + StringRef Name; + error(errorToErrorCode(Symbol.takeError())); + error(coff->getSymbolName(*Symbol, Name)); + + outs() << "[" << format("%2d", SI) << "]" + << "(sec " << format("%2d", int(Symbol->getSectionNumber())) << ")" + << "(fl 0x00)" // Flag bits, which COFF doesn't have. + << "(ty " << format("%3x", unsigned(Symbol->getType())) << ")" + << "(scl " << format("%3x", unsigned(Symbol->getStorageClass())) + << ") " + << "(nx " << unsigned(Symbol->getNumberOfAuxSymbols()) << ") " + << "0x" << format("%08x", unsigned(Symbol->getValue())) << " " + << Name << "\n"; + + for (unsigned AI = 0, AE = Symbol->getNumberOfAuxSymbols(); AI < AE; + ++AI, ++SI) { + if (Symbol->isSectionDefinition()) { + const coff_aux_section_definition *asd; + error(coff->getAuxSymbol(SI + 1, asd)); + + int32_t AuxNumber = asd->getNumber(Symbol->isBigObj()); + + outs() << "AUX " + << format("scnlen 0x%x nreloc %d nlnno %d checksum 0x%x ", + unsigned(asd->Length), + unsigned(asd->NumberOfRelocations), + unsigned(asd->NumberOfLinenumbers), + unsigned(asd->CheckSum)) + << format("assoc %d comdat %d\n", unsigned(AuxNumber), + unsigned(asd->Selection)); + } else if (Symbol->isFileRecord()) { + const char *FileName; + error(coff->getAuxSymbol(SI + 1, FileName)); + + StringRef Name(FileName, Symbol->getNumberOfAuxSymbols() * + coff->getSymbolTableEntrySize()); + outs() << "AUX " << Name.rtrim(StringRef("\0", 1)) << '\n'; + + SI = SI + Symbol->getNumberOfAuxSymbols(); + break; + } else if (Symbol->isWeakExternal()) { + const coff_aux_weak_external *awe; + error(coff->getAuxSymbol(SI + 1, awe)); + + outs() << "AUX " + << format("indx %d srch %d\n", + static_cast(awe->TagIndex), + static_cast(awe->Characteristics)); + } else { + outs() << "AUX Unknown\n"; + } + } + } +} Index: tools/llvm-mctoll/ELFDump.cpp =================================================================== --- /dev/null +++ tools/llvm-mctoll/ELFDump.cpp @@ -0,0 +1,105 @@ +//===-- ELFDump.cpp - ELF-specific dumper -----------------------*- C++ -*-===// +// +// The LLVM Compiler Infrastructure +// +// This file is distributed under the University of Illinois Open Source +// License. See LICENSE.TXT for details. +// +//===----------------------------------------------------------------------===// +/// +/// \file +/// \brief This file implements the ELF-specific dumper for llvm-objdump. +/// +//===----------------------------------------------------------------------===// + +#include "llvm-mctoll.h" +#include "llvm/Object/ELFObjectFile.h" +#include "llvm/Support/Format.h" +#include "llvm/Support/MathExtras.h" +#include "llvm/Support/raw_ostream.h" + +using namespace llvm; +using namespace llvm::object; + +template void printProgramHeaders(const ELFFile *o) { + typedef ELFFile ELFO; + outs() << "Program Header:\n"; + auto ProgramHeaderOrError = o->program_headers(); + if (!ProgramHeaderOrError) + report_fatal_error( + errorToErrorCode(ProgramHeaderOrError.takeError()).message()); + for (const typename ELFO::Elf_Phdr &Phdr : *ProgramHeaderOrError) { + switch (Phdr.p_type) { + case ELF::PT_DYNAMIC: + outs() << " DYNAMIC "; + break; + case ELF::PT_GNU_EH_FRAME: + outs() << "EH_FRAME "; + break; + case ELF::PT_GNU_RELRO: + outs() << " RELRO "; + break; + case ELF::PT_GNU_STACK: + outs() << " STACK "; + break; + case ELF::PT_INTERP: + outs() << " INTERP "; + break; + case ELF::PT_LOAD: + outs() << " LOAD "; + break; + case ELF::PT_NOTE: + outs() << " NOTE "; + break; + case ELF::PT_OPENBSD_BOOTDATA: + outs() << " OPENBSD_BOOTDATA "; + break; + case ELF::PT_OPENBSD_RANDOMIZE: + outs() << " OPENBSD_RANDOMIZE "; + break; + case ELF::PT_OPENBSD_WXNEEDED: + outs() << " OPENBSD_WXNEEDED "; + break; + case ELF::PT_PHDR: + outs() << " PHDR "; + break; + case ELF::PT_TLS: + outs() << " TLS "; + break; + default: + outs() << " UNKNOWN "; + } + + const char *Fmt = ELFT::Is64Bits ? "0x%016" PRIx64 " " : "0x%08" PRIx64 " "; + + outs() << "off " << format(Fmt, (uint64_t)Phdr.p_offset) << "vaddr " + << format(Fmt, (uint64_t)Phdr.p_vaddr) << "paddr " + << format(Fmt, (uint64_t)Phdr.p_paddr) + << format("align 2**%u\n", + countTrailingZeros(Phdr.p_align)) + << " filesz " << format(Fmt, (uint64_t)Phdr.p_filesz) + << "memsz " << format(Fmt, (uint64_t)Phdr.p_memsz) << "flags " + << ((Phdr.p_flags & ELF::PF_R) ? "r" : "-") + << ((Phdr.p_flags & ELF::PF_W) ? "w" : "-") + << ((Phdr.p_flags & ELF::PF_X) ? "x" : "-") << "\n"; + } + outs() << "\n"; +} + +void llvm::printELFFileHeader(const object::ObjectFile *Obj) { + // Little-endian 32-bit + if (const ELF32LEObjectFile *ELFObj = dyn_cast(Obj)) + printProgramHeaders(ELFObj->getELFFile()); + + // Big-endian 32-bit + if (const ELF32BEObjectFile *ELFObj = dyn_cast(Obj)) + printProgramHeaders(ELFObj->getELFFile()); + + // Little-endian 64-bit + if (const ELF64LEObjectFile *ELFObj = dyn_cast(Obj)) + printProgramHeaders(ELFObj->getELFFile()); + + // Big-endian 64-bit + if (const ELF64BEObjectFile *ELFObj = dyn_cast(Obj)) + printProgramHeaders(ELFObj->getELFFile()); +} Index: tools/llvm-mctoll/EmitRaisedOutputPass.h =================================================================== --- /dev/null +++ tools/llvm-mctoll/EmitRaisedOutputPass.h @@ -0,0 +1,48 @@ +//===----------- EmitRaisedOutputPass.h -------------*- C++ -*-===// +// +// The LLVM Compiler Infrastructure +// +// This file is distributed under the University of Illinois Open Source +// License. See LICENSE.TXT for details. +// +//===----------------------------------------------------------------------===// +// +// This file contains the declaration of EmitRaisedOutputPass for use by +// llvm-mctoll. This class is provided to inhibit printing of target line +// and keep the resulting output architecture-neutral. +// +//===----------------------------------------------------------------------===// + +#ifndef LLVM_TOOLS_LLVM_MCTOLL_EMITRAISEDOUTPUTPASS_H +#define LLVM_TOOLS_LLVM_MCTOLL_EMITRAISEDOUTPUTPASS_H + +#include "llvm/Bitcode/BitcodeWriterPass.h" +#include "llvm/IR/IRPrintingPasses.h" +#include "llvm/IR/Module.h" +#include "llvm/IR/PassManager.h" +#include "llvm/Target/TargetMachine.h" + +using namespace llvm; + +class EmitRaisedOutputPass : public ModulePass { + TargetMachine::CodeGenFileType OutFileType; + PrintModulePass PrintAsmPass; + BitcodeWriterPass PrintBitCodePass; + +public: + static char ID; + EmitRaisedOutputPass() + : ModulePass(ID), OutFileType(TargetMachine::CGFT_Null), + PrintBitCodePass(dbgs()) {} + EmitRaisedOutputPass(raw_ostream &OS, TargetMachine::CodeGenFileType CGFT, + const std::string &Banner = "", + bool ShouldPreserveUseListOrder = false) + : ModulePass(ID), OutFileType(CGFT), + PrintAsmPass(OS, Banner, ShouldPreserveUseListOrder), + PrintBitCodePass(OS, ShouldPreserveUseListOrder) {} + + bool runOnModule(Module &M) override; + + void getAnalysisUsage(AnalysisUsage &AU) const override; +}; +#endif // LLVM_TOOLS_LLVM_MCTOLL_EMITRAISEDOUTPUTPASS_H Index: tools/llvm-mctoll/EmitRaisedOutputPass.cpp =================================================================== --- /dev/null +++ tools/llvm-mctoll/EmitRaisedOutputPass.cpp @@ -0,0 +1,46 @@ +//===- EmitRaisedOutputPass.cpp - Binary raiser utility llvm-mctoll -----===// +// +// The LLVM Compiler Infrastructure +// +// This file is distributed under the University of Illinois Open Source +// License. See LICENSE.TXT for details. +// +//===----------------------------------------------------------------------===// +// +// This file contains the implementation of EmitRaisedOutputPass +// for use by llvm-mctoll. +// +//===----------------------------------------------------------------------===// + +#include "EmitRaisedOutputPass.h" + +char EmitRaisedOutputPass::ID = 0; + +bool EmitRaisedOutputPass::runOnModule(Module &M) { + ModuleAnalysisManager DummyMAM; + // Save current data layout of the module + auto DL = M.getDataLayout(); + // Set data layout to prevent emiting of architecture-specific information in + // the output. + M.setDataLayout(""); + // Call the appropriate printer + switch (OutFileType) { + case TargetMachine::CGFT_AssemblyFile: + PrintAsmPass.run(M, DummyMAM); + break; + case TargetMachine::CGFT_ObjectFile: + PrintBitCodePass.run(M, DummyMAM); + break; + case TargetMachine::CGFT_Null: + // Do nothing - corresponds to the command line option + // -output-format=null + break; + } + // restore data layout information to the module. + M.setDataLayout(DL); + return false; +} + +void EmitRaisedOutputPass::getAnalysisUsage(AnalysisUsage &AU) const { + AU.setPreservesAll(); +} Index: tools/llvm-mctoll/ExternalFunctions.h =================================================================== --- /dev/null +++ tools/llvm-mctoll/ExternalFunctions.h @@ -0,0 +1,40 @@ +//===-- ExternalFunctions.h - Binary raiser utility llvm-mctoll -------===// +// +// The LLVM Compiler Infrastructure +// +// This file is distributed under the University of Illinois Open Source +// License. See LICENSE.TXT for details. +// +//===----------------------------------------------------------------------===// +// +// This file contains the declaration of the ExternalFunction class +// and the table of known external functions. +// +//===----------------------------------------------------------------------===// + +#ifndef LLVM_TOOLS_LLVM_MCTOLL_EXTERNALFUNCTIONS_H +#define LLVM_TOOLS_LLVM_MCTOLL_EXTERNALFUNCTIONS_H + +#include "llvm/IR/Function.h" +#include "llvm/IR/Module.h" + +using namespace llvm; + +class ExternalFunctions { + ExternalFunctions(){}; + ~ExternalFunctions(){}; + + typedef struct { + StringRef ReturnType; + std::vector Arguments; + bool isVariadic; + } RetAndArgs; + +public: + static Function *Create(StringRef &, Module &); + static Type *getPrimitiveType(const StringRef &, LLVMContext &); + // Table of known glibc function prototypes + static const std::map + GlibcFunctions; +}; +#endif // LLVM_TOOLS_LLVM_MCTOLL_EXTERNALFUNCTIONS_H Index: tools/llvm-mctoll/ExternalFunctions.cpp =================================================================== --- /dev/null +++ tools/llvm-mctoll/ExternalFunctions.cpp @@ -0,0 +1,89 @@ +//===-- ExternalFunctions.h - Binary raiser utility llvm-mctoll -------===// +// +// The LLVM Compiler Infrastructure +// +// This file is distributed under the University of Illinois Open Source +// License. See LICENSE.TXT for details. +// +//===----------------------------------------------------------------------===// +// +// This file contains the implementation of the ExternalFunction class +// and the table of known external functions. +// +//===----------------------------------------------------------------------===// + +#include "ExternalFunctions.h" + +const std::map + ExternalFunctions::GlibcFunctions = { + {"printf", {"i32", {"i8*"}, true}}, + {"malloc", {"i8*", {"i64"}, false}}, + {"memcpy", {"i8*", {"i8*", "i8*", "i64"}, false}}, + {"strcpy", {"i8*", {"i8*", "i8*"}, false}}, + {"__isoc99_scanf", {"i32", {"i8*"}, true}}, + {"time", {"i64", {"i64*"}, false}}}; + +// Given the primitive type's string representation, return the Type* +// corresponding to it. +Type *ExternalFunctions::getPrimitiveType(const StringRef &TypeStr, + LLVMContext &llvmCtx) { + Type *retType = nullptr; + if (TypeStr.equals("void")) { + retType = Type::getVoidTy(llvmCtx); + } else if (TypeStr.equals("i8")) { + retType = Type::getInt8Ty(llvmCtx); + } else if (TypeStr.equals("i16")) { + retType = Type::getInt16Ty(llvmCtx); + } else if (TypeStr.equals("i32")) { + retType = Type::getInt32Ty(llvmCtx); + } else if (TypeStr.equals("i64")) { + retType = Type::getInt64Ty(llvmCtx); + } else if (TypeStr.equals("i8*")) { + retType = Type::getInt8PtrTy(llvmCtx); + } else if (TypeStr.equals("i16*")) { + retType = Type::getInt16PtrTy(llvmCtx); + } else if (TypeStr.equals("i32*")) { + retType = Type::getInt32PtrTy(llvmCtx); + } else if (TypeStr.equals("i64*")) { + retType = Type::getInt64PtrTy(llvmCtx); + } + assert((retType != nullptr) && + "Unsupported primitive type specified in known function prototype"); + return retType; +} + +// Construct and return a Function* corresponding to a known glibc function. +Function *ExternalFunctions::Create(StringRef &CFuncName, Module &module) { + Function *Func = nullptr; + llvm::LLVMContext &llvmContext(module.getContext()); + FunctionType *FuncType = nullptr; + auto iter = ExternalFunctions::GlibcFunctions.find(CFuncName); + if (iter == ExternalFunctions::GlibcFunctions.end()) { + errs() << CFuncName.data() << "\n"; + assert(false && "Unspported undefined function"); + } + Func = module.getFunction(CFuncName); + if (Func == nullptr) { + const ExternalFunctions::RetAndArgs &retAndArgs = iter->second; + Type *RetType = + ExternalFunctions::getPrimitiveType(retAndArgs.ReturnType, llvmContext); + std::vector ArgVec; + for (StringRef arg : retAndArgs.Arguments) { + Type *argType = ExternalFunctions::getPrimitiveType(arg, llvmContext); + ArgVec.push_back(argType); + } + ArrayRef Args(ArgVec); + FuncType = FunctionType::get(RetType, Args, retAndArgs.isVariadic); + if (FuncType == nullptr) { + errs() << CFuncName.data() << "\n"; + assert(false && + "Failed to construct function type for external function"); + } + Constant *FC = module.getOrInsertFunction(CFuncName, FuncType); + assert(isa(FC) && "Expect Function"); + + Func = reinterpret_cast(FC); + } + + return Func; +} Index: tools/llvm-mctoll/LICENSE.TXT =================================================================== --- /dev/null +++ tools/llvm-mctoll/LICENSE.TXT @@ -0,0 +1,68 @@ +============================================================================== +LLVM Release License +============================================================================== +University of Illinois/NCSA +Open Source License + +Copyright (c) 2003-2017 University of Illinois at Urbana-Champaign. +All rights reserved. + +Developed by: + + LLVM Team + + University of Illinois at Urbana-Champaign + + http://llvm.org + +Permission is hereby granted, free of charge, to any person obtaining a copy of +this software and associated documentation files (the "Software"), to deal with +the Software without restriction, including without limitation the rights to +use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies +of the Software, and to permit persons to whom the Software is furnished to do +so, subject to the following conditions: + + * Redistributions of source code must retain the above copyright notice, + this list of conditions and the following disclaimers. + + * Redistributions in binary form must reproduce the above copyright notice, + this list of conditions and the following disclaimers in the + documentation and/or other materials provided with the distribution. + + * Neither the names of the LLVM Team, University of Illinois at + Urbana-Champaign, nor the names of its contributors may be used to + endorse or promote products derived from this Software without specific + prior written permission. + +THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR +IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS +FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE +CONTRIBUTORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER +LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, +OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS WITH THE +SOFTWARE. + +============================================================================== +Copyrights and Licenses for Third Party Software Distributed with LLVM: +============================================================================== +The LLVM software contains code written by third parties. Such software will +have its own individual LICENSE.TXT file in the directory in which it appears. +This file will describe the copyrights, license, and restrictions which apply +to that code. + +The disclaimer of warranty in the University of Illinois Open Source License +applies to all code in the LLVM Distribution, and nothing in any of the +other licenses gives permission to use the names of the LLVM Team or the +University of Illinois to endorse or promote products derived from this +Software. + +The following pieces of software have additional or alternate copyrights, +licenses, and/or restrictions: + +Program Directory +------- --------- +Google Test llvm/utils/unittest/googletest +OpenBSD regex llvm/lib/Support/{reg*, COPYRIGHT.regex} +pyyaml tests llvm/test/YAMLParser/{*.data, LICENSE.TXT} +ARM contributions llvm/lib/Target/ARM/LICENSE.TXT +md5 contributions llvm/lib/Support/MD5.cpp llvm/include/llvm/Support/MD5.h Index: tools/llvm-mctoll/LLVMBuild.txt =================================================================== --- /dev/null +++ tools/llvm-mctoll/LLVMBuild.txt @@ -0,0 +1,22 @@ +;===- ./tools/llvm-mctoll/LLVMBuild.txt -----------------------*- Conf -*--===; +; +; The LLVM Compiler Infrastructure +; +; This file is distributed under the University of Illinois Open Source +; License. See LICENSE.TXT for details. +; +;===------------------------------------------------------------------------===; +; +; This is an LLVMBuild description file for the components in this subdirectory. +; +; For more information on the LLVMBuild system, please see: +; +; http://llvm.org/docs/LLVMBuild.html +; +;===------------------------------------------------------------------------===; + +[component_0] +type = Tool +name = llvm-mctoll +parent = Tools +required_libraries = DebugInfoDWARF DebugInfoPDB Symbolize Index: tools/llvm-mctoll/LLVMVersion.txt =================================================================== --- /dev/null +++ tools/llvm-mctoll/LLVMVersion.txt @@ -0,0 +1,34 @@ +NOTE: This information is expected to be updated each time an updated + LLVM/Clang tree is used to build llvm-mctoll. + +Following is the tip of the git trees used for successful build of llvm-mctoll. + +llvm: + +commit f8fba9029f6973515711af39198fab1c940d927e +Author: Anastasis Grammenos +Date: Fri Aug 3 20:27:13 2018 +0000 + + [TRE][DebugInfo] Preserve Debug Location in new branch instruction + + There are two branch instructions created + so the new test covers them both. + + Differential Revision: https://reviews.llvm.org/D50263 + + git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@338917 91177308-0d34-0410-b5e6-96231b3b80d8 + + +tools/clang: + +commit 18481d833dc0b2f992b8b99e2a9d5347721bfd68 +Author: Reka Kovacs +Date: Fri Aug 3 20:42:02 2018 +0000 + + [analyzer] Add test for a crash fixed in r338775. + + Do not crash if a CXXRecordDecl cannot be obtained for an object. + + Special thanks for the reproduction to Alexander Kornienko. + + git-svn-id: https://llvm.org/svn/llvm-project/cfe/trunk@338918 91177308-0d34-0410-b5e6-96231b3b80d8 Index: tools/llvm-mctoll/MCInstOrData.h =================================================================== --- /dev/null +++ tools/llvm-mctoll/MCInstOrData.h @@ -0,0 +1,46 @@ +//===---- MCInstOrData.h - Binary raiser utility llvm-mctoll --------------===// +// +// The LLVM Compiler Infrastructure +// +// This file is distributed under the University of Illinois Open Source +// License. See LICENSE.TXT for details. +// +//===----------------------------------------------------------------------===// +// +// This file contains the declaration of MCInstOrData class for use by +// llvm-mctoll. +// +//===----------------------------------------------------------------------===// + +#ifndef LLVM_TOOLS_LLVM_MCTOLL_MCINSTORDATA_H +#define LLVM_TOOLS_LLVM_MCTOLL_MCINSTORDATA_H + +#include "llvm/MC/MCInst.h" + +using namespace llvm; + +class MCInstOrData { +private: + enum class Tag { DATA, INSTRUCTION }; + + union { + uint32_t d; + MCInst i; + }; + + Tag type; + +public: + ~MCInstOrData(); + MCInstOrData &operator=(const MCInstOrData &); + MCInstOrData(const MCInstOrData &); + MCInstOrData(const MCInst &); + MCInstOrData(const uint32_t); + MCInst get_mcInst() const; + uint32_t get_data() const; + bool is_data() const { return (type == Tag::DATA); } + bool is_mcInst() const { return (type == Tag::INSTRUCTION); } + void dump() const; +}; + +#endif // LLVM_TOOLS_LLVM_MCTOLL_MCINSTRAISER_H Index: tools/llvm-mctoll/MCInstOrData.cpp =================================================================== --- /dev/null +++ tools/llvm-mctoll/MCInstOrData.cpp @@ -0,0 +1,84 @@ +//===-- MCInstOrData.cpp - Binary raiser utility llvm-mctoll --------------===// +// +// The LLVM Compiler Infrastructure +// +// This file is distributed under the University of Illinois Open Source +// License. See LICENSE.TXT for details. +// +//===----------------------------------------------------------------------===// +// +// This file contains the implementation of MCInstrOrData class for use by +// llvm-mctoll. +// +//===----------------------------------------------------------------------===// + +#include "MCInstOrData.h" +#include "llvm/Support/Format.h" +#include "llvm/Support/raw_ostream.h" + +MCInstOrData::MCInstOrData(const MCInstOrData &v) { + type = v.type; + + switch (v.type) { + case Tag::DATA: + d = v.d; + break; + case Tag::INSTRUCTION: + new (&i) MCInst(v.i); + } +} + +MCInstOrData::MCInstOrData(const MCInst &v) { + type = Tag::INSTRUCTION; + new (&i) MCInst(v); // placement new: explicitly construct MCInst +} + +MCInstOrData::MCInstOrData(const uint32_t v) { + type = Tag::DATA; + d = v; +} + +uint32_t MCInstOrData::get_data() const { + assert(type == Tag::DATA); + return d; +} + +MCInst MCInstOrData::get_mcInst() const { + assert(type == Tag::INSTRUCTION); + return i; +} + +// This is needed because of user-defined variant MCInst being part of MCInst +MCInstOrData &MCInstOrData::operator=(const MCInstOrData &e) { + if (type == Tag::INSTRUCTION && e.type == Tag::INSTRUCTION) { + i = e.i; // Usual MCInst assignment + return *this; + } + if (type == Tag::INSTRUCTION) + i.~MCInst(); // Explicit destroy + + switch (e.type) { + case Tag::DATA: + d = e.d; + break; + case Tag::INSTRUCTION: + new (&i) MCInst(e.i); + type = e.type; + } + return *this; +} + +void MCInstOrData::dump() const { + switch (type) { + case Tag::DATA: + outs() << "0x" << format("%04" PRIx16, d) << "\n"; + break; + case Tag::INSTRUCTION: + i.dump(); + break; + } +} +MCInstOrData::~MCInstOrData() { + if (type == Tag::INSTRUCTION) + i.~MCInst(); // explicit destroy +} Index: tools/llvm-mctoll/MCInstRaiser.h =================================================================== --- /dev/null +++ tools/llvm-mctoll/MCInstRaiser.h @@ -0,0 +1,146 @@ +//===---- MCInstRaiser.h - Binary raiser utility llvm-mctoll --------------===// +// +// The LLVM Compiler Infrastructure +// +// This file is distributed under the University of Illinois Open Source +// License. See LICENSE.TXT for details. +// +//===----------------------------------------------------------------------===// +// +// This file contains the declaration of MCInstRaiser class for use by +// llvm-mctoll. +// +//===----------------------------------------------------------------------===// + +#ifndef LLVM_TOOLS_LLVM_MCTOLL_MCINSTRAISER_H +#define LLVM_TOOLS_LLVM_MCTOLL_MCINSTRAISER_H + +#include "MCInstOrData.h" +#include "llvm/CodeGen/MachineFunction.h" +#include "llvm/MC/MCInstrAnalysis.h" +#include +#include +#include +#include + +using namespace llvm; + +// Class that encapsulates raising for MCInst vector to MachineInstrs +class MCInstRaiser { +public: + using const_mcinst_iter = std::map::const_iterator; + + MCInstRaiser(uint64_t fStart, uint64_t fEnd) + : FuncStart(fStart), FuncEnd(fEnd), dataInCode(false){}; + void addTarget(uint64_t targetIndex) { + // Add targetIndex only if it falls within the function start and end + // assert((targetIndex >= FuncStart) && (targetIndex <= FuncEnd) && + // "Failed to add target that is outside the function range"); + if (!((targetIndex >= FuncStart) && (targetIndex <= FuncEnd))) { + errs() << "*** WARNING Out of range target not added.\n"; + return; + } + targetIndices.insert(targetIndex); + } + void addMCInstOrData(uint64_t index, MCInstOrData mcInst); + + void buildCFG(MachineFunction &MF, const MCInstrAnalysis *mia, + const MCInstrInfo *mii); + + std::set getTargetIndices() const { return targetIndices; } + uint64_t getFuncStart() const { return FuncStart; } + uint64_t getFuncEnd() const { return FuncEnd; } + // Change the value of function end to a new value greater than current value + bool adjustFuncEnd(uint64_t n); + // Is Index in range of this function? + bool isMCInstInRange(uint64_t Index) { + return ((Index >= FuncStart) && (Index <= FuncEnd)); + } + // Dump routine + void dump() const; + // Data in Code + void setDataInCode(bool v) { dataInCode = v; } + bool hasDataInCode() { return dataInCode; } + + // Get the MBB number that corresponds to MCInst at Offset. + // MBB has the raised MachineInstr corresponding to MCInst at + // Offset is the first instruction + uint64_t getMBBNumberOfMCInstOffset(uint64_t Offset) const { + auto iter = mcInstToMBBNum.find(Offset); + assert(iter != mcInstToMBBNum.end() && "Non-existent MCInst offset"); + return (*iter).second; + } + + // Returns the iterator pointing to MCInstOrData at Offset in + // input instruction stream. + const_mcinst_iter getMCInstAt(uint64_t Offset) const { + return mcInstMap.find(Offset); + } + + const_mcinst_iter const_mcinstr_end() const { return mcInstMap.end(); } + // Get the size of instruction + uint64_t getMCInstSize(uint64_t Offset) const { + const_mcinst_iter iter = mcInstMap.find(Offset); + const_mcinst_iter end = mcInstMap.end(); + uint64_t InstSize = 0; + assert(iter != end && "Attempt to find MCInst at non-existent offset"); + if (iter.operator++() != end) { + uint64_t NextOffset = (*iter).first; + InstSize = NextOffset - Offset; + } else { + // The instruction at Offset is the last instriuction in the input stream + assert(Offset < FuncEnd && + "Attempt to find MCInst at offset beyond function end"); + InstSize = FuncEnd - Offset; + } + return InstSize; + } + + uint64_t getMCInstIndex(const MachineInstr &MI) { + unsigned NumExpOps = MI.getNumExplicitOperands(); + const MachineOperand &MO = MI.getOperand(NumExpOps); + assert(MO.isMetadata() && + "Unexpected non-metadata operand in branch instruction"); + const MDNode *MDN = MO.getMetadata(); + // Unwrap metadata of the instruction to get the MCInstIndex of + // the MCInst corresponding to this MachineInstr. + ConstantAsMetadata *CAM = dyn_cast(MDN->getOperand(0)); + assert(CAM != nullptr && "Unexpected metadata type"); + Constant *CV = CAM->getValue(); + ConstantInt *CI = dyn_cast(CV); + assert(CI != nullptr && "Unexpected metadata constant type"); + APInt ArbPrecInt = CI->getValue(); + return ArbPrecInt.getSExtValue(); + } + +private: + // NOTE: The following data structures are implemented to record instruction + // targets. Separate data structures are used instead of aggregating the + // target information to minimize the amount of memory allocated + // per instruction - given the ratio of control flow instructions is + // not high, in general. However it is important to populate the target + // information during binary parse time AND is not duplicated. + // A sequential list of source MCInsts or 32-bit data with corresponding index + // Iteration over std::map contents is in non-descending order of keys. So, + // the order in the map is guaranteed to be the order of instructions in the + // insertion order i.e., code stream order. + std::map mcInstMap; + // All targets recorded in a set to avoid duplicate entries + std::set targetIndices; + // A map of MCInst index, mci, to MachineBasicBlock number, mbbnum. The first + // instruction of MachineBasicBlock number mbbnum is the MachineInstr + // representation of the MCinst at the index, mci + std::map mcInstToMBBNum; + + std::map> MBBNumToMCInstTargetsMap; + MachineInstr *RaiseMCInst(const MCInstrInfo &, MachineFunction &, MCInst, + uint64_t); + // Start and End offsets of the array of MCInsts in mcInstVector; + uint64_t FuncStart; + uint64_t FuncEnd; + // Flag to indicate that the mcInstVector includes data (or uint32_ sized + // quantities that the disassembler was unable to recognize as instrictions + // and are considered data + bool dataInCode; +}; +#endif // LLVM_TOOLS_LLVM_MCTOLL_MCINSTRAISER_H Index: tools/llvm-mctoll/MCInstRaiser.cpp =================================================================== --- /dev/null +++ tools/llvm-mctoll/MCInstRaiser.cpp @@ -0,0 +1,244 @@ +//===-- MCInstRaiser.cpp - Binary raiser utility llvm-mctoll --------------===// +// +// The LLVM Compiler Infrastructure +// +// This file is distributed under the University of Illinois Open Source +// License. See LICENSE.TXT for details. +// +//===----------------------------------------------------------------------===// +// +// This file contains the implementation of MCInstrRaiser class for use by +// llvm-mctoll. +// +//===----------------------------------------------------------------------===// +#include "MCInstRaiser.h" +#include "llvm/CodeGen/MachineInstrBuilder.h" +#include "llvm/Support/raw_ostream.h" + +void MCInstRaiser::buildCFG(MachineFunction &MF, const MCInstrAnalysis *MIA, + const MCInstrInfo *MII) { + bool PrintAll = + (cl::getRegisteredOptions()["print-after-all"]->getNumOccurrences() > 0); + + if (PrintAll) { + outs() << "Running buildCFG\n"; + } + + // Set the first instruction index as the entry of current MBB + // Walk the mcInstMap + // a) if the current instruction is a target instruction + // record the (entry, current MBB) pair + // create a new MBB + // set current instruction index as entry of current MBB + // b) add raised MachineInstr to current MBB. + auto targetIndicesEnd = targetIndices.end(); + uint64_t curMBBEntryInstIndex; + + for (auto mcInstorDataIter = mcInstMap.begin(); + mcInstorDataIter != mcInstMap.end(); mcInstorDataIter++) { + uint64_t mcInstIndex = mcInstorDataIter->first; + MCInstOrData mcInstorData = mcInstorDataIter->second; + // If the current mcInst is a target of some instruction, + // i) record the target of previous instruction and fall-through as + // needed. + // ii) start a new MachineBasicBlock + if (targetIndices.find(mcInstIndex) != targetIndicesEnd) { + // Create a map of curMBBEntryInstIndex to the current + // MachineBasicBlock for use later to create control flow edges + // - except when creating the first MBB. + if (MF.size()) { + // Find the target MCInst indices of the previous MCInst + uint64_t prevMCInstIndex = std::prev(mcInstorDataIter)->first; + MCInstOrData prevTextSecBytes = std::prev(mcInstorDataIter)->second; + std::vector prevMCInstTargets; + + // If handling a mcInst + if (mcInstorData.is_mcInst()) { + MCInst mcInst = mcInstorData.get_mcInst(); + // If this instruction is preceeded by mcInst + if (prevTextSecBytes.is_mcInst()) { + MCInst prevMCInst = prevTextSecBytes.get_mcInst(); + // If previous MCInst is a branch + if (MIA->isBranch(prevMCInst)) { + uint64_t Target; + // Get its target + if (MIA->evaluateBranch(prevMCInst, prevMCInstIndex, + (mcInstIndex - prevMCInstIndex), + Target)) { + // Record its target if it is within the function start + // and function end. Branch instructions with such + // targets are - for now - treated not to be instructions + // but most likely data bytes embedded in instruction stream. + // TODO: How to handle any branches out of these bounds? + // Does such a situation exist? + if ((Target >= FuncStart) && (Target <= FuncEnd)) { + prevMCInstTargets.push_back(Target); + // If previous instruction is a conditional branch, the + // next instruction is also a target + if (MIA->isConditionalBranch(prevMCInst)) { + if ((mcInstIndex >= FuncStart) && + (mcInstIndex <= FuncEnd)) { + prevMCInstTargets.push_back(mcInstIndex); + } + } + } + } + } + // Previous MCInst is not a branch. So, current instruction is a + // target + else { + if ((mcInstIndex >= FuncStart) && (mcInstIndex <= FuncEnd)) { + prevMCInstTargets.push_back(mcInstIndex); + } + } + // Add to MBB -> targets map + MBBNumToMCInstTargetsMap.insert( + std::make_pair(MF.back().getNumber(), prevMCInstTargets)); + mcInstToMBBNum.insert( + std::make_pair(curMBBEntryInstIndex, MF.back().getNumber())); + } else { + // This is preceded by data. Note that this mcInst is a target. + // So need to start a new basic block + // Add to MBB -> targets map + MBBNumToMCInstTargetsMap.insert( + std::make_pair(MF.back().getNumber(), prevMCInstTargets)); + mcInstToMBBNum.insert( + std::make_pair(curMBBEntryInstIndex, MF.back().getNumber())); + } + } + } + // Add the new MBB to MachineFunction + if (mcInstorData.is_mcInst()) { + MF.push_back(MF.CreateMachineBasicBlock()); + curMBBEntryInstIndex = mcInstIndex; + } + } + if (mcInstorData.is_mcInst()) { + // add raised MachineInstr to current MBB. + MF.back().push_back( + RaiseMCInst(*MII, MF, mcInstorData.get_mcInst(), mcInstIndex)); + } + } + + // Add the entry intruction -> MBB map entry for the last MBB + if (MF.size()) { + MBBNumToMCInstTargetsMap.insert( + std::make_pair(MF.back().getNumber(), std::vector())); + mcInstToMBBNum.insert( + std::make_pair(curMBBEntryInstIndex, MF.back().getNumber())); + } + + // Walk all MachineBasicBlocks in MF to add control flow edges + unsigned mbbCount = MF.getNumBlockIDs(); + for (unsigned mbbIndex = 0; mbbIndex < mbbCount; mbbIndex++) { + // Get the MBB + MachineBasicBlock *currentMBB = MF.getBlockNumbered(mbbIndex); + std::map>::iterator iter = + MBBNumToMCInstTargetsMap.find(mbbIndex); + assert(iter != MBBNumToMCInstTargetsMap.end()); + std::vector targetMCInstIndices = iter->second; + for (auto mbbMCInstTgt : targetMCInstIndices) { + std::map::iterator tgtIter = + mcInstToMBBNum.find(mbbMCInstTgt); + // If the target is not found, it could be outside the function + // being constructed. + // TODO: Need to keep track of all such targets and link them in + // a later global pass over all MachineFunctions of the module. + if (tgtIter == mcInstToMBBNum.end()) { + outs() << "**** Warning : Index "; + outs().write_hex(mbbMCInstTgt); + outs() << " not found\n"; + // assert(0); + } else { + MachineBasicBlock *succ = MF.getBlockNumbered(tgtIter->second); + currentMBB->addSuccessorWithoutProb(succ); + } + } + } + // Print the Machine function (which contains the reconstructed + // MachineBasicBlocks. + if (PrintAll) { + MF.dump(); + } +} + +MachineInstr *MCInstRaiser::RaiseMCInst(const MCInstrInfo &mcInstrInfo, + MachineFunction &machineFunction, + MCInst mcInst, uint64_t mcInstIndex) { + // Construct MachineInstr that is the raised abstraction of MCInstr + const MCInstrDesc &mcInstrDesc = mcInstrInfo.get(mcInst.getOpcode()); + DebugLoc *debugLoc = new DebugLoc(); + MachineInstrBuilder builder = + BuildMI(machineFunction, *debugLoc, mcInstrDesc); + + const unsigned int defCount = mcInstrDesc.getNumDefs(); + // Get the number of declared MachineOperands for this + // MachineInstruction and add them to the MachineInstr being + // constructed. Any implicitDefs or implicitDefs would already have + // been added while MachineInstr is created during the construction + // of builder object above. + const unsigned int numOperands = mcInstrDesc.getNumOperands(); + for (unsigned int indx = 0; indx < numOperands; indx++) { + // Raise operand + MCOperand mcOperand = mcInst.getOperand(indx); + if (mcOperand.isImm()) { + builder.addImm(mcOperand.getImm()); + } else if (mcOperand.isReg()) { + // The first defCount operands are defines (i.e., out operands). + if (indx < defCount) { + builder.addDef(mcOperand.getReg()); + } else { + builder.addUse(mcOperand.getReg()); + } + } else { + outs() << "**** Unhandled Operand : "; + mcOperand.dump(); + } + } + LLVMContext &C = machineFunction.getFunction().getContext(); + // Creation of MDNode representing Metadata with mcInstIndex may be done using + // the following couple of lines of code. But I just wanted to spell it out + // for better understanding. + + // MDNode* temp_N = MDNode::get(C, ConstantAsMetadata::get(ConstantInt::get(C, + // llvm::APInt(64, + // mcInstIndex, + // false)))); + // MDNode* N = MDNode::get(C, temp_N); + + // Create arbitrary precision + // integer + llvm::APInt ArbPrecInt(64, mcInstIndex, false); + // Create ConstantAsMetadata + ConstantAsMetadata *CMD = + ConstantAsMetadata::get(ConstantInt::get(C, ArbPrecInt)); + // MDNode* temp_N = MDNode::get(C, CMD); + MDNode *N = MDNode::get(C, CMD); + builder.addMetadata(N); + return builder.getInstr(); +} + +void MCInstRaiser::dump() const { + for (auto in : mcInstMap) { + outs() << in.first << " : "; + in.second.dump(); + } +} + +bool MCInstRaiser::adjustFuncEnd(uint64_t n) { + // NOTE: At present it appears that we only need it to increase the function + // end index. + if (FuncEnd > n) { + return false; + } + FuncEnd = n; + return true; +} + +void MCInstRaiser::addMCInstOrData(uint64_t index, MCInstOrData mcInst) { + // Set dataInCode flag as appropriate + if (mcInst.is_data() && !dataInCode) { + dataInCode = true; + } + mcInstMap.insert(std::make_pair(index, mcInst)); +} Index: tools/llvm-mctoll/MachODump.cpp =================================================================== --- /dev/null +++ tools/llvm-mctoll/MachODump.cpp @@ -0,0 +1,9596 @@ +//===-- MachODump.cpp - Object file dumping utility for llvm --------------===// +// +// The LLVM Compiler Infrastructure +// +// This file is distributed under the University of Illinois Open Source +// License. See LICENSE.TXT for details. +// +//===----------------------------------------------------------------------===// +// +// This file implements the MachO-specific dumper for llvm-mctoll. +// +//===----------------------------------------------------------------------===// + +#include "llvm-mctoll.h" +#include "llvm-c/Disassembler.h" +#include "llvm/ADT/STLExtras.h" +#include "llvm/ADT/StringExtras.h" +#include "llvm/ADT/Triple.h" +#include "llvm/BinaryFormat/MachO.h" +#include "llvm/Config/config.h" +#include "llvm/DebugInfo/DIContext.h" +#include "llvm/DebugInfo/DWARF/DWARFContext.h" +#include "llvm/Demangle/Demangle.h" +#include "llvm/MC/MCAsmInfo.h" +#include "llvm/MC/MCContext.h" +#include "llvm/MC/MCDisassembler/MCDisassembler.h" +#include "llvm/MC/MCInst.h" +#include "llvm/MC/MCInstPrinter.h" +#include "llvm/MC/MCInstrDesc.h" +#include "llvm/MC/MCInstrInfo.h" +#include "llvm/MC/MCRegisterInfo.h" +#include "llvm/MC/MCSubtargetInfo.h" +#include "llvm/Object/MachO.h" +#include "llvm/Object/MachOUniversal.h" +#include "llvm/Support/Casting.h" +#include "llvm/Support/CommandLine.h" +#include "llvm/Support/Debug.h" +#include "llvm/Support/Endian.h" +#include "llvm/Support/Format.h" +#include "llvm/Support/FormattedStream.h" +#include "llvm/Support/GraphWriter.h" +#include "llvm/Support/LEB128.h" +#include "llvm/Support/MemoryBuffer.h" +#include "llvm/Support/TargetRegistry.h" +#include "llvm/Support/TargetSelect.h" +#include "llvm/Support/ToolOutputFile.h" +#include "llvm/Support/raw_ostream.h" +#include +#include +#include + +#ifdef HAVE_LIBXAR +extern "C" { +#include +} +#endif + +using namespace llvm; +using namespace object; + +extern cl::opt MCPU; +extern cl::list MAttrs; + +static cl::opt + UseDbg("g", + cl::desc("Print line information from debug info if available")); + +static cl::opt DSYMFile("dsym", + cl::desc("Use .dSYM file for debug info")); + +static cl::opt FullLeadingAddr("full-leading-addr", + cl::desc("Print full leading address")); + +static cl::opt NoLeadingHeaders("no-leading-headers", + cl::desc("Print no leading headers")); +cl::opt llvm::UniversalHeaders("universal-headers", + cl::desc("Print Mach-O universal headers " + "(requires -macho)")); + +cl::opt + llvm::ArchiveHeaders("archive-headers", + cl::desc("Print archive headers for Mach-O archives " + "(requires -macho)")); + +cl::opt + ArchiveMemberOffsets("archive-member-offsets", + cl::desc("Print the offset to each archive member for " + "Mach-O archives (requires -macho and " + "-archive-headers)")); + +cl::opt + llvm::IndirectSymbols("indirect-symbols", + cl::desc("Print indirect symbol table for Mach-O " + "objects (requires -macho)")); + +cl::opt + llvm::DataInCode("data-in-code", + cl::desc("Print the data in code table for Mach-O objects " + "(requires -macho)")); + +cl::opt + llvm::LinkOptHints("link-opt-hints", + cl::desc("Print the linker optimization hints for " + "Mach-O objects (requires -macho)")); + +cl::opt + llvm::InfoPlist("info-plist", + cl::desc("Print the info plist section as strings for " + "Mach-O objects (requires -macho)")); + +cl::opt + llvm::DylibsUsed("dylibs-used", + cl::desc("Print the shared libraries used for linked " + "Mach-O files (requires -macho)")); + +cl::opt + llvm::DylibId("dylib-id", + cl::desc("Print the shared library's id for the dylib Mach-O " + "file (requires -macho)")); + +cl::opt + llvm::NonVerbose("non-verbose", + cl::desc("Print the info for Mach-O objects in " + "non-verbose or numeric form (requires -macho)")); + +cl::opt + llvm::ObjcMetaData("objc-meta-data", + cl::desc("Print the Objective-C runtime meta data for " + "Mach-O files (requires -macho)")); + +cl::opt llvm::DisSymName( + "dis-symname", + cl::desc("disassemble just this symbol's instructions (requires -macho)")); + +static cl::opt NoSymbolicOperands( + "no-symbolic-operands", + cl::desc("do not symbolic operands when disassembling (requires -macho)")); + +static cl::list + ArchFlags("arch", cl::desc("architecture(s) from a Mach-O file to dump"), + cl::ZeroOrMore); + +bool ArchAll = false; + +static std::string ThumbTripleName; + +static const Target *GetTarget(const MachOObjectFile *MachOObj, + const char **McpuDefault, + const Target **ThumbTarget) { + // Figure out the target triple. + llvm::Triple TT(TripleName); + if (TripleName.empty()) { + TT = MachOObj->getArchTriple(McpuDefault); + TripleName = TT.str(); + } + + if (TT.getArch() == Triple::arm) { + // We've inferred a 32-bit ARM target from the object file. All MachO CPUs + // that support ARM are also capable of Thumb mode. + llvm::Triple ThumbTriple = TT; + std::string ThumbName = (Twine("thumb") + TT.getArchName().substr(3)).str(); + ThumbTriple.setArchName(ThumbName); + ThumbTripleName = ThumbTriple.str(); + } + + // Get the target specific parser. + std::string Error; + const Target *TheTarget = TargetRegistry::lookupTarget(TripleName, Error); + if (TheTarget && ThumbTripleName.empty()) + return TheTarget; + + *ThumbTarget = TargetRegistry::lookupTarget(ThumbTripleName, Error); + if (*ThumbTarget) + return TheTarget; + + errs() << "llvm-mctoll: error: unable to get target for '"; + if (!TheTarget) + errs() << TripleName; + else + errs() << ThumbTripleName; + errs() << "', see --version and --triple.\n"; + return nullptr; +} + +struct SymbolSorter { + bool operator()(const SymbolRef &A, const SymbolRef &B) { + Expected ATypeOrErr = A.getType(); + if (!ATypeOrErr) + report_error(A.getObject()->getFileName(), ATypeOrErr.takeError()); + SymbolRef::Type AType = *ATypeOrErr; + Expected BTypeOrErr = B.getType(); + if (!BTypeOrErr) + report_error(B.getObject()->getFileName(), BTypeOrErr.takeError()); + SymbolRef::Type BType = *BTypeOrErr; + uint64_t AAddr = (AType != SymbolRef::ST_Function) ? 0 : A.getValue(); + uint64_t BAddr = (BType != SymbolRef::ST_Function) ? 0 : B.getValue(); + return AAddr < BAddr; + } +}; + +// Types for the storted data in code table that is built before disassembly +// and the predicate function to sort them. +typedef std::pair DiceTableEntry; +typedef std::vector DiceTable; +typedef DiceTable::iterator dice_table_iterator; + +// This is used to search for a data in code table entry for the PC being +// disassembled. The j parameter has the PC in j.first. A single data in code +// table entry can cover many bytes for each of its Kind's. So if the offset, +// aka the i.first value, of the data in code table entry plus its Length +// covers the PC being searched for this will return true. If not it will +// return false. +static bool compareDiceTableEntries(const DiceTableEntry &i, + const DiceTableEntry &j) { + uint16_t Length; + i.second.getLength(Length); + + return j.first >= i.first && j.first < i.first + Length; +} + +static uint64_t DumpDataInCode(const uint8_t *bytes, uint64_t Length, + unsigned short Kind) { + uint32_t Value, Size = 1; + + switch (Kind) { + default: + case MachO::DICE_KIND_DATA: + if (Length >= 4) { + if (!NoShowRawInsn) + dumpBytes(makeArrayRef(bytes, 4), outs()); + Value = bytes[3] << 24 | bytes[2] << 16 | bytes[1] << 8 | bytes[0]; + outs() << "\t.long " << Value; + Size = 4; + } else if (Length >= 2) { + if (!NoShowRawInsn) + dumpBytes(makeArrayRef(bytes, 2), outs()); + Value = bytes[1] << 8 | bytes[0]; + outs() << "\t.short " << Value; + Size = 2; + } else { + if (!NoShowRawInsn) + dumpBytes(makeArrayRef(bytes, 2), outs()); + Value = bytes[0]; + outs() << "\t.byte " << Value; + Size = 1; + } + if (Kind == MachO::DICE_KIND_DATA) + outs() << "\t@ KIND_DATA\n"; + else + outs() << "\t@ data in code kind = " << Kind << "\n"; + break; + case MachO::DICE_KIND_JUMP_TABLE8: + if (!NoShowRawInsn) + dumpBytes(makeArrayRef(bytes, 1), outs()); + Value = bytes[0]; + outs() << "\t.byte " << format("%3u", Value) << "\t@ KIND_JUMP_TABLE8\n"; + Size = 1; + break; + case MachO::DICE_KIND_JUMP_TABLE16: + if (!NoShowRawInsn) + dumpBytes(makeArrayRef(bytes, 2), outs()); + Value = bytes[1] << 8 | bytes[0]; + outs() << "\t.short " << format("%5u", Value & 0xffff) + << "\t@ KIND_JUMP_TABLE16\n"; + Size = 2; + break; + case MachO::DICE_KIND_JUMP_TABLE32: + case MachO::DICE_KIND_ABS_JUMP_TABLE32: + if (!NoShowRawInsn) + dumpBytes(makeArrayRef(bytes, 4), outs()); + Value = bytes[3] << 24 | bytes[2] << 16 | bytes[1] << 8 | bytes[0]; + outs() << "\t.long " << Value; + if (Kind == MachO::DICE_KIND_JUMP_TABLE32) + outs() << "\t@ KIND_JUMP_TABLE32\n"; + else + outs() << "\t@ KIND_ABS_JUMP_TABLE32\n"; + Size = 4; + break; + } + return Size; +} + +static void getSectionsAndSymbols(MachOObjectFile *MachOObj, + std::vector &Sections, + std::vector &Symbols, + SmallVectorImpl &FoundFns, + uint64_t &BaseSegmentAddress) { + for (const SymbolRef &Symbol : MachOObj->symbols()) { + Expected SymName = Symbol.getName(); + if (!SymName) + report_error(MachOObj->getFileName(), SymName.takeError()); + if (!SymName->startswith("ltmp")) + Symbols.push_back(Symbol); + } + + for (const SectionRef &Section : MachOObj->sections()) { + StringRef SectName; + Section.getName(SectName); + Sections.push_back(Section); + } + + bool BaseSegmentAddressSet = false; + for (const auto &Command : MachOObj->load_commands()) { + if (Command.C.cmd == MachO::LC_FUNCTION_STARTS) { + // We found a function starts segment, parse the addresses for later + // consumption. + MachO::linkedit_data_command LLC = + MachOObj->getLinkeditDataLoadCommand(Command); + + MachOObj->ReadULEB128s(LLC.dataoff, FoundFns); + } else if (Command.C.cmd == MachO::LC_SEGMENT) { + MachO::segment_command SLC = MachOObj->getSegmentLoadCommand(Command); + StringRef SegName = SLC.segname; + if (!BaseSegmentAddressSet && SegName != "__PAGEZERO") { + BaseSegmentAddressSet = true; + BaseSegmentAddress = SLC.vmaddr; + } + } + } +} + +static void PrintIndirectSymbolTable(MachOObjectFile *O, bool verbose, + uint32_t n, uint32_t count, + uint32_t stride, uint64_t addr) { + MachO::dysymtab_command Dysymtab = O->getDysymtabLoadCommand(); + uint32_t nindirectsyms = Dysymtab.nindirectsyms; + if (n > nindirectsyms) + outs() << " (entries start past the end of the indirect symbol " + "table) (reserved1 field greater than the table size)"; + else if (n + count > nindirectsyms) + outs() << " (entries extends past the end of the indirect symbol " + "table)"; + outs() << "\n"; + uint32_t cputype = O->getHeader().cputype; + if (cputype & MachO::CPU_ARCH_ABI64) + outs() << "address index"; + else + outs() << "address index"; + if (verbose) + outs() << " name\n"; + else + outs() << "\n"; + for (uint32_t j = 0; j < count && n + j < nindirectsyms; j++) { + if (cputype & MachO::CPU_ARCH_ABI64) + outs() << format("0x%016" PRIx64, addr + j * stride) << " "; + else + outs() << format("0x%08" PRIx32, (uint32_t)addr + j * stride) << " "; + MachO::dysymtab_command Dysymtab = O->getDysymtabLoadCommand(); + uint32_t indirect_symbol = O->getIndirectSymbolTableEntry(Dysymtab, n + j); + if (indirect_symbol == MachO::INDIRECT_SYMBOL_LOCAL) { + outs() << "LOCAL\n"; + continue; + } + if (indirect_symbol == + (MachO::INDIRECT_SYMBOL_LOCAL | MachO::INDIRECT_SYMBOL_ABS)) { + outs() << "LOCAL ABSOLUTE\n"; + continue; + } + if (indirect_symbol == MachO::INDIRECT_SYMBOL_ABS) { + outs() << "ABSOLUTE\n"; + continue; + } + outs() << format("%5u ", indirect_symbol); + if (verbose) { + MachO::symtab_command Symtab = O->getSymtabLoadCommand(); + if (indirect_symbol < Symtab.nsyms) { + symbol_iterator Sym = O->getSymbolByIndex(indirect_symbol); + SymbolRef Symbol = *Sym; + Expected SymName = Symbol.getName(); + if (!SymName) + report_error(O->getFileName(), SymName.takeError()); + outs() << *SymName; + } else { + outs() << "?"; + } + } + outs() << "\n"; + } +} + +static void PrintIndirectSymbols(MachOObjectFile *O, bool verbose) { + for (const auto &Load : O->load_commands()) { + if (Load.C.cmd == MachO::LC_SEGMENT_64) { + MachO::segment_command_64 Seg = O->getSegment64LoadCommand(Load); + for (unsigned J = 0; J < Seg.nsects; ++J) { + MachO::section_64 Sec = O->getSection64(Load, J); + uint32_t section_type = Sec.flags & MachO::SECTION_TYPE; + if (section_type == MachO::S_NON_LAZY_SYMBOL_POINTERS || + section_type == MachO::S_LAZY_SYMBOL_POINTERS || + section_type == MachO::S_LAZY_DYLIB_SYMBOL_POINTERS || + section_type == MachO::S_THREAD_LOCAL_VARIABLE_POINTERS || + section_type == MachO::S_SYMBOL_STUBS) { + uint32_t stride; + if (section_type == MachO::S_SYMBOL_STUBS) + stride = Sec.reserved2; + else + stride = 8; + if (stride == 0) { + outs() << "Can't print indirect symbols for (" << Sec.segname << "," + << Sec.sectname << ") " + << "(size of stubs in reserved2 field is zero)\n"; + continue; + } + uint32_t count = Sec.size / stride; + outs() << "Indirect symbols for (" << Sec.segname << "," + << Sec.sectname << ") " << count << " entries"; + uint32_t n = Sec.reserved1; + PrintIndirectSymbolTable(O, verbose, n, count, stride, Sec.addr); + } + } + } else if (Load.C.cmd == MachO::LC_SEGMENT) { + MachO::segment_command Seg = O->getSegmentLoadCommand(Load); + for (unsigned J = 0; J < Seg.nsects; ++J) { + MachO::section Sec = O->getSection(Load, J); + uint32_t section_type = Sec.flags & MachO::SECTION_TYPE; + if (section_type == MachO::S_NON_LAZY_SYMBOL_POINTERS || + section_type == MachO::S_LAZY_SYMBOL_POINTERS || + section_type == MachO::S_LAZY_DYLIB_SYMBOL_POINTERS || + section_type == MachO::S_THREAD_LOCAL_VARIABLE_POINTERS || + section_type == MachO::S_SYMBOL_STUBS) { + uint32_t stride; + if (section_type == MachO::S_SYMBOL_STUBS) + stride = Sec.reserved2; + else + stride = 4; + if (stride == 0) { + outs() << "Can't print indirect symbols for (" << Sec.segname << "," + << Sec.sectname << ") " + << "(size of stubs in reserved2 field is zero)\n"; + continue; + } + uint32_t count = Sec.size / stride; + outs() << "Indirect symbols for (" << Sec.segname << "," + << Sec.sectname << ") " << count << " entries"; + uint32_t n = Sec.reserved1; + PrintIndirectSymbolTable(O, verbose, n, count, stride, Sec.addr); + } + } + } + } +} + +static void PrintDataInCodeTable(MachOObjectFile *O, bool verbose) { + MachO::linkedit_data_command DIC = O->getDataInCodeLoadCommand(); + uint32_t nentries = DIC.datasize / sizeof(struct MachO::data_in_code_entry); + outs() << "Data in code table (" << nentries << " entries)\n"; + outs() << "offset length kind\n"; + for (dice_iterator DI = O->begin_dices(), DE = O->end_dices(); DI != DE; + ++DI) { + uint32_t Offset; + DI->getOffset(Offset); + outs() << format("0x%08" PRIx32, Offset) << " "; + uint16_t Length; + DI->getLength(Length); + outs() << format("%6u", Length) << " "; + uint16_t Kind; + DI->getKind(Kind); + if (verbose) { + switch (Kind) { + case MachO::DICE_KIND_DATA: + outs() << "DATA"; + break; + case MachO::DICE_KIND_JUMP_TABLE8: + outs() << "JUMP_TABLE8"; + break; + case MachO::DICE_KIND_JUMP_TABLE16: + outs() << "JUMP_TABLE16"; + break; + case MachO::DICE_KIND_JUMP_TABLE32: + outs() << "JUMP_TABLE32"; + break; + case MachO::DICE_KIND_ABS_JUMP_TABLE32: + outs() << "ABS_JUMP_TABLE32"; + break; + default: + outs() << format("0x%04" PRIx32, Kind); + break; + } + } else + outs() << format("0x%04" PRIx32, Kind); + outs() << "\n"; + } +} + +static void PrintLinkOptHints(MachOObjectFile *O) { + MachO::linkedit_data_command LohLC = O->getLinkOptHintsLoadCommand(); + const char *loh = O->getData().substr(LohLC.dataoff, 1).data(); + uint32_t nloh = LohLC.datasize; + outs() << "Linker optimiztion hints (" << nloh << " total bytes)\n"; + for (uint32_t i = 0; i < nloh;) { + unsigned n; + uint64_t identifier = decodeULEB128((const uint8_t *)(loh + i), &n); + i += n; + outs() << " identifier " << identifier << " "; + if (i >= nloh) + return; + switch (identifier) { + case 1: + outs() << "AdrpAdrp\n"; + break; + case 2: + outs() << "AdrpLdr\n"; + break; + case 3: + outs() << "AdrpAddLdr\n"; + break; + case 4: + outs() << "AdrpLdrGotLdr\n"; + break; + case 5: + outs() << "AdrpAddStr\n"; + break; + case 6: + outs() << "AdrpLdrGotStr\n"; + break; + case 7: + outs() << "AdrpAdd\n"; + break; + case 8: + outs() << "AdrpLdrGot\n"; + break; + default: + outs() << "Unknown identifier value\n"; + break; + } + uint64_t narguments = decodeULEB128((const uint8_t *)(loh + i), &n); + i += n; + outs() << " narguments " << narguments << "\n"; + if (i >= nloh) + return; + + for (uint32_t j = 0; j < narguments; j++) { + uint64_t value = decodeULEB128((const uint8_t *)(loh + i), &n); + i += n; + outs() << "\tvalue " << format("0x%" PRIx64, value) << "\n"; + if (i >= nloh) + return; + } + } +} + +static void PrintDylibs(MachOObjectFile *O, bool JustId) { + unsigned Index = 0; + for (const auto &Load : O->load_commands()) { + if ((JustId && Load.C.cmd == MachO::LC_ID_DYLIB) || + (!JustId && (Load.C.cmd == MachO::LC_ID_DYLIB || + Load.C.cmd == MachO::LC_LOAD_DYLIB || + Load.C.cmd == MachO::LC_LOAD_WEAK_DYLIB || + Load.C.cmd == MachO::LC_REEXPORT_DYLIB || + Load.C.cmd == MachO::LC_LAZY_LOAD_DYLIB || + Load.C.cmd == MachO::LC_LOAD_UPWARD_DYLIB))) { + MachO::dylib_command dl = O->getDylibIDLoadCommand(Load); + if (dl.dylib.name < dl.cmdsize) { + const char *p = (const char *)(Load.Ptr) + dl.dylib.name; + if (JustId) + outs() << p << "\n"; + else { + outs() << "\t" << p; + outs() << " (compatibility version " + << ((dl.dylib.compatibility_version >> 16) & 0xffff) << "." + << ((dl.dylib.compatibility_version >> 8) & 0xff) << "." + << (dl.dylib.compatibility_version & 0xff) << ","; + outs() << " current version " + << ((dl.dylib.current_version >> 16) & 0xffff) << "." + << ((dl.dylib.current_version >> 8) & 0xff) << "." + << (dl.dylib.current_version & 0xff) << ")\n"; + } + } else { + outs() << "\tBad offset (" << dl.dylib.name << ") for name of "; + if (Load.C.cmd == MachO::LC_ID_DYLIB) + outs() << "LC_ID_DYLIB "; + else if (Load.C.cmd == MachO::LC_LOAD_DYLIB) + outs() << "LC_LOAD_DYLIB "; + else if (Load.C.cmd == MachO::LC_LOAD_WEAK_DYLIB) + outs() << "LC_LOAD_WEAK_DYLIB "; + else if (Load.C.cmd == MachO::LC_LAZY_LOAD_DYLIB) + outs() << "LC_LAZY_LOAD_DYLIB "; + else if (Load.C.cmd == MachO::LC_REEXPORT_DYLIB) + outs() << "LC_REEXPORT_DYLIB "; + else if (Load.C.cmd == MachO::LC_LOAD_UPWARD_DYLIB) + outs() << "LC_LOAD_UPWARD_DYLIB "; + else + outs() << "LC_??? "; + outs() << "command " << Index++ << "\n"; + } + } + } +} + +typedef DenseMap SymbolAddressMap; + +static void CreateSymbolAddressMap(MachOObjectFile *O, + SymbolAddressMap *AddrMap) { + // Create a map of symbol addresses to symbol names. + for (const SymbolRef &Symbol : O->symbols()) { + Expected STOrErr = Symbol.getType(); + if (!STOrErr) + report_error(O->getFileName(), STOrErr.takeError()); + SymbolRef::Type ST = *STOrErr; + if (ST == SymbolRef::ST_Function || ST == SymbolRef::ST_Data || + ST == SymbolRef::ST_Other) { + uint64_t Address = Symbol.getValue(); + Expected SymNameOrErr = Symbol.getName(); + if (!SymNameOrErr) + report_error(O->getFileName(), SymNameOrErr.takeError()); + StringRef SymName = *SymNameOrErr; + if (!SymName.startswith(".objc")) + (*AddrMap)[Address] = SymName; + } + } +} + +// GuessSymbolName is passed the address of what might be a symbol and a +// pointer to the SymbolAddressMap. It returns the name of a symbol +// with that address or nullptr if no symbol is found with that address. +static const char *GuessSymbolName(uint64_t value, SymbolAddressMap *AddrMap) { + const char *SymbolName = nullptr; + // A DenseMap can't lookup up some values. + if (value != 0xffffffffffffffffULL && value != 0xfffffffffffffffeULL) { + StringRef name = AddrMap->lookup(value); + if (!name.empty()) + SymbolName = name.data(); + } + return SymbolName; +} + +static void DumpCstringChar(const char c) { + char p[2]; + p[0] = c; + p[1] = '\0'; + outs().write_escaped(p); +} + +static void DumpCstringSection(MachOObjectFile *O, const char *sect, + uint32_t sect_size, uint64_t sect_addr, + bool print_addresses) { + for (uint32_t i = 0; i < sect_size; i++) { + if (print_addresses) { + if (O->is64Bit()) + outs() << format("%016" PRIx64, sect_addr + i) << " "; + else + outs() << format("%08" PRIx64, sect_addr + i) << " "; + } + for (; i < sect_size && sect[i] != '\0'; i++) + DumpCstringChar(sect[i]); + if (i < sect_size && sect[i] == '\0') + outs() << "\n"; + } +} + +static void DumpLiteral4(uint32_t l, float f) { + outs() << format("0x%08" PRIx32, l); + if ((l & 0x7f800000) != 0x7f800000) + outs() << format(" (%.16e)\n", f); + else { + if (l == 0x7f800000) + outs() << " (+Infinity)\n"; + else if (l == 0xff800000) + outs() << " (-Infinity)\n"; + else if ((l & 0x00400000) == 0x00400000) + outs() << " (non-signaling Not-a-Number)\n"; + else + outs() << " (signaling Not-a-Number)\n"; + } +} + +static void DumpLiteral4Section(MachOObjectFile *O, const char *sect, + uint32_t sect_size, uint64_t sect_addr, + bool print_addresses) { + for (uint32_t i = 0; i < sect_size; i += sizeof(float)) { + if (print_addresses) { + if (O->is64Bit()) + outs() << format("%016" PRIx64, sect_addr + i) << " "; + else + outs() << format("%08" PRIx64, sect_addr + i) << " "; + } + float f; + memcpy(&f, sect + i, sizeof(float)); + if (O->isLittleEndian() != sys::IsLittleEndianHost) + sys::swapByteOrder(f); + uint32_t l; + memcpy(&l, sect + i, sizeof(uint32_t)); + if (O->isLittleEndian() != sys::IsLittleEndianHost) + sys::swapByteOrder(l); + DumpLiteral4(l, f); + } +} + +static void DumpLiteral8(MachOObjectFile *O, uint32_t l0, uint32_t l1, + double d) { + outs() << format("0x%08" PRIx32, l0) << " " << format("0x%08" PRIx32, l1); + uint32_t Hi, Lo; + Hi = (O->isLittleEndian()) ? l1 : l0; + Lo = (O->isLittleEndian()) ? l0 : l1; + + // Hi is the high word, so this is equivalent to if(isfinite(d)) + if ((Hi & 0x7ff00000) != 0x7ff00000) + outs() << format(" (%.16e)\n", d); + else { + if (Hi == 0x7ff00000 && Lo == 0) + outs() << " (+Infinity)\n"; + else if (Hi == 0xfff00000 && Lo == 0) + outs() << " (-Infinity)\n"; + else if ((Hi & 0x00080000) == 0x00080000) + outs() << " (non-signaling Not-a-Number)\n"; + else + outs() << " (signaling Not-a-Number)\n"; + } +} + +static void DumpLiteral8Section(MachOObjectFile *O, const char *sect, + uint32_t sect_size, uint64_t sect_addr, + bool print_addresses) { + for (uint32_t i = 0; i < sect_size; i += sizeof(double)) { + if (print_addresses) { + if (O->is64Bit()) + outs() << format("%016" PRIx64, sect_addr + i) << " "; + else + outs() << format("%08" PRIx64, sect_addr + i) << " "; + } + double d; + memcpy(&d, sect + i, sizeof(double)); + if (O->isLittleEndian() != sys::IsLittleEndianHost) + sys::swapByteOrder(d); + uint32_t l0, l1; + memcpy(&l0, sect + i, sizeof(uint32_t)); + memcpy(&l1, sect + i + sizeof(uint32_t), sizeof(uint32_t)); + if (O->isLittleEndian() != sys::IsLittleEndianHost) { + sys::swapByteOrder(l0); + sys::swapByteOrder(l1); + } + DumpLiteral8(O, l0, l1, d); + } +} + +static void DumpLiteral16(uint32_t l0, uint32_t l1, uint32_t l2, uint32_t l3) { + outs() << format("0x%08" PRIx32, l0) << " "; + outs() << format("0x%08" PRIx32, l1) << " "; + outs() << format("0x%08" PRIx32, l2) << " "; + outs() << format("0x%08" PRIx32, l3) << "\n"; +} + +static void DumpLiteral16Section(MachOObjectFile *O, const char *sect, + uint32_t sect_size, uint64_t sect_addr, + bool print_addresses) { + for (uint32_t i = 0; i < sect_size; i += 16) { + if (print_addresses) { + if (O->is64Bit()) + outs() << format("%016" PRIx64, sect_addr + i) << " "; + else + outs() << format("%08" PRIx64, sect_addr + i) << " "; + } + uint32_t l0, l1, l2, l3; + memcpy(&l0, sect + i, sizeof(uint32_t)); + memcpy(&l1, sect + i + sizeof(uint32_t), sizeof(uint32_t)); + memcpy(&l2, sect + i + 2 * sizeof(uint32_t), sizeof(uint32_t)); + memcpy(&l3, sect + i + 3 * sizeof(uint32_t), sizeof(uint32_t)); + if (O->isLittleEndian() != sys::IsLittleEndianHost) { + sys::swapByteOrder(l0); + sys::swapByteOrder(l1); + sys::swapByteOrder(l2); + sys::swapByteOrder(l3); + } + DumpLiteral16(l0, l1, l2, l3); + } +} + +static void DumpLiteralPointerSection(MachOObjectFile *O, + const SectionRef &Section, + const char *sect, uint32_t sect_size, + uint64_t sect_addr, + bool print_addresses) { + // Collect the literal sections in this Mach-O file. + std::vector LiteralSections; + for (const SectionRef &Section : O->sections()) { + DataRefImpl Ref = Section.getRawDataRefImpl(); + uint32_t section_type; + if (O->is64Bit()) { + const MachO::section_64 Sec = O->getSection64(Ref); + section_type = Sec.flags & MachO::SECTION_TYPE; + } else { + const MachO::section Sec = O->getSection(Ref); + section_type = Sec.flags & MachO::SECTION_TYPE; + } + if (section_type == MachO::S_CSTRING_LITERALS || + section_type == MachO::S_4BYTE_LITERALS || + section_type == MachO::S_8BYTE_LITERALS || + section_type == MachO::S_16BYTE_LITERALS) + LiteralSections.push_back(Section); + } + + // Set the size of the literal pointer. + uint32_t lp_size = O->is64Bit() ? 8 : 4; + + // Collect the external relocation symbols for the literal pointers. + std::vector> Relocs; + for (const RelocationRef &Reloc : Section.relocations()) { + DataRefImpl Rel; + MachO::any_relocation_info RE; + bool isExtern = false; + Rel = Reloc.getRawDataRefImpl(); + RE = O->getRelocation(Rel); + isExtern = O->getPlainRelocationExternal(RE); + if (isExtern) { + uint64_t RelocOffset = Reloc.getOffset(); + symbol_iterator RelocSym = Reloc.getSymbol(); + Relocs.push_back(std::make_pair(RelocOffset, *RelocSym)); + } + } + array_pod_sort(Relocs.begin(), Relocs.end()); + + // Dump each literal pointer. + for (uint32_t i = 0; i < sect_size; i += lp_size) { + if (print_addresses) { + if (O->is64Bit()) + outs() << format("%016" PRIx64, sect_addr + i) << " "; + else + outs() << format("%08" PRIx64, sect_addr + i) << " "; + } + uint64_t lp; + if (O->is64Bit()) { + memcpy(&lp, sect + i, sizeof(uint64_t)); + if (O->isLittleEndian() != sys::IsLittleEndianHost) + sys::swapByteOrder(lp); + } else { + uint32_t li; + memcpy(&li, sect + i, sizeof(uint32_t)); + if (O->isLittleEndian() != sys::IsLittleEndianHost) + sys::swapByteOrder(li); + lp = li; + } + + // First look for an external relocation entry for this literal pointer. + auto Reloc = find_if(Relocs, [&](const std::pair &P) { + return P.first == i; + }); + if (Reloc != Relocs.end()) { + symbol_iterator RelocSym = Reloc->second; + Expected SymName = RelocSym->getName(); + if (!SymName) + report_error(O->getFileName(), SymName.takeError()); + outs() << "external relocation entry for symbol:" << *SymName << "\n"; + continue; + } + + // For local references see what the section the literal pointer points to. + auto Sect = find_if(LiteralSections, [&](const SectionRef &R) { + return lp >= R.getAddress() && lp < R.getAddress() + R.getSize(); + }); + if (Sect == LiteralSections.end()) { + outs() << format("0x%" PRIx64, lp) << " (not in a literal section)\n"; + continue; + } + + uint64_t SectAddress = Sect->getAddress(); + uint64_t SectSize = Sect->getSize(); + + StringRef SectName; + Sect->getName(SectName); + DataRefImpl Ref = Sect->getRawDataRefImpl(); + StringRef SegmentName = O->getSectionFinalSegmentName(Ref); + outs() << SegmentName << ":" << SectName << ":"; + + uint32_t section_type; + if (O->is64Bit()) { + const MachO::section_64 Sec = O->getSection64(Ref); + section_type = Sec.flags & MachO::SECTION_TYPE; + } else { + const MachO::section Sec = O->getSection(Ref); + section_type = Sec.flags & MachO::SECTION_TYPE; + } + + StringRef BytesStr; + Sect->getContents(BytesStr); + const char *Contents = reinterpret_cast(BytesStr.data()); + + switch (section_type) { + case MachO::S_CSTRING_LITERALS: + for (uint64_t i = lp - SectAddress; i < SectSize && Contents[i] != '\0'; + i++) { + DumpCstringChar(Contents[i]); + } + outs() << "\n"; + break; + case MachO::S_4BYTE_LITERALS: + float f; + memcpy(&f, Contents + (lp - SectAddress), sizeof(float)); + uint32_t l; + memcpy(&l, Contents + (lp - SectAddress), sizeof(uint32_t)); + if (O->isLittleEndian() != sys::IsLittleEndianHost) { + sys::swapByteOrder(f); + sys::swapByteOrder(l); + } + DumpLiteral4(l, f); + break; + case MachO::S_8BYTE_LITERALS: { + double d; + memcpy(&d, Contents + (lp - SectAddress), sizeof(double)); + uint32_t l0, l1; + memcpy(&l0, Contents + (lp - SectAddress), sizeof(uint32_t)); + memcpy(&l1, Contents + (lp - SectAddress) + sizeof(uint32_t), + sizeof(uint32_t)); + if (O->isLittleEndian() != sys::IsLittleEndianHost) { + sys::swapByteOrder(f); + sys::swapByteOrder(l0); + sys::swapByteOrder(l1); + } + DumpLiteral8(O, l0, l1, d); + break; + } + case MachO::S_16BYTE_LITERALS: { + uint32_t l0, l1, l2, l3; + memcpy(&l0, Contents + (lp - SectAddress), sizeof(uint32_t)); + memcpy(&l1, Contents + (lp - SectAddress) + sizeof(uint32_t), + sizeof(uint32_t)); + memcpy(&l2, Contents + (lp - SectAddress) + 2 * sizeof(uint32_t), + sizeof(uint32_t)); + memcpy(&l3, Contents + (lp - SectAddress) + 3 * sizeof(uint32_t), + sizeof(uint32_t)); + if (O->isLittleEndian() != sys::IsLittleEndianHost) { + sys::swapByteOrder(l0); + sys::swapByteOrder(l1); + sys::swapByteOrder(l2); + sys::swapByteOrder(l3); + } + DumpLiteral16(l0, l1, l2, l3); + break; + } + } + } +} + +static void DumpInitTermPointerSection(MachOObjectFile *O, const char *sect, + uint32_t sect_size, uint64_t sect_addr, + SymbolAddressMap *AddrMap, + bool verbose) { + uint32_t stride; + stride = (O->is64Bit()) ? sizeof(uint64_t) : sizeof(uint32_t); + for (uint32_t i = 0; i < sect_size; i += stride) { + const char *SymbolName = nullptr; + if (O->is64Bit()) { + outs() << format("0x%016" PRIx64, sect_addr + i * stride) << " "; + uint64_t pointer_value; + memcpy(&pointer_value, sect + i, stride); + if (O->isLittleEndian() != sys::IsLittleEndianHost) + sys::swapByteOrder(pointer_value); + outs() << format("0x%016" PRIx64, pointer_value); + if (verbose) + SymbolName = GuessSymbolName(pointer_value, AddrMap); + } else { + outs() << format("0x%08" PRIx64, sect_addr + i * stride) << " "; + uint32_t pointer_value; + memcpy(&pointer_value, sect + i, stride); + if (O->isLittleEndian() != sys::IsLittleEndianHost) + sys::swapByteOrder(pointer_value); + outs() << format("0x%08" PRIx32, pointer_value); + if (verbose) + SymbolName = GuessSymbolName(pointer_value, AddrMap); + } + if (SymbolName) + outs() << " " << SymbolName; + outs() << "\n"; + } +} + +static void DumpRawSectionContents(MachOObjectFile *O, const char *sect, + uint32_t size, uint64_t addr) { + uint32_t cputype = O->getHeader().cputype; + if (cputype == MachO::CPU_TYPE_I386 || cputype == MachO::CPU_TYPE_X86_64) { + uint32_t j; + for (uint32_t i = 0; i < size; i += j, addr += j) { + if (O->is64Bit()) + outs() << format("%016" PRIx64, addr) << "\t"; + else + outs() << format("%08" PRIx64, addr) << "\t"; + for (j = 0; j < 16 && i + j < size; j++) { + uint8_t byte_word = *(sect + i + j); + outs() << format("%02" PRIx32, (uint32_t)byte_word) << " "; + } + outs() << "\n"; + } + } else { + uint32_t j; + for (uint32_t i = 0; i < size; i += j, addr += j) { + if (O->is64Bit()) + outs() << format("%016" PRIx64, addr) << "\t"; + else + outs() << format("%08" PRIx64, addr) << "\t"; + for (j = 0; j < 4 * sizeof(int32_t) && i + j < size; + j += sizeof(int32_t)) { + if (i + j + sizeof(int32_t) <= size) { + uint32_t long_word; + memcpy(&long_word, sect + i + j, sizeof(int32_t)); + if (O->isLittleEndian() != sys::IsLittleEndianHost) + sys::swapByteOrder(long_word); + outs() << format("%08" PRIx32, long_word) << " "; + } else { + for (uint32_t k = 0; i + j + k < size; k++) { + uint8_t byte_word = *(sect + i + j + k); + outs() << format("%02" PRIx32, (uint32_t)byte_word) << " "; + } + } + } + outs() << "\n"; + } + } +} + +static void DisassembleMachO(StringRef Filename, MachOObjectFile *MachOOF, + StringRef DisSegName, StringRef DisSectName); +static void DumpProtocolSection(MachOObjectFile *O, const char *sect, + uint32_t size, uint32_t addr); +#ifdef HAVE_LIBXAR +static void DumpBitcodeSection(MachOObjectFile *O, const char *sect, + uint32_t size, bool verbose, bool PrintXarHeader, + bool PrintXarFileHeaders, + std::string XarMemberName); +#endif // defined(HAVE_LIBXAR) + +static void DumpSectionContents(StringRef Filename, MachOObjectFile *O, + bool verbose) { + SymbolAddressMap AddrMap; + if (verbose) + CreateSymbolAddressMap(O, &AddrMap); + + for (unsigned i = 0; i < FilterSections.size(); ++i) { + StringRef DumpSection = FilterSections[i]; + std::pair DumpSegSectName; + DumpSegSectName = DumpSection.split(','); + StringRef DumpSegName, DumpSectName; + if (DumpSegSectName.second.size()) { + DumpSegName = DumpSegSectName.first; + DumpSectName = DumpSegSectName.second; + } else { + DumpSegName = ""; + DumpSectName = DumpSegSectName.first; + } + for (const SectionRef &Section : O->sections()) { + StringRef SectName; + Section.getName(SectName); + DataRefImpl Ref = Section.getRawDataRefImpl(); + StringRef SegName = O->getSectionFinalSegmentName(Ref); + if ((DumpSegName.empty() || SegName == DumpSegName) && + (SectName == DumpSectName)) { + + uint32_t section_flags; + if (O->is64Bit()) { + const MachO::section_64 Sec = O->getSection64(Ref); + section_flags = Sec.flags; + + } else { + const MachO::section Sec = O->getSection(Ref); + section_flags = Sec.flags; + } + uint32_t section_type = section_flags & MachO::SECTION_TYPE; + + StringRef BytesStr; + Section.getContents(BytesStr); + const char *sect = reinterpret_cast(BytesStr.data()); + uint32_t sect_size = BytesStr.size(); + uint64_t sect_addr = Section.getAddress(); + + outs() << "Contents of (" << SegName << "," << SectName + << ") section\n"; + + if (verbose) { + if ((section_flags & MachO::S_ATTR_PURE_INSTRUCTIONS) || + (section_flags & MachO::S_ATTR_SOME_INSTRUCTIONS)) { + DisassembleMachO(Filename, O, SegName, SectName); + continue; + } + if (SegName == "__TEXT" && SectName == "__info_plist") { + outs() << sect; + continue; + } + if (SegName == "__OBJC" && SectName == "__protocol") { + DumpProtocolSection(O, sect, sect_size, sect_addr); + continue; + } +#ifdef HAVE_LIBXAR + if (SegName == "__LLVM" && SectName == "__bundle") { + DumpBitcodeSection(O, sect, sect_size, verbose, !NoSymbolicOperands, + ArchiveHeaders, ""); + continue; + } +#endif // defined(HAVE_LIBXAR) + switch (section_type) { + case MachO::S_REGULAR: + DumpRawSectionContents(O, sect, sect_size, sect_addr); + break; + case MachO::S_ZEROFILL: + outs() << "zerofill section and has no contents in the file\n"; + break; + case MachO::S_CSTRING_LITERALS: + DumpCstringSection(O, sect, sect_size, sect_addr, !NoLeadingAddr); + break; + case MachO::S_4BYTE_LITERALS: + DumpLiteral4Section(O, sect, sect_size, sect_addr, !NoLeadingAddr); + break; + case MachO::S_8BYTE_LITERALS: + DumpLiteral8Section(O, sect, sect_size, sect_addr, !NoLeadingAddr); + break; + case MachO::S_16BYTE_LITERALS: + DumpLiteral16Section(O, sect, sect_size, sect_addr, !NoLeadingAddr); + break; + case MachO::S_LITERAL_POINTERS: + DumpLiteralPointerSection(O, Section, sect, sect_size, sect_addr, + !NoLeadingAddr); + break; + case MachO::S_MOD_INIT_FUNC_POINTERS: + case MachO::S_MOD_TERM_FUNC_POINTERS: + DumpInitTermPointerSection(O, sect, sect_size, sect_addr, &AddrMap, + verbose); + break; + default: + outs() << "Unknown section type (" + << format("0x%08" PRIx32, section_type) << ")\n"; + DumpRawSectionContents(O, sect, sect_size, sect_addr); + break; + } + } else { + if (section_type == MachO::S_ZEROFILL) + outs() << "zerofill section and has no contents in the file\n"; + else + DumpRawSectionContents(O, sect, sect_size, sect_addr); + } + } + } + } +} + +static void DumpInfoPlistSectionContents(StringRef Filename, + MachOObjectFile *O) { + for (const SectionRef &Section : O->sections()) { + StringRef SectName; + Section.getName(SectName); + DataRefImpl Ref = Section.getRawDataRefImpl(); + StringRef SegName = O->getSectionFinalSegmentName(Ref); + if (SegName == "__TEXT" && SectName == "__info_plist") { + if (!NoLeadingHeaders) + outs() << "Contents of (" << SegName << "," << SectName + << ") section\n"; + StringRef BytesStr; + Section.getContents(BytesStr); + const char *sect = reinterpret_cast(BytesStr.data()); + outs() << format("%.*s", BytesStr.size(), sect) << "\n"; + return; + } + } +} + +// checkMachOAndArchFlags() checks to see if the ObjectFile is a Mach-O file +// and if it is and there is a list of architecture flags is specified then +// check to make sure this Mach-O file is one of those architectures or all +// architectures were specified. If not then an error is generated and this +// routine returns false. Else it returns true. +static bool checkMachOAndArchFlags(ObjectFile *O, StringRef Filename) { + auto *MachO = dyn_cast(O); + + if (!MachO || ArchAll || ArchFlags.empty()) + return true; + + MachO::mach_header H; + MachO::mach_header_64 H_64; + Triple T; + const char *McpuDefault, *ArchFlag; + if (MachO->is64Bit()) { + H_64 = MachO->MachOObjectFile::getHeader64(); + T = MachOObjectFile::getArchTriple(H_64.cputype, H_64.cpusubtype, + &McpuDefault, &ArchFlag); + } else { + H = MachO->MachOObjectFile::getHeader(); + T = MachOObjectFile::getArchTriple(H.cputype, H.cpusubtype, &McpuDefault, + &ArchFlag); + } + const std::string ArchFlagName(ArchFlag); + if (none_of(ArchFlags, + [&](const std::string &Name) { return Name == ArchFlagName; })) { + errs() << "llvm-mctoll: " + Filename + ": No architecture specified.\n"; + return false; + } + return true; +} + +static void printObjcMetaData(MachOObjectFile *O, bool verbose); + +// ProcessMachO() is passed a single opened Mach-O file, which may be an +// archive member and or in a slice of a universal file. It prints the +// the file name and header info and then processes it according to the +// command line options. +static void ProcessMachO(StringRef Name, MachOObjectFile *MachOOF, + StringRef ArchiveMemberName = StringRef(), + StringRef ArchitectureName = StringRef()) { + // If we are doing some processing here on the Mach-O file print the header + // info. And don't print it otherwise like in the case of printing the + // UniversalHeaders or ArchiveHeaders. + if (Disassemble || PrivateHeaders || ExportsTrie || Rebase || Bind || + SymbolTable || LazyBind || WeakBind || IndirectSymbols || DataInCode || + LinkOptHints || DylibsUsed || DylibId || ObjcMetaData || + (FilterSections.size() != 0)) { + if (!NoLeadingHeaders) { + outs() << Name; + if (!ArchiveMemberName.empty()) + outs() << '(' << ArchiveMemberName << ')'; + if (!ArchitectureName.empty()) + outs() << " (architecture " << ArchitectureName << ")"; + outs() << ":\n"; + } + } + // To use the report_error() form with an ArchiveName and FileName set + // these up based on what is passed for Name and ArchiveMemberName. + StringRef ArchiveName; + StringRef FileName; + if (!ArchiveMemberName.empty()) { + ArchiveName = Name; + FileName = ArchiveMemberName; + } else { + ArchiveName = StringRef(); + FileName = Name; + } + + // If we need the symbol table to do the operation then check it here to + // produce a good error message as to where the Mach-O file comes from in + // the error message. + if (Disassemble || IndirectSymbols || FilterSections.size() != 0 || + UnwindInfo) + if (Error Err = MachOOF->checkSymbolTable()) + report_error(ArchiveName, FileName, std::move(Err), ArchitectureName); + + if (Disassemble) { + if (MachOOF->getHeader().filetype == MachO::MH_KEXT_BUNDLE && + MachOOF->getHeader().cputype == MachO::CPU_TYPE_ARM64) + DisassembleMachO(FileName, MachOOF, "__TEXT_EXEC", "__text"); + else + DisassembleMachO(FileName, MachOOF, "__TEXT", "__text"); + } + if (IndirectSymbols) + PrintIndirectSymbols(MachOOF, !NonVerbose); + if (DataInCode) + PrintDataInCodeTable(MachOOF, !NonVerbose); + if (LinkOptHints) + PrintLinkOptHints(MachOOF); + if (SectionHeaders) + PrintSectionHeaders(MachOOF); + if (FilterSections.size() != 0) + DumpSectionContents(FileName, MachOOF, !NonVerbose); + if (InfoPlist) + DumpInfoPlistSectionContents(FileName, MachOOF); + if (DylibsUsed) + PrintDylibs(MachOOF, false); + if (DylibId) + PrintDylibs(MachOOF, true); + if (SymbolTable) + PrintSymbolTable(MachOOF, ArchiveName, ArchitectureName); + if (UnwindInfo) + printMachOUnwindInfo(MachOOF); + if (PrivateHeaders) { + printMachOFileHeader(MachOOF); + printMachOLoadCommands(MachOOF); + } + if (FirstPrivateHeader) + printMachOFileHeader(MachOOF); + if (ObjcMetaData) + printObjcMetaData(MachOOF, !NonVerbose); + if (ExportsTrie) + printExportsTrie(MachOOF); + if (Rebase) + printRebaseTable(MachOOF); + if (Bind) + printBindTable(MachOOF); + if (LazyBind) + printLazyBindTable(MachOOF); + if (WeakBind) + printWeakBindTable(MachOOF); +} + +// printUnknownCPUType() helps print_fat_headers for unknown CPU's. +static void printUnknownCPUType(uint32_t cputype, uint32_t cpusubtype) { + outs() << " cputype (" << cputype << ")\n"; + outs() << " cpusubtype (" << cpusubtype << ")\n"; +} + +// printCPUType() helps print_fat_headers by printing the cputype and +// pusubtype (symbolically for the one's it knows about). +static void printCPUType(uint32_t cputype, uint32_t cpusubtype) { + switch (cputype) { + case MachO::CPU_TYPE_I386: + switch (cpusubtype) { + case MachO::CPU_SUBTYPE_I386_ALL: + outs() << " cputype CPU_TYPE_I386\n"; + outs() << " cpusubtype CPU_SUBTYPE_I386_ALL\n"; + break; + default: + printUnknownCPUType(cputype, cpusubtype); + break; + } + break; + case MachO::CPU_TYPE_X86_64: + switch (cpusubtype) { + case MachO::CPU_SUBTYPE_X86_64_ALL: + outs() << " cputype CPU_TYPE_X86_64\n"; + outs() << " cpusubtype CPU_SUBTYPE_X86_64_ALL\n"; + break; + case MachO::CPU_SUBTYPE_X86_64_H: + outs() << " cputype CPU_TYPE_X86_64\n"; + outs() << " cpusubtype CPU_SUBTYPE_X86_64_H\n"; + break; + default: + printUnknownCPUType(cputype, cpusubtype); + break; + } + break; + case MachO::CPU_TYPE_ARM: + switch (cpusubtype) { + case MachO::CPU_SUBTYPE_ARM_ALL: + outs() << " cputype CPU_TYPE_ARM\n"; + outs() << " cpusubtype CPU_SUBTYPE_ARM_ALL\n"; + break; + case MachO::CPU_SUBTYPE_ARM_V4T: + outs() << " cputype CPU_TYPE_ARM\n"; + outs() << " cpusubtype CPU_SUBTYPE_ARM_V4T\n"; + break; + case MachO::CPU_SUBTYPE_ARM_V5TEJ: + outs() << " cputype CPU_TYPE_ARM\n"; + outs() << " cpusubtype CPU_SUBTYPE_ARM_V5TEJ\n"; + break; + case MachO::CPU_SUBTYPE_ARM_XSCALE: + outs() << " cputype CPU_TYPE_ARM\n"; + outs() << " cpusubtype CPU_SUBTYPE_ARM_XSCALE\n"; + break; + case MachO::CPU_SUBTYPE_ARM_V6: + outs() << " cputype CPU_TYPE_ARM\n"; + outs() << " cpusubtype CPU_SUBTYPE_ARM_V6\n"; + break; + case MachO::CPU_SUBTYPE_ARM_V6M: + outs() << " cputype CPU_TYPE_ARM\n"; + outs() << " cpusubtype CPU_SUBTYPE_ARM_V6M\n"; + break; + case MachO::CPU_SUBTYPE_ARM_V7: + outs() << " cputype CPU_TYPE_ARM\n"; + outs() << " cpusubtype CPU_SUBTYPE_ARM_V7\n"; + break; + case MachO::CPU_SUBTYPE_ARM_V7EM: + outs() << " cputype CPU_TYPE_ARM\n"; + outs() << " cpusubtype CPU_SUBTYPE_ARM_V7EM\n"; + break; + case MachO::CPU_SUBTYPE_ARM_V7K: + outs() << " cputype CPU_TYPE_ARM\n"; + outs() << " cpusubtype CPU_SUBTYPE_ARM_V7K\n"; + break; + case MachO::CPU_SUBTYPE_ARM_V7M: + outs() << " cputype CPU_TYPE_ARM\n"; + outs() << " cpusubtype CPU_SUBTYPE_ARM_V7M\n"; + break; + case MachO::CPU_SUBTYPE_ARM_V7S: + outs() << " cputype CPU_TYPE_ARM\n"; + outs() << " cpusubtype CPU_SUBTYPE_ARM_V7S\n"; + break; + default: + printUnknownCPUType(cputype, cpusubtype); + break; + } + break; + case MachO::CPU_TYPE_ARM64: + switch (cpusubtype & ~MachO::CPU_SUBTYPE_MASK) { + case MachO::CPU_SUBTYPE_ARM64_ALL: + outs() << " cputype CPU_TYPE_ARM64\n"; + outs() << " cpusubtype CPU_SUBTYPE_ARM64_ALL\n"; + break; + default: + printUnknownCPUType(cputype, cpusubtype); + break; + } + break; + default: + printUnknownCPUType(cputype, cpusubtype); + break; + } +} + +static void printMachOUniversalHeaders(const object::MachOUniversalBinary *UB, + bool verbose) { + outs() << "Fat headers\n"; + if (verbose) { + if (UB->getMagic() == MachO::FAT_MAGIC) + outs() << "fat_magic FAT_MAGIC\n"; + else // UB->getMagic() == MachO::FAT_MAGIC_64 + outs() << "fat_magic FAT_MAGIC_64\n"; + } else + outs() << "fat_magic " << format("0x%" PRIx32, MachO::FAT_MAGIC) << "\n"; + + uint32_t nfat_arch = UB->getNumberOfObjects(); + StringRef Buf = UB->getData(); + uint64_t size = Buf.size(); + uint64_t big_size = sizeof(struct MachO::fat_header) + + nfat_arch * sizeof(struct MachO::fat_arch); + outs() << "nfat_arch " << UB->getNumberOfObjects(); + if (nfat_arch == 0) + outs() << " (malformed, contains zero architecture types)\n"; + else if (big_size > size) + outs() << " (malformed, architectures past end of file)\n"; + else + outs() << "\n"; + + for (uint32_t i = 0; i < nfat_arch; ++i) { + MachOUniversalBinary::ObjectForArch OFA(UB, i); + uint32_t cputype = OFA.getCPUType(); + uint32_t cpusubtype = OFA.getCPUSubType(); + outs() << "architecture "; + for (uint32_t j = 0; i != 0 && j <= i - 1; j++) { + MachOUniversalBinary::ObjectForArch other_OFA(UB, j); + uint32_t other_cputype = other_OFA.getCPUType(); + uint32_t other_cpusubtype = other_OFA.getCPUSubType(); + if (cputype != 0 && cpusubtype != 0 && cputype == other_cputype && + (cpusubtype & ~MachO::CPU_SUBTYPE_MASK) == + (other_cpusubtype & ~MachO::CPU_SUBTYPE_MASK)) { + outs() << "(illegal duplicate architecture) "; + break; + } + } + if (verbose) { + outs() << OFA.getArchFlagName() << "\n"; + printCPUType(cputype, cpusubtype & ~MachO::CPU_SUBTYPE_MASK); + } else { + outs() << i << "\n"; + outs() << " cputype " << cputype << "\n"; + outs() << " cpusubtype " << (cpusubtype & ~MachO::CPU_SUBTYPE_MASK) + << "\n"; + } + if (verbose && + (cpusubtype & MachO::CPU_SUBTYPE_MASK) == MachO::CPU_SUBTYPE_LIB64) + outs() << " capabilities CPU_SUBTYPE_LIB64\n"; + else + outs() << " capabilities " + << format("0x%" PRIx32, + (cpusubtype & MachO::CPU_SUBTYPE_MASK) >> 24) + << "\n"; + outs() << " offset " << OFA.getOffset(); + if (OFA.getOffset() > size) + outs() << " (past end of file)"; + if (OFA.getOffset() % (1 << OFA.getAlign()) != 0) + outs() << " (not aligned on it's alignment (2^" << OFA.getAlign() << ")"; + outs() << "\n"; + outs() << " size " << OFA.getSize(); + big_size = OFA.getOffset() + OFA.getSize(); + if (big_size > size) + outs() << " (past end of file)"; + outs() << "\n"; + outs() << " align 2^" << OFA.getAlign() << " (" << (1 << OFA.getAlign()) + << ")\n"; + } +} + +static void printArchiveChild(StringRef Filename, const Archive::Child &C, + bool verbose, bool print_offset, + StringRef ArchitectureName = StringRef()) { + if (print_offset) + outs() << C.getChildOffset() << "\t"; + Expected ModeOrErr = C.getAccessMode(); + if (!ModeOrErr) + report_error(Filename, C, ModeOrErr.takeError(), ArchitectureName); + sys::fs::perms Mode = ModeOrErr.get(); + if (verbose) { + // FIXME: this first dash, "-", is for (Mode & S_IFMT) == S_IFREG. + // But there is nothing in sys::fs::perms for S_IFMT or S_IFREG. + outs() << "-"; + outs() << ((Mode & sys::fs::owner_read) ? "r" : "-"); + outs() << ((Mode & sys::fs::owner_write) ? "w" : "-"); + outs() << ((Mode & sys::fs::owner_exe) ? "x" : "-"); + outs() << ((Mode & sys::fs::group_read) ? "r" : "-"); + outs() << ((Mode & sys::fs::group_write) ? "w" : "-"); + outs() << ((Mode & sys::fs::group_exe) ? "x" : "-"); + outs() << ((Mode & sys::fs::others_read) ? "r" : "-"); + outs() << ((Mode & sys::fs::others_write) ? "w" : "-"); + outs() << ((Mode & sys::fs::others_exe) ? "x" : "-"); + } else { + outs() << format("0%o ", Mode); + } + + Expected UIDOrErr = C.getUID(); + if (!UIDOrErr) + report_error(Filename, C, UIDOrErr.takeError(), ArchitectureName); + unsigned UID = UIDOrErr.get(); + outs() << format("%3d/", UID); + Expected GIDOrErr = C.getGID(); + if (!GIDOrErr) + report_error(Filename, C, GIDOrErr.takeError(), ArchitectureName); + unsigned GID = GIDOrErr.get(); + outs() << format("%-3d ", GID); + Expected Size = C.getRawSize(); + if (!Size) + report_error(Filename, C, Size.takeError(), ArchitectureName); + outs() << format("%5" PRId64, Size.get()) << " "; + + StringRef RawLastModified = C.getRawLastModified(); + if (verbose) { + unsigned Seconds; + if (RawLastModified.getAsInteger(10, Seconds)) + outs() << "(date: \"" << RawLastModified + << "\" contains non-decimal chars) "; + else { + // Since cime(3) returns a 26 character string of the form: + // "Sun Sep 16 01:03:52 1973\n\0" + // just print 24 characters. + time_t t = Seconds; + outs() << format("%.24s ", ctime(&t)); + } + } else { + outs() << RawLastModified << " "; + } + + if (verbose) { + Expected NameOrErr = C.getName(); + if (!NameOrErr) { + consumeError(NameOrErr.takeError()); + Expected NameOrErr = C.getRawName(); + if (!NameOrErr) + report_error(Filename, C, NameOrErr.takeError(), ArchitectureName); + StringRef RawName = NameOrErr.get(); + outs() << RawName << "\n"; + } else { + StringRef Name = NameOrErr.get(); + outs() << Name << "\n"; + } + } else { + Expected NameOrErr = C.getRawName(); + if (!NameOrErr) + report_error(Filename, C, NameOrErr.takeError(), ArchitectureName); + StringRef RawName = NameOrErr.get(); + outs() << RawName << "\n"; + } +} + +static void printArchiveHeaders(StringRef Filename, Archive *A, bool verbose, + bool print_offset, + StringRef ArchitectureName = StringRef()) { + Error Err = Error::success(); + ; + for (const auto &C : A->children(Err, false)) + printArchiveChild(Filename, C, verbose, print_offset, ArchitectureName); + + if (Err) + report_error(StringRef(), Filename, std::move(Err), ArchitectureName); +} + +// ParseInputMachO() parses the named Mach-O file in Filename and handles the +// -arch flags selecting just those slices as specified by them and also parses +// archive files. Then for each individual Mach-O file ProcessMachO() is +// called to process the file based on the command line options. +void llvm::ParseInputMachO(StringRef Filename) { + // Check for -arch all and verifiy the -arch flags are valid. + for (unsigned i = 0; i < ArchFlags.size(); ++i) { + if (ArchFlags[i] == "all") { + ArchAll = true; + } else { + if (!MachOObjectFile::isValidArch(ArchFlags[i])) { + errs() << "llvm-mctoll: Unknown architecture named '" + ArchFlags[i] + + "'for the -arch option\n"; + return; + } + } + } + + // Attempt to open the binary. + Expected> BinaryOrErr = createBinary(Filename); + if (!BinaryOrErr) { + if (auto E = isNotObjectErrorInvalidFileType(BinaryOrErr.takeError())) + report_error(Filename, std::move(E)); + else + outs() << Filename << ": is not an object file\n"; + return; + } + Binary &Bin = *BinaryOrErr.get().getBinary(); + + if (Archive *A = dyn_cast(&Bin)) { + outs() << "Archive : " << Filename << "\n"; + if (ArchiveHeaders) + printArchiveHeaders(Filename, A, !NonVerbose, ArchiveMemberOffsets); + + Error Err = Error::success(); + for (auto &C : A->children(Err)) { + Expected> ChildOrErr = C.getAsBinary(); + if (!ChildOrErr) { + if (auto E = isNotObjectErrorInvalidFileType(ChildOrErr.takeError())) + report_error(Filename, C, std::move(E)); + continue; + } + if (MachOObjectFile *O = dyn_cast(&*ChildOrErr.get())) { + if (!checkMachOAndArchFlags(O, Filename)) + return; + ProcessMachO(Filename, O, O->getFileName()); + } + } + if (Err) + report_error(Filename, std::move(Err)); + return; + } + if (UniversalHeaders) { + if (MachOUniversalBinary *UB = dyn_cast(&Bin)) + printMachOUniversalHeaders(UB, !NonVerbose); + } + if (MachOUniversalBinary *UB = dyn_cast(&Bin)) { + // If we have a list of architecture flags specified dump only those. + if (!ArchAll && ArchFlags.size() != 0) { + // Look for a slice in the universal binary that matches each ArchFlag. + bool ArchFound; + for (unsigned i = 0; i < ArchFlags.size(); ++i) { + ArchFound = false; + for (MachOUniversalBinary::object_iterator I = UB->begin_objects(), + E = UB->end_objects(); + I != E; ++I) { + if (ArchFlags[i] == I->getArchFlagName()) { + ArchFound = true; + Expected> ObjOrErr = + I->getAsObjectFile(); + std::string ArchitectureName = ""; + if (ArchFlags.size() > 1) + ArchitectureName = I->getArchFlagName(); + if (ObjOrErr) { + ObjectFile &O = *ObjOrErr.get(); + if (MachOObjectFile *MachOOF = dyn_cast(&O)) + ProcessMachO(Filename, MachOOF, "", ArchitectureName); + } else if (auto E = isNotObjectErrorInvalidFileType( + ObjOrErr.takeError())) { + report_error(Filename, StringRef(), std::move(E), + ArchitectureName); + continue; + } else if (Expected> AOrErr = + I->getAsArchive()) { + std::unique_ptr &A = *AOrErr; + outs() << "Archive : " << Filename; + if (!ArchitectureName.empty()) + outs() << " (architecture " << ArchitectureName << ")"; + outs() << "\n"; + if (ArchiveHeaders) + printArchiveHeaders(Filename, A.get(), !NonVerbose, + ArchiveMemberOffsets, ArchitectureName); + Error Err = Error::success(); + for (auto &C : A->children(Err)) { + Expected> ChildOrErr = C.getAsBinary(); + if (!ChildOrErr) { + if (auto E = isNotObjectErrorInvalidFileType( + ChildOrErr.takeError())) + report_error(Filename, C, std::move(E), ArchitectureName); + continue; + } + if (MachOObjectFile *O = + dyn_cast(&*ChildOrErr.get())) + ProcessMachO(Filename, O, O->getFileName(), ArchitectureName); + } + if (Err) + report_error(Filename, std::move(Err)); + } else { + consumeError(AOrErr.takeError()); + error("Mach-O universal file: " + Filename + " for " + + "architecture " + StringRef(I->getArchFlagName()) + + " is not a Mach-O file or an archive file"); + } + } + } + if (!ArchFound) { + errs() << "llvm-mctoll: file: " + Filename + " does not contain " + << "architecture: " + ArchFlags[i] + "\n"; + return; + } + } + return; + } + // No architecture flags were specified so if this contains a slice that + // matches the host architecture dump only that. + if (!ArchAll) { + for (MachOUniversalBinary::object_iterator I = UB->begin_objects(), + E = UB->end_objects(); + I != E; ++I) { + if (MachOObjectFile::getHostArch().getArchName() == + I->getArchFlagName()) { + Expected> ObjOrErr = I->getAsObjectFile(); + std::string ArchiveName; + ArchiveName.clear(); + if (ObjOrErr) { + ObjectFile &O = *ObjOrErr.get(); + if (MachOObjectFile *MachOOF = dyn_cast(&O)) + ProcessMachO(Filename, MachOOF); + } else if (auto E = isNotObjectErrorInvalidFileType( + ObjOrErr.takeError())) { + report_error(Filename, std::move(E)); + continue; + } else if (Expected> AOrErr = + I->getAsArchive()) { + std::unique_ptr &A = *AOrErr; + outs() << "Archive : " << Filename << "\n"; + if (ArchiveHeaders) + printArchiveHeaders(Filename, A.get(), !NonVerbose, + ArchiveMemberOffsets); + Error Err = Error::success(); + for (auto &C : A->children(Err)) { + Expected> ChildOrErr = C.getAsBinary(); + if (!ChildOrErr) { + if (auto E = + isNotObjectErrorInvalidFileType(ChildOrErr.takeError())) + report_error(Filename, C, std::move(E)); + continue; + } + if (MachOObjectFile *O = + dyn_cast(&*ChildOrErr.get())) + ProcessMachO(Filename, O, O->getFileName()); + } + if (Err) + report_error(Filename, std::move(Err)); + } else { + consumeError(AOrErr.takeError()); + error("Mach-O universal file: " + Filename + " for architecture " + + StringRef(I->getArchFlagName()) + + " is not a Mach-O file or an archive file"); + } + return; + } + } + } + // Either all architectures have been specified or none have been specified + // and this does not contain the host architecture so dump all the slices. + bool moreThanOneArch = UB->getNumberOfObjects() > 1; + for (MachOUniversalBinary::object_iterator I = UB->begin_objects(), + E = UB->end_objects(); + I != E; ++I) { + Expected> ObjOrErr = I->getAsObjectFile(); + std::string ArchitectureName = ""; + if (moreThanOneArch) + ArchitectureName = I->getArchFlagName(); + if (ObjOrErr) { + ObjectFile &Obj = *ObjOrErr.get(); + if (MachOObjectFile *MachOOF = dyn_cast(&Obj)) + ProcessMachO(Filename, MachOOF, "", ArchitectureName); + } else if (auto E = + isNotObjectErrorInvalidFileType(ObjOrErr.takeError())) { + report_error(StringRef(), Filename, std::move(E), ArchitectureName); + continue; + } else if (Expected> AOrErr = + I->getAsArchive()) { + std::unique_ptr &A = *AOrErr; + outs() << "Archive : " << Filename; + if (!ArchitectureName.empty()) + outs() << " (architecture " << ArchitectureName << ")"; + outs() << "\n"; + if (ArchiveHeaders) + printArchiveHeaders(Filename, A.get(), !NonVerbose, + ArchiveMemberOffsets, ArchitectureName); + Error Err = Error::success(); + for (auto &C : A->children(Err)) { + Expected> ChildOrErr = C.getAsBinary(); + if (!ChildOrErr) { + if (auto E = + isNotObjectErrorInvalidFileType(ChildOrErr.takeError())) + report_error(Filename, C, std::move(E), ArchitectureName); + continue; + } + if (MachOObjectFile *O = + dyn_cast(&*ChildOrErr.get())) { + if (MachOObjectFile *MachOOF = dyn_cast(O)) + ProcessMachO(Filename, MachOOF, MachOOF->getFileName(), + ArchitectureName); + } + } + if (Err) + report_error(Filename, std::move(Err)); + } else { + consumeError(AOrErr.takeError()); + error("Mach-O universal file: " + Filename + " for architecture " + + StringRef(I->getArchFlagName()) + + " is not a Mach-O file or an archive file"); + } + } + return; + } + if (ObjectFile *O = dyn_cast(&Bin)) { + if (!checkMachOAndArchFlags(O, Filename)) + return; + if (MachOObjectFile *MachOOF = dyn_cast(&*O)) { + ProcessMachO(Filename, MachOOF); + } else + errs() << "llvm-mctoll: '" << Filename << "': " + << "Object is not a Mach-O file type.\n"; + return; + } + llvm_unreachable("Input object can't be invalid at this point"); +} + +// The block of info used by the Symbolizer call backs. +struct DisassembleInfo { + bool verbose; + MachOObjectFile *O; + SectionRef S; + SymbolAddressMap *AddrMap; + std::vector *Sections; + const char *class_name; + const char *selector_name; + char *method; + char *demangled_name; + uint64_t adrp_addr; + uint32_t adrp_inst; + std::unique_ptr bindtable; + uint32_t depth; +}; + +// SymbolizerGetOpInfo() is the operand information call back function. +// This is called to get the symbolic information for operand(s) of an +// instruction when it is being done. This routine does this from +// the relocation information, symbol table, etc. That block of information +// is a pointer to the struct DisassembleInfo that was passed when the +// disassembler context was created and passed to back to here when +// called back by the disassembler for instruction operands that could have +// relocation information. The address of the instruction containing operand is +// at the Pc parameter. The immediate value the operand has is passed in +// op_info->Value and is at Offset past the start of the instruction and has a +// byte Size of 1, 2 or 4. The symbolc information is returned in TagBuf is the +// LLVMOpInfo1 struct defined in the header "llvm-c/Disassembler.h" as symbol +// names and addends of the symbolic expression to add for the operand. The +// value of TagType is currently 1 (for the LLVMOpInfo1 struct). If symbolic +// information is returned then this function returns 1 else it returns 0. +static int SymbolizerGetOpInfo(void *DisInfo, uint64_t Pc, uint64_t Offset, + uint64_t Size, int TagType, void *TagBuf) { + struct DisassembleInfo *info = (struct DisassembleInfo *)DisInfo; + struct LLVMOpInfo1 *op_info = (struct LLVMOpInfo1 *)TagBuf; + uint64_t value = op_info->Value; + + // Make sure all fields returned are zero if we don't set them. + memset((void *)op_info, '\0', sizeof(struct LLVMOpInfo1)); + op_info->Value = value; + + // If the TagType is not the value 1 which it code knows about or if no + // verbose symbolic information is wanted then just return 0, indicating no + // information is being returned. + if (TagType != 1 || !info->verbose) + return 0; + + unsigned int Arch = info->O->getArch(); + if (Arch == Triple::x86) { + if (Size != 1 && Size != 2 && Size != 4 && Size != 0) + return 0; + if (info->O->getHeader().filetype != MachO::MH_OBJECT) { + // TODO: + // Search the external relocation entries of a fully linked image + // (if any) for an entry that matches this segment offset. + // uint32_t seg_offset = (Pc + Offset); + return 0; + } + // In MH_OBJECT filetypes search the section's relocation entries (if any) + // for an entry for this section offset. + uint32_t sect_addr = info->S.getAddress(); + uint32_t sect_offset = (Pc + Offset) - sect_addr; + bool reloc_found = false; + DataRefImpl Rel; + MachO::any_relocation_info RE; + bool isExtern = false; + SymbolRef Symbol; + bool r_scattered = false; + uint32_t r_value, pair_r_value, r_type; + for (const RelocationRef &Reloc : info->S.relocations()) { + uint64_t RelocOffset = Reloc.getOffset(); + if (RelocOffset == sect_offset) { + Rel = Reloc.getRawDataRefImpl(); + RE = info->O->getRelocation(Rel); + r_type = info->O->getAnyRelocationType(RE); + r_scattered = info->O->isRelocationScattered(RE); + if (r_scattered) { + r_value = info->O->getScatteredRelocationValue(RE); + if (r_type == MachO::GENERIC_RELOC_SECTDIFF || + r_type == MachO::GENERIC_RELOC_LOCAL_SECTDIFF) { + DataRefImpl RelNext = Rel; + info->O->moveRelocationNext(RelNext); + MachO::any_relocation_info RENext; + RENext = info->O->getRelocation(RelNext); + if (info->O->isRelocationScattered(RENext)) + pair_r_value = info->O->getScatteredRelocationValue(RENext); + else + return 0; + } + } else { + isExtern = info->O->getPlainRelocationExternal(RE); + if (isExtern) { + symbol_iterator RelocSym = Reloc.getSymbol(); + Symbol = *RelocSym; + } + } + reloc_found = true; + break; + } + } + if (reloc_found && isExtern) { + Expected SymName = Symbol.getName(); + if (!SymName) + report_error(info->O->getFileName(), SymName.takeError()); + const char *name = SymName->data(); + op_info->AddSymbol.Present = 1; + op_info->AddSymbol.Name = name; + // For i386 extern relocation entries the value in the instruction is + // the offset from the symbol, and value is already set in op_info->Value. + return 1; + } + if (reloc_found && (r_type == MachO::GENERIC_RELOC_SECTDIFF || + r_type == MachO::GENERIC_RELOC_LOCAL_SECTDIFF)) { + const char *add = GuessSymbolName(r_value, info->AddrMap); + const char *sub = GuessSymbolName(pair_r_value, info->AddrMap); + uint32_t offset = value - (r_value - pair_r_value); + op_info->AddSymbol.Present = 1; + if (add != nullptr) + op_info->AddSymbol.Name = add; + else + op_info->AddSymbol.Value = r_value; + op_info->SubtractSymbol.Present = 1; + if (sub != nullptr) + op_info->SubtractSymbol.Name = sub; + else + op_info->SubtractSymbol.Value = pair_r_value; + op_info->Value = offset; + return 1; + } + return 0; + } + if (Arch == Triple::x86_64) { + if (Size != 1 && Size != 2 && Size != 4 && Size != 0) + return 0; + // For non MH_OBJECT types, like MH_KEXT_BUNDLE, Search the external + // relocation entries of a linked image (if any) for an entry that matches + // this segment offset. + if (info->O->getHeader().filetype != MachO::MH_OBJECT) { + uint64_t seg_offset = Pc + Offset; + bool reloc_found = false; + DataRefImpl Rel; + MachO::any_relocation_info RE; + bool isExtern = false; + SymbolRef Symbol; + for (const RelocationRef &Reloc : info->O->external_relocations()) { + uint64_t RelocOffset = Reloc.getOffset(); + if (RelocOffset == seg_offset) { + Rel = Reloc.getRawDataRefImpl(); + RE = info->O->getRelocation(Rel); + // external relocation entries should always be external. + isExtern = info->O->getPlainRelocationExternal(RE); + if (isExtern) { + symbol_iterator RelocSym = Reloc.getSymbol(); + Symbol = *RelocSym; + } + reloc_found = true; + break; + } + } + if (reloc_found && isExtern) { + // The Value passed in will be adjusted by the Pc if the instruction + // adds the Pc. But for x86_64 external relocation entries the Value + // is the offset from the external symbol. + if (info->O->getAnyRelocationPCRel(RE)) + op_info->Value -= Pc + Offset + Size; + Expected SymName = Symbol.getName(); + if (!SymName) + report_error(info->O->getFileName(), SymName.takeError()); + const char *name = SymName->data(); + op_info->AddSymbol.Present = 1; + op_info->AddSymbol.Name = name; + return 1; + } + return 0; + } + // In MH_OBJECT filetypes search the section's relocation entries (if any) + // for an entry for this section offset. + uint64_t sect_addr = info->S.getAddress(); + uint64_t sect_offset = (Pc + Offset) - sect_addr; + bool reloc_found = false; + DataRefImpl Rel; + MachO::any_relocation_info RE; + bool isExtern = false; + SymbolRef Symbol; + for (const RelocationRef &Reloc : info->S.relocations()) { + uint64_t RelocOffset = Reloc.getOffset(); + if (RelocOffset == sect_offset) { + Rel = Reloc.getRawDataRefImpl(); + RE = info->O->getRelocation(Rel); + // NOTE: Scattered relocations don't exist on x86_64. + isExtern = info->O->getPlainRelocationExternal(RE); + if (isExtern) { + symbol_iterator RelocSym = Reloc.getSymbol(); + Symbol = *RelocSym; + } + reloc_found = true; + break; + } + } + if (reloc_found && isExtern) { + // The Value passed in will be adjusted by the Pc if the instruction + // adds the Pc. But for x86_64 external relocation entries the Value + // is the offset from the external symbol. + if (info->O->getAnyRelocationPCRel(RE)) + op_info->Value -= Pc + Offset + Size; + Expected SymName = Symbol.getName(); + if (!SymName) + report_error(info->O->getFileName(), SymName.takeError()); + const char *name = SymName->data(); + unsigned Type = info->O->getAnyRelocationType(RE); + if (Type == MachO::X86_64_RELOC_SUBTRACTOR) { + DataRefImpl RelNext = Rel; + info->O->moveRelocationNext(RelNext); + MachO::any_relocation_info RENext = info->O->getRelocation(RelNext); + unsigned TypeNext = info->O->getAnyRelocationType(RENext); + bool isExternNext = info->O->getPlainRelocationExternal(RENext); + unsigned SymbolNum = info->O->getPlainRelocationSymbolNum(RENext); + if (TypeNext == MachO::X86_64_RELOC_UNSIGNED && isExternNext) { + op_info->SubtractSymbol.Present = 1; + op_info->SubtractSymbol.Name = name; + symbol_iterator RelocSymNext = info->O->getSymbolByIndex(SymbolNum); + Symbol = *RelocSymNext; + Expected SymNameNext = Symbol.getName(); + if (!SymNameNext) + report_error(info->O->getFileName(), SymNameNext.takeError()); + name = SymNameNext->data(); + } + } + // TODO: add the VariantKinds to op_info->VariantKind for relocation types + // like: X86_64_RELOC_TLV, X86_64_RELOC_GOT_LOAD and X86_64_RELOC_GOT. + op_info->AddSymbol.Present = 1; + op_info->AddSymbol.Name = name; + return 1; + } + return 0; + } + if (Arch == Triple::arm) { + if (Offset != 0 || (Size != 4 && Size != 2)) + return 0; + if (info->O->getHeader().filetype != MachO::MH_OBJECT) { + // TODO: + // Search the external relocation entries of a fully linked image + // (if any) for an entry that matches this segment offset. + // uint32_t seg_offset = (Pc + Offset); + return 0; + } + // In MH_OBJECT filetypes search the section's relocation entries (if any) + // for an entry for this section offset. + uint32_t sect_addr = info->S.getAddress(); + uint32_t sect_offset = (Pc + Offset) - sect_addr; + DataRefImpl Rel; + MachO::any_relocation_info RE; + bool isExtern = false; + SymbolRef Symbol; + bool r_scattered = false; + uint32_t r_value, pair_r_value, r_type, r_length, other_half; + auto Reloc = + find_if(info->S.relocations(), [&](const RelocationRef &Reloc) { + uint64_t RelocOffset = Reloc.getOffset(); + return RelocOffset == sect_offset; + }); + + if (Reloc == info->S.relocations().end()) + return 0; + + Rel = Reloc->getRawDataRefImpl(); + RE = info->O->getRelocation(Rel); + r_length = info->O->getAnyRelocationLength(RE); + r_scattered = info->O->isRelocationScattered(RE); + if (r_scattered) { + r_value = info->O->getScatteredRelocationValue(RE); + r_type = info->O->getScatteredRelocationType(RE); + } else { + r_type = info->O->getAnyRelocationType(RE); + isExtern = info->O->getPlainRelocationExternal(RE); + if (isExtern) { + symbol_iterator RelocSym = Reloc->getSymbol(); + Symbol = *RelocSym; + } + } + if (r_type == MachO::ARM_RELOC_HALF || + r_type == MachO::ARM_RELOC_SECTDIFF || + r_type == MachO::ARM_RELOC_LOCAL_SECTDIFF || + r_type == MachO::ARM_RELOC_HALF_SECTDIFF) { + DataRefImpl RelNext = Rel; + info->O->moveRelocationNext(RelNext); + MachO::any_relocation_info RENext; + RENext = info->O->getRelocation(RelNext); + other_half = info->O->getAnyRelocationAddress(RENext) & 0xffff; + if (info->O->isRelocationScattered(RENext)) + pair_r_value = info->O->getScatteredRelocationValue(RENext); + } + + if (isExtern) { + Expected SymName = Symbol.getName(); + if (!SymName) + report_error(info->O->getFileName(), SymName.takeError()); + const char *name = SymName->data(); + op_info->AddSymbol.Present = 1; + op_info->AddSymbol.Name = name; + switch (r_type) { + case MachO::ARM_RELOC_HALF: + if ((r_length & 0x1) == 1) { + op_info->Value = value << 16 | other_half; + op_info->VariantKind = LLVMDisassembler_VariantKind_ARM_HI16; + } else { + op_info->Value = other_half << 16 | value; + op_info->VariantKind = LLVMDisassembler_VariantKind_ARM_LO16; + } + break; + default: + break; + } + return 1; + } + // If we have a branch that is not an external relocation entry then + // return 0 so the code in tryAddingSymbolicOperand() can use the + // SymbolLookUp call back with the branch target address to look up the + // symbol and possibility add an annotation for a symbol stub. + if (isExtern == 0 && (r_type == MachO::ARM_RELOC_BR24 || + r_type == MachO::ARM_THUMB_RELOC_BR22)) + return 0; + + uint32_t offset = 0; + if (r_type == MachO::ARM_RELOC_HALF || + r_type == MachO::ARM_RELOC_HALF_SECTDIFF) { + if ((r_length & 0x1) == 1) + value = value << 16 | other_half; + else + value = other_half << 16 | value; + } + if (r_scattered && (r_type != MachO::ARM_RELOC_HALF && + r_type != MachO::ARM_RELOC_HALF_SECTDIFF)) { + offset = value - r_value; + value = r_value; + } + + if (r_type == MachO::ARM_RELOC_HALF_SECTDIFF) { + if ((r_length & 0x1) == 1) + op_info->VariantKind = LLVMDisassembler_VariantKind_ARM_HI16; + else + op_info->VariantKind = LLVMDisassembler_VariantKind_ARM_LO16; + const char *add = GuessSymbolName(r_value, info->AddrMap); + const char *sub = GuessSymbolName(pair_r_value, info->AddrMap); + int32_t offset = value - (r_value - pair_r_value); + op_info->AddSymbol.Present = 1; + if (add != nullptr) + op_info->AddSymbol.Name = add; + else + op_info->AddSymbol.Value = r_value; + op_info->SubtractSymbol.Present = 1; + if (sub != nullptr) + op_info->SubtractSymbol.Name = sub; + else + op_info->SubtractSymbol.Value = pair_r_value; + op_info->Value = offset; + return 1; + } + + op_info->AddSymbol.Present = 1; + op_info->Value = offset; + if (r_type == MachO::ARM_RELOC_HALF) { + if ((r_length & 0x1) == 1) + op_info->VariantKind = LLVMDisassembler_VariantKind_ARM_HI16; + else + op_info->VariantKind = LLVMDisassembler_VariantKind_ARM_LO16; + } + const char *add = GuessSymbolName(value, info->AddrMap); + if (add != nullptr) { + op_info->AddSymbol.Name = add; + return 1; + } + op_info->AddSymbol.Value = value; + return 1; + } + if (Arch == Triple::aarch64) { + if (Offset != 0 || Size != 4) + return 0; + if (info->O->getHeader().filetype != MachO::MH_OBJECT) { + // TODO: + // Search the external relocation entries of a fully linked image + // (if any) for an entry that matches this segment offset. + // uint64_t seg_offset = (Pc + Offset); + return 0; + } + // In MH_OBJECT filetypes search the section's relocation entries (if any) + // for an entry for this section offset. + uint64_t sect_addr = info->S.getAddress(); + uint64_t sect_offset = (Pc + Offset) - sect_addr; + auto Reloc = + find_if(info->S.relocations(), [&](const RelocationRef &Reloc) { + uint64_t RelocOffset = Reloc.getOffset(); + return RelocOffset == sect_offset; + }); + + if (Reloc == info->S.relocations().end()) + return 0; + + DataRefImpl Rel = Reloc->getRawDataRefImpl(); + MachO::any_relocation_info RE = info->O->getRelocation(Rel); + uint32_t r_type = info->O->getAnyRelocationType(RE); + if (r_type == MachO::ARM64_RELOC_ADDEND) { + DataRefImpl RelNext = Rel; + info->O->moveRelocationNext(RelNext); + MachO::any_relocation_info RENext = info->O->getRelocation(RelNext); + if (value == 0) { + value = info->O->getPlainRelocationSymbolNum(RENext); + op_info->Value = value; + } + } + // NOTE: Scattered relocations don't exist on arm64. + if (!info->O->getPlainRelocationExternal(RE)) + return 0; + Expected SymName = Reloc->getSymbol()->getName(); + if (!SymName) + report_error(info->O->getFileName(), SymName.takeError()); + const char *name = SymName->data(); + op_info->AddSymbol.Present = 1; + op_info->AddSymbol.Name = name; + + switch (r_type) { + case MachO::ARM64_RELOC_PAGE21: + /* @page */ + op_info->VariantKind = LLVMDisassembler_VariantKind_ARM64_PAGE; + break; + case MachO::ARM64_RELOC_PAGEOFF12: + /* @pageoff */ + op_info->VariantKind = LLVMDisassembler_VariantKind_ARM64_PAGEOFF; + break; + case MachO::ARM64_RELOC_GOT_LOAD_PAGE21: + /* @gotpage */ + op_info->VariantKind = LLVMDisassembler_VariantKind_ARM64_GOTPAGE; + break; + case MachO::ARM64_RELOC_GOT_LOAD_PAGEOFF12: + /* @gotpageoff */ + op_info->VariantKind = LLVMDisassembler_VariantKind_ARM64_GOTPAGEOFF; + break; + case MachO::ARM64_RELOC_TLVP_LOAD_PAGE21: + /* @tvlppage is not implemented in llvm-mc */ + op_info->VariantKind = LLVMDisassembler_VariantKind_ARM64_TLVP; + break; + case MachO::ARM64_RELOC_TLVP_LOAD_PAGEOFF12: + /* @tvlppageoff is not implemented in llvm-mc */ + op_info->VariantKind = LLVMDisassembler_VariantKind_ARM64_TLVOFF; + break; + default: + case MachO::ARM64_RELOC_BRANCH26: + op_info->VariantKind = LLVMDisassembler_VariantKind_None; + break; + } + return 1; + } + return 0; +} + +// GuessCstringPointer is passed the address of what might be a pointer to a +// literal string in a cstring section. If that address is in a cstring section +// it returns a pointer to that string. Else it returns nullptr. +static const char *GuessCstringPointer(uint64_t ReferenceValue, + struct DisassembleInfo *info) { + for (const auto &Load : info->O->load_commands()) { + if (Load.C.cmd == MachO::LC_SEGMENT_64) { + MachO::segment_command_64 Seg = info->O->getSegment64LoadCommand(Load); + for (unsigned J = 0; J < Seg.nsects; ++J) { + MachO::section_64 Sec = info->O->getSection64(Load, J); + uint32_t section_type = Sec.flags & MachO::SECTION_TYPE; + if (section_type == MachO::S_CSTRING_LITERALS && + ReferenceValue >= Sec.addr && + ReferenceValue < Sec.addr + Sec.size) { + uint64_t sect_offset = ReferenceValue - Sec.addr; + uint64_t object_offset = Sec.offset + sect_offset; + StringRef MachOContents = info->O->getData(); + uint64_t object_size = MachOContents.size(); + const char *object_addr = (const char *)MachOContents.data(); + if (object_offset < object_size) { + const char *name = object_addr + object_offset; + return name; + } else { + return nullptr; + } + } + } + } else if (Load.C.cmd == MachO::LC_SEGMENT) { + MachO::segment_command Seg = info->O->getSegmentLoadCommand(Load); + for (unsigned J = 0; J < Seg.nsects; ++J) { + MachO::section Sec = info->O->getSection(Load, J); + uint32_t section_type = Sec.flags & MachO::SECTION_TYPE; + if (section_type == MachO::S_CSTRING_LITERALS && + ReferenceValue >= Sec.addr && + ReferenceValue < Sec.addr + Sec.size) { + uint64_t sect_offset = ReferenceValue - Sec.addr; + uint64_t object_offset = Sec.offset + sect_offset; + StringRef MachOContents = info->O->getData(); + uint64_t object_size = MachOContents.size(); + const char *object_addr = (const char *)MachOContents.data(); + if (object_offset < object_size) { + const char *name = object_addr + object_offset; + return name; + } else { + return nullptr; + } + } + } + } + } + return nullptr; +} + +// GuessIndirectSymbol returns the name of the indirect symbol for the +// ReferenceValue passed in or nullptr. This is used when ReferenceValue maybe +// an address of a symbol stub or a lazy or non-lazy pointer to associate the +// symbol name being referenced by the stub or pointer. +static const char *GuessIndirectSymbol(uint64_t ReferenceValue, + struct DisassembleInfo *info) { + MachO::dysymtab_command Dysymtab = info->O->getDysymtabLoadCommand(); + MachO::symtab_command Symtab = info->O->getSymtabLoadCommand(); + for (const auto &Load : info->O->load_commands()) { + if (Load.C.cmd == MachO::LC_SEGMENT_64) { + MachO::segment_command_64 Seg = info->O->getSegment64LoadCommand(Load); + for (unsigned J = 0; J < Seg.nsects; ++J) { + MachO::section_64 Sec = info->O->getSection64(Load, J); + uint32_t section_type = Sec.flags & MachO::SECTION_TYPE; + if ((section_type == MachO::S_NON_LAZY_SYMBOL_POINTERS || + section_type == MachO::S_LAZY_SYMBOL_POINTERS || + section_type == MachO::S_LAZY_DYLIB_SYMBOL_POINTERS || + section_type == MachO::S_THREAD_LOCAL_VARIABLE_POINTERS || + section_type == MachO::S_SYMBOL_STUBS) && + ReferenceValue >= Sec.addr && + ReferenceValue < Sec.addr + Sec.size) { + uint32_t stride; + if (section_type == MachO::S_SYMBOL_STUBS) + stride = Sec.reserved2; + else + stride = 8; + if (stride == 0) + return nullptr; + uint32_t index = Sec.reserved1 + (ReferenceValue - Sec.addr) / stride; + if (index < Dysymtab.nindirectsyms) { + uint32_t indirect_symbol = + info->O->getIndirectSymbolTableEntry(Dysymtab, index); + if (indirect_symbol < Symtab.nsyms) { + symbol_iterator Sym = info->O->getSymbolByIndex(indirect_symbol); + SymbolRef Symbol = *Sym; + Expected SymName = Symbol.getName(); + if (!SymName) + report_error(info->O->getFileName(), SymName.takeError()); + const char *name = SymName->data(); + return name; + } + } + } + } + } else if (Load.C.cmd == MachO::LC_SEGMENT) { + MachO::segment_command Seg = info->O->getSegmentLoadCommand(Load); + for (unsigned J = 0; J < Seg.nsects; ++J) { + MachO::section Sec = info->O->getSection(Load, J); + uint32_t section_type = Sec.flags & MachO::SECTION_TYPE; + if ((section_type == MachO::S_NON_LAZY_SYMBOL_POINTERS || + section_type == MachO::S_LAZY_SYMBOL_POINTERS || + section_type == MachO::S_LAZY_DYLIB_SYMBOL_POINTERS || + section_type == MachO::S_THREAD_LOCAL_VARIABLE_POINTERS || + section_type == MachO::S_SYMBOL_STUBS) && + ReferenceValue >= Sec.addr && + ReferenceValue < Sec.addr + Sec.size) { + uint32_t stride; + if (section_type == MachO::S_SYMBOL_STUBS) + stride = Sec.reserved2; + else + stride = 4; + if (stride == 0) + return nullptr; + uint32_t index = Sec.reserved1 + (ReferenceValue - Sec.addr) / stride; + if (index < Dysymtab.nindirectsyms) { + uint32_t indirect_symbol = + info->O->getIndirectSymbolTableEntry(Dysymtab, index); + if (indirect_symbol < Symtab.nsyms) { + symbol_iterator Sym = info->O->getSymbolByIndex(indirect_symbol); + SymbolRef Symbol = *Sym; + Expected SymName = Symbol.getName(); + if (!SymName) + report_error(info->O->getFileName(), SymName.takeError()); + const char *name = SymName->data(); + return name; + } + } + } + } + } + } + return nullptr; +} + +// method_reference() is called passing it the ReferenceName that might be +// a reference it to an Objective-C method call. If so then it allocates and +// assembles a method call string with the values last seen and saved in +// the DisassembleInfo's class_name and selector_name fields. This is saved +// into the method field of the info and any previous string is free'ed. +// Then the class_name field in the info is set to nullptr. The method call +// string is set into ReferenceName and ReferenceType is set to +// LLVMDisassembler_ReferenceType_Out_Objc_Message. If this not a method call +// then both ReferenceType and ReferenceName are left unchanged. +static void method_reference(struct DisassembleInfo *info, + uint64_t *ReferenceType, + const char **ReferenceName) { + unsigned int Arch = info->O->getArch(); + if (*ReferenceName != nullptr) { + if (strcmp(*ReferenceName, "_objc_msgSend") == 0) { + if (info->selector_name != nullptr) { + if (info->method != nullptr) + free(info->method); + if (info->class_name != nullptr) { + info->method = (char *)malloc(5 + strlen(info->class_name) + + strlen(info->selector_name)); + if (info->method != nullptr) { + strcpy(info->method, "+["); + strcat(info->method, info->class_name); + strcat(info->method, " "); + strcat(info->method, info->selector_name); + strcat(info->method, "]"); + *ReferenceName = info->method; + *ReferenceType = LLVMDisassembler_ReferenceType_Out_Objc_Message; + } + } else { + info->method = (char *)malloc(9 + strlen(info->selector_name)); + if (info->method != nullptr) { + if (Arch == Triple::x86_64) + strcpy(info->method, "-[%rdi "); + else if (Arch == Triple::aarch64) + strcpy(info->method, "-[x0 "); + else + strcpy(info->method, "-[r? "); + strcat(info->method, info->selector_name); + strcat(info->method, "]"); + *ReferenceName = info->method; + *ReferenceType = LLVMDisassembler_ReferenceType_Out_Objc_Message; + } + } + info->class_name = nullptr; + } + } else if (strcmp(*ReferenceName, "_objc_msgSendSuper2") == 0) { + if (info->selector_name != nullptr) { + if (info->method != nullptr) + free(info->method); + info->method = (char *)malloc(17 + strlen(info->selector_name)); + if (info->method != nullptr) { + if (Arch == Triple::x86_64) + strcpy(info->method, "-[[%rdi super] "); + else if (Arch == Triple::aarch64) + strcpy(info->method, "-[[x0 super] "); + else + strcpy(info->method, "-[[r? super] "); + strcat(info->method, info->selector_name); + strcat(info->method, "]"); + *ReferenceName = info->method; + *ReferenceType = LLVMDisassembler_ReferenceType_Out_Objc_Message; + } + info->class_name = nullptr; + } + } + } +} + +// GuessPointerPointer() is passed the address of what might be a pointer to +// a reference to an Objective-C class, selector, message ref or cfstring. +// If so the value of the pointer is returned and one of the booleans are set +// to true. If not zero is returned and all the booleans are set to false. +static uint64_t GuessPointerPointer(uint64_t ReferenceValue, + struct DisassembleInfo *info, + bool &classref, bool &selref, bool &msgref, + bool &cfstring) { + classref = false; + selref = false; + msgref = false; + cfstring = false; + for (const auto &Load : info->O->load_commands()) { + if (Load.C.cmd == MachO::LC_SEGMENT_64) { + MachO::segment_command_64 Seg = info->O->getSegment64LoadCommand(Load); + for (unsigned J = 0; J < Seg.nsects; ++J) { + MachO::section_64 Sec = info->O->getSection64(Load, J); + if ((strncmp(Sec.sectname, "__objc_selrefs", 16) == 0 || + strncmp(Sec.sectname, "__objc_classrefs", 16) == 0 || + strncmp(Sec.sectname, "__objc_superrefs", 16) == 0 || + strncmp(Sec.sectname, "__objc_msgrefs", 16) == 0 || + strncmp(Sec.sectname, "__cfstring", 16) == 0) && + ReferenceValue >= Sec.addr && + ReferenceValue < Sec.addr + Sec.size) { + uint64_t sect_offset = ReferenceValue - Sec.addr; + uint64_t object_offset = Sec.offset + sect_offset; + StringRef MachOContents = info->O->getData(); + uint64_t object_size = MachOContents.size(); + const char *object_addr = (const char *)MachOContents.data(); + if (object_offset < object_size) { + uint64_t pointer_value; + memcpy(&pointer_value, object_addr + object_offset, + sizeof(uint64_t)); + if (info->O->isLittleEndian() != sys::IsLittleEndianHost) + sys::swapByteOrder(pointer_value); + if (strncmp(Sec.sectname, "__objc_selrefs", 16) == 0) + selref = true; + else if (strncmp(Sec.sectname, "__objc_classrefs", 16) == 0 || + strncmp(Sec.sectname, "__objc_superrefs", 16) == 0) + classref = true; + else if (strncmp(Sec.sectname, "__objc_msgrefs", 16) == 0 && + ReferenceValue + 8 < Sec.addr + Sec.size) { + msgref = true; + memcpy(&pointer_value, object_addr + object_offset + 8, + sizeof(uint64_t)); + if (info->O->isLittleEndian() != sys::IsLittleEndianHost) + sys::swapByteOrder(pointer_value); + } else if (strncmp(Sec.sectname, "__cfstring", 16) == 0) + cfstring = true; + return pointer_value; + } else { + return 0; + } + } + } + } + // TODO: Look for LC_SEGMENT for 32-bit Mach-O files. + } + return 0; +} + +// get_pointer_64 returns a pointer to the bytes in the object file at the +// Address from a section in the Mach-O file. And indirectly returns the +// offset into the section, number of bytes left in the section past the offset +// and which section is was being referenced. If the Address is not in a +// section nullptr is returned. +static const char *get_pointer_64(uint64_t Address, uint32_t &offset, + uint32_t &left, SectionRef &S, + DisassembleInfo *info, + bool objc_only = false) { + offset = 0; + left = 0; + S = SectionRef(); + for (unsigned SectIdx = 0; SectIdx != info->Sections->size(); SectIdx++) { + uint64_t SectAddress = ((*(info->Sections))[SectIdx]).getAddress(); + uint64_t SectSize = ((*(info->Sections))[SectIdx]).getSize(); + if (SectSize == 0) + continue; + if (objc_only) { + StringRef SectName; + ((*(info->Sections))[SectIdx]).getName(SectName); + DataRefImpl Ref = ((*(info->Sections))[SectIdx]).getRawDataRefImpl(); + StringRef SegName = info->O->getSectionFinalSegmentName(Ref); + if (SegName != "__OBJC" && SectName != "__cstring") + continue; + } + if (Address >= SectAddress && Address < SectAddress + SectSize) { + S = (*(info->Sections))[SectIdx]; + offset = Address - SectAddress; + left = SectSize - offset; + StringRef SectContents; + ((*(info->Sections))[SectIdx]).getContents(SectContents); + return SectContents.data() + offset; + } + } + return nullptr; +} + +static const char *get_pointer_32(uint32_t Address, uint32_t &offset, + uint32_t &left, SectionRef &S, + DisassembleInfo *info, + bool objc_only = false) { + return get_pointer_64(Address, offset, left, S, info, objc_only); +} + +// get_symbol_64() returns the name of a symbol (or nullptr) and the address of +// the symbol indirectly through n_value. Based on the relocation information +// for the specified section offset in the specified section reference. +// If no relocation information is found and a non-zero ReferenceValue for the +// symbol is passed, look up that address in the info's AddrMap. +static const char *get_symbol_64(uint32_t sect_offset, SectionRef S, + DisassembleInfo *info, uint64_t &n_value, + uint64_t ReferenceValue = 0) { + n_value = 0; + if (!info->verbose) + return nullptr; + + // See if there is an external relocation entry at the sect_offset. + bool reloc_found = false; + DataRefImpl Rel; + MachO::any_relocation_info RE; + bool isExtern = false; + SymbolRef Symbol; + for (const RelocationRef &Reloc : S.relocations()) { + uint64_t RelocOffset = Reloc.getOffset(); + if (RelocOffset == sect_offset) { + Rel = Reloc.getRawDataRefImpl(); + RE = info->O->getRelocation(Rel); + if (info->O->isRelocationScattered(RE)) + continue; + isExtern = info->O->getPlainRelocationExternal(RE); + if (isExtern) { + symbol_iterator RelocSym = Reloc.getSymbol(); + Symbol = *RelocSym; + } + reloc_found = true; + break; + } + } + // If there is an external relocation entry for a symbol in this section + // at this section_offset then use that symbol's value for the n_value + // and return its name. + const char *SymbolName = nullptr; + if (reloc_found && isExtern) { + n_value = Symbol.getValue(); + Expected NameOrError = Symbol.getName(); + if (!NameOrError) + report_error(info->O->getFileName(), NameOrError.takeError()); + StringRef Name = *NameOrError; + if (!Name.empty()) { + SymbolName = Name.data(); + return SymbolName; + } + } + + // TODO: For fully linked images, look through the external relocation + // entries off the dynamic symtab command. For these the r_offset is from the + // start of the first writeable segment in the Mach-O file. So the offset + // to this section from that segment is passed to this routine by the caller, + // as the database_offset. Which is the difference of the section's starting + // address and the first writable segment. + // + // NOTE: need add passing the database_offset to this routine. + + // We did not find an external relocation entry so look up the ReferenceValue + // as an address of a symbol and if found return that symbol's name. + SymbolName = GuessSymbolName(ReferenceValue, info->AddrMap); + + return SymbolName; +} + +static const char *get_symbol_32(uint32_t sect_offset, SectionRef S, + DisassembleInfo *info, + uint32_t ReferenceValue) { + uint64_t n_value64; + return get_symbol_64(sect_offset, S, info, n_value64, ReferenceValue); +} + +// These are structs in the Objective-C meta data and read to produce the +// comments for disassembly. While these are part of the ABI they are no +// public defintions. So the are here not in include/llvm/BinaryFormat/MachO.h +// . + +// The cfstring object in a 64-bit Mach-O file. +struct cfstring64_t { + uint64_t isa; // class64_t * (64-bit pointer) + uint64_t flags; // flag bits + uint64_t characters; // char * (64-bit pointer) + uint64_t length; // number of non-NULL characters in above +}; + +// The class object in a 64-bit Mach-O file. +struct class64_t { + uint64_t isa; // class64_t * (64-bit pointer) + uint64_t superclass; // class64_t * (64-bit pointer) + uint64_t cache; // Cache (64-bit pointer) + uint64_t vtable; // IMP * (64-bit pointer) + uint64_t data; // class_ro64_t * (64-bit pointer) +}; + +struct class32_t { + uint32_t isa; /* class32_t * (32-bit pointer) */ + uint32_t superclass; /* class32_t * (32-bit pointer) */ + uint32_t cache; /* Cache (32-bit pointer) */ + uint32_t vtable; /* IMP * (32-bit pointer) */ + uint32_t data; /* class_ro32_t * (32-bit pointer) */ +}; + +struct class_ro64_t { + uint32_t flags; + uint32_t instanceStart; + uint32_t instanceSize; + uint32_t reserved; + uint64_t ivarLayout; // const uint8_t * (64-bit pointer) + uint64_t name; // const char * (64-bit pointer) + uint64_t baseMethods; // const method_list_t * (64-bit pointer) + uint64_t baseProtocols; // const protocol_list_t * (64-bit pointer) + uint64_t ivars; // const ivar_list_t * (64-bit pointer) + uint64_t weakIvarLayout; // const uint8_t * (64-bit pointer) + uint64_t baseProperties; // const struct objc_property_list (64-bit pointer) +}; + +struct class_ro32_t { + uint32_t flags; + uint32_t instanceStart; + uint32_t instanceSize; + uint32_t ivarLayout; /* const uint8_t * (32-bit pointer) */ + uint32_t name; /* const char * (32-bit pointer) */ + uint32_t baseMethods; /* const method_list_t * (32-bit pointer) */ + uint32_t baseProtocols; /* const protocol_list_t * (32-bit pointer) */ + uint32_t ivars; /* const ivar_list_t * (32-bit pointer) */ + uint32_t weakIvarLayout; /* const uint8_t * (32-bit pointer) */ + uint32_t baseProperties; /* const struct objc_property_list * + (32-bit pointer) */ +}; + +/* Values for class_ro{64,32}_t->flags */ +#define RO_META (1 << 0) +#define RO_ROOT (1 << 1) +#define RO_HAS_CXX_STRUCTORS (1 << 2) + +struct method_list64_t { + uint32_t entsize; + uint32_t count; + /* struct method64_t first; These structures follow inline */ +}; + +struct method_list32_t { + uint32_t entsize; + uint32_t count; + /* struct method32_t first; These structures follow inline */ +}; + +struct method64_t { + uint64_t name; /* SEL (64-bit pointer) */ + uint64_t types; /* const char * (64-bit pointer) */ + uint64_t imp; /* IMP (64-bit pointer) */ +}; + +struct method32_t { + uint32_t name; /* SEL (32-bit pointer) */ + uint32_t types; /* const char * (32-bit pointer) */ + uint32_t imp; /* IMP (32-bit pointer) */ +}; + +struct protocol_list64_t { + uint64_t count; /* uintptr_t (a 64-bit value) */ + /* struct protocol64_t * list[0]; These pointers follow inline */ +}; + +struct protocol_list32_t { + uint32_t count; /* uintptr_t (a 32-bit value) */ + /* struct protocol32_t * list[0]; These pointers follow inline */ +}; + +struct protocol64_t { + uint64_t isa; /* id * (64-bit pointer) */ + uint64_t name; /* const char * (64-bit pointer) */ + uint64_t protocols; /* struct protocol_list64_t * + (64-bit pointer) */ + uint64_t instanceMethods; /* method_list_t * (64-bit pointer) */ + uint64_t classMethods; /* method_list_t * (64-bit pointer) */ + uint64_t optionalInstanceMethods; /* method_list_t * (64-bit pointer) */ + uint64_t optionalClassMethods; /* method_list_t * (64-bit pointer) */ + uint64_t instanceProperties; /* struct objc_property_list * + (64-bit pointer) */ +}; + +struct protocol32_t { + uint32_t isa; /* id * (32-bit pointer) */ + uint32_t name; /* const char * (32-bit pointer) */ + uint32_t protocols; /* struct protocol_list_t * + (32-bit pointer) */ + uint32_t instanceMethods; /* method_list_t * (32-bit pointer) */ + uint32_t classMethods; /* method_list_t * (32-bit pointer) */ + uint32_t optionalInstanceMethods; /* method_list_t * (32-bit pointer) */ + uint32_t optionalClassMethods; /* method_list_t * (32-bit pointer) */ + uint32_t instanceProperties; /* struct objc_property_list * + (32-bit pointer) */ +}; + +struct ivar_list64_t { + uint32_t entsize; + uint32_t count; + /* struct ivar64_t first; These structures follow inline */ +}; + +struct ivar_list32_t { + uint32_t entsize; + uint32_t count; + /* struct ivar32_t first; These structures follow inline */ +}; + +struct ivar64_t { + uint64_t offset; /* uintptr_t * (64-bit pointer) */ + uint64_t name; /* const char * (64-bit pointer) */ + uint64_t type; /* const char * (64-bit pointer) */ + uint32_t alignment; + uint32_t size; +}; + +struct ivar32_t { + uint32_t offset; /* uintptr_t * (32-bit pointer) */ + uint32_t name; /* const char * (32-bit pointer) */ + uint32_t type; /* const char * (32-bit pointer) */ + uint32_t alignment; + uint32_t size; +}; + +struct objc_property_list64 { + uint32_t entsize; + uint32_t count; + /* struct objc_property64 first; These structures follow inline */ +}; + +struct objc_property_list32 { + uint32_t entsize; + uint32_t count; + /* struct objc_property32 first; These structures follow inline */ +}; + +struct objc_property64 { + uint64_t name; /* const char * (64-bit pointer) */ + uint64_t attributes; /* const char * (64-bit pointer) */ +}; + +struct objc_property32 { + uint32_t name; /* const char * (32-bit pointer) */ + uint32_t attributes; /* const char * (32-bit pointer) */ +}; + +struct category64_t { + uint64_t name; /* const char * (64-bit pointer) */ + uint64_t cls; /* struct class_t * (64-bit pointer) */ + uint64_t instanceMethods; /* struct method_list_t * (64-bit pointer) */ + uint64_t classMethods; /* struct method_list_t * (64-bit pointer) */ + uint64_t protocols; /* struct protocol_list_t * (64-bit pointer) */ + uint64_t instanceProperties; /* struct objc_property_list * + (64-bit pointer) */ +}; + +struct category32_t { + uint32_t name; /* const char * (32-bit pointer) */ + uint32_t cls; /* struct class_t * (32-bit pointer) */ + uint32_t instanceMethods; /* struct method_list_t * (32-bit pointer) */ + uint32_t classMethods; /* struct method_list_t * (32-bit pointer) */ + uint32_t protocols; /* struct protocol_list_t * (32-bit pointer) */ + uint32_t instanceProperties; /* struct objc_property_list * + (32-bit pointer) */ +}; + +struct objc_image_info64 { + uint32_t version; + uint32_t flags; +}; +struct objc_image_info32 { + uint32_t version; + uint32_t flags; +}; +struct imageInfo_t { + uint32_t version; + uint32_t flags; +}; +/* masks for objc_image_info.flags */ +#define OBJC_IMAGE_IS_REPLACEMENT (1 << 0) +#define OBJC_IMAGE_SUPPORTS_GC (1 << 1) + +struct message_ref64 { + uint64_t imp; /* IMP (64-bit pointer) */ + uint64_t sel; /* SEL (64-bit pointer) */ +}; + +struct message_ref32 { + uint32_t imp; /* IMP (32-bit pointer) */ + uint32_t sel; /* SEL (32-bit pointer) */ +}; + +// Objective-C 1 (32-bit only) meta data structs. + +struct objc_module_t { + uint32_t version; + uint32_t size; + uint32_t name; /* char * (32-bit pointer) */ + uint32_t symtab; /* struct objc_symtab * (32-bit pointer) */ +}; + +struct objc_symtab_t { + uint32_t sel_ref_cnt; + uint32_t refs; /* SEL * (32-bit pointer) */ + uint16_t cls_def_cnt; + uint16_t cat_def_cnt; + // uint32_t defs[1]; /* void * (32-bit pointer) variable size */ +}; + +struct objc_class_t { + uint32_t isa; /* struct objc_class * (32-bit pointer) */ + uint32_t super_class; /* struct objc_class * (32-bit pointer) */ + uint32_t name; /* const char * (32-bit pointer) */ + int32_t version; + int32_t info; + int32_t instance_size; + uint32_t ivars; /* struct objc_ivar_list * (32-bit pointer) */ + uint32_t methodLists; /* struct objc_method_list ** (32-bit pointer) */ + uint32_t cache; /* struct objc_cache * (32-bit pointer) */ + uint32_t protocols; /* struct objc_protocol_list * (32-bit pointer) */ +}; + +#define CLS_GETINFO(cls, infomask) ((cls)->info & (infomask)) +// class is not a metaclass +#define CLS_CLASS 0x1 +// class is a metaclass +#define CLS_META 0x2 + +struct objc_category_t { + uint32_t category_name; /* char * (32-bit pointer) */ + uint32_t class_name; /* char * (32-bit pointer) */ + uint32_t instance_methods; /* struct objc_method_list * (32-bit pointer) */ + uint32_t class_methods; /* struct objc_method_list * (32-bit pointer) */ + uint32_t protocols; /* struct objc_protocol_list * (32-bit ptr) */ +}; + +struct objc_ivar_t { + uint32_t ivar_name; /* char * (32-bit pointer) */ + uint32_t ivar_type; /* char * (32-bit pointer) */ + int32_t ivar_offset; +}; + +struct objc_ivar_list_t { + int32_t ivar_count; + // struct objc_ivar_t ivar_list[1]; /* variable length structure */ +}; + +struct objc_method_list_t { + uint32_t obsolete; /* struct objc_method_list * (32-bit pointer) */ + int32_t method_count; + // struct objc_method_t method_list[1]; /* variable length structure */ +}; + +struct objc_method_t { + uint32_t method_name; /* SEL, aka struct objc_selector * (32-bit pointer) */ + uint32_t method_types; /* char * (32-bit pointer) */ + uint32_t method_imp; /* IMP, aka function pointer, (*IMP)(id, SEL, ...) + (32-bit pointer) */ +}; + +struct objc_protocol_list_t { + uint32_t next; /* struct objc_protocol_list * (32-bit pointer) */ + int32_t count; + // uint32_t list[1]; /* Protocol *, aka struct objc_protocol_t * + // (32-bit pointer) */ +}; + +struct objc_protocol_t { + uint32_t isa; /* struct objc_class * (32-bit pointer) */ + uint32_t protocol_name; /* char * (32-bit pointer) */ + uint32_t protocol_list; /* struct objc_protocol_list * (32-bit pointer) */ + uint32_t instance_methods; /* struct objc_method_description_list * + (32-bit pointer) */ + uint32_t class_methods; /* struct objc_method_description_list * + (32-bit pointer) */ +}; + +struct objc_method_description_list_t { + int32_t count; + // struct objc_method_description_t list[1]; +}; + +struct objc_method_description_t { + uint32_t name; /* SEL, aka struct objc_selector * (32-bit pointer) */ + uint32_t types; /* char * (32-bit pointer) */ +}; + +inline void swapStruct(struct cfstring64_t &cfs) { + sys::swapByteOrder(cfs.isa); + sys::swapByteOrder(cfs.flags); + sys::swapByteOrder(cfs.characters); + sys::swapByteOrder(cfs.length); +} + +inline void swapStruct(struct class64_t &c) { + sys::swapByteOrder(c.isa); + sys::swapByteOrder(c.superclass); + sys::swapByteOrder(c.cache); + sys::swapByteOrder(c.vtable); + sys::swapByteOrder(c.data); +} + +inline void swapStruct(struct class32_t &c) { + sys::swapByteOrder(c.isa); + sys::swapByteOrder(c.superclass); + sys::swapByteOrder(c.cache); + sys::swapByteOrder(c.vtable); + sys::swapByteOrder(c.data); +} + +inline void swapStruct(struct class_ro64_t &cro) { + sys::swapByteOrder(cro.flags); + sys::swapByteOrder(cro.instanceStart); + sys::swapByteOrder(cro.instanceSize); + sys::swapByteOrder(cro.reserved); + sys::swapByteOrder(cro.ivarLayout); + sys::swapByteOrder(cro.name); + sys::swapByteOrder(cro.baseMethods); + sys::swapByteOrder(cro.baseProtocols); + sys::swapByteOrder(cro.ivars); + sys::swapByteOrder(cro.weakIvarLayout); + sys::swapByteOrder(cro.baseProperties); +} + +inline void swapStruct(struct class_ro32_t &cro) { + sys::swapByteOrder(cro.flags); + sys::swapByteOrder(cro.instanceStart); + sys::swapByteOrder(cro.instanceSize); + sys::swapByteOrder(cro.ivarLayout); + sys::swapByteOrder(cro.name); + sys::swapByteOrder(cro.baseMethods); + sys::swapByteOrder(cro.baseProtocols); + sys::swapByteOrder(cro.ivars); + sys::swapByteOrder(cro.weakIvarLayout); + sys::swapByteOrder(cro.baseProperties); +} + +inline void swapStruct(struct method_list64_t &ml) { + sys::swapByteOrder(ml.entsize); + sys::swapByteOrder(ml.count); +} + +inline void swapStruct(struct method_list32_t &ml) { + sys::swapByteOrder(ml.entsize); + sys::swapByteOrder(ml.count); +} + +inline void swapStruct(struct method64_t &m) { + sys::swapByteOrder(m.name); + sys::swapByteOrder(m.types); + sys::swapByteOrder(m.imp); +} + +inline void swapStruct(struct method32_t &m) { + sys::swapByteOrder(m.name); + sys::swapByteOrder(m.types); + sys::swapByteOrder(m.imp); +} + +inline void swapStruct(struct protocol_list64_t &pl) { + sys::swapByteOrder(pl.count); +} + +inline void swapStruct(struct protocol_list32_t &pl) { + sys::swapByteOrder(pl.count); +} + +inline void swapStruct(struct protocol64_t &p) { + sys::swapByteOrder(p.isa); + sys::swapByteOrder(p.name); + sys::swapByteOrder(p.protocols); + sys::swapByteOrder(p.instanceMethods); + sys::swapByteOrder(p.classMethods); + sys::swapByteOrder(p.optionalInstanceMethods); + sys::swapByteOrder(p.optionalClassMethods); + sys::swapByteOrder(p.instanceProperties); +} + +inline void swapStruct(struct protocol32_t &p) { + sys::swapByteOrder(p.isa); + sys::swapByteOrder(p.name); + sys::swapByteOrder(p.protocols); + sys::swapByteOrder(p.instanceMethods); + sys::swapByteOrder(p.classMethods); + sys::swapByteOrder(p.optionalInstanceMethods); + sys::swapByteOrder(p.optionalClassMethods); + sys::swapByteOrder(p.instanceProperties); +} + +inline void swapStruct(struct ivar_list64_t &il) { + sys::swapByteOrder(il.entsize); + sys::swapByteOrder(il.count); +} + +inline void swapStruct(struct ivar_list32_t &il) { + sys::swapByteOrder(il.entsize); + sys::swapByteOrder(il.count); +} + +inline void swapStruct(struct ivar64_t &i) { + sys::swapByteOrder(i.offset); + sys::swapByteOrder(i.name); + sys::swapByteOrder(i.type); + sys::swapByteOrder(i.alignment); + sys::swapByteOrder(i.size); +} + +inline void swapStruct(struct ivar32_t &i) { + sys::swapByteOrder(i.offset); + sys::swapByteOrder(i.name); + sys::swapByteOrder(i.type); + sys::swapByteOrder(i.alignment); + sys::swapByteOrder(i.size); +} + +inline void swapStruct(struct objc_property_list64 &pl) { + sys::swapByteOrder(pl.entsize); + sys::swapByteOrder(pl.count); +} + +inline void swapStruct(struct objc_property_list32 &pl) { + sys::swapByteOrder(pl.entsize); + sys::swapByteOrder(pl.count); +} + +inline void swapStruct(struct objc_property64 &op) { + sys::swapByteOrder(op.name); + sys::swapByteOrder(op.attributes); +} + +inline void swapStruct(struct objc_property32 &op) { + sys::swapByteOrder(op.name); + sys::swapByteOrder(op.attributes); +} + +inline void swapStruct(struct category64_t &c) { + sys::swapByteOrder(c.name); + sys::swapByteOrder(c.cls); + sys::swapByteOrder(c.instanceMethods); + sys::swapByteOrder(c.classMethods); + sys::swapByteOrder(c.protocols); + sys::swapByteOrder(c.instanceProperties); +} + +inline void swapStruct(struct category32_t &c) { + sys::swapByteOrder(c.name); + sys::swapByteOrder(c.cls); + sys::swapByteOrder(c.instanceMethods); + sys::swapByteOrder(c.classMethods); + sys::swapByteOrder(c.protocols); + sys::swapByteOrder(c.instanceProperties); +} + +inline void swapStruct(struct objc_image_info64 &o) { + sys::swapByteOrder(o.version); + sys::swapByteOrder(o.flags); +} + +inline void swapStruct(struct objc_image_info32 &o) { + sys::swapByteOrder(o.version); + sys::swapByteOrder(o.flags); +} + +inline void swapStruct(struct imageInfo_t &o) { + sys::swapByteOrder(o.version); + sys::swapByteOrder(o.flags); +} + +inline void swapStruct(struct message_ref64 &mr) { + sys::swapByteOrder(mr.imp); + sys::swapByteOrder(mr.sel); +} + +inline void swapStruct(struct message_ref32 &mr) { + sys::swapByteOrder(mr.imp); + sys::swapByteOrder(mr.sel); +} + +inline void swapStruct(struct objc_module_t &module) { + sys::swapByteOrder(module.version); + sys::swapByteOrder(module.size); + sys::swapByteOrder(module.name); + sys::swapByteOrder(module.symtab); +} + +inline void swapStruct(struct objc_symtab_t &symtab) { + sys::swapByteOrder(symtab.sel_ref_cnt); + sys::swapByteOrder(symtab.refs); + sys::swapByteOrder(symtab.cls_def_cnt); + sys::swapByteOrder(symtab.cat_def_cnt); +} + +inline void swapStruct(struct objc_class_t &objc_class) { + sys::swapByteOrder(objc_class.isa); + sys::swapByteOrder(objc_class.super_class); + sys::swapByteOrder(objc_class.name); + sys::swapByteOrder(objc_class.version); + sys::swapByteOrder(objc_class.info); + sys::swapByteOrder(objc_class.instance_size); + sys::swapByteOrder(objc_class.ivars); + sys::swapByteOrder(objc_class.methodLists); + sys::swapByteOrder(objc_class.cache); + sys::swapByteOrder(objc_class.protocols); +} + +inline void swapStruct(struct objc_category_t &objc_category) { + sys::swapByteOrder(objc_category.category_name); + sys::swapByteOrder(objc_category.class_name); + sys::swapByteOrder(objc_category.instance_methods); + sys::swapByteOrder(objc_category.class_methods); + sys::swapByteOrder(objc_category.protocols); +} + +inline void swapStruct(struct objc_ivar_list_t &objc_ivar_list) { + sys::swapByteOrder(objc_ivar_list.ivar_count); +} + +inline void swapStruct(struct objc_ivar_t &objc_ivar) { + sys::swapByteOrder(objc_ivar.ivar_name); + sys::swapByteOrder(objc_ivar.ivar_type); + sys::swapByteOrder(objc_ivar.ivar_offset); +} + +inline void swapStruct(struct objc_method_list_t &method_list) { + sys::swapByteOrder(method_list.obsolete); + sys::swapByteOrder(method_list.method_count); +} + +inline void swapStruct(struct objc_method_t &method) { + sys::swapByteOrder(method.method_name); + sys::swapByteOrder(method.method_types); + sys::swapByteOrder(method.method_imp); +} + +inline void swapStruct(struct objc_protocol_list_t &protocol_list) { + sys::swapByteOrder(protocol_list.next); + sys::swapByteOrder(protocol_list.count); +} + +inline void swapStruct(struct objc_protocol_t &protocol) { + sys::swapByteOrder(protocol.isa); + sys::swapByteOrder(protocol.protocol_name); + sys::swapByteOrder(protocol.protocol_list); + sys::swapByteOrder(protocol.instance_methods); + sys::swapByteOrder(protocol.class_methods); +} + +inline void swapStruct(struct objc_method_description_list_t &mdl) { + sys::swapByteOrder(mdl.count); +} + +inline void swapStruct(struct objc_method_description_t &md) { + sys::swapByteOrder(md.name); + sys::swapByteOrder(md.types); +} + +static const char *get_dyld_bind_info_symbolname(uint64_t ReferenceValue, + struct DisassembleInfo *info); + +// get_objc2_64bit_class_name() is used for disassembly and is passed a pointer +// to an Objective-C class and returns the class name. It is also passed the +// address of the pointer, so when the pointer is zero as it can be in an .o +// file, that is used to look for an external relocation entry with a symbol +// name. +static const char *get_objc2_64bit_class_name(uint64_t pointer_value, + uint64_t ReferenceValue, + struct DisassembleInfo *info) { + const char *r; + uint32_t offset, left; + SectionRef S; + + // The pointer_value can be 0 in an object file and have a relocation + // entry for the class symbol at the ReferenceValue (the address of the + // pointer). + if (pointer_value == 0) { + r = get_pointer_64(ReferenceValue, offset, left, S, info); + if (r == nullptr || left < sizeof(uint64_t)) + return nullptr; + uint64_t n_value; + const char *symbol_name = get_symbol_64(offset, S, info, n_value); + if (symbol_name == nullptr) + return nullptr; + const char *class_name = strrchr(symbol_name, '$'); + if (class_name != nullptr && class_name[1] == '_' && class_name[2] != '\0') + return class_name + 2; + else + return nullptr; + } + + // The case were the pointer_value is non-zero and points to a class defined + // in this Mach-O file. + r = get_pointer_64(pointer_value, offset, left, S, info); + if (r == nullptr || left < sizeof(struct class64_t)) + return nullptr; + struct class64_t c; + memcpy(&c, r, sizeof(struct class64_t)); + if (info->O->isLittleEndian() != sys::IsLittleEndianHost) + swapStruct(c); + if (c.data == 0) + return nullptr; + r = get_pointer_64(c.data, offset, left, S, info); + if (r == nullptr || left < sizeof(struct class_ro64_t)) + return nullptr; + struct class_ro64_t cro; + memcpy(&cro, r, sizeof(struct class_ro64_t)); + if (info->O->isLittleEndian() != sys::IsLittleEndianHost) + swapStruct(cro); + if (cro.name == 0) + return nullptr; + const char *name = get_pointer_64(cro.name, offset, left, S, info); + return name; +} + +// get_objc2_64bit_cfstring_name is used for disassembly and is passed a +// pointer to a cfstring and returns its name or nullptr. +static const char *get_objc2_64bit_cfstring_name(uint64_t ReferenceValue, + struct DisassembleInfo *info) { + const char *r, *name; + uint32_t offset, left; + SectionRef S; + struct cfstring64_t cfs; + uint64_t cfs_characters; + + r = get_pointer_64(ReferenceValue, offset, left, S, info); + if (r == nullptr || left < sizeof(struct cfstring64_t)) + return nullptr; + memcpy(&cfs, r, sizeof(struct cfstring64_t)); + if (info->O->isLittleEndian() != sys::IsLittleEndianHost) + swapStruct(cfs); + if (cfs.characters == 0) { + uint64_t n_value; + const char *symbol_name = get_symbol_64( + offset + offsetof(struct cfstring64_t, characters), S, info, n_value); + if (symbol_name == nullptr) + return nullptr; + cfs_characters = n_value; + } else + cfs_characters = cfs.characters; + name = get_pointer_64(cfs_characters, offset, left, S, info); + + return name; +} + +// get_objc2_64bit_selref() is used for disassembly and is passed a the address +// of a pointer to an Objective-C selector reference when the pointer value is +// zero as in a .o file and is likely to have a external relocation entry with +// who's symbol's n_value is the real pointer to the selector name. If that is +// the case the real pointer to the selector name is returned else 0 is +// returned +static uint64_t get_objc2_64bit_selref(uint64_t ReferenceValue, + struct DisassembleInfo *info) { + uint32_t offset, left; + SectionRef S; + + const char *r = get_pointer_64(ReferenceValue, offset, left, S, info); + if (r == nullptr || left < sizeof(uint64_t)) + return 0; + uint64_t n_value; + const char *symbol_name = get_symbol_64(offset, S, info, n_value); + if (symbol_name == nullptr) + return 0; + return n_value; +} + +static const SectionRef get_section(MachOObjectFile *O, const char *segname, + const char *sectname) { + for (const SectionRef &Section : O->sections()) { + StringRef SectName; + Section.getName(SectName); + DataRefImpl Ref = Section.getRawDataRefImpl(); + StringRef SegName = O->getSectionFinalSegmentName(Ref); + if (SegName == segname && SectName == sectname) + return Section; + } + return SectionRef(); +} + +static void +walk_pointer_list_64(const char *listname, const SectionRef S, + MachOObjectFile *O, struct DisassembleInfo *info, + void (*func)(uint64_t, struct DisassembleInfo *info)) { + if (S == SectionRef()) + return; + + StringRef SectName; + S.getName(SectName); + DataRefImpl Ref = S.getRawDataRefImpl(); + StringRef SegName = O->getSectionFinalSegmentName(Ref); + outs() << "Contents of (" << SegName << "," << SectName << ") section\n"; + + StringRef BytesStr; + S.getContents(BytesStr); + const char *Contents = reinterpret_cast(BytesStr.data()); + + for (uint32_t i = 0; i < S.getSize(); i += sizeof(uint64_t)) { + uint32_t left = S.getSize() - i; + uint32_t size = left < sizeof(uint64_t) ? left : sizeof(uint64_t); + uint64_t p = 0; + memcpy(&p, Contents + i, size); + if (i + sizeof(uint64_t) > S.getSize()) + outs() << listname << " list pointer extends past end of (" << SegName + << "," << SectName << ") section\n"; + outs() << format("%016" PRIx64, S.getAddress() + i) << " "; + + if (O->isLittleEndian() != sys::IsLittleEndianHost) + sys::swapByteOrder(p); + + uint64_t n_value = 0; + const char *name = get_symbol_64(i, S, info, n_value, p); + if (name == nullptr) + name = get_dyld_bind_info_symbolname(S.getAddress() + i, info); + + if (n_value != 0) { + outs() << format("0x%" PRIx64, n_value); + if (p != 0) + outs() << " + " << format("0x%" PRIx64, p); + } else + outs() << format("0x%" PRIx64, p); + if (name != nullptr) + outs() << " " << name; + outs() << "\n"; + + p += n_value; + if (func) + func(p, info); + } +} + +static void +walk_pointer_list_32(const char *listname, const SectionRef S, + MachOObjectFile *O, struct DisassembleInfo *info, + void (*func)(uint32_t, struct DisassembleInfo *info)) { + if (S == SectionRef()) + return; + + StringRef SectName; + S.getName(SectName); + DataRefImpl Ref = S.getRawDataRefImpl(); + StringRef SegName = O->getSectionFinalSegmentName(Ref); + outs() << "Contents of (" << SegName << "," << SectName << ") section\n"; + + StringRef BytesStr; + S.getContents(BytesStr); + const char *Contents = reinterpret_cast(BytesStr.data()); + + for (uint32_t i = 0; i < S.getSize(); i += sizeof(uint32_t)) { + uint32_t left = S.getSize() - i; + uint32_t size = left < sizeof(uint32_t) ? left : sizeof(uint32_t); + uint32_t p = 0; + memcpy(&p, Contents + i, size); + if (i + sizeof(uint32_t) > S.getSize()) + outs() << listname << " list pointer extends past end of (" << SegName + << "," << SectName << ") section\n"; + uint32_t Address = S.getAddress() + i; + outs() << format("%08" PRIx32, Address) << " "; + + if (O->isLittleEndian() != sys::IsLittleEndianHost) + sys::swapByteOrder(p); + outs() << format("0x%" PRIx32, p); + + const char *name = get_symbol_32(i, S, info, p); + if (name != nullptr) + outs() << " " << name; + outs() << "\n"; + + if (func) + func(p, info); + } +} + +static void print_layout_map(const char *layout_map, uint32_t left) { + if (layout_map == nullptr) + return; + outs() << " layout map: "; + do { + outs() << format("0x%02" PRIx32, (*layout_map) & 0xff) << " "; + left--; + layout_map++; + } while (*layout_map != '\0' && left != 0); + outs() << "\n"; +} + +static void print_layout_map64(uint64_t p, struct DisassembleInfo *info) { + uint32_t offset, left; + SectionRef S; + const char *layout_map; + + if (p == 0) + return; + layout_map = get_pointer_64(p, offset, left, S, info); + print_layout_map(layout_map, left); +} + +static void print_layout_map32(uint32_t p, struct DisassembleInfo *info) { + uint32_t offset, left; + SectionRef S; + const char *layout_map; + + if (p == 0) + return; + layout_map = get_pointer_32(p, offset, left, S, info); + print_layout_map(layout_map, left); +} + +static void print_method_list64_t(uint64_t p, struct DisassembleInfo *info, + const char *indent) { + struct method_list64_t ml; + struct method64_t m; + const char *r; + uint32_t offset, xoffset, left, i; + SectionRef S, xS; + const char *name, *sym_name; + uint64_t n_value; + + r = get_pointer_64(p, offset, left, S, info); + if (r == nullptr) + return; + memset(&ml, '\0', sizeof(struct method_list64_t)); + if (left < sizeof(struct method_list64_t)) { + memcpy(&ml, r, left); + outs() << " (method_list_t entends past the end of the section)\n"; + } else + memcpy(&ml, r, sizeof(struct method_list64_t)); + if (info->O->isLittleEndian() != sys::IsLittleEndianHost) + swapStruct(ml); + outs() << indent << "\t\t entsize " << ml.entsize << "\n"; + outs() << indent << "\t\t count " << ml.count << "\n"; + + p += sizeof(struct method_list64_t); + offset += sizeof(struct method_list64_t); + for (i = 0; i < ml.count; i++) { + r = get_pointer_64(p, offset, left, S, info); + if (r == nullptr) + return; + memset(&m, '\0', sizeof(struct method64_t)); + if (left < sizeof(struct method64_t)) { + memcpy(&m, r, left); + outs() << indent << " (method_t extends past the end of the section)\n"; + } else + memcpy(&m, r, sizeof(struct method64_t)); + if (info->O->isLittleEndian() != sys::IsLittleEndianHost) + swapStruct(m); + + outs() << indent << "\t\t name "; + sym_name = get_symbol_64(offset + offsetof(struct method64_t, name), S, + info, n_value, m.name); + if (n_value != 0) { + if (info->verbose && sym_name != nullptr) + outs() << sym_name; + else + outs() << format("0x%" PRIx64, n_value); + if (m.name != 0) + outs() << " + " << format("0x%" PRIx64, m.name); + } else + outs() << format("0x%" PRIx64, m.name); + name = get_pointer_64(m.name + n_value, xoffset, left, xS, info); + if (name != nullptr) + outs() << format(" %.*s", left, name); + outs() << "\n"; + + outs() << indent << "\t\t types "; + sym_name = get_symbol_64(offset + offsetof(struct method64_t, types), S, + info, n_value, m.types); + if (n_value != 0) { + if (info->verbose && sym_name != nullptr) + outs() << sym_name; + else + outs() << format("0x%" PRIx64, n_value); + if (m.types != 0) + outs() << " + " << format("0x%" PRIx64, m.types); + } else + outs() << format("0x%" PRIx64, m.types); + name = get_pointer_64(m.types + n_value, xoffset, left, xS, info); + if (name != nullptr) + outs() << format(" %.*s", left, name); + outs() << "\n"; + + outs() << indent << "\t\t imp "; + name = get_symbol_64(offset + offsetof(struct method64_t, imp), S, info, + n_value, m.imp); + if (info->verbose && name == nullptr) { + if (n_value != 0) { + outs() << format("0x%" PRIx64, n_value) << " "; + if (m.imp != 0) + outs() << "+ " << format("0x%" PRIx64, m.imp) << " "; + } else + outs() << format("0x%" PRIx64, m.imp) << " "; + } + if (name != nullptr) + outs() << name; + outs() << "\n"; + + p += sizeof(struct method64_t); + offset += sizeof(struct method64_t); + } +} + +static void print_method_list32_t(uint64_t p, struct DisassembleInfo *info, + const char *indent) { + struct method_list32_t ml; + struct method32_t m; + const char *r, *name; + uint32_t offset, xoffset, left, i; + SectionRef S, xS; + + r = get_pointer_32(p, offset, left, S, info); + if (r == nullptr) + return; + memset(&ml, '\0', sizeof(struct method_list32_t)); + if (left < sizeof(struct method_list32_t)) { + memcpy(&ml, r, left); + outs() << " (method_list_t entends past the end of the section)\n"; + } else + memcpy(&ml, r, sizeof(struct method_list32_t)); + if (info->O->isLittleEndian() != sys::IsLittleEndianHost) + swapStruct(ml); + outs() << indent << "\t\t entsize " << ml.entsize << "\n"; + outs() << indent << "\t\t count " << ml.count << "\n"; + + p += sizeof(struct method_list32_t); + offset += sizeof(struct method_list32_t); + for (i = 0; i < ml.count; i++) { + r = get_pointer_32(p, offset, left, S, info); + if (r == nullptr) + return; + memset(&m, '\0', sizeof(struct method32_t)); + if (left < sizeof(struct method32_t)) { + memcpy(&ml, r, left); + outs() << indent << " (method_t entends past the end of the section)\n"; + } else + memcpy(&m, r, sizeof(struct method32_t)); + if (info->O->isLittleEndian() != sys::IsLittleEndianHost) + swapStruct(m); + + outs() << indent << "\t\t name " << format("0x%" PRIx32, m.name); + name = get_pointer_32(m.name, xoffset, left, xS, info); + if (name != nullptr) + outs() << format(" %.*s", left, name); + outs() << "\n"; + + outs() << indent << "\t\t types " << format("0x%" PRIx32, m.types); + name = get_pointer_32(m.types, xoffset, left, xS, info); + if (name != nullptr) + outs() << format(" %.*s", left, name); + outs() << "\n"; + + outs() << indent << "\t\t imp " << format("0x%" PRIx32, m.imp); + name = get_symbol_32(offset + offsetof(struct method32_t, imp), S, info, + m.imp); + if (name != nullptr) + outs() << " " << name; + outs() << "\n"; + + p += sizeof(struct method32_t); + offset += sizeof(struct method32_t); + } +} + +static bool print_method_list(uint32_t p, struct DisassembleInfo *info) { + uint32_t offset, left, xleft; + SectionRef S; + struct objc_method_list_t method_list; + struct objc_method_t method; + const char *r, *methods, *name, *SymbolName; + int32_t i; + + r = get_pointer_32(p, offset, left, S, info, true); + if (r == nullptr) + return true; + + outs() << "\n"; + if (left > sizeof(struct objc_method_list_t)) { + memcpy(&method_list, r, sizeof(struct objc_method_list_t)); + } else { + outs() << "\t\t objc_method_list extends past end of the section\n"; + memset(&method_list, '\0', sizeof(struct objc_method_list_t)); + memcpy(&method_list, r, left); + } + if (info->O->isLittleEndian() != sys::IsLittleEndianHost) + swapStruct(method_list); + + outs() << "\t\t obsolete " + << format("0x%08" PRIx32, method_list.obsolete) << "\n"; + outs() << "\t\t method_count " << method_list.method_count << "\n"; + + methods = r + sizeof(struct objc_method_list_t); + for (i = 0; i < method_list.method_count; i++) { + if ((i + 1) * sizeof(struct objc_method_t) > left) { + outs() << "\t\t remaining method's extend past the of the section\n"; + break; + } + memcpy(&method, methods + i * sizeof(struct objc_method_t), + sizeof(struct objc_method_t)); + if (info->O->isLittleEndian() != sys::IsLittleEndianHost) + swapStruct(method); + + outs() << "\t\t method_name " + << format("0x%08" PRIx32, method.method_name); + if (info->verbose) { + name = get_pointer_32(method.method_name, offset, xleft, S, info, true); + if (name != nullptr) + outs() << format(" %.*s", xleft, name); + else + outs() << " (not in an __OBJC section)"; + } + outs() << "\n"; + + outs() << "\t\t method_types " + << format("0x%08" PRIx32, method.method_types); + if (info->verbose) { + name = get_pointer_32(method.method_types, offset, xleft, S, info, true); + if (name != nullptr) + outs() << format(" %.*s", xleft, name); + else + outs() << " (not in an __OBJC section)"; + } + outs() << "\n"; + + outs() << "\t\t method_imp " + << format("0x%08" PRIx32, method.method_imp) << " "; + if (info->verbose) { + SymbolName = GuessSymbolName(method.method_imp, info->AddrMap); + if (SymbolName != nullptr) + outs() << SymbolName; + } + outs() << "\n"; + } + return false; +} + +static void print_protocol_list64_t(uint64_t p, struct DisassembleInfo *info) { + struct protocol_list64_t pl; + uint64_t q, n_value; + struct protocol64_t pc; + const char *r; + uint32_t offset, xoffset, left, i; + SectionRef S, xS; + const char *name, *sym_name; + + r = get_pointer_64(p, offset, left, S, info); + if (r == nullptr) + return; + memset(&pl, '\0', sizeof(struct protocol_list64_t)); + if (left < sizeof(struct protocol_list64_t)) { + memcpy(&pl, r, left); + outs() << " (protocol_list_t entends past the end of the section)\n"; + } else + memcpy(&pl, r, sizeof(struct protocol_list64_t)); + if (info->O->isLittleEndian() != sys::IsLittleEndianHost) + swapStruct(pl); + outs() << " count " << pl.count << "\n"; + + p += sizeof(struct protocol_list64_t); + offset += sizeof(struct protocol_list64_t); + for (i = 0; i < pl.count; i++) { + r = get_pointer_64(p, offset, left, S, info); + if (r == nullptr) + return; + q = 0; + if (left < sizeof(uint64_t)) { + memcpy(&q, r, left); + outs() << " (protocol_t * entends past the end of the section)\n"; + } else + memcpy(&q, r, sizeof(uint64_t)); + if (info->O->isLittleEndian() != sys::IsLittleEndianHost) + sys::swapByteOrder(q); + + outs() << "\t\t list[" << i << "] "; + sym_name = get_symbol_64(offset, S, info, n_value, q); + if (n_value != 0) { + if (info->verbose && sym_name != nullptr) + outs() << sym_name; + else + outs() << format("0x%" PRIx64, n_value); + if (q != 0) + outs() << " + " << format("0x%" PRIx64, q); + } else + outs() << format("0x%" PRIx64, q); + outs() << " (struct protocol_t *)\n"; + + r = get_pointer_64(q + n_value, offset, left, S, info); + if (r == nullptr) + return; + memset(&pc, '\0', sizeof(struct protocol64_t)); + if (left < sizeof(struct protocol64_t)) { + memcpy(&pc, r, left); + outs() << " (protocol_t entends past the end of the section)\n"; + } else + memcpy(&pc, r, sizeof(struct protocol64_t)); + if (info->O->isLittleEndian() != sys::IsLittleEndianHost) + swapStruct(pc); + + outs() << "\t\t\t isa " << format("0x%" PRIx64, pc.isa) << "\n"; + + outs() << "\t\t\t name "; + sym_name = get_symbol_64(offset + offsetof(struct protocol64_t, name), S, + info, n_value, pc.name); + if (n_value != 0) { + if (info->verbose && sym_name != nullptr) + outs() << sym_name; + else + outs() << format("0x%" PRIx64, n_value); + if (pc.name != 0) + outs() << " + " << format("0x%" PRIx64, pc.name); + } else + outs() << format("0x%" PRIx64, pc.name); + name = get_pointer_64(pc.name + n_value, xoffset, left, xS, info); + if (name != nullptr) + outs() << format(" %.*s", left, name); + outs() << "\n"; + + outs() << "\t\t\tprotocols " << format("0x%" PRIx64, pc.protocols) << "\n"; + + outs() << "\t\t instanceMethods "; + sym_name = + get_symbol_64(offset + offsetof(struct protocol64_t, instanceMethods), + S, info, n_value, pc.instanceMethods); + if (n_value != 0) { + if (info->verbose && sym_name != nullptr) + outs() << sym_name; + else + outs() << format("0x%" PRIx64, n_value); + if (pc.instanceMethods != 0) + outs() << " + " << format("0x%" PRIx64, pc.instanceMethods); + } else + outs() << format("0x%" PRIx64, pc.instanceMethods); + outs() << " (struct method_list_t *)\n"; + if (pc.instanceMethods + n_value != 0) + print_method_list64_t(pc.instanceMethods + n_value, info, "\t"); + + outs() << "\t\t classMethods "; + sym_name = + get_symbol_64(offset + offsetof(struct protocol64_t, classMethods), S, + info, n_value, pc.classMethods); + if (n_value != 0) { + if (info->verbose && sym_name != nullptr) + outs() << sym_name; + else + outs() << format("0x%" PRIx64, n_value); + if (pc.classMethods != 0) + outs() << " + " << format("0x%" PRIx64, pc.classMethods); + } else + outs() << format("0x%" PRIx64, pc.classMethods); + outs() << " (struct method_list_t *)\n"; + if (pc.classMethods + n_value != 0) + print_method_list64_t(pc.classMethods + n_value, info, "\t"); + + outs() << "\t optionalInstanceMethods " + << format("0x%" PRIx64, pc.optionalInstanceMethods) << "\n"; + outs() << "\t optionalClassMethods " + << format("0x%" PRIx64, pc.optionalClassMethods) << "\n"; + outs() << "\t instanceProperties " + << format("0x%" PRIx64, pc.instanceProperties) << "\n"; + + p += sizeof(uint64_t); + offset += sizeof(uint64_t); + } +} + +static void print_protocol_list32_t(uint32_t p, struct DisassembleInfo *info) { + struct protocol_list32_t pl; + uint32_t q; + struct protocol32_t pc; + const char *r; + uint32_t offset, xoffset, left, i; + SectionRef S, xS; + const char *name; + + r = get_pointer_32(p, offset, left, S, info); + if (r == nullptr) + return; + memset(&pl, '\0', sizeof(struct protocol_list32_t)); + if (left < sizeof(struct protocol_list32_t)) { + memcpy(&pl, r, left); + outs() << " (protocol_list_t entends past the end of the section)\n"; + } else + memcpy(&pl, r, sizeof(struct protocol_list32_t)); + if (info->O->isLittleEndian() != sys::IsLittleEndianHost) + swapStruct(pl); + outs() << " count " << pl.count << "\n"; + + p += sizeof(struct protocol_list32_t); + offset += sizeof(struct protocol_list32_t); + for (i = 0; i < pl.count; i++) { + r = get_pointer_32(p, offset, left, S, info); + if (r == nullptr) + return; + q = 0; + if (left < sizeof(uint32_t)) { + memcpy(&q, r, left); + outs() << " (protocol_t * entends past the end of the section)\n"; + } else + memcpy(&q, r, sizeof(uint32_t)); + if (info->O->isLittleEndian() != sys::IsLittleEndianHost) + sys::swapByteOrder(q); + outs() << "\t\t list[" << i << "] " << format("0x%" PRIx32, q) + << " (struct protocol_t *)\n"; + r = get_pointer_32(q, offset, left, S, info); + if (r == nullptr) + return; + memset(&pc, '\0', sizeof(struct protocol32_t)); + if (left < sizeof(struct protocol32_t)) { + memcpy(&pc, r, left); + outs() << " (protocol_t entends past the end of the section)\n"; + } else + memcpy(&pc, r, sizeof(struct protocol32_t)); + if (info->O->isLittleEndian() != sys::IsLittleEndianHost) + swapStruct(pc); + outs() << "\t\t\t isa " << format("0x%" PRIx32, pc.isa) << "\n"; + outs() << "\t\t\t name " << format("0x%" PRIx32, pc.name); + name = get_pointer_32(pc.name, xoffset, left, xS, info); + if (name != nullptr) + outs() << format(" %.*s", left, name); + outs() << "\n"; + outs() << "\t\t\tprotocols " << format("0x%" PRIx32, pc.protocols) << "\n"; + outs() << "\t\t instanceMethods " + << format("0x%" PRIx32, pc.instanceMethods) + << " (struct method_list_t *)\n"; + if (pc.instanceMethods != 0) + print_method_list32_t(pc.instanceMethods, info, "\t"); + outs() << "\t\t classMethods " << format("0x%" PRIx32, pc.classMethods) + << " (struct method_list_t *)\n"; + if (pc.classMethods != 0) + print_method_list32_t(pc.classMethods, info, "\t"); + outs() << "\t optionalInstanceMethods " + << format("0x%" PRIx32, pc.optionalInstanceMethods) << "\n"; + outs() << "\t optionalClassMethods " + << format("0x%" PRIx32, pc.optionalClassMethods) << "\n"; + outs() << "\t instanceProperties " + << format("0x%" PRIx32, pc.instanceProperties) << "\n"; + p += sizeof(uint32_t); + offset += sizeof(uint32_t); + } +} + +static void print_indent(uint32_t indent) { + for (uint32_t i = 0; i < indent;) { + if (indent - i >= 8) { + outs() << "\t"; + i += 8; + } else { + for (uint32_t j = i; j < indent; j++) + outs() << " "; + return; + } + } +} + +static bool print_method_description_list(uint32_t p, uint32_t indent, + struct DisassembleInfo *info) { + uint32_t offset, left, xleft; + SectionRef S; + struct objc_method_description_list_t mdl; + struct objc_method_description_t md; + const char *r, *list, *name; + int32_t i; + + r = get_pointer_32(p, offset, left, S, info, true); + if (r == nullptr) + return true; + + outs() << "\n"; + if (left > sizeof(struct objc_method_description_list_t)) { + memcpy(&mdl, r, sizeof(struct objc_method_description_list_t)); + } else { + print_indent(indent); + outs() << " objc_method_description_list extends past end of the section\n"; + memset(&mdl, '\0', sizeof(struct objc_method_description_list_t)); + memcpy(&mdl, r, left); + } + if (info->O->isLittleEndian() != sys::IsLittleEndianHost) + swapStruct(mdl); + + print_indent(indent); + outs() << " count " << mdl.count << "\n"; + + list = r + sizeof(struct objc_method_description_list_t); + for (i = 0; i < mdl.count; i++) { + if ((i + 1) * sizeof(struct objc_method_description_t) > left) { + print_indent(indent); + outs() << " remaining list entries extend past the of the section\n"; + break; + } + print_indent(indent); + outs() << " list[" << i << "]\n"; + memcpy(&md, list + i * sizeof(struct objc_method_description_t), + sizeof(struct objc_method_description_t)); + if (info->O->isLittleEndian() != sys::IsLittleEndianHost) + swapStruct(md); + + print_indent(indent); + outs() << " name " << format("0x%08" PRIx32, md.name); + if (info->verbose) { + name = get_pointer_32(md.name, offset, xleft, S, info, true); + if (name != nullptr) + outs() << format(" %.*s", xleft, name); + else + outs() << " (not in an __OBJC section)"; + } + outs() << "\n"; + + print_indent(indent); + outs() << " types " << format("0x%08" PRIx32, md.types); + if (info->verbose) { + name = get_pointer_32(md.types, offset, xleft, S, info, true); + if (name != nullptr) + outs() << format(" %.*s", xleft, name); + else + outs() << " (not in an __OBJC section)"; + } + outs() << "\n"; + } + return false; +} + +static bool print_protocol_list(uint32_t p, uint32_t indent, + struct DisassembleInfo *info); + +static bool print_protocol(uint32_t p, uint32_t indent, + struct DisassembleInfo *info) { + uint32_t offset, left; + SectionRef S; + struct objc_protocol_t protocol; + const char *r, *name; + + r = get_pointer_32(p, offset, left, S, info, true); + if (r == nullptr) + return true; + + outs() << "\n"; + if (left >= sizeof(struct objc_protocol_t)) { + memcpy(&protocol, r, sizeof(struct objc_protocol_t)); + } else { + print_indent(indent); + outs() << " Protocol extends past end of the section\n"; + memset(&protocol, '\0', sizeof(struct objc_protocol_t)); + memcpy(&protocol, r, left); + } + if (info->O->isLittleEndian() != sys::IsLittleEndianHost) + swapStruct(protocol); + + print_indent(indent); + outs() << " isa " << format("0x%08" PRIx32, protocol.isa) + << "\n"; + + print_indent(indent); + outs() << " protocol_name " + << format("0x%08" PRIx32, protocol.protocol_name); + if (info->verbose) { + name = get_pointer_32(protocol.protocol_name, offset, left, S, info, true); + if (name != nullptr) + outs() << format(" %.*s", left, name); + else + outs() << " (not in an __OBJC section)"; + } + outs() << "\n"; + + print_indent(indent); + outs() << " protocol_list " + << format("0x%08" PRIx32, protocol.protocol_list); + if (print_protocol_list(protocol.protocol_list, indent + 4, info)) + outs() << " (not in an __OBJC section)\n"; + + print_indent(indent); + outs() << " instance_methods " + << format("0x%08" PRIx32, protocol.instance_methods); + if (print_method_description_list(protocol.instance_methods, indent, info)) + outs() << " (not in an __OBJC section)\n"; + + print_indent(indent); + outs() << " class_methods " + << format("0x%08" PRIx32, protocol.class_methods); + if (print_method_description_list(protocol.class_methods, indent, info)) + outs() << " (not in an __OBJC section)\n"; + + return false; +} + +static bool print_protocol_list(uint32_t p, uint32_t indent, + struct DisassembleInfo *info) { + uint32_t offset, left, l; + SectionRef S; + struct objc_protocol_list_t protocol_list; + const char *r, *list; + int32_t i; + + r = get_pointer_32(p, offset, left, S, info, true); + if (r == nullptr) + return true; + + outs() << "\n"; + if (left > sizeof(struct objc_protocol_list_t)) { + memcpy(&protocol_list, r, sizeof(struct objc_protocol_list_t)); + } else { + outs() << "\t\t objc_protocol_list_t extends past end of the section\n"; + memset(&protocol_list, '\0', sizeof(struct objc_protocol_list_t)); + memcpy(&protocol_list, r, left); + } + if (info->O->isLittleEndian() != sys::IsLittleEndianHost) + swapStruct(protocol_list); + + print_indent(indent); + outs() << " next " << format("0x%08" PRIx32, protocol_list.next) + << "\n"; + print_indent(indent); + outs() << " count " << protocol_list.count << "\n"; + + list = r + sizeof(struct objc_protocol_list_t); + for (i = 0; i < protocol_list.count; i++) { + if ((i + 1) * sizeof(uint32_t) > left) { + outs() << "\t\t remaining list entries extend past the of the section\n"; + break; + } + memcpy(&l, list + i * sizeof(uint32_t), sizeof(uint32_t)); + if (info->O->isLittleEndian() != sys::IsLittleEndianHost) + sys::swapByteOrder(l); + + print_indent(indent); + outs() << " list[" << i << "] " << format("0x%08" PRIx32, l); + if (print_protocol(l, indent, info)) + outs() << "(not in an __OBJC section)\n"; + } + return false; +} + +static void print_ivar_list64_t(uint64_t p, struct DisassembleInfo *info) { + struct ivar_list64_t il; + struct ivar64_t i; + const char *r; + uint32_t offset, xoffset, left, j; + SectionRef S, xS; + const char *name, *sym_name, *ivar_offset_p; + uint64_t ivar_offset, n_value; + + r = get_pointer_64(p, offset, left, S, info); + if (r == nullptr) + return; + memset(&il, '\0', sizeof(struct ivar_list64_t)); + if (left < sizeof(struct ivar_list64_t)) { + memcpy(&il, r, left); + outs() << " (ivar_list_t entends past the end of the section)\n"; + } else + memcpy(&il, r, sizeof(struct ivar_list64_t)); + if (info->O->isLittleEndian() != sys::IsLittleEndianHost) + swapStruct(il); + outs() << " entsize " << il.entsize << "\n"; + outs() << " count " << il.count << "\n"; + + p += sizeof(struct ivar_list64_t); + offset += sizeof(struct ivar_list64_t); + for (j = 0; j < il.count; j++) { + r = get_pointer_64(p, offset, left, S, info); + if (r == nullptr) + return; + memset(&i, '\0', sizeof(struct ivar64_t)); + if (left < sizeof(struct ivar64_t)) { + memcpy(&i, r, left); + outs() << " (ivar_t entends past the end of the section)\n"; + } else + memcpy(&i, r, sizeof(struct ivar64_t)); + if (info->O->isLittleEndian() != sys::IsLittleEndianHost) + swapStruct(i); + + outs() << "\t\t\t offset "; + sym_name = get_symbol_64(offset + offsetof(struct ivar64_t, offset), S, + info, n_value, i.offset); + if (n_value != 0) { + if (info->verbose && sym_name != nullptr) + outs() << sym_name; + else + outs() << format("0x%" PRIx64, n_value); + if (i.offset != 0) + outs() << " + " << format("0x%" PRIx64, i.offset); + } else + outs() << format("0x%" PRIx64, i.offset); + ivar_offset_p = get_pointer_64(i.offset + n_value, xoffset, left, xS, info); + if (ivar_offset_p != nullptr && left >= sizeof(*ivar_offset_p)) { + memcpy(&ivar_offset, ivar_offset_p, sizeof(ivar_offset)); + if (info->O->isLittleEndian() != sys::IsLittleEndianHost) + sys::swapByteOrder(ivar_offset); + outs() << " " << ivar_offset << "\n"; + } else + outs() << "\n"; + + outs() << "\t\t\t name "; + sym_name = get_symbol_64(offset + offsetof(struct ivar64_t, name), S, info, + n_value, i.name); + if (n_value != 0) { + if (info->verbose && sym_name != nullptr) + outs() << sym_name; + else + outs() << format("0x%" PRIx64, n_value); + if (i.name != 0) + outs() << " + " << format("0x%" PRIx64, i.name); + } else + outs() << format("0x%" PRIx64, i.name); + name = get_pointer_64(i.name + n_value, xoffset, left, xS, info); + if (name != nullptr) + outs() << format(" %.*s", left, name); + outs() << "\n"; + + outs() << "\t\t\t type "; + sym_name = get_symbol_64(offset + offsetof(struct ivar64_t, type), S, info, + n_value, i.name); + name = get_pointer_64(i.type + n_value, xoffset, left, xS, info); + if (n_value != 0) { + if (info->verbose && sym_name != nullptr) + outs() << sym_name; + else + outs() << format("0x%" PRIx64, n_value); + if (i.type != 0) + outs() << " + " << format("0x%" PRIx64, i.type); + } else + outs() << format("0x%" PRIx64, i.type); + if (name != nullptr) + outs() << format(" %.*s", left, name); + outs() << "\n"; + + outs() << "\t\t\talignment " << i.alignment << "\n"; + outs() << "\t\t\t size " << i.size << "\n"; + + p += sizeof(struct ivar64_t); + offset += sizeof(struct ivar64_t); + } +} + +static void print_ivar_list32_t(uint32_t p, struct DisassembleInfo *info) { + struct ivar_list32_t il; + struct ivar32_t i; + const char *r; + uint32_t offset, xoffset, left, j; + SectionRef S, xS; + const char *name, *ivar_offset_p; + uint32_t ivar_offset; + + r = get_pointer_32(p, offset, left, S, info); + if (r == nullptr) + return; + memset(&il, '\0', sizeof(struct ivar_list32_t)); + if (left < sizeof(struct ivar_list32_t)) { + memcpy(&il, r, left); + outs() << " (ivar_list_t entends past the end of the section)\n"; + } else + memcpy(&il, r, sizeof(struct ivar_list32_t)); + if (info->O->isLittleEndian() != sys::IsLittleEndianHost) + swapStruct(il); + outs() << " entsize " << il.entsize << "\n"; + outs() << " count " << il.count << "\n"; + + p += sizeof(struct ivar_list32_t); + offset += sizeof(struct ivar_list32_t); + for (j = 0; j < il.count; j++) { + r = get_pointer_32(p, offset, left, S, info); + if (r == nullptr) + return; + memset(&i, '\0', sizeof(struct ivar32_t)); + if (left < sizeof(struct ivar32_t)) { + memcpy(&i, r, left); + outs() << " (ivar_t entends past the end of the section)\n"; + } else + memcpy(&i, r, sizeof(struct ivar32_t)); + if (info->O->isLittleEndian() != sys::IsLittleEndianHost) + swapStruct(i); + + outs() << "\t\t\t offset " << format("0x%" PRIx32, i.offset); + ivar_offset_p = get_pointer_32(i.offset, xoffset, left, xS, info); + if (ivar_offset_p != nullptr && left >= sizeof(*ivar_offset_p)) { + memcpy(&ivar_offset, ivar_offset_p, sizeof(ivar_offset)); + if (info->O->isLittleEndian() != sys::IsLittleEndianHost) + sys::swapByteOrder(ivar_offset); + outs() << " " << ivar_offset << "\n"; + } else + outs() << "\n"; + + outs() << "\t\t\t name " << format("0x%" PRIx32, i.name); + name = get_pointer_32(i.name, xoffset, left, xS, info); + if (name != nullptr) + outs() << format(" %.*s", left, name); + outs() << "\n"; + + outs() << "\t\t\t type " << format("0x%" PRIx32, i.type); + name = get_pointer_32(i.type, xoffset, left, xS, info); + if (name != nullptr) + outs() << format(" %.*s", left, name); + outs() << "\n"; + + outs() << "\t\t\talignment " << i.alignment << "\n"; + outs() << "\t\t\t size " << i.size << "\n"; + + p += sizeof(struct ivar32_t); + offset += sizeof(struct ivar32_t); + } +} + +static void print_objc_property_list64(uint64_t p, + struct DisassembleInfo *info) { + struct objc_property_list64 opl; + struct objc_property64 op; + const char *r; + uint32_t offset, xoffset, left, j; + SectionRef S, xS; + const char *name, *sym_name; + uint64_t n_value; + + r = get_pointer_64(p, offset, left, S, info); + if (r == nullptr) + return; + memset(&opl, '\0', sizeof(struct objc_property_list64)); + if (left < sizeof(struct objc_property_list64)) { + memcpy(&opl, r, left); + outs() << " (objc_property_list entends past the end of the section)\n"; + } else + memcpy(&opl, r, sizeof(struct objc_property_list64)); + if (info->O->isLittleEndian() != sys::IsLittleEndianHost) + swapStruct(opl); + outs() << " entsize " << opl.entsize << "\n"; + outs() << " count " << opl.count << "\n"; + + p += sizeof(struct objc_property_list64); + offset += sizeof(struct objc_property_list64); + for (j = 0; j < opl.count; j++) { + r = get_pointer_64(p, offset, left, S, info); + if (r == nullptr) + return; + memset(&op, '\0', sizeof(struct objc_property64)); + if (left < sizeof(struct objc_property64)) { + memcpy(&op, r, left); + outs() << " (objc_property entends past the end of the section)\n"; + } else + memcpy(&op, r, sizeof(struct objc_property64)); + if (info->O->isLittleEndian() != sys::IsLittleEndianHost) + swapStruct(op); + + outs() << "\t\t\t name "; + sym_name = get_symbol_64(offset + offsetof(struct objc_property64, name), S, + info, n_value, op.name); + if (n_value != 0) { + if (info->verbose && sym_name != nullptr) + outs() << sym_name; + else + outs() << format("0x%" PRIx64, n_value); + if (op.name != 0) + outs() << " + " << format("0x%" PRIx64, op.name); + } else + outs() << format("0x%" PRIx64, op.name); + name = get_pointer_64(op.name + n_value, xoffset, left, xS, info); + if (name != nullptr) + outs() << format(" %.*s", left, name); + outs() << "\n"; + + outs() << "\t\t\tattributes "; + sym_name = + get_symbol_64(offset + offsetof(struct objc_property64, attributes), S, + info, n_value, op.attributes); + if (n_value != 0) { + if (info->verbose && sym_name != nullptr) + outs() << sym_name; + else + outs() << format("0x%" PRIx64, n_value); + if (op.attributes != 0) + outs() << " + " << format("0x%" PRIx64, op.attributes); + } else + outs() << format("0x%" PRIx64, op.attributes); + name = get_pointer_64(op.attributes + n_value, xoffset, left, xS, info); + if (name != nullptr) + outs() << format(" %.*s", left, name); + outs() << "\n"; + + p += sizeof(struct objc_property64); + offset += sizeof(struct objc_property64); + } +} + +static void print_objc_property_list32(uint32_t p, + struct DisassembleInfo *info) { + struct objc_property_list32 opl; + struct objc_property32 op; + const char *r; + uint32_t offset, xoffset, left, j; + SectionRef S, xS; + const char *name; + + r = get_pointer_32(p, offset, left, S, info); + if (r == nullptr) + return; + memset(&opl, '\0', sizeof(struct objc_property_list32)); + if (left < sizeof(struct objc_property_list32)) { + memcpy(&opl, r, left); + outs() << " (objc_property_list entends past the end of the section)\n"; + } else + memcpy(&opl, r, sizeof(struct objc_property_list32)); + if (info->O->isLittleEndian() != sys::IsLittleEndianHost) + swapStruct(opl); + outs() << " entsize " << opl.entsize << "\n"; + outs() << " count " << opl.count << "\n"; + + p += sizeof(struct objc_property_list32); + offset += sizeof(struct objc_property_list32); + for (j = 0; j < opl.count; j++) { + r = get_pointer_32(p, offset, left, S, info); + if (r == nullptr) + return; + memset(&op, '\0', sizeof(struct objc_property32)); + if (left < sizeof(struct objc_property32)) { + memcpy(&op, r, left); + outs() << " (objc_property entends past the end of the section)\n"; + } else + memcpy(&op, r, sizeof(struct objc_property32)); + if (info->O->isLittleEndian() != sys::IsLittleEndianHost) + swapStruct(op); + + outs() << "\t\t\t name " << format("0x%" PRIx32, op.name); + name = get_pointer_32(op.name, xoffset, left, xS, info); + if (name != nullptr) + outs() << format(" %.*s", left, name); + outs() << "\n"; + + outs() << "\t\t\tattributes " << format("0x%" PRIx32, op.attributes); + name = get_pointer_32(op.attributes, xoffset, left, xS, info); + if (name != nullptr) + outs() << format(" %.*s", left, name); + outs() << "\n"; + + p += sizeof(struct objc_property32); + offset += sizeof(struct objc_property32); + } +} + +static bool print_class_ro64_t(uint64_t p, struct DisassembleInfo *info, + bool &is_meta_class) { + struct class_ro64_t cro; + const char *r; + uint32_t offset, xoffset, left; + SectionRef S, xS; + const char *name, *sym_name; + uint64_t n_value; + + r = get_pointer_64(p, offset, left, S, info); + if (r == nullptr || left < sizeof(struct class_ro64_t)) + return false; + memcpy(&cro, r, sizeof(struct class_ro64_t)); + if (info->O->isLittleEndian() != sys::IsLittleEndianHost) + swapStruct(cro); + outs() << " flags " << format("0x%" PRIx32, cro.flags); + if (cro.flags & RO_META) + outs() << " RO_META"; + if (cro.flags & RO_ROOT) + outs() << " RO_ROOT"; + if (cro.flags & RO_HAS_CXX_STRUCTORS) + outs() << " RO_HAS_CXX_STRUCTORS"; + outs() << "\n"; + outs() << " instanceStart " << cro.instanceStart << "\n"; + outs() << " instanceSize " << cro.instanceSize << "\n"; + outs() << " reserved " << format("0x%" PRIx32, cro.reserved) + << "\n"; + outs() << " ivarLayout " << format("0x%" PRIx64, cro.ivarLayout) + << "\n"; + print_layout_map64(cro.ivarLayout, info); + + outs() << " name "; + sym_name = get_symbol_64(offset + offsetof(struct class_ro64_t, name), S, + info, n_value, cro.name); + if (n_value != 0) { + if (info->verbose && sym_name != nullptr) + outs() << sym_name; + else + outs() << format("0x%" PRIx64, n_value); + if (cro.name != 0) + outs() << " + " << format("0x%" PRIx64, cro.name); + } else + outs() << format("0x%" PRIx64, cro.name); + name = get_pointer_64(cro.name + n_value, xoffset, left, xS, info); + if (name != nullptr) + outs() << format(" %.*s", left, name); + outs() << "\n"; + + outs() << " baseMethods "; + sym_name = get_symbol_64(offset + offsetof(struct class_ro64_t, baseMethods), + S, info, n_value, cro.baseMethods); + if (n_value != 0) { + if (info->verbose && sym_name != nullptr) + outs() << sym_name; + else + outs() << format("0x%" PRIx64, n_value); + if (cro.baseMethods != 0) + outs() << " + " << format("0x%" PRIx64, cro.baseMethods); + } else + outs() << format("0x%" PRIx64, cro.baseMethods); + outs() << " (struct method_list_t *)\n"; + if (cro.baseMethods + n_value != 0) + print_method_list64_t(cro.baseMethods + n_value, info, ""); + + outs() << " baseProtocols "; + sym_name = + get_symbol_64(offset + offsetof(struct class_ro64_t, baseProtocols), S, + info, n_value, cro.baseProtocols); + if (n_value != 0) { + if (info->verbose && sym_name != nullptr) + outs() << sym_name; + else + outs() << format("0x%" PRIx64, n_value); + if (cro.baseProtocols != 0) + outs() << " + " << format("0x%" PRIx64, cro.baseProtocols); + } else + outs() << format("0x%" PRIx64, cro.baseProtocols); + outs() << "\n"; + if (cro.baseProtocols + n_value != 0) + print_protocol_list64_t(cro.baseProtocols + n_value, info); + + outs() << " ivars "; + sym_name = get_symbol_64(offset + offsetof(struct class_ro64_t, ivars), S, + info, n_value, cro.ivars); + if (n_value != 0) { + if (info->verbose && sym_name != nullptr) + outs() << sym_name; + else + outs() << format("0x%" PRIx64, n_value); + if (cro.ivars != 0) + outs() << " + " << format("0x%" PRIx64, cro.ivars); + } else + outs() << format("0x%" PRIx64, cro.ivars); + outs() << "\n"; + if (cro.ivars + n_value != 0) + print_ivar_list64_t(cro.ivars + n_value, info); + + outs() << " weakIvarLayout "; + sym_name = + get_symbol_64(offset + offsetof(struct class_ro64_t, weakIvarLayout), S, + info, n_value, cro.weakIvarLayout); + if (n_value != 0) { + if (info->verbose && sym_name != nullptr) + outs() << sym_name; + else + outs() << format("0x%" PRIx64, n_value); + if (cro.weakIvarLayout != 0) + outs() << " + " << format("0x%" PRIx64, cro.weakIvarLayout); + } else + outs() << format("0x%" PRIx64, cro.weakIvarLayout); + outs() << "\n"; + print_layout_map64(cro.weakIvarLayout + n_value, info); + + outs() << " baseProperties "; + sym_name = + get_symbol_64(offset + offsetof(struct class_ro64_t, baseProperties), S, + info, n_value, cro.baseProperties); + if (n_value != 0) { + if (info->verbose && sym_name != nullptr) + outs() << sym_name; + else + outs() << format("0x%" PRIx64, n_value); + if (cro.baseProperties != 0) + outs() << " + " << format("0x%" PRIx64, cro.baseProperties); + } else + outs() << format("0x%" PRIx64, cro.baseProperties); + outs() << "\n"; + if (cro.baseProperties + n_value != 0) + print_objc_property_list64(cro.baseProperties + n_value, info); + + is_meta_class = (cro.flags & RO_META) != 0; + return true; +} + +static bool print_class_ro32_t(uint32_t p, struct DisassembleInfo *info, + bool &is_meta_class) { + struct class_ro32_t cro; + const char *r; + uint32_t offset, xoffset, left; + SectionRef S, xS; + const char *name; + + r = get_pointer_32(p, offset, left, S, info); + if (r == nullptr) + return false; + memset(&cro, '\0', sizeof(struct class_ro32_t)); + if (left < sizeof(struct class_ro32_t)) { + memcpy(&cro, r, left); + outs() << " (class_ro_t entends past the end of the section)\n"; + } else + memcpy(&cro, r, sizeof(struct class_ro32_t)); + if (info->O->isLittleEndian() != sys::IsLittleEndianHost) + swapStruct(cro); + outs() << " flags " << format("0x%" PRIx32, cro.flags); + if (cro.flags & RO_META) + outs() << " RO_META"; + if (cro.flags & RO_ROOT) + outs() << " RO_ROOT"; + if (cro.flags & RO_HAS_CXX_STRUCTORS) + outs() << " RO_HAS_CXX_STRUCTORS"; + outs() << "\n"; + outs() << " instanceStart " << cro.instanceStart << "\n"; + outs() << " instanceSize " << cro.instanceSize << "\n"; + outs() << " ivarLayout " << format("0x%" PRIx32, cro.ivarLayout) + << "\n"; + print_layout_map32(cro.ivarLayout, info); + + outs() << " name " << format("0x%" PRIx32, cro.name); + name = get_pointer_32(cro.name, xoffset, left, xS, info); + if (name != nullptr) + outs() << format(" %.*s", left, name); + outs() << "\n"; + + outs() << " baseMethods " + << format("0x%" PRIx32, cro.baseMethods) + << " (struct method_list_t *)\n"; + if (cro.baseMethods != 0) + print_method_list32_t(cro.baseMethods, info, ""); + + outs() << " baseProtocols " + << format("0x%" PRIx32, cro.baseProtocols) << "\n"; + if (cro.baseProtocols != 0) + print_protocol_list32_t(cro.baseProtocols, info); + outs() << " ivars " << format("0x%" PRIx32, cro.ivars) + << "\n"; + if (cro.ivars != 0) + print_ivar_list32_t(cro.ivars, info); + outs() << " weakIvarLayout " + << format("0x%" PRIx32, cro.weakIvarLayout) << "\n"; + print_layout_map32(cro.weakIvarLayout, info); + outs() << " baseProperties " + << format("0x%" PRIx32, cro.baseProperties) << "\n"; + if (cro.baseProperties != 0) + print_objc_property_list32(cro.baseProperties, info); + is_meta_class = (cro.flags & RO_META) != 0; + return true; +} + +static void print_class64_t(uint64_t p, struct DisassembleInfo *info) { + struct class64_t c; + const char *r; + uint32_t offset, left; + SectionRef S; + const char *name; + uint64_t isa_n_value, n_value; + + r = get_pointer_64(p, offset, left, S, info); + if (r == nullptr || left < sizeof(struct class64_t)) + return; + memcpy(&c, r, sizeof(struct class64_t)); + if (info->O->isLittleEndian() != sys::IsLittleEndianHost) + swapStruct(c); + + outs() << " isa " << format("0x%" PRIx64, c.isa); + name = get_symbol_64(offset + offsetof(struct class64_t, isa), S, info, + isa_n_value, c.isa); + if (name != nullptr) + outs() << " " << name; + outs() << "\n"; + + outs() << " superclass " << format("0x%" PRIx64, c.superclass); + name = get_symbol_64(offset + offsetof(struct class64_t, superclass), S, info, + n_value, c.superclass); + if (name != nullptr) + outs() << " " << name; + else { + name = get_dyld_bind_info_symbolname( + S.getAddress() + offset + offsetof(struct class64_t, superclass), info); + if (name != nullptr) + outs() << " " << name; + } + outs() << "\n"; + + outs() << " cache " << format("0x%" PRIx64, c.cache); + name = get_symbol_64(offset + offsetof(struct class64_t, cache), S, info, + n_value, c.cache); + if (name != nullptr) + outs() << " " << name; + outs() << "\n"; + + outs() << " vtable " << format("0x%" PRIx64, c.vtable); + name = get_symbol_64(offset + offsetof(struct class64_t, vtable), S, info, + n_value, c.vtable); + if (name != nullptr) + outs() << " " << name; + outs() << "\n"; + + name = get_symbol_64(offset + offsetof(struct class64_t, data), S, info, + n_value, c.data); + outs() << " data "; + if (n_value != 0) { + if (info->verbose && name != nullptr) + outs() << name; + else + outs() << format("0x%" PRIx64, n_value); + if (c.data != 0) + outs() << " + " << format("0x%" PRIx64, c.data); + } else + outs() << format("0x%" PRIx64, c.data); + outs() << " (struct class_ro_t *)"; + + // This is a Swift class if some of the low bits of the pointer are set. + if ((c.data + n_value) & 0x7) + outs() << " Swift class"; + outs() << "\n"; + bool is_meta_class; + if (!print_class_ro64_t((c.data + n_value) & ~0x7, info, is_meta_class)) + return; + + if (!is_meta_class && c.isa + isa_n_value != p && c.isa + isa_n_value != 0 && + info->depth < 100) { + info->depth++; + outs() << "Meta Class\n"; + print_class64_t(c.isa + isa_n_value, info); + } +} + +static void print_class32_t(uint32_t p, struct DisassembleInfo *info) { + struct class32_t c; + const char *r; + uint32_t offset, left; + SectionRef S; + const char *name; + + r = get_pointer_32(p, offset, left, S, info); + if (r == nullptr) + return; + memset(&c, '\0', sizeof(struct class32_t)); + if (left < sizeof(struct class32_t)) { + memcpy(&c, r, left); + outs() << " (class_t entends past the end of the section)\n"; + } else + memcpy(&c, r, sizeof(struct class32_t)); + if (info->O->isLittleEndian() != sys::IsLittleEndianHost) + swapStruct(c); + + outs() << " isa " << format("0x%" PRIx32, c.isa); + name = + get_symbol_32(offset + offsetof(struct class32_t, isa), S, info, c.isa); + if (name != nullptr) + outs() << " " << name; + outs() << "\n"; + + outs() << " superclass " << format("0x%" PRIx32, c.superclass); + name = get_symbol_32(offset + offsetof(struct class32_t, superclass), S, info, + c.superclass); + if (name != nullptr) + outs() << " " << name; + outs() << "\n"; + + outs() << " cache " << format("0x%" PRIx32, c.cache); + name = get_symbol_32(offset + offsetof(struct class32_t, cache), S, info, + c.cache); + if (name != nullptr) + outs() << " " << name; + outs() << "\n"; + + outs() << " vtable " << format("0x%" PRIx32, c.vtable); + name = get_symbol_32(offset + offsetof(struct class32_t, vtable), S, info, + c.vtable); + if (name != nullptr) + outs() << " " << name; + outs() << "\n"; + + name = + get_symbol_32(offset + offsetof(struct class32_t, data), S, info, c.data); + outs() << " data " << format("0x%" PRIx32, c.data) + << " (struct class_ro_t *)"; + + // This is a Swift class if some of the low bits of the pointer are set. + if (c.data & 0x3) + outs() << " Swift class"; + outs() << "\n"; + bool is_meta_class; + if (!print_class_ro32_t(c.data & ~0x3, info, is_meta_class)) + return; + + if (!is_meta_class) { + outs() << "Meta Class\n"; + print_class32_t(c.isa, info); + } +} + +static void print_objc_class_t(struct objc_class_t *objc_class, + struct DisassembleInfo *info) { + uint32_t offset, left, xleft; + const char *name, *p, *ivar_list; + SectionRef S; + int32_t i; + struct objc_ivar_list_t objc_ivar_list; + struct objc_ivar_t ivar; + + outs() << "\t\t isa " << format("0x%08" PRIx32, objc_class->isa); + if (info->verbose && CLS_GETINFO(objc_class, CLS_META)) { + name = get_pointer_32(objc_class->isa, offset, left, S, info, true); + if (name != nullptr) + outs() << format(" %.*s", left, name); + else + outs() << " (not in an __OBJC section)"; + } + outs() << "\n"; + + outs() << "\t super_class " + << format("0x%08" PRIx32, objc_class->super_class); + if (info->verbose) { + name = get_pointer_32(objc_class->super_class, offset, left, S, info, true); + if (name != nullptr) + outs() << format(" %.*s", left, name); + else + outs() << " (not in an __OBJC section)"; + } + outs() << "\n"; + + outs() << "\t\t name " << format("0x%08" PRIx32, objc_class->name); + if (info->verbose) { + name = get_pointer_32(objc_class->name, offset, left, S, info, true); + if (name != nullptr) + outs() << format(" %.*s", left, name); + else + outs() << " (not in an __OBJC section)"; + } + outs() << "\n"; + + outs() << "\t\t version " << format("0x%08" PRIx32, objc_class->version) + << "\n"; + + outs() << "\t\t info " << format("0x%08" PRIx32, objc_class->info); + if (info->verbose) { + if (CLS_GETINFO(objc_class, CLS_CLASS)) + outs() << " CLS_CLASS"; + else if (CLS_GETINFO(objc_class, CLS_META)) + outs() << " CLS_META"; + } + outs() << "\n"; + + outs() << "\t instance_size " + << format("0x%08" PRIx32, objc_class->instance_size) << "\n"; + + p = get_pointer_32(objc_class->ivars, offset, left, S, info, true); + outs() << "\t\t ivars " << format("0x%08" PRIx32, objc_class->ivars); + if (p != nullptr) { + if (left > sizeof(struct objc_ivar_list_t)) { + outs() << "\n"; + memcpy(&objc_ivar_list, p, sizeof(struct objc_ivar_list_t)); + } else { + outs() << " (entends past the end of the section)\n"; + memset(&objc_ivar_list, '\0', sizeof(struct objc_ivar_list_t)); + memcpy(&objc_ivar_list, p, left); + } + if (info->O->isLittleEndian() != sys::IsLittleEndianHost) + swapStruct(objc_ivar_list); + outs() << "\t\t ivar_count " << objc_ivar_list.ivar_count << "\n"; + ivar_list = p + sizeof(struct objc_ivar_list_t); + for (i = 0; i < objc_ivar_list.ivar_count; i++) { + if ((i + 1) * sizeof(struct objc_ivar_t) > left) { + outs() << "\t\t remaining ivar's extend past the of the section\n"; + break; + } + memcpy(&ivar, ivar_list + i * sizeof(struct objc_ivar_t), + sizeof(struct objc_ivar_t)); + if (info->O->isLittleEndian() != sys::IsLittleEndianHost) + swapStruct(ivar); + + outs() << "\t\t\tivar_name " << format("0x%08" PRIx32, ivar.ivar_name); + if (info->verbose) { + name = get_pointer_32(ivar.ivar_name, offset, xleft, S, info, true); + if (name != nullptr) + outs() << format(" %.*s", xleft, name); + else + outs() << " (not in an __OBJC section)"; + } + outs() << "\n"; + + outs() << "\t\t\tivar_type " << format("0x%08" PRIx32, ivar.ivar_type); + if (info->verbose) { + name = get_pointer_32(ivar.ivar_type, offset, xleft, S, info, true); + if (name != nullptr) + outs() << format(" %.*s", xleft, name); + else + outs() << " (not in an __OBJC section)"; + } + outs() << "\n"; + + outs() << "\t\t ivar_offset " + << format("0x%08" PRIx32, ivar.ivar_offset) << "\n"; + } + } else { + outs() << " (not in an __OBJC section)\n"; + } + + outs() << "\t\t methods " << format("0x%08" PRIx32, objc_class->methodLists); + if (print_method_list(objc_class->methodLists, info)) + outs() << " (not in an __OBJC section)\n"; + + outs() << "\t\t cache " << format("0x%08" PRIx32, objc_class->cache) + << "\n"; + + outs() << "\t\tprotocols " << format("0x%08" PRIx32, objc_class->protocols); + if (print_protocol_list(objc_class->protocols, 16, info)) + outs() << " (not in an __OBJC section)\n"; +} + +static void print_objc_objc_category_t(struct objc_category_t *objc_category, + struct DisassembleInfo *info) { + uint32_t offset, left; + const char *name; + SectionRef S; + + outs() << "\t category name " + << format("0x%08" PRIx32, objc_category->category_name); + if (info->verbose) { + name = get_pointer_32(objc_category->category_name, offset, left, S, info, + true); + if (name != nullptr) + outs() << format(" %.*s", left, name); + else + outs() << " (not in an __OBJC section)"; + } + outs() << "\n"; + + outs() << "\t\t class name " + << format("0x%08" PRIx32, objc_category->class_name); + if (info->verbose) { + name = + get_pointer_32(objc_category->class_name, offset, left, S, info, true); + if (name != nullptr) + outs() << format(" %.*s", left, name); + else + outs() << " (not in an __OBJC section)"; + } + outs() << "\n"; + + outs() << "\t instance methods " + << format("0x%08" PRIx32, objc_category->instance_methods); + if (print_method_list(objc_category->instance_methods, info)) + outs() << " (not in an __OBJC section)\n"; + + outs() << "\t class methods " + << format("0x%08" PRIx32, objc_category->class_methods); + if (print_method_list(objc_category->class_methods, info)) + outs() << " (not in an __OBJC section)\n"; +} + +static void print_category64_t(uint64_t p, struct DisassembleInfo *info) { + struct category64_t c; + const char *r; + uint32_t offset, xoffset, left; + SectionRef S, xS; + const char *name, *sym_name; + uint64_t n_value; + + r = get_pointer_64(p, offset, left, S, info); + if (r == nullptr) + return; + memset(&c, '\0', sizeof(struct category64_t)); + if (left < sizeof(struct category64_t)) { + memcpy(&c, r, left); + outs() << " (category_t entends past the end of the section)\n"; + } else + memcpy(&c, r, sizeof(struct category64_t)); + if (info->O->isLittleEndian() != sys::IsLittleEndianHost) + swapStruct(c); + + outs() << " name "; + sym_name = get_symbol_64(offset + offsetof(struct category64_t, name), S, + info, n_value, c.name); + if (n_value != 0) { + if (info->verbose && sym_name != nullptr) + outs() << sym_name; + else + outs() << format("0x%" PRIx64, n_value); + if (c.name != 0) + outs() << " + " << format("0x%" PRIx64, c.name); + } else + outs() << format("0x%" PRIx64, c.name); + name = get_pointer_64(c.name + n_value, xoffset, left, xS, info); + if (name != nullptr) + outs() << format(" %.*s", left, name); + outs() << "\n"; + + outs() << " cls "; + sym_name = get_symbol_64(offset + offsetof(struct category64_t, cls), S, info, + n_value, c.cls); + if (n_value != 0) { + if (info->verbose && sym_name != nullptr) + outs() << sym_name; + else + outs() << format("0x%" PRIx64, n_value); + if (c.cls != 0) + outs() << " + " << format("0x%" PRIx64, c.cls); + } else + outs() << format("0x%" PRIx64, c.cls); + outs() << "\n"; + if (c.cls + n_value != 0) + print_class64_t(c.cls + n_value, info); + + outs() << " instanceMethods "; + sym_name = + get_symbol_64(offset + offsetof(struct category64_t, instanceMethods), S, + info, n_value, c.instanceMethods); + if (n_value != 0) { + if (info->verbose && sym_name != nullptr) + outs() << sym_name; + else + outs() << format("0x%" PRIx64, n_value); + if (c.instanceMethods != 0) + outs() << " + " << format("0x%" PRIx64, c.instanceMethods); + } else + outs() << format("0x%" PRIx64, c.instanceMethods); + outs() << "\n"; + if (c.instanceMethods + n_value != 0) + print_method_list64_t(c.instanceMethods + n_value, info, ""); + + outs() << " classMethods "; + sym_name = get_symbol_64(offset + offsetof(struct category64_t, classMethods), + S, info, n_value, c.classMethods); + if (n_value != 0) { + if (info->verbose && sym_name != nullptr) + outs() << sym_name; + else + outs() << format("0x%" PRIx64, n_value); + if (c.classMethods != 0) + outs() << " + " << format("0x%" PRIx64, c.classMethods); + } else + outs() << format("0x%" PRIx64, c.classMethods); + outs() << "\n"; + if (c.classMethods + n_value != 0) + print_method_list64_t(c.classMethods + n_value, info, ""); + + outs() << " protocols "; + sym_name = get_symbol_64(offset + offsetof(struct category64_t, protocols), S, + info, n_value, c.protocols); + if (n_value != 0) { + if (info->verbose && sym_name != nullptr) + outs() << sym_name; + else + outs() << format("0x%" PRIx64, n_value); + if (c.protocols != 0) + outs() << " + " << format("0x%" PRIx64, c.protocols); + } else + outs() << format("0x%" PRIx64, c.protocols); + outs() << "\n"; + if (c.protocols + n_value != 0) + print_protocol_list64_t(c.protocols + n_value, info); + + outs() << "instanceProperties "; + sym_name = + get_symbol_64(offset + offsetof(struct category64_t, instanceProperties), + S, info, n_value, c.instanceProperties); + if (n_value != 0) { + if (info->verbose && sym_name != nullptr) + outs() << sym_name; + else + outs() << format("0x%" PRIx64, n_value); + if (c.instanceProperties != 0) + outs() << " + " << format("0x%" PRIx64, c.instanceProperties); + } else + outs() << format("0x%" PRIx64, c.instanceProperties); + outs() << "\n"; + if (c.instanceProperties + n_value != 0) + print_objc_property_list64(c.instanceProperties + n_value, info); +} + +static void print_category32_t(uint32_t p, struct DisassembleInfo *info) { + struct category32_t c; + const char *r; + uint32_t offset, left; + SectionRef S, xS; + const char *name; + + r = get_pointer_32(p, offset, left, S, info); + if (r == nullptr) + return; + memset(&c, '\0', sizeof(struct category32_t)); + if (left < sizeof(struct category32_t)) { + memcpy(&c, r, left); + outs() << " (category_t entends past the end of the section)\n"; + } else + memcpy(&c, r, sizeof(struct category32_t)); + if (info->O->isLittleEndian() != sys::IsLittleEndianHost) + swapStruct(c); + + outs() << " name " << format("0x%" PRIx32, c.name); + name = get_symbol_32(offset + offsetof(struct category32_t, name), S, info, + c.name); + if (name) + outs() << " " << name; + outs() << "\n"; + + outs() << " cls " << format("0x%" PRIx32, c.cls) << "\n"; + if (c.cls != 0) + print_class32_t(c.cls, info); + outs() << " instanceMethods " << format("0x%" PRIx32, c.instanceMethods) + << "\n"; + if (c.instanceMethods != 0) + print_method_list32_t(c.instanceMethods, info, ""); + outs() << " classMethods " << format("0x%" PRIx32, c.classMethods) + << "\n"; + if (c.classMethods != 0) + print_method_list32_t(c.classMethods, info, ""); + outs() << " protocols " << format("0x%" PRIx32, c.protocols) << "\n"; + if (c.protocols != 0) + print_protocol_list32_t(c.protocols, info); + outs() << "instanceProperties " << format("0x%" PRIx32, c.instanceProperties) + << "\n"; + if (c.instanceProperties != 0) + print_objc_property_list32(c.instanceProperties, info); +} + +static void print_message_refs64(SectionRef S, struct DisassembleInfo *info) { + uint32_t i, left, offset, xoffset; + uint64_t p, n_value; + struct message_ref64 mr; + const char *name, *sym_name; + const char *r; + SectionRef xS; + + if (S == SectionRef()) + return; + + StringRef SectName; + S.getName(SectName); + DataRefImpl Ref = S.getRawDataRefImpl(); + StringRef SegName = info->O->getSectionFinalSegmentName(Ref); + outs() << "Contents of (" << SegName << "," << SectName << ") section\n"; + offset = 0; + for (i = 0; i < S.getSize(); i += sizeof(struct message_ref64)) { + p = S.getAddress() + i; + r = get_pointer_64(p, offset, left, S, info); + if (r == nullptr) + return; + memset(&mr, '\0', sizeof(struct message_ref64)); + if (left < sizeof(struct message_ref64)) { + memcpy(&mr, r, left); + outs() << " (message_ref entends past the end of the section)\n"; + } else + memcpy(&mr, r, sizeof(struct message_ref64)); + if (info->O->isLittleEndian() != sys::IsLittleEndianHost) + swapStruct(mr); + + outs() << " imp "; + name = get_symbol_64(offset + offsetof(struct message_ref64, imp), S, info, + n_value, mr.imp); + if (n_value != 0) { + outs() << format("0x%" PRIx64, n_value) << " "; + if (mr.imp != 0) + outs() << "+ " << format("0x%" PRIx64, mr.imp) << " "; + } else + outs() << format("0x%" PRIx64, mr.imp) << " "; + if (name != nullptr) + outs() << " " << name; + outs() << "\n"; + + outs() << " sel "; + sym_name = get_symbol_64(offset + offsetof(struct message_ref64, sel), S, + info, n_value, mr.sel); + if (n_value != 0) { + if (info->verbose && sym_name != nullptr) + outs() << sym_name; + else + outs() << format("0x%" PRIx64, n_value); + if (mr.sel != 0) + outs() << " + " << format("0x%" PRIx64, mr.sel); + } else + outs() << format("0x%" PRIx64, mr.sel); + name = get_pointer_64(mr.sel + n_value, xoffset, left, xS, info); + if (name != nullptr) + outs() << format(" %.*s", left, name); + outs() << "\n"; + + offset += sizeof(struct message_ref64); + } +} + +static void print_message_refs32(SectionRef S, struct DisassembleInfo *info) { + uint32_t i, left, offset, xoffset, p; + struct message_ref32 mr; + const char *name, *r; + SectionRef xS; + + if (S == SectionRef()) + return; + + StringRef SectName; + S.getName(SectName); + DataRefImpl Ref = S.getRawDataRefImpl(); + StringRef SegName = info->O->getSectionFinalSegmentName(Ref); + outs() << "Contents of (" << SegName << "," << SectName << ") section\n"; + offset = 0; + for (i = 0; i < S.getSize(); i += sizeof(struct message_ref64)) { + p = S.getAddress() + i; + r = get_pointer_32(p, offset, left, S, info); + if (r == nullptr) + return; + memset(&mr, '\0', sizeof(struct message_ref32)); + if (left < sizeof(struct message_ref32)) { + memcpy(&mr, r, left); + outs() << " (message_ref entends past the end of the section)\n"; + } else + memcpy(&mr, r, sizeof(struct message_ref32)); + if (info->O->isLittleEndian() != sys::IsLittleEndianHost) + swapStruct(mr); + + outs() << " imp " << format("0x%" PRIx32, mr.imp); + name = get_symbol_32(offset + offsetof(struct message_ref32, imp), S, info, + mr.imp); + if (name != nullptr) + outs() << " " << name; + outs() << "\n"; + + outs() << " sel " << format("0x%" PRIx32, mr.sel); + name = get_pointer_32(mr.sel, xoffset, left, xS, info); + if (name != nullptr) + outs() << " " << name; + outs() << "\n"; + + offset += sizeof(struct message_ref32); + } +} + +static void print_image_info64(SectionRef S, struct DisassembleInfo *info) { + uint32_t left, offset, swift_version; + uint64_t p; + struct objc_image_info64 o; + const char *r; + + if (S == SectionRef()) + return; + + StringRef SectName; + S.getName(SectName); + DataRefImpl Ref = S.getRawDataRefImpl(); + StringRef SegName = info->O->getSectionFinalSegmentName(Ref); + outs() << "Contents of (" << SegName << "," << SectName << ") section\n"; + p = S.getAddress(); + r = get_pointer_64(p, offset, left, S, info); + if (r == nullptr) + return; + memset(&o, '\0', sizeof(struct objc_image_info64)); + if (left < sizeof(struct objc_image_info64)) { + memcpy(&o, r, left); + outs() << " (objc_image_info entends past the end of the section)\n"; + } else + memcpy(&o, r, sizeof(struct objc_image_info64)); + if (info->O->isLittleEndian() != sys::IsLittleEndianHost) + swapStruct(o); + outs() << " version " << o.version << "\n"; + outs() << " flags " << format("0x%" PRIx32, o.flags); + if (o.flags & OBJC_IMAGE_IS_REPLACEMENT) + outs() << " OBJC_IMAGE_IS_REPLACEMENT"; + if (o.flags & OBJC_IMAGE_SUPPORTS_GC) + outs() << " OBJC_IMAGE_SUPPORTS_GC"; + swift_version = (o.flags >> 8) & 0xff; + if (swift_version != 0) { + if (swift_version == 1) + outs() << " Swift 1.0"; + else if (swift_version == 2) + outs() << " Swift 1.1"; + else + outs() << " unknown future Swift version (" << swift_version << ")"; + } + outs() << "\n"; +} + +static void print_image_info32(SectionRef S, struct DisassembleInfo *info) { + uint32_t left, offset, swift_version, p; + struct objc_image_info32 o; + const char *r; + + if (S == SectionRef()) + return; + + StringRef SectName; + S.getName(SectName); + DataRefImpl Ref = S.getRawDataRefImpl(); + StringRef SegName = info->O->getSectionFinalSegmentName(Ref); + outs() << "Contents of (" << SegName << "," << SectName << ") section\n"; + p = S.getAddress(); + r = get_pointer_32(p, offset, left, S, info); + if (r == nullptr) + return; + memset(&o, '\0', sizeof(struct objc_image_info32)); + if (left < sizeof(struct objc_image_info32)) { + memcpy(&o, r, left); + outs() << " (objc_image_info entends past the end of the section)\n"; + } else + memcpy(&o, r, sizeof(struct objc_image_info32)); + if (info->O->isLittleEndian() != sys::IsLittleEndianHost) + swapStruct(o); + outs() << " version " << o.version << "\n"; + outs() << " flags " << format("0x%" PRIx32, o.flags); + if (o.flags & OBJC_IMAGE_IS_REPLACEMENT) + outs() << " OBJC_IMAGE_IS_REPLACEMENT"; + if (o.flags & OBJC_IMAGE_SUPPORTS_GC) + outs() << " OBJC_IMAGE_SUPPORTS_GC"; + swift_version = (o.flags >> 8) & 0xff; + if (swift_version != 0) { + if (swift_version == 1) + outs() << " Swift 1.0"; + else if (swift_version == 2) + outs() << " Swift 1.1"; + else + outs() << " unknown future Swift version (" << swift_version << ")"; + } + outs() << "\n"; +} + +static void print_image_info(SectionRef S, struct DisassembleInfo *info) { + uint32_t left, offset, p; + struct imageInfo_t o; + const char *r; + + StringRef SectName; + S.getName(SectName); + DataRefImpl Ref = S.getRawDataRefImpl(); + StringRef SegName = info->O->getSectionFinalSegmentName(Ref); + outs() << "Contents of (" << SegName << "," << SectName << ") section\n"; + p = S.getAddress(); + r = get_pointer_32(p, offset, left, S, info); + if (r == nullptr) + return; + memset(&o, '\0', sizeof(struct imageInfo_t)); + if (left < sizeof(struct imageInfo_t)) { + memcpy(&o, r, left); + outs() << " (imageInfo entends past the end of the section)\n"; + } else + memcpy(&o, r, sizeof(struct imageInfo_t)); + if (info->O->isLittleEndian() != sys::IsLittleEndianHost) + swapStruct(o); + outs() << " version " << o.version << "\n"; + outs() << " flags " << format("0x%" PRIx32, o.flags); + if (o.flags & 0x1) + outs() << " F&C"; + if (o.flags & 0x2) + outs() << " GC"; + if (o.flags & 0x4) + outs() << " GC-only"; + else + outs() << " RR"; + outs() << "\n"; +} + +static void printObjc2_64bit_MetaData(MachOObjectFile *O, bool verbose) { + SymbolAddressMap AddrMap; + if (verbose) + CreateSymbolAddressMap(O, &AddrMap); + + std::vector Sections; + for (const SectionRef &Section : O->sections()) { + StringRef SectName; + Section.getName(SectName); + Sections.push_back(Section); + } + + struct DisassembleInfo info; + // Set up the block of info used by the Symbolizer call backs. + info.verbose = verbose; + info.O = O; + info.AddrMap = &AddrMap; + info.Sections = &Sections; + info.class_name = nullptr; + info.selector_name = nullptr; + info.method = nullptr; + info.demangled_name = nullptr; + info.bindtable = nullptr; + info.adrp_addr = 0; + info.adrp_inst = 0; + + info.depth = 0; + SectionRef CL = get_section(O, "__OBJC2", "__class_list"); + if (CL == SectionRef()) + CL = get_section(O, "__DATA", "__objc_classlist"); + if (CL == SectionRef()) + CL = get_section(O, "__DATA_CONST", "__objc_classlist"); + if (CL == SectionRef()) + CL = get_section(O, "__DATA_DIRTY", "__objc_classlist"); + info.S = CL; + walk_pointer_list_64("class", CL, O, &info, print_class64_t); + + SectionRef CR = get_section(O, "__OBJC2", "__class_refs"); + if (CR == SectionRef()) + CR = get_section(O, "__DATA", "__objc_classrefs"); + if (CR == SectionRef()) + CR = get_section(O, "__DATA_CONST", "__objc_classrefs"); + if (CR == SectionRef()) + CR = get_section(O, "__DATA_DIRTY", "__objc_classrefs"); + info.S = CR; + walk_pointer_list_64("class refs", CR, O, &info, nullptr); + + SectionRef SR = get_section(O, "__OBJC2", "__super_refs"); + if (SR == SectionRef()) + SR = get_section(O, "__DATA", "__objc_superrefs"); + if (SR == SectionRef()) + SR = get_section(O, "__DATA_CONST", "__objc_superrefs"); + if (SR == SectionRef()) + SR = get_section(O, "__DATA_DIRTY", "__objc_superrefs"); + info.S = SR; + walk_pointer_list_64("super refs", SR, O, &info, nullptr); + + SectionRef CA = get_section(O, "__OBJC2", "__category_list"); + if (CA == SectionRef()) + CA = get_section(O, "__DATA", "__objc_catlist"); + if (CA == SectionRef()) + CA = get_section(O, "__DATA_CONST", "__objc_catlist"); + if (CA == SectionRef()) + CA = get_section(O, "__DATA_DIRTY", "__objc_catlist"); + info.S = CA; + walk_pointer_list_64("category", CA, O, &info, print_category64_t); + + SectionRef PL = get_section(O, "__OBJC2", "__protocol_list"); + if (PL == SectionRef()) + PL = get_section(O, "__DATA", "__objc_protolist"); + if (PL == SectionRef()) + PL = get_section(O, "__DATA_CONST", "__objc_protolist"); + if (PL == SectionRef()) + PL = get_section(O, "__DATA_DIRTY", "__objc_protolist"); + info.S = PL; + walk_pointer_list_64("protocol", PL, O, &info, nullptr); + + SectionRef MR = get_section(O, "__OBJC2", "__message_refs"); + if (MR == SectionRef()) + MR = get_section(O, "__DATA", "__objc_msgrefs"); + if (MR == SectionRef()) + MR = get_section(O, "__DATA_CONST", "__objc_msgrefs"); + if (MR == SectionRef()) + MR = get_section(O, "__DATA_DIRTY", "__objc_msgrefs"); + info.S = MR; + print_message_refs64(MR, &info); + + SectionRef II = get_section(O, "__OBJC2", "__image_info"); + if (II == SectionRef()) + II = get_section(O, "__DATA", "__objc_imageinfo"); + if (II == SectionRef()) + II = get_section(O, "__DATA_CONST", "__objc_imageinfo"); + if (II == SectionRef()) + II = get_section(O, "__DATA_DIRTY", "__objc_imageinfo"); + info.S = II; + print_image_info64(II, &info); +} + +static void printObjc2_32bit_MetaData(MachOObjectFile *O, bool verbose) { + SymbolAddressMap AddrMap; + if (verbose) + CreateSymbolAddressMap(O, &AddrMap); + + std::vector Sections; + for (const SectionRef &Section : O->sections()) { + StringRef SectName; + Section.getName(SectName); + Sections.push_back(Section); + } + + struct DisassembleInfo info; + // Set up the block of info used by the Symbolizer call backs. + info.verbose = verbose; + info.O = O; + info.AddrMap = &AddrMap; + info.Sections = &Sections; + info.class_name = nullptr; + info.selector_name = nullptr; + info.method = nullptr; + info.demangled_name = nullptr; + info.bindtable = nullptr; + info.adrp_addr = 0; + info.adrp_inst = 0; + + SectionRef CL = get_section(O, "__OBJC2", "__class_list"); + if (CL == SectionRef()) + CL = get_section(O, "__DATA", "__objc_classlist"); + if (CL == SectionRef()) + CL = get_section(O, "__DATA_CONST", "__objc_classlist"); + if (CL == SectionRef()) + CL = get_section(O, "__DATA_DIRTY", "__objc_classlist"); + info.S = CL; + walk_pointer_list_32("class", CL, O, &info, print_class32_t); + + SectionRef CR = get_section(O, "__OBJC2", "__class_refs"); + if (CR == SectionRef()) + CR = get_section(O, "__DATA", "__objc_classrefs"); + if (CR == SectionRef()) + CR = get_section(O, "__DATA_CONST", "__objc_classrefs"); + if (CR == SectionRef()) + CR = get_section(O, "__DATA_DIRTY", "__objc_classrefs"); + info.S = CR; + walk_pointer_list_32("class refs", CR, O, &info, nullptr); + + SectionRef SR = get_section(O, "__OBJC2", "__super_refs"); + if (SR == SectionRef()) + SR = get_section(O, "__DATA", "__objc_superrefs"); + if (SR == SectionRef()) + SR = get_section(O, "__DATA_CONST", "__objc_superrefs"); + if (SR == SectionRef()) + SR = get_section(O, "__DATA_DIRTY", "__objc_superrefs"); + info.S = SR; + walk_pointer_list_32("super refs", SR, O, &info, nullptr); + + SectionRef CA = get_section(O, "__OBJC2", "__category_list"); + if (CA == SectionRef()) + CA = get_section(O, "__DATA", "__objc_catlist"); + if (CA == SectionRef()) + CA = get_section(O, "__DATA_CONST", "__objc_catlist"); + if (CA == SectionRef()) + CA = get_section(O, "__DATA_DIRTY", "__objc_catlist"); + info.S = CA; + walk_pointer_list_32("category", CA, O, &info, print_category32_t); + + SectionRef PL = get_section(O, "__OBJC2", "__protocol_list"); + if (PL == SectionRef()) + PL = get_section(O, "__DATA", "__objc_protolist"); + if (PL == SectionRef()) + PL = get_section(O, "__DATA_CONST", "__objc_protolist"); + if (PL == SectionRef()) + PL = get_section(O, "__DATA_DIRTY", "__objc_protolist"); + info.S = PL; + walk_pointer_list_32("protocol", PL, O, &info, nullptr); + + SectionRef MR = get_section(O, "__OBJC2", "__message_refs"); + if (MR == SectionRef()) + MR = get_section(O, "__DATA", "__objc_msgrefs"); + if (MR == SectionRef()) + MR = get_section(O, "__DATA_CONST", "__objc_msgrefs"); + if (MR == SectionRef()) + MR = get_section(O, "__DATA_DIRTY", "__objc_msgrefs"); + info.S = MR; + print_message_refs32(MR, &info); + + SectionRef II = get_section(O, "__OBJC2", "__image_info"); + if (II == SectionRef()) + II = get_section(O, "__DATA", "__objc_imageinfo"); + if (II == SectionRef()) + II = get_section(O, "__DATA_CONST", "__objc_imageinfo"); + if (II == SectionRef()) + II = get_section(O, "__DATA_DIRTY", "__objc_imageinfo"); + info.S = II; + print_image_info32(II, &info); +} + +static bool printObjc1_32bit_MetaData(MachOObjectFile *O, bool verbose) { + uint32_t i, j, p, offset, xoffset, left, defs_left, def; + const char *r, *name, *defs; + struct objc_module_t module; + SectionRef S, xS; + struct objc_symtab_t symtab; + struct objc_class_t objc_class; + struct objc_category_t objc_category; + + outs() << "Objective-C segment\n"; + S = get_section(O, "__OBJC", "__module_info"); + if (S == SectionRef()) + return false; + + SymbolAddressMap AddrMap; + if (verbose) + CreateSymbolAddressMap(O, &AddrMap); + + std::vector Sections; + for (const SectionRef &Section : O->sections()) { + StringRef SectName; + Section.getName(SectName); + Sections.push_back(Section); + } + + struct DisassembleInfo info; + // Set up the block of info used by the Symbolizer call backs. + info.verbose = verbose; + info.O = O; + info.AddrMap = &AddrMap; + info.Sections = &Sections; + info.class_name = nullptr; + info.selector_name = nullptr; + info.method = nullptr; + info.demangled_name = nullptr; + info.bindtable = nullptr; + info.adrp_addr = 0; + info.adrp_inst = 0; + + for (i = 0; i < S.getSize(); i += sizeof(struct objc_module_t)) { + p = S.getAddress() + i; + r = get_pointer_32(p, offset, left, S, &info, true); + if (r == nullptr) + return true; + memset(&module, '\0', sizeof(struct objc_module_t)); + if (left < sizeof(struct objc_module_t)) { + memcpy(&module, r, left); + outs() << " (module extends past end of __module_info section)\n"; + } else + memcpy(&module, r, sizeof(struct objc_module_t)); + if (O->isLittleEndian() != sys::IsLittleEndianHost) + swapStruct(module); + + outs() << "Module " << format("0x%" PRIx32, p) << "\n"; + outs() << " version " << module.version << "\n"; + outs() << " size " << module.size << "\n"; + outs() << " name "; + name = get_pointer_32(module.name, xoffset, left, xS, &info, true); + if (name != nullptr) + outs() << format("%.*s", left, name); + else + outs() << format("0x%08" PRIx32, module.name) + << "(not in an __OBJC section)"; + outs() << "\n"; + + r = get_pointer_32(module.symtab, xoffset, left, xS, &info, true); + if (module.symtab == 0 || r == nullptr) { + outs() << " symtab " << format("0x%08" PRIx32, module.symtab) + << " (not in an __OBJC section)\n"; + continue; + } + outs() << " symtab " << format("0x%08" PRIx32, module.symtab) << "\n"; + memset(&symtab, '\0', sizeof(struct objc_symtab_t)); + defs_left = 0; + defs = nullptr; + if (left < sizeof(struct objc_symtab_t)) { + memcpy(&symtab, r, left); + outs() << "\tsymtab extends past end of an __OBJC section)\n"; + } else { + memcpy(&symtab, r, sizeof(struct objc_symtab_t)); + if (left > sizeof(struct objc_symtab_t)) { + defs_left = left - sizeof(struct objc_symtab_t); + defs = r + sizeof(struct objc_symtab_t); + } + } + if (O->isLittleEndian() != sys::IsLittleEndianHost) + swapStruct(symtab); + + outs() << "\tsel_ref_cnt " << symtab.sel_ref_cnt << "\n"; + r = get_pointer_32(symtab.refs, xoffset, left, xS, &info, true); + outs() << "\trefs " << format("0x%08" PRIx32, symtab.refs); + if (r == nullptr) + outs() << " (not in an __OBJC section)"; + outs() << "\n"; + outs() << "\tcls_def_cnt " << symtab.cls_def_cnt << "\n"; + outs() << "\tcat_def_cnt " << symtab.cat_def_cnt << "\n"; + if (symtab.cls_def_cnt > 0) + outs() << "\tClass Definitions\n"; + for (j = 0; j < symtab.cls_def_cnt; j++) { + if ((j + 1) * sizeof(uint32_t) > defs_left) { + outs() << "\t(remaining class defs entries entends past the end of the " + << "section)\n"; + break; + } + memcpy(&def, defs + j * sizeof(uint32_t), sizeof(uint32_t)); + if (O->isLittleEndian() != sys::IsLittleEndianHost) + sys::swapByteOrder(def); + + r = get_pointer_32(def, xoffset, left, xS, &info, true); + outs() << "\tdefs[" << j << "] " << format("0x%08" PRIx32, def); + if (r != nullptr) { + if (left > sizeof(struct objc_class_t)) { + outs() << "\n"; + memcpy(&objc_class, r, sizeof(struct objc_class_t)); + } else { + outs() << " (entends past the end of the section)\n"; + memset(&objc_class, '\0', sizeof(struct objc_class_t)); + memcpy(&objc_class, r, left); + } + if (O->isLittleEndian() != sys::IsLittleEndianHost) + swapStruct(objc_class); + print_objc_class_t(&objc_class, &info); + } else { + outs() << "(not in an __OBJC section)\n"; + } + + if (CLS_GETINFO(&objc_class, CLS_CLASS)) { + outs() << "\tMeta Class"; + r = get_pointer_32(objc_class.isa, xoffset, left, xS, &info, true); + if (r != nullptr) { + if (left > sizeof(struct objc_class_t)) { + outs() << "\n"; + memcpy(&objc_class, r, sizeof(struct objc_class_t)); + } else { + outs() << " (entends past the end of the section)\n"; + memset(&objc_class, '\0', sizeof(struct objc_class_t)); + memcpy(&objc_class, r, left); + } + if (O->isLittleEndian() != sys::IsLittleEndianHost) + swapStruct(objc_class); + print_objc_class_t(&objc_class, &info); + } else { + outs() << "(not in an __OBJC section)\n"; + } + } + } + if (symtab.cat_def_cnt > 0) + outs() << "\tCategory Definitions\n"; + for (j = 0; j < symtab.cat_def_cnt; j++) { + if ((j + symtab.cls_def_cnt + 1) * sizeof(uint32_t) > defs_left) { + outs() << "\t(remaining category defs entries entends past the end of " + << "the section)\n"; + break; + } + memcpy(&def, defs + (j + symtab.cls_def_cnt) * sizeof(uint32_t), + sizeof(uint32_t)); + if (O->isLittleEndian() != sys::IsLittleEndianHost) + sys::swapByteOrder(def); + + r = get_pointer_32(def, xoffset, left, xS, &info, true); + outs() << "\tdefs[" << j + symtab.cls_def_cnt << "] " + << format("0x%08" PRIx32, def); + if (r != nullptr) { + if (left > sizeof(struct objc_category_t)) { + outs() << "\n"; + memcpy(&objc_category, r, sizeof(struct objc_category_t)); + } else { + outs() << " (entends past the end of the section)\n"; + memset(&objc_category, '\0', sizeof(struct objc_category_t)); + memcpy(&objc_category, r, left); + } + if (O->isLittleEndian() != sys::IsLittleEndianHost) + swapStruct(objc_category); + print_objc_objc_category_t(&objc_category, &info); + } else { + outs() << "(not in an __OBJC section)\n"; + } + } + } + const SectionRef II = get_section(O, "__OBJC", "__image_info"); + if (II != SectionRef()) + print_image_info(II, &info); + + return true; +} + +static void DumpProtocolSection(MachOObjectFile *O, const char *sect, + uint32_t size, uint32_t addr) { + SymbolAddressMap AddrMap; + CreateSymbolAddressMap(O, &AddrMap); + + std::vector Sections; + for (const SectionRef &Section : O->sections()) { + StringRef SectName; + Section.getName(SectName); + Sections.push_back(Section); + } + + struct DisassembleInfo info; + // Set up the block of info used by the Symbolizer call backs. + info.verbose = true; + info.O = O; + info.AddrMap = &AddrMap; + info.Sections = &Sections; + info.class_name = nullptr; + info.selector_name = nullptr; + info.method = nullptr; + info.demangled_name = nullptr; + info.bindtable = nullptr; + info.adrp_addr = 0; + info.adrp_inst = 0; + + const char *p; + struct objc_protocol_t protocol; + uint32_t left, paddr; + for (p = sect; p < sect + size; p += sizeof(struct objc_protocol_t)) { + memset(&protocol, '\0', sizeof(struct objc_protocol_t)); + left = size - (p - sect); + if (left < sizeof(struct objc_protocol_t)) { + outs() << "Protocol extends past end of __protocol section\n"; + memcpy(&protocol, p, left); + } else + memcpy(&protocol, p, sizeof(struct objc_protocol_t)); + if (O->isLittleEndian() != sys::IsLittleEndianHost) + swapStruct(protocol); + paddr = addr + (p - sect); + outs() << "Protocol " << format("0x%" PRIx32, paddr); + if (print_protocol(paddr, 0, &info)) + outs() << "(not in an __OBJC section)\n"; + } +} + +#ifdef HAVE_LIBXAR +inline void swapStruct(struct xar_header &xar) { + sys::swapByteOrder(xar.magic); + sys::swapByteOrder(xar.size); + sys::swapByteOrder(xar.version); + sys::swapByteOrder(xar.toc_length_compressed); + sys::swapByteOrder(xar.toc_length_uncompressed); + sys::swapByteOrder(xar.cksum_alg); +} + +static void PrintModeVerbose(uint32_t mode) { + switch (mode & S_IFMT) { + case S_IFDIR: + outs() << "d"; + break; + case S_IFCHR: + outs() << "c"; + break; + case S_IFBLK: + outs() << "b"; + break; + case S_IFREG: + outs() << "-"; + break; + case S_IFLNK: + outs() << "l"; + break; + case S_IFSOCK: + outs() << "s"; + break; + default: + outs() << "?"; + break; + } + + /* owner permissions */ + if (mode & S_IREAD) + outs() << "r"; + else + outs() << "-"; + if (mode & S_IWRITE) + outs() << "w"; + else + outs() << "-"; + if (mode & S_ISUID) + outs() << "s"; + else if (mode & S_IEXEC) + outs() << "x"; + else + outs() << "-"; + + /* group permissions */ + if (mode & (S_IREAD >> 3)) + outs() << "r"; + else + outs() << "-"; + if (mode & (S_IWRITE >> 3)) + outs() << "w"; + else + outs() << "-"; + if (mode & S_ISGID) + outs() << "s"; + else if (mode & (S_IEXEC >> 3)) + outs() << "x"; + else + outs() << "-"; + + /* other permissions */ + if (mode & (S_IREAD >> 6)) + outs() << "r"; + else + outs() << "-"; + if (mode & (S_IWRITE >> 6)) + outs() << "w"; + else + outs() << "-"; + if (mode & S_ISVTX) + outs() << "t"; + else if (mode & (S_IEXEC >> 6)) + outs() << "x"; + else + outs() << "-"; +} + +static void PrintXarFilesSummary(const char *XarFilename, xar_t xar) { + xar_iter_t xi; + xar_file_t xf; + xar_iter_t xp; + const char *key, *type, *mode, *user, *group, *size, *mtime, *name, *m; + char *endp; + uint32_t mode_value; + + xi = xar_iter_new(); + if (!xi) { + errs() << "Can't obtain an xar iterator for xar archive " << XarFilename + << "\n"; + return; + } + + // Go through the xar's files. + for (xf = xar_file_first(xar, xi); xf; xf = xar_file_next(xi)) { + xp = xar_iter_new(); + if (!xp) { + errs() << "Can't obtain an xar iterator for xar archive " << XarFilename + << "\n"; + return; + } + type = nullptr; + mode = nullptr; + user = nullptr; + group = nullptr; + size = nullptr; + mtime = nullptr; + name = nullptr; + for (key = xar_prop_first(xf, xp); key; key = xar_prop_next(xp)) { + const char *val = nullptr; + xar_prop_get(xf, key, &val); +#if 0 // Useful for debugging. + outs() << "key: " << key << " value: " << val << "\n"; +#endif + if (strcmp(key, "type") == 0) + type = val; + if (strcmp(key, "mode") == 0) + mode = val; + if (strcmp(key, "user") == 0) + user = val; + if (strcmp(key, "group") == 0) + group = val; + if (strcmp(key, "data/size") == 0) + size = val; + if (strcmp(key, "mtime") == 0) + mtime = val; + if (strcmp(key, "name") == 0) + name = val; + } + if (mode != nullptr) { + mode_value = strtoul(mode, &endp, 8); + if (*endp != '\0') + outs() << "(mode: \"" << mode << "\" contains non-octal chars) "; + if (strcmp(type, "file") == 0) + mode_value |= S_IFREG; + PrintModeVerbose(mode_value); + outs() << " "; + } + if (user != nullptr) + outs() << format("%10s/", user); + if (group != nullptr) + outs() << format("%-10s ", group); + if (size != nullptr) + outs() << format("%7s ", size); + if (mtime != nullptr) { + for (m = mtime; *m != 'T' && *m != '\0'; m++) + outs() << *m; + if (*m == 'T') + m++; + outs() << " "; + for (; *m != 'Z' && *m != '\0'; m++) + outs() << *m; + outs() << " "; + } + if (name != nullptr) + outs() << name; + outs() << "\n"; + } +} + +static void DumpBitcodeSection(MachOObjectFile *O, const char *sect, + uint32_t size, bool verbose, bool PrintXarHeader, + bool PrintXarFileHeaders, + std::string XarMemberName) { + if (size < sizeof(struct xar_header)) { + outs() << "size of (__LLVM,__bundle) section too small (smaller than size " + "of struct xar_header)\n"; + return; + } + struct xar_header XarHeader; + memcpy(&XarHeader, sect, sizeof(struct xar_header)); + if (sys::IsLittleEndianHost) + swapStruct(XarHeader); + if (PrintXarHeader) { + if (!XarMemberName.empty()) + outs() << "In xar member " << XarMemberName << ": "; + else + outs() << "For (__LLVM,__bundle) section: "; + outs() << "xar header\n"; + if (XarHeader.magic == XAR_HEADER_MAGIC) + outs() << " magic XAR_HEADER_MAGIC\n"; + else + outs() << " magic " + << format_hex(XarHeader.magic, 10, true) + << " (not XAR_HEADER_MAGIC)\n"; + outs() << " size " << XarHeader.size << "\n"; + outs() << " version " << XarHeader.version << "\n"; + outs() << " toc_length_compressed " << XarHeader.toc_length_compressed + << "\n"; + outs() << "toc_length_uncompressed " << XarHeader.toc_length_uncompressed + << "\n"; + outs() << " cksum_alg "; + switch (XarHeader.cksum_alg) { + case XAR_CKSUM_NONE: + outs() << "XAR_CKSUM_NONE\n"; + break; + case XAR_CKSUM_SHA1: + outs() << "XAR_CKSUM_SHA1\n"; + break; + case XAR_CKSUM_MD5: + outs() << "XAR_CKSUM_MD5\n"; + break; +#ifdef XAR_CKSUM_SHA256 + case XAR_CKSUM_SHA256: + outs() << "XAR_CKSUM_SHA256\n"; + break; +#endif +#ifdef XAR_CKSUM_SHA512 + case XAR_CKSUM_SHA512: + outs() << "XAR_CKSUM_SHA512\n"; + break; +#endif + default: + outs() << XarHeader.cksum_alg << "\n"; + } + } + + SmallString<128> XarFilename; + int FD; + std::error_code XarEC = + sys::fs::createTemporaryFile("llvm-mctoll", "xar", FD, XarFilename); + if (XarEC) { + errs() << XarEC.message() << "\n"; + return; + } + ToolOutputFile XarFile(XarFilename, FD); + raw_fd_ostream &XarOut = XarFile.os(); + StringRef XarContents(sect, size); + XarOut << XarContents; + XarOut.close(); + if (XarOut.has_error()) + return; + + xar_t xar = xar_open(XarFilename.c_str(), READ); + if (!xar) { + errs() << "Can't create temporary xar archive " << XarFilename << "\n"; + return; + } + + SmallString<128> TocFilename; + std::error_code TocEC = + sys::fs::createTemporaryFile("llvm-mctoll", "toc", TocFilename); + if (TocEC) { + errs() << TocEC.message() << "\n"; + return; + } + xar_serialize(xar, TocFilename.c_str()); + + if (PrintXarFileHeaders) { + if (!XarMemberName.empty()) + outs() << "In xar member " << XarMemberName << ": "; + else + outs() << "For (__LLVM,__bundle) section: "; + outs() << "xar archive files:\n"; + PrintXarFilesSummary(XarFilename.c_str(), xar); + } + + ErrorOr> FileOrErr = + MemoryBuffer::getFileOrSTDIN(TocFilename.c_str()); + if (std::error_code EC = FileOrErr.getError()) { + errs() << EC.message() << "\n"; + return; + } + std::unique_ptr &Buffer = FileOrErr.get(); + + if (!XarMemberName.empty()) + outs() << "In xar member " << XarMemberName << ": "; + else + outs() << "For (__LLVM,__bundle) section: "; + outs() << "xar table of contents:\n"; + outs() << Buffer->getBuffer() << "\n"; + + // TODO: Go through the xar's files. + xar_iter_t xi = xar_iter_new(); + if (!xi) { + errs() << "Can't obtain an xar iterator for xar archive " + << XarFilename.c_str() << "\n"; + xar_close(xar); + return; + } + for (xar_file_t xf = xar_file_first(xar, xi); xf; xf = xar_file_next(xi)) { + const char *key; + xar_iter_t xp; + const char *member_name, *member_type, *member_size_string; + size_t member_size; + + xp = xar_iter_new(); + if (!xp) { + errs() << "Can't obtain an xar iterator for xar archive " + << XarFilename.c_str() << "\n"; + xar_close(xar); + return; + } + member_name = NULL; + member_type = NULL; + member_size_string = NULL; + for (key = xar_prop_first(xf, xp); key; key = xar_prop_next(xp)) { + const char *val = nullptr; + xar_prop_get(xf, key, &val); +#if 0 // Useful for debugging. + outs() << "key: " << key << " value: " << val << "\n"; +#endif + if (strcmp(key, "name") == 0) + member_name = val; + if (strcmp(key, "type") == 0) + member_type = val; + if (strcmp(key, "data/size") == 0) + member_size_string = val; + } + /* + * If we find a file with a name, date/size and type properties + * and with the type being "file" see if that is a xar file. + */ + if (member_name != NULL && member_type != NULL && + strcmp(member_type, "file") == 0 && member_size_string != NULL) { + // Extract the file into a buffer. + char *endptr; + member_size = strtoul(member_size_string, &endptr, 10); + if (*endptr == '\0' && member_size != 0) { + char *buffer = (char *)::operator new(member_size); + if (xar_extract_tobuffersz(xar, xf, &buffer, &member_size) == 0) { +#if 0 // Useful for debugging. + outs() << "xar member: " << member_name << " extracted\n"; +#endif + // Set the XarMemberName we want to see printed in the header. + std::string OldXarMemberName; + // If XarMemberName is already set this is nested. So + // save the old name and create the nested name. + if (!XarMemberName.empty()) { + OldXarMemberName = XarMemberName; + XarMemberName = + (Twine("[") + XarMemberName + "]" + member_name).str(); + } else { + OldXarMemberName = ""; + XarMemberName = member_name; + } + // See if this is could be a xar file (nested). + if (member_size >= sizeof(struct xar_header)) { +#if 0 // Useful for debugging. + outs() << "could be a xar file: " << member_name << "\n"; +#endif + memcpy((char *)&XarHeader, buffer, sizeof(struct xar_header)); + if (sys::IsLittleEndianHost) + swapStruct(XarHeader); + if (XarHeader.magic == XAR_HEADER_MAGIC) + DumpBitcodeSection(O, buffer, member_size, verbose, + PrintXarHeader, PrintXarFileHeaders, + XarMemberName); + } + XarMemberName = OldXarMemberName; + } + delete buffer; + } + } + xar_iter_free(xp); + } + xar_close(xar); +} +#endif // defined(HAVE_LIBXAR) + +static void printObjcMetaData(MachOObjectFile *O, bool verbose) { + if (O->is64Bit()) + printObjc2_64bit_MetaData(O, verbose); + else { + MachO::mach_header H; + H = O->getHeader(); + if (H.cputype == MachO::CPU_TYPE_ARM) + printObjc2_32bit_MetaData(O, verbose); + else { + // This is the 32-bit non-arm cputype case. Which is normally + // the first Objective-C ABI. But it may be the case of a + // binary for the iOS simulator which is the second Objective-C + // ABI. In that case printObjc1_32bit_MetaData() will determine that + // and return false. + if (!printObjc1_32bit_MetaData(O, verbose)) + printObjc2_32bit_MetaData(O, verbose); + } + } +} + +// GuessLiteralPointer returns a string which for the item in the Mach-O file +// for the address passed in as ReferenceValue for printing as a comment with +// the instruction and also returns the corresponding type of that item +// indirectly through ReferenceType. +// +// If ReferenceValue is an address of literal cstring then a pointer to the +// cstring is returned and ReferenceType is set to +// LLVMDisassembler_ReferenceType_Out_LitPool_CstrAddr . +// +// If ReferenceValue is an address of an Objective-C CFString, Selector ref or +// Class ref that name is returned and the ReferenceType is set accordingly. +// +// Lastly, literals which are Symbol address in a literal pool are looked for +// and if found the symbol name is returned and ReferenceType is set to +// LLVMDisassembler_ReferenceType_Out_LitPool_SymAddr . +// +// If there is no item in the Mach-O file for the address passed in as +// ReferenceValue nullptr is returned and ReferenceType is unchanged. +static const char *GuessLiteralPointer(uint64_t ReferenceValue, + uint64_t ReferencePC, + uint64_t *ReferenceType, + struct DisassembleInfo *info) { + // First see if there is an external relocation entry at the ReferencePC. + if (info->O->getHeader().filetype == MachO::MH_OBJECT) { + uint64_t sect_addr = info->S.getAddress(); + uint64_t sect_offset = ReferencePC - sect_addr; + bool reloc_found = false; + DataRefImpl Rel; + MachO::any_relocation_info RE; + bool isExtern = false; + SymbolRef Symbol; + for (const RelocationRef &Reloc : info->S.relocations()) { + uint64_t RelocOffset = Reloc.getOffset(); + if (RelocOffset == sect_offset) { + Rel = Reloc.getRawDataRefImpl(); + RE = info->O->getRelocation(Rel); + if (info->O->isRelocationScattered(RE)) + continue; + isExtern = info->O->getPlainRelocationExternal(RE); + if (isExtern) { + symbol_iterator RelocSym = Reloc.getSymbol(); + Symbol = *RelocSym; + } + reloc_found = true; + break; + } + } + // If there is an external relocation entry for a symbol in a section + // then used that symbol's value for the value of the reference. + if (reloc_found && isExtern) { + if (info->O->getAnyRelocationPCRel(RE)) { + unsigned Type = info->O->getAnyRelocationType(RE); + if (Type == MachO::X86_64_RELOC_SIGNED) { + ReferenceValue = Symbol.getValue(); + } + } + } + } + + // Look for literals such as Objective-C CFStrings refs, Selector refs, + // Message refs and Class refs. + bool classref, selref, msgref, cfstring; + uint64_t pointer_value = GuessPointerPointer(ReferenceValue, info, classref, + selref, msgref, cfstring); + if (classref && pointer_value == 0) { + // Note the ReferenceValue is a pointer into the __objc_classrefs section. + // And the pointer_value in that section is typically zero as it will be + // set by dyld as part of the "bind information". + const char *name = get_dyld_bind_info_symbolname(ReferenceValue, info); + if (name != nullptr) { + *ReferenceType = LLVMDisassembler_ReferenceType_Out_Objc_Class_Ref; + const char *class_name = strrchr(name, '$'); + if (class_name != nullptr && class_name[1] == '_' && + class_name[2] != '\0') { + info->class_name = class_name + 2; + return name; + } + } + } + + if (classref) { + *ReferenceType = LLVMDisassembler_ReferenceType_Out_Objc_Class_Ref; + const char *name = + get_objc2_64bit_class_name(pointer_value, ReferenceValue, info); + if (name != nullptr) + info->class_name = name; + else + name = "bad class ref"; + return name; + } + + if (cfstring) { + *ReferenceType = LLVMDisassembler_ReferenceType_Out_Objc_CFString_Ref; + const char *name = get_objc2_64bit_cfstring_name(ReferenceValue, info); + return name; + } + + if (selref && pointer_value == 0) + pointer_value = get_objc2_64bit_selref(ReferenceValue, info); + + if (pointer_value != 0) + ReferenceValue = pointer_value; + + const char *name = GuessCstringPointer(ReferenceValue, info); + if (name) { + if (pointer_value != 0 && selref) { + *ReferenceType = LLVMDisassembler_ReferenceType_Out_Objc_Selector_Ref; + info->selector_name = name; + } else if (pointer_value != 0 && msgref) { + info->class_name = nullptr; + *ReferenceType = LLVMDisassembler_ReferenceType_Out_Objc_Message_Ref; + info->selector_name = name; + } else + *ReferenceType = LLVMDisassembler_ReferenceType_Out_LitPool_CstrAddr; + return name; + } + + // Lastly look for an indirect symbol with this ReferenceValue which is in + // a literal pool. If found return that symbol name. + name = GuessIndirectSymbol(ReferenceValue, info); + if (name) { + *ReferenceType = LLVMDisassembler_ReferenceType_Out_LitPool_SymAddr; + return name; + } + + return nullptr; +} + +// SymbolizerSymbolLookUp is the symbol lookup function passed when creating +// the Symbolizer. It looks up the ReferenceValue using the info passed via the +// pointer to the struct DisassembleInfo that was passed when MCSymbolizer +// is created and returns the symbol name that matches the ReferenceValue or +// nullptr if none. The ReferenceType is passed in for the IN type of +// reference the instruction is making from the values in defined in the header +// "llvm-c/Disassembler.h". On return the ReferenceType can set to a specific +// Out type and the ReferenceName will also be set which is added as a comment +// to the disassembled instruction. +// +// If the symbol name is a C++ mangled name then the demangled name is +// returned through ReferenceName and ReferenceType is set to +// LLVMDisassembler_ReferenceType_DeMangled_Name . +// +// When this is called to get a symbol name for a branch target then the +// ReferenceType will be LLVMDisassembler_ReferenceType_In_Branch and then +// SymbolValue will be looked for in the indirect symbol table to determine if +// it is an address for a symbol stub. If so then the symbol name for that +// stub is returned indirectly through ReferenceName and then ReferenceType is +// set to LLVMDisassembler_ReferenceType_Out_SymbolStub. +// +// When this is called with an value loaded via a PC relative load then +// ReferenceType will be LLVMDisassembler_ReferenceType_In_PCrel_Load then the +// SymbolValue is checked to be an address of literal pointer, symbol pointer, +// or an Objective-C meta data reference. If so the output ReferenceType is +// set to correspond to that as well as setting the ReferenceName. +static const char *SymbolizerSymbolLookUp(void *DisInfo, + uint64_t ReferenceValue, + uint64_t *ReferenceType, + uint64_t ReferencePC, + const char **ReferenceName) { + struct DisassembleInfo *info = (struct DisassembleInfo *)DisInfo; + // If no verbose symbolic information is wanted then just return nullptr. + if (!info->verbose) { + *ReferenceName = nullptr; + *ReferenceType = LLVMDisassembler_ReferenceType_InOut_None; + return nullptr; + } + + const char *SymbolName = GuessSymbolName(ReferenceValue, info->AddrMap); + + if (*ReferenceType == LLVMDisassembler_ReferenceType_In_Branch) { + *ReferenceName = GuessIndirectSymbol(ReferenceValue, info); + if (*ReferenceName != nullptr) { + method_reference(info, ReferenceType, ReferenceName); + if (*ReferenceType != LLVMDisassembler_ReferenceType_Out_Objc_Message) + *ReferenceType = LLVMDisassembler_ReferenceType_Out_SymbolStub; + } else if (SymbolName != nullptr && strncmp(SymbolName, "__Z", 3) == 0) { + if (info->demangled_name != nullptr) + free(info->demangled_name); + int status; + info->demangled_name = + itaniumDemangle(SymbolName + 1, nullptr, nullptr, &status); + if (info->demangled_name != nullptr) { + *ReferenceName = info->demangled_name; + *ReferenceType = LLVMDisassembler_ReferenceType_DeMangled_Name; + } else + *ReferenceType = LLVMDisassembler_ReferenceType_InOut_None; + } else + *ReferenceType = LLVMDisassembler_ReferenceType_InOut_None; + } else if (*ReferenceType == LLVMDisassembler_ReferenceType_In_PCrel_Load) { + *ReferenceName = + GuessLiteralPointer(ReferenceValue, ReferencePC, ReferenceType, info); + if (*ReferenceName) + method_reference(info, ReferenceType, ReferenceName); + else + *ReferenceType = LLVMDisassembler_ReferenceType_InOut_None; + // If this is arm64 and the reference is an adrp instruction save the + // instruction, passed in ReferenceValue and the address of the instruction + // for use later if we see and add immediate instruction. + } else if (info->O->getArch() == Triple::aarch64 && + *ReferenceType == LLVMDisassembler_ReferenceType_In_ARM64_ADRP) { + info->adrp_inst = ReferenceValue; + info->adrp_addr = ReferencePC; + SymbolName = nullptr; + *ReferenceName = nullptr; + *ReferenceType = LLVMDisassembler_ReferenceType_InOut_None; + // If this is arm64 and reference is an add immediate instruction and we + // have + // seen an adrp instruction just before it and the adrp's Xd register + // matches + // this add's Xn register reconstruct the value being referenced and look to + // see if it is a literal pointer. Note the add immediate instruction is + // passed in ReferenceValue. + } else if (info->O->getArch() == Triple::aarch64 && + *ReferenceType == LLVMDisassembler_ReferenceType_In_ARM64_ADDXri && + ReferencePC - 4 == info->adrp_addr && + (info->adrp_inst & 0x9f000000) == 0x90000000 && + (info->adrp_inst & 0x1f) == ((ReferenceValue >> 5) & 0x1f)) { + uint32_t addxri_inst; + uint64_t adrp_imm, addxri_imm; + + adrp_imm = + ((info->adrp_inst & 0x00ffffe0) >> 3) | ((info->adrp_inst >> 29) & 0x3); + if (info->adrp_inst & 0x0200000) + adrp_imm |= 0xfffffffffc000000LL; + + addxri_inst = ReferenceValue; + addxri_imm = (addxri_inst >> 10) & 0xfff; + if (((addxri_inst >> 22) & 0x3) == 1) + addxri_imm <<= 12; + + ReferenceValue = (info->adrp_addr & 0xfffffffffffff000LL) + + (adrp_imm << 12) + addxri_imm; + + *ReferenceName = + GuessLiteralPointer(ReferenceValue, ReferencePC, ReferenceType, info); + if (*ReferenceName == nullptr) + *ReferenceType = LLVMDisassembler_ReferenceType_InOut_None; + // If this is arm64 and the reference is a load register instruction and we + // have seen an adrp instruction just before it and the adrp's Xd register + // matches this add's Xn register reconstruct the value being referenced and + // look to see if it is a literal pointer. Note the load register + // instruction is passed in ReferenceValue. + } else if (info->O->getArch() == Triple::aarch64 && + *ReferenceType == LLVMDisassembler_ReferenceType_In_ARM64_LDRXui && + ReferencePC - 4 == info->adrp_addr && + (info->adrp_inst & 0x9f000000) == 0x90000000 && + (info->adrp_inst & 0x1f) == ((ReferenceValue >> 5) & 0x1f)) { + uint32_t ldrxui_inst; + uint64_t adrp_imm, ldrxui_imm; + + adrp_imm = + ((info->adrp_inst & 0x00ffffe0) >> 3) | ((info->adrp_inst >> 29) & 0x3); + if (info->adrp_inst & 0x0200000) + adrp_imm |= 0xfffffffffc000000LL; + + ldrxui_inst = ReferenceValue; + ldrxui_imm = (ldrxui_inst >> 10) & 0xfff; + + ReferenceValue = (info->adrp_addr & 0xfffffffffffff000LL) + + (adrp_imm << 12) + (ldrxui_imm << 3); + + *ReferenceName = + GuessLiteralPointer(ReferenceValue, ReferencePC, ReferenceType, info); + if (*ReferenceName == nullptr) + *ReferenceType = LLVMDisassembler_ReferenceType_InOut_None; + } + // If this arm64 and is an load register (PC-relative) instruction the + // ReferenceValue is the PC plus the immediate value. + else if (info->O->getArch() == Triple::aarch64 && + (*ReferenceType == LLVMDisassembler_ReferenceType_In_ARM64_LDRXl || + *ReferenceType == LLVMDisassembler_ReferenceType_In_ARM64_ADR)) { + *ReferenceName = + GuessLiteralPointer(ReferenceValue, ReferencePC, ReferenceType, info); + if (*ReferenceName == nullptr) + *ReferenceType = LLVMDisassembler_ReferenceType_InOut_None; + } else if (SymbolName != nullptr && strncmp(SymbolName, "__Z", 3) == 0) { + if (info->demangled_name != nullptr) + free(info->demangled_name); + int status; + info->demangled_name = + itaniumDemangle(SymbolName + 1, nullptr, nullptr, &status); + if (info->demangled_name != nullptr) { + *ReferenceName = info->demangled_name; + *ReferenceType = LLVMDisassembler_ReferenceType_DeMangled_Name; + } + } else { + *ReferenceName = nullptr; + *ReferenceType = LLVMDisassembler_ReferenceType_InOut_None; + } + + return SymbolName; +} + +/// \brief Emits the comments that are stored in the CommentStream. +/// Each comment in the CommentStream must end with a newline. +static void emitComments(raw_svector_ostream &CommentStream, + SmallString<128> &CommentsToEmit, + formatted_raw_ostream &FormattedOS, + const MCAsmInfo &MAI) { + // Flush the stream before taking its content. + StringRef Comments = CommentsToEmit.str(); + // Get the default information for printing a comment. + StringRef CommentBegin = MAI.getCommentString(); + unsigned CommentColumn = MAI.getCommentColumn(); + bool IsFirst = true; + while (!Comments.empty()) { + if (!IsFirst) + FormattedOS << '\n'; + // Emit a line of comments. + FormattedOS.PadToColumn(CommentColumn); + size_t Position = Comments.find('\n'); + FormattedOS << CommentBegin << ' ' << Comments.substr(0, Position); + // Move after the newline character. + Comments = Comments.substr(Position + 1); + IsFirst = false; + } + FormattedOS.flush(); + + // Tell the comment stream that the vector changed underneath it. + CommentsToEmit.clear(); +} + +static void DisassembleMachO(StringRef Filename, MachOObjectFile *MachOOF, + StringRef DisSegName, StringRef DisSectName) { + const char *McpuDefault = nullptr; + const Target *ThumbTarget = nullptr; + const Target *TheTarget = GetTarget(MachOOF, &McpuDefault, &ThumbTarget); + if (!TheTarget) { + // GetTarget prints out stuff. + return; + } + if (MCPU.empty() && McpuDefault) + MCPU = McpuDefault; + + std::unique_ptr InstrInfo(TheTarget->createMCInstrInfo()); + std::unique_ptr ThumbInstrInfo; + if (ThumbTarget) + ThumbInstrInfo.reset(ThumbTarget->createMCInstrInfo()); + + // Package up features to be passed to target/subtarget + std::string FeaturesStr; + if (MAttrs.size()) { + SubtargetFeatures Features; + for (unsigned i = 0; i != MAttrs.size(); ++i) + Features.AddFeature(MAttrs[i]); + FeaturesStr = Features.getString(); + } + + // Set up disassembler. + std::unique_ptr MRI( + TheTarget->createMCRegInfo(TripleName)); + std::unique_ptr AsmInfo( + TheTarget->createMCAsmInfo(*MRI, TripleName)); + std::unique_ptr STI( + TheTarget->createMCSubtargetInfo(TripleName, MCPU, FeaturesStr)); + MCContext Ctx(AsmInfo.get(), MRI.get(), nullptr); + std::unique_ptr DisAsm( + TheTarget->createMCDisassembler(*STI, Ctx)); + std::unique_ptr Symbolizer; + struct DisassembleInfo SymbolizerInfo; + std::unique_ptr RelInfo( + TheTarget->createMCRelocationInfo(TripleName, Ctx)); + if (RelInfo) { + Symbolizer.reset(TheTarget->createMCSymbolizer( + TripleName, SymbolizerGetOpInfo, SymbolizerSymbolLookUp, + &SymbolizerInfo, &Ctx, std::move(RelInfo))); + DisAsm->setSymbolizer(std::move(Symbolizer)); + } + int AsmPrinterVariant = AsmInfo->getAssemblerDialect(); + std::unique_ptr IP(TheTarget->createMCInstPrinter( + Triple(TripleName), AsmPrinterVariant, *AsmInfo, *InstrInfo, *MRI)); + // Set the display preference for hex vs. decimal immediates. + IP->setPrintImmHex(PrintImmHex); + // Comment stream and backing vector. + SmallString<128> CommentsToEmit; + raw_svector_ostream CommentStream(CommentsToEmit); + // FIXME: Setting the CommentStream in the InstPrinter is problematic in that + // if it is done then arm64 comments for string literals don't get printed + // and some constant get printed instead and not setting it causes intel + // (32-bit and 64-bit) comments printed with different spacing before the + // comment causing different diffs with the 'C' disassembler library API. + // IP->setCommentStream(CommentStream); + + if (!AsmInfo || !STI || !DisAsm || !IP) { + errs() << "error: couldn't initialize disassembler for target " + << TripleName << '\n'; + return; + } + + // Set up separate thumb disassembler if needed. + std::unique_ptr ThumbMRI; + std::unique_ptr ThumbAsmInfo; + std::unique_ptr ThumbSTI; + std::unique_ptr ThumbDisAsm; + std::unique_ptr ThumbIP; + std::unique_ptr ThumbCtx; + std::unique_ptr ThumbSymbolizer; + struct DisassembleInfo ThumbSymbolizerInfo; + std::unique_ptr ThumbRelInfo; + if (ThumbTarget) { + ThumbMRI.reset(ThumbTarget->createMCRegInfo(ThumbTripleName)); + ThumbAsmInfo.reset( + ThumbTarget->createMCAsmInfo(*ThumbMRI, ThumbTripleName)); + ThumbSTI.reset( + ThumbTarget->createMCSubtargetInfo(ThumbTripleName, MCPU, FeaturesStr)); + ThumbCtx.reset(new MCContext(ThumbAsmInfo.get(), ThumbMRI.get(), nullptr)); + ThumbDisAsm.reset(ThumbTarget->createMCDisassembler(*ThumbSTI, *ThumbCtx)); + MCContext *PtrThumbCtx = ThumbCtx.get(); + ThumbRelInfo.reset( + ThumbTarget->createMCRelocationInfo(ThumbTripleName, *PtrThumbCtx)); + if (ThumbRelInfo) { + ThumbSymbolizer.reset(ThumbTarget->createMCSymbolizer( + ThumbTripleName, SymbolizerGetOpInfo, SymbolizerSymbolLookUp, + &ThumbSymbolizerInfo, PtrThumbCtx, std::move(ThumbRelInfo))); + ThumbDisAsm->setSymbolizer(std::move(ThumbSymbolizer)); + } + int ThumbAsmPrinterVariant = ThumbAsmInfo->getAssemblerDialect(); + ThumbIP.reset(ThumbTarget->createMCInstPrinter( + Triple(ThumbTripleName), ThumbAsmPrinterVariant, *ThumbAsmInfo, + *ThumbInstrInfo, *ThumbMRI)); + // Set the display preference for hex vs. decimal immediates. + ThumbIP->setPrintImmHex(PrintImmHex); + } + + if (ThumbTarget && (!ThumbAsmInfo || !ThumbSTI || !ThumbDisAsm || !ThumbIP)) { + errs() << "error: couldn't initialize disassembler for target " + << ThumbTripleName << '\n'; + return; + } + + MachO::mach_header Header = MachOOF->getHeader(); + + // FIXME: Using the -cfg command line option, this code used to be able to + // annotate relocations with the referenced symbol's name, and if this was + // inside a __[cf]string section, the data it points to. This is now replaced + // by the upcoming MCSymbolizer, which needs the appropriate setup done above. + std::vector Sections; + std::vector Symbols; + SmallVector FoundFns; + uint64_t BaseSegmentAddress; + + getSectionsAndSymbols(MachOOF, Sections, Symbols, FoundFns, + BaseSegmentAddress); + + // Sort the symbols by address, just in case they didn't come in that way. + std::sort(Symbols.begin(), Symbols.end(), SymbolSorter()); + + // Build a data in code table that is sorted on by the address of each entry. + uint64_t BaseAddress = 0; + if (Header.filetype == MachO::MH_OBJECT) + BaseAddress = Sections[0].getAddress(); + else + BaseAddress = BaseSegmentAddress; + DiceTable Dices; + for (dice_iterator DI = MachOOF->begin_dices(), DE = MachOOF->end_dices(); + DI != DE; ++DI) { + uint32_t Offset; + DI->getOffset(Offset); + Dices.push_back(std::make_pair(BaseAddress + Offset, *DI)); + } + array_pod_sort(Dices.begin(), Dices.end()); + +#ifndef NDEBUG + raw_ostream &DebugOut = DebugFlag ? dbgs() : nulls(); +#else + raw_ostream &DebugOut = nulls(); +#endif + + std::unique_ptr diContext; + ObjectFile *DbgObj = MachOOF; + // Try to find debug info and set up the DIContext for it. + if (UseDbg) { + // A separate DSym file path was specified, parse it as a macho file, + // get the sections and supply it to the section name parsing machinery. + if (!DSYMFile.empty()) { + ErrorOr> BufOrErr = + MemoryBuffer::getFileOrSTDIN(DSYMFile); + if (std::error_code EC = BufOrErr.getError()) { + errs() << "llvm-mctoll: " << Filename << ": " << EC.message() << '\n'; + return; + } + DbgObj = + ObjectFile::createMachOObjectFile(BufOrErr.get()->getMemBufferRef()) + .get() + .release(); + } + + // Setup the DIContext + diContext = DWARFContext::create(*DbgObj); + } + + if (FilterSections.size() == 0) + outs() << "(" << DisSegName << "," << DisSectName << ") section\n"; + + for (unsigned SectIdx = 0; SectIdx != Sections.size(); SectIdx++) { + StringRef SectName; + if (Sections[SectIdx].getName(SectName) || SectName != DisSectName) + continue; + + DataRefImpl DR = Sections[SectIdx].getRawDataRefImpl(); + + StringRef SegmentName = MachOOF->getSectionFinalSegmentName(DR); + if (SegmentName != DisSegName) + continue; + + StringRef BytesStr; + Sections[SectIdx].getContents(BytesStr); + ArrayRef Bytes(reinterpret_cast(BytesStr.data()), + BytesStr.size()); + uint64_t SectAddress = Sections[SectIdx].getAddress(); + + bool symbolTableWorked = false; + + // Create a map of symbol addresses to symbol names for use by + // the SymbolizerSymbolLookUp() routine. + SymbolAddressMap AddrMap; + bool DisSymNameFound = false; + for (const SymbolRef &Symbol : MachOOF->symbols()) { + Expected STOrErr = Symbol.getType(); + if (!STOrErr) + report_error(MachOOF->getFileName(), STOrErr.takeError()); + SymbolRef::Type ST = *STOrErr; + if (ST == SymbolRef::ST_Function || ST == SymbolRef::ST_Data || + ST == SymbolRef::ST_Other) { + uint64_t Address = Symbol.getValue(); + Expected SymNameOrErr = Symbol.getName(); + if (!SymNameOrErr) + report_error(MachOOF->getFileName(), SymNameOrErr.takeError()); + StringRef SymName = *SymNameOrErr; + AddrMap[Address] = SymName; + if (!DisSymName.empty() && DisSymName == SymName) + DisSymNameFound = true; + } + } + if (!DisSymName.empty() && !DisSymNameFound) { + outs() << "Can't find -dis-symname: " << DisSymName << "\n"; + return; + } + // Set up the block of info used by the Symbolizer call backs. + SymbolizerInfo.verbose = !NoSymbolicOperands; + SymbolizerInfo.O = MachOOF; + SymbolizerInfo.S = Sections[SectIdx]; + SymbolizerInfo.AddrMap = &AddrMap; + SymbolizerInfo.Sections = &Sections; + SymbolizerInfo.class_name = nullptr; + SymbolizerInfo.selector_name = nullptr; + SymbolizerInfo.method = nullptr; + SymbolizerInfo.demangled_name = nullptr; + SymbolizerInfo.bindtable = nullptr; + SymbolizerInfo.adrp_addr = 0; + SymbolizerInfo.adrp_inst = 0; + // Same for the ThumbSymbolizer + ThumbSymbolizerInfo.verbose = !NoSymbolicOperands; + ThumbSymbolizerInfo.O = MachOOF; + ThumbSymbolizerInfo.S = Sections[SectIdx]; + ThumbSymbolizerInfo.AddrMap = &AddrMap; + ThumbSymbolizerInfo.Sections = &Sections; + ThumbSymbolizerInfo.class_name = nullptr; + ThumbSymbolizerInfo.selector_name = nullptr; + ThumbSymbolizerInfo.method = nullptr; + ThumbSymbolizerInfo.demangled_name = nullptr; + ThumbSymbolizerInfo.bindtable = nullptr; + ThumbSymbolizerInfo.adrp_addr = 0; + ThumbSymbolizerInfo.adrp_inst = 0; + + unsigned int Arch = MachOOF->getArch(); + + // Skip all symbols if this is a stubs file. + if (Bytes.size() == 0) + return; + + // If the section has symbols but no symbol at the start of the section + // these are used to make sure the bytes before the first symbol are + // disassembled. + bool FirstSymbol = true; + bool FirstSymbolAtSectionStart = true; + + // Disassemble symbol by symbol. + for (unsigned SymIdx = 0; SymIdx != Symbols.size(); SymIdx++) { + Expected SymNameOrErr = Symbols[SymIdx].getName(); + if (!SymNameOrErr) + report_error(MachOOF->getFileName(), SymNameOrErr.takeError()); + StringRef SymName = *SymNameOrErr; + + Expected STOrErr = Symbols[SymIdx].getType(); + if (!STOrErr) + report_error(MachOOF->getFileName(), STOrErr.takeError()); + SymbolRef::Type ST = *STOrErr; + if (ST != SymbolRef::ST_Function && ST != SymbolRef::ST_Data) + continue; + + // Make sure the symbol is defined in this section. + bool containsSym = Sections[SectIdx].containsSymbol(Symbols[SymIdx]); + if (!containsSym) { + if (!DisSymName.empty() && DisSymName == SymName) { + outs() << "-dis-symname: " << DisSymName << " not in the section\n"; + return; + } + continue; + } + // The __mh_execute_header is special and we need to deal with that fact + // this symbol is before the start of the (__TEXT,__text) section and at + // the address of the start of the __TEXT segment. This is because this + // symbol is an N_SECT symbol in the (__TEXT,__text) but its address is + // before the start of the section in a standard MH_EXECUTE filetype. + if (!DisSymName.empty() && DisSymName == "__mh_execute_header") { + outs() << "-dis-symname: __mh_execute_header not in any section\n"; + return; + } + // When this code is trying to disassemble a symbol at a time and in the + // case there is only the __mh_execute_header symbol left as in a stripped + // executable, we need to deal with this by ignoring this symbol so the + // whole section is disassembled and this symbol is then not displayed. + if (SymName == "__mh_execute_header" || SymName == "__mh_dylib_header" || + SymName == "__mh_bundle_header" || SymName == "__mh_object_header" || + SymName == "__mh_preload_header" || SymName == "__mh_dylinker_header") + continue; + + // If we are only disassembling one symbol see if this is that symbol. + if (!DisSymName.empty() && DisSymName != SymName) + continue; + + // Start at the address of the symbol relative to the section's address. + uint64_t SectSize = Sections[SectIdx].getSize(); + uint64_t Start = Symbols[SymIdx].getValue(); + uint64_t SectionAddress = Sections[SectIdx].getAddress(); + Start -= SectionAddress; + + if (Start > SectSize) { + outs() << "section data ends, " << SymName + << " lies outside valid range\n"; + return; + } + + // Stop disassembling either at the beginning of the next symbol or at + // the end of the section. + bool containsNextSym = false; + uint64_t NextSym = 0; + uint64_t NextSymIdx = SymIdx + 1; + while (Symbols.size() > NextSymIdx) { + Expected STOrErr = Symbols[NextSymIdx].getType(); + if (!STOrErr) + report_error(MachOOF->getFileName(), STOrErr.takeError()); + SymbolRef::Type NextSymType = *STOrErr; + if (NextSymType == SymbolRef::ST_Function) { + containsNextSym = + Sections[SectIdx].containsSymbol(Symbols[NextSymIdx]); + NextSym = Symbols[NextSymIdx].getValue(); + NextSym -= SectionAddress; + break; + } + ++NextSymIdx; + } + + uint64_t End = containsNextSym ? std::min(NextSym, SectSize) : SectSize; + uint64_t Size; + + symbolTableWorked = true; + + DataRefImpl Symb = Symbols[SymIdx].getRawDataRefImpl(); + bool IsThumb = MachOOF->getSymbolFlags(Symb) & SymbolRef::SF_Thumb; + + // We only need the dedicated Thumb target if there's a real choice + // (i.e. we're not targeting M-class) and the function is Thumb. + bool UseThumbTarget = IsThumb && ThumbTarget; + + // If we are not specifying a symbol to start disassembly with and this + // is the first symbol in the section but not at the start of the section + // then move the disassembly index to the start of the section and + // don't print the symbol name just yet. This is so the bytes before the + // first symbol are disassembled. + uint64_t SymbolStart = Start; + if (DisSymName.empty() && FirstSymbol && Start != 0) { + FirstSymbolAtSectionStart = false; + Start = 0; + } else + outs() << SymName << ":\n"; + + DILineInfo lastLine; + for (uint64_t Index = Start; Index < End; Index += Size) { + MCInst Inst; + + // If this is the first symbol in the section and it was not at the + // start of the section, see if we are at its Index now and if so print + // the symbol name. + if (FirstSymbol && !FirstSymbolAtSectionStart && Index == SymbolStart) + outs() << SymName << ":\n"; + + uint64_t PC = SectAddress + Index; + if (!NoLeadingAddr) { + if (FullLeadingAddr) { + if (MachOOF->is64Bit()) + outs() << format("%016" PRIx64, PC); + else + outs() << format("%08" PRIx64, PC); + } else { + outs() << format("%8" PRIx64 ":", PC); + } + } + if (!NoShowRawInsn || Arch == Triple::arm) + outs() << "\t"; + + // Check the data in code table here to see if this is data not an + // instruction to be disassembled. + DiceTable Dice; + Dice.push_back(std::make_pair(PC, DiceRef())); + dice_table_iterator DTI = + std::search(Dices.begin(), Dices.end(), Dice.begin(), Dice.end(), + compareDiceTableEntries); + if (DTI != Dices.end()) { + uint16_t Length; + DTI->second.getLength(Length); + uint16_t Kind; + DTI->second.getKind(Kind); + Size = DumpDataInCode(Bytes.data() + Index, Length, Kind); + if ((Kind == MachO::DICE_KIND_JUMP_TABLE8) && + (PC == (DTI->first + Length - 1)) && (Length & 1)) + Size++; + continue; + } + + SmallVector AnnotationsBytes; + raw_svector_ostream Annotations(AnnotationsBytes); + + bool gotInst; + if (UseThumbTarget) + gotInst = ThumbDisAsm->getInstruction(Inst, Size, Bytes.slice(Index), + PC, DebugOut, Annotations); + else + gotInst = DisAsm->getInstruction(Inst, Size, Bytes.slice(Index), PC, + DebugOut, Annotations); + if (gotInst) { + if (!NoShowRawInsn || Arch == Triple::arm) { + dumpBytes(makeArrayRef(Bytes.data() + Index, Size), outs()); + } + formatted_raw_ostream FormattedOS(outs()); + StringRef AnnotationsStr = Annotations.str(); + if (UseThumbTarget) + ThumbIP->printInst(&Inst, FormattedOS, AnnotationsStr, *ThumbSTI); + else + IP->printInst(&Inst, FormattedOS, AnnotationsStr, *STI); + emitComments(CommentStream, CommentsToEmit, FormattedOS, *AsmInfo); + + // Print debug info. + if (diContext) { + DILineInfo dli = diContext->getLineInfoForAddress(PC); + // Print valid line info if it changed. + if (dli != lastLine && dli.Line != 0) + outs() << "\t## " << dli.FileName << ':' << dli.Line << ':' + << dli.Column; + lastLine = dli; + } + outs() << "\n"; + } else { + unsigned int Arch = MachOOF->getArch(); + if (Arch == Triple::x86_64 || Arch == Triple::x86) { + outs() << format("\t.byte 0x%02x #bad opcode\n", + *(Bytes.data() + Index) & 0xff); + Size = 1; // skip exactly one illegible byte and move on. + } else if (Arch == Triple::aarch64 || + (Arch == Triple::arm && !IsThumb)) { + uint32_t opcode = (*(Bytes.data() + Index) & 0xff) | + (*(Bytes.data() + Index + 1) & 0xff) << 8 | + (*(Bytes.data() + Index + 2) & 0xff) << 16 | + (*(Bytes.data() + Index + 3) & 0xff) << 24; + outs() << format("\t.long\t0x%08x\n", opcode); + Size = 4; + } else if (Arch == Triple::arm) { + assert(IsThumb && "ARM mode should have been dealt with above"); + uint32_t opcode = (*(Bytes.data() + Index) & 0xff) | + (*(Bytes.data() + Index + 1) & 0xff) << 8; + outs() << format("\t.short\t0x%04x\n", opcode); + Size = 2; + } else { + errs() << "llvm-mctoll: warning: invalid instruction encoding\n"; + if (Size == 0) + Size = 1; // skip illegible bytes + } + } + } + // Now that we are done disassembled the first symbol set the bool that + // were doing this to false. + FirstSymbol = false; + } + if (!symbolTableWorked) { + // Reading the symbol table didn't work, disassemble the whole section. + uint64_t SectAddress = Sections[SectIdx].getAddress(); + uint64_t SectSize = Sections[SectIdx].getSize(); + uint64_t InstSize; + for (uint64_t Index = 0; Index < SectSize; Index += InstSize) { + MCInst Inst; + + uint64_t PC = SectAddress + Index; + SmallVector AnnotationsBytes; + raw_svector_ostream Annotations(AnnotationsBytes); + if (DisAsm->getInstruction(Inst, InstSize, Bytes.slice(Index), PC, + DebugOut, Annotations)) { + if (!NoLeadingAddr) { + if (FullLeadingAddr) { + if (MachOOF->is64Bit()) + outs() << format("%016" PRIx64, PC); + else + outs() << format("%08" PRIx64, PC); + } else { + outs() << format("%8" PRIx64 ":", PC); + } + } + if (!NoShowRawInsn || Arch == Triple::arm) { + outs() << "\t"; + dumpBytes(makeArrayRef(Bytes.data() + Index, InstSize), outs()); + } + StringRef AnnotationsStr = Annotations.str(); + IP->printInst(&Inst, outs(), AnnotationsStr, *STI); + outs() << "\n"; + } else { + unsigned int Arch = MachOOF->getArch(); + if (Arch == Triple::x86_64 || Arch == Triple::x86) { + outs() << format("\t.byte 0x%02x #bad opcode\n", + *(Bytes.data() + Index) & 0xff); + InstSize = 1; // skip exactly one illegible byte and move on. + } else { + errs() << "llvm-mctoll: warning: invalid instruction encoding\n"; + if (InstSize == 0) + InstSize = 1; // skip illegible bytes + } + } + } + } + // The TripleName's need to be reset if we are called again for a different + // archtecture. + TripleName = ""; + ThumbTripleName = ""; + + if (SymbolizerInfo.method != nullptr) + free(SymbolizerInfo.method); + if (SymbolizerInfo.demangled_name != nullptr) + free(SymbolizerInfo.demangled_name); + if (ThumbSymbolizerInfo.method != nullptr) + free(ThumbSymbolizerInfo.method); + if (ThumbSymbolizerInfo.demangled_name != nullptr) + free(ThumbSymbolizerInfo.demangled_name); + } +} + +//===----------------------------------------------------------------------===// +// __compact_unwind section dumping +//===----------------------------------------------------------------------===// + +namespace { + +template static uint64_t readNext(const char *&Buf) { + using llvm::support::little; + using llvm::support::unaligned; + + uint64_t Val = support::endian::read(Buf); + Buf += sizeof(T); + return Val; +} + +struct CompactUnwindEntry { + uint32_t OffsetInSection; + + uint64_t FunctionAddr; + uint32_t Length; + uint32_t CompactEncoding; + uint64_t PersonalityAddr; + uint64_t LSDAAddr; + + RelocationRef FunctionReloc; + RelocationRef PersonalityReloc; + RelocationRef LSDAReloc; + + CompactUnwindEntry(StringRef Contents, unsigned Offset, bool Is64) + : OffsetInSection(Offset) { + if (Is64) + read(Contents.data() + Offset); + else + read(Contents.data() + Offset); + } + +private: + template void read(const char *Buf) { + FunctionAddr = readNext(Buf); + Length = readNext(Buf); + CompactEncoding = readNext(Buf); + PersonalityAddr = readNext(Buf); + LSDAAddr = readNext(Buf); + } +}; +} // namespace + +/// Given a relocation from __compact_unwind, consisting of the RelocationRef +/// and data being relocated, determine the best base Name and Addend to use for +/// display purposes. +/// +/// 1. An Extern relocation will directly reference a symbol (and the data is +/// then already an addend), so use that. +/// 2. Otherwise the data is an offset in the object file's layout; try to find +// a symbol before it in the same section, and use the offset from there. +/// 3. Finally, if all that fails, fall back to an offset from the start of the +/// referenced section. +static void findUnwindRelocNameAddend(const MachOObjectFile *Obj, + std::map &Symbols, + const RelocationRef &Reloc, uint64_t Addr, + StringRef &Name, uint64_t &Addend) { + if (Reloc.getSymbol() != Obj->symbol_end()) { + Expected NameOrErr = Reloc.getSymbol()->getName(); + if (!NameOrErr) + report_error(Obj->getFileName(), NameOrErr.takeError()); + Name = *NameOrErr; + Addend = Addr; + return; + } + + auto RE = Obj->getRelocation(Reloc.getRawDataRefImpl()); + SectionRef RelocSection = Obj->getAnyRelocationSection(RE); + + uint64_t SectionAddr = RelocSection.getAddress(); + + auto Sym = Symbols.upper_bound(Addr); + if (Sym == Symbols.begin()) { + // The first symbol in the object is after this reference, the best we can + // do is section-relative notation. + RelocSection.getName(Name); + Addend = Addr - SectionAddr; + return; + } + + // Go back one so that SymbolAddress <= Addr. + --Sym; + + auto SectOrErr = Sym->second.getSection(); + if (!SectOrErr) + report_error(Obj->getFileName(), SectOrErr.takeError()); + section_iterator SymSection = *SectOrErr; + if (RelocSection == *SymSection) { + // There's a valid symbol in the same section before this reference. + Expected NameOrErr = Sym->second.getName(); + if (!NameOrErr) + report_error(Obj->getFileName(), NameOrErr.takeError()); + Name = *NameOrErr; + Addend = Addr - Sym->first; + return; + } + + // There is a symbol before this reference, but it's in a different + // section. Probably not helpful to mention it, so use the section name. + RelocSection.getName(Name); + Addend = Addr - SectionAddr; +} + +static void printUnwindRelocDest(const MachOObjectFile *Obj, + std::map &Symbols, + const RelocationRef &Reloc, uint64_t Addr) { + StringRef Name; + uint64_t Addend; + + if (!Reloc.getObject()) + return; + + findUnwindRelocNameAddend(Obj, Symbols, Reloc, Addr, Name, Addend); + + outs() << Name; + if (Addend) + outs() << " + " << format("0x%" PRIx64, Addend); +} + +static void +printMachOCompactUnwindSection(const MachOObjectFile *Obj, + std::map &Symbols, + const SectionRef &CompactUnwind) { + + if (!Obj->isLittleEndian()) { + outs() << "Skipping big-endian __compact_unwind section\n"; + return; + } + + bool Is64 = Obj->is64Bit(); + uint32_t PointerSize = Is64 ? sizeof(uint64_t) : sizeof(uint32_t); + uint32_t EntrySize = 3 * PointerSize + 2 * sizeof(uint32_t); + + StringRef Contents; + CompactUnwind.getContents(Contents); + + SmallVector CompactUnwinds; + + // First populate the initial raw offsets, encodings and so on from the entry. + for (unsigned Offset = 0; Offset < Contents.size(); Offset += EntrySize) { + CompactUnwindEntry Entry(Contents.data(), Offset, Is64); + CompactUnwinds.push_back(Entry); + } + + // Next we need to look at the relocations to find out what objects are + // actually being referred to. + for (const RelocationRef &Reloc : CompactUnwind.relocations()) { + uint64_t RelocAddress = Reloc.getOffset(); + + uint32_t EntryIdx = RelocAddress / EntrySize; + uint32_t OffsetInEntry = RelocAddress - EntryIdx * EntrySize; + CompactUnwindEntry &Entry = CompactUnwinds[EntryIdx]; + + if (OffsetInEntry == 0) + Entry.FunctionReloc = Reloc; + else if (OffsetInEntry == PointerSize + 2 * sizeof(uint32_t)) + Entry.PersonalityReloc = Reloc; + else if (OffsetInEntry == 2 * PointerSize + 2 * sizeof(uint32_t)) + Entry.LSDAReloc = Reloc; + else { + outs() << "Invalid relocation in __compact_unwind section\n"; + return; + } + } + + // Finally, we're ready to print the data we've gathered. + outs() << "Contents of __compact_unwind section:\n"; + for (auto &Entry : CompactUnwinds) { + outs() << " Entry at offset " + << format("0x%" PRIx32, Entry.OffsetInSection) << ":\n"; + + // 1. Start of the region this entry applies to. + outs() << " start: " + << format("0x%" PRIx64, Entry.FunctionAddr) << ' '; + printUnwindRelocDest(Obj, Symbols, Entry.FunctionReloc, Entry.FunctionAddr); + outs() << '\n'; + + // 2. Length of the region this entry applies to. + outs() << " length: " << format("0x%" PRIx32, Entry.Length) + << '\n'; + // 3. The 32-bit compact encoding. + outs() << " compact encoding: " + << format("0x%08" PRIx32, Entry.CompactEncoding) << '\n'; + + // 4. The personality function, if present. + if (Entry.PersonalityReloc.getObject()) { + outs() << " personality function: " + << format("0x%" PRIx64, Entry.PersonalityAddr) << ' '; + printUnwindRelocDest(Obj, Symbols, Entry.PersonalityReloc, + Entry.PersonalityAddr); + outs() << '\n'; + } + + // 5. This entry's language-specific data area. + if (Entry.LSDAReloc.getObject()) { + outs() << " LSDA: " + << format("0x%" PRIx64, Entry.LSDAAddr) << ' '; + printUnwindRelocDest(Obj, Symbols, Entry.LSDAReloc, Entry.LSDAAddr); + outs() << '\n'; + } + } +} + +//===----------------------------------------------------------------------===// +// __unwind_info section dumping +//===----------------------------------------------------------------------===// + +static void printRegularSecondLevelUnwindPage(const char *PageStart) { + const char *Pos = PageStart; + uint32_t Kind = readNext(Pos); + (void)Kind; + assert(Kind == 2 && "kind for a regular 2nd level index should be 2"); + + uint16_t EntriesStart = readNext(Pos); + uint16_t NumEntries = readNext(Pos); + + Pos = PageStart + EntriesStart; + for (unsigned i = 0; i < NumEntries; ++i) { + uint32_t FunctionOffset = readNext(Pos); + uint32_t Encoding = readNext(Pos); + + outs() << " [" << i << "]: " + << "function offset=" << format("0x%08" PRIx32, FunctionOffset) + << ", " + << "encoding=" << format("0x%08" PRIx32, Encoding) << '\n'; + } +} + +static void printCompressedSecondLevelUnwindPage( + const char *PageStart, uint32_t FunctionBase, + const SmallVectorImpl &CommonEncodings) { + const char *Pos = PageStart; + uint32_t Kind = readNext(Pos); + (void)Kind; + assert(Kind == 3 && "kind for a compressed 2nd level index should be 3"); + + uint16_t EntriesStart = readNext(Pos); + uint16_t NumEntries = readNext(Pos); + + uint16_t EncodingsStart = readNext(Pos); + readNext(Pos); + const auto *PageEncodings = reinterpret_cast( + PageStart + EncodingsStart); + + Pos = PageStart + EntriesStart; + for (unsigned i = 0; i < NumEntries; ++i) { + uint32_t Entry = readNext(Pos); + uint32_t FunctionOffset = FunctionBase + (Entry & 0xffffff); + uint32_t EncodingIdx = Entry >> 24; + + uint32_t Encoding; + if (EncodingIdx < CommonEncodings.size()) + Encoding = CommonEncodings[EncodingIdx]; + else + Encoding = PageEncodings[EncodingIdx - CommonEncodings.size()]; + + outs() << " [" << i << "]: " + << "function offset=" << format("0x%08" PRIx32, FunctionOffset) + << ", " + << "encoding[" << EncodingIdx + << "]=" << format("0x%08" PRIx32, Encoding) << '\n'; + } +} + +static void printMachOUnwindInfoSection(const MachOObjectFile *Obj, + std::map &Symbols, + const SectionRef &UnwindInfo) { + + if (!Obj->isLittleEndian()) { + outs() << "Skipping big-endian __unwind_info section\n"; + return; + } + + outs() << "Contents of __unwind_info section:\n"; + + StringRef Contents; + UnwindInfo.getContents(Contents); + const char *Pos = Contents.data(); + + //===---------------------------------- + // Section header + //===---------------------------------- + + uint32_t Version = readNext(Pos); + outs() << " Version: " + << format("0x%" PRIx32, Version) << '\n'; + if (Version != 1) { + outs() << " Skipping section with unknown version\n"; + return; + } + + uint32_t CommonEncodingsStart = readNext(Pos); + outs() << " Common encodings array section offset: " + << format("0x%" PRIx32, CommonEncodingsStart) << '\n'; + uint32_t NumCommonEncodings = readNext(Pos); + outs() << " Number of common encodings in array: " + << format("0x%" PRIx32, NumCommonEncodings) << '\n'; + + uint32_t PersonalitiesStart = readNext(Pos); + outs() << " Personality function array section offset: " + << format("0x%" PRIx32, PersonalitiesStart) << '\n'; + uint32_t NumPersonalities = readNext(Pos); + outs() << " Number of personality functions in array: " + << format("0x%" PRIx32, NumPersonalities) << '\n'; + + uint32_t IndicesStart = readNext(Pos); + outs() << " Index array section offset: " + << format("0x%" PRIx32, IndicesStart) << '\n'; + uint32_t NumIndices = readNext(Pos); + outs() << " Number of indices in array: " + << format("0x%" PRIx32, NumIndices) << '\n'; + + //===---------------------------------- + // A shared list of common encodings + //===---------------------------------- + + // These occupy indices in the range [0, N] whenever an encoding is referenced + // from a compressed 2nd level index table. In practice the linker only + // creates ~128 of these, so that indices are available to embed encodings in + // the 2nd level index. + + SmallVector CommonEncodings; + outs() << " Common encodings: (count = " << NumCommonEncodings << ")\n"; + Pos = Contents.data() + CommonEncodingsStart; + for (unsigned i = 0; i < NumCommonEncodings; ++i) { + uint32_t Encoding = readNext(Pos); + CommonEncodings.push_back(Encoding); + + outs() << " encoding[" << i << "]: " << format("0x%08" PRIx32, Encoding) + << '\n'; + } + + //===---------------------------------- + // Personality functions used in this executable + //===---------------------------------- + + // There should be only a handful of these (one per source language, + // roughly). Particularly since they only get 2 bits in the compact encoding. + + outs() << " Personality functions: (count = " << NumPersonalities << ")\n"; + Pos = Contents.data() + PersonalitiesStart; + for (unsigned i = 0; i < NumPersonalities; ++i) { + uint32_t PersonalityFn = readNext(Pos); + outs() << " personality[" << i + 1 + << "]: " << format("0x%08" PRIx32, PersonalityFn) << '\n'; + } + + //===---------------------------------- + // The level 1 index entries + //===---------------------------------- + + // These specify an approximate place to start searching for the more detailed + // information, sorted by PC. + + struct IndexEntry { + uint32_t FunctionOffset; + uint32_t SecondLevelPageStart; + uint32_t LSDAStart; + }; + + SmallVector IndexEntries; + + outs() << " Top level indices: (count = " << NumIndices << ")\n"; + Pos = Contents.data() + IndicesStart; + for (unsigned i = 0; i < NumIndices; ++i) { + IndexEntry Entry; + + Entry.FunctionOffset = readNext(Pos); + Entry.SecondLevelPageStart = readNext(Pos); + Entry.LSDAStart = readNext(Pos); + IndexEntries.push_back(Entry); + + outs() << " [" << i << "]: " + << "function offset=" << format("0x%08" PRIx32, Entry.FunctionOffset) + << ", " + << "2nd level page offset=" + << format("0x%08" PRIx32, Entry.SecondLevelPageStart) << ", " + << "LSDA offset=" << format("0x%08" PRIx32, Entry.LSDAStart) << '\n'; + } + + //===---------------------------------- + // Next come the LSDA tables + //===---------------------------------- + + // The LSDA layout is rather implicit: it's a contiguous array of entries from + // the first top-level index's LSDAOffset to the last (sentinel). + + outs() << " LSDA descriptors:\n"; + Pos = Contents.data() + IndexEntries[0].LSDAStart; + int NumLSDAs = (IndexEntries.back().LSDAStart - IndexEntries[0].LSDAStart) / + (2 * sizeof(uint32_t)); + for (int i = 0; i < NumLSDAs; ++i) { + uint32_t FunctionOffset = readNext(Pos); + uint32_t LSDAOffset = readNext(Pos); + outs() << " [" << i << "]: " + << "function offset=" << format("0x%08" PRIx32, FunctionOffset) + << ", " + << "LSDA offset=" << format("0x%08" PRIx32, LSDAOffset) << '\n'; + } + + //===---------------------------------- + // Finally, the 2nd level indices + //===---------------------------------- + + // Generally these are 4K in size, and have 2 possible forms: + // + Regular stores up to 511 entries with disparate encodings + // + Compressed stores up to 1021 entries if few enough compact encoding + // values are used. + outs() << " Second level indices:\n"; + for (unsigned i = 0; i < IndexEntries.size() - 1; ++i) { + // The final sentinel top-level index has no associated 2nd level page + if (IndexEntries[i].SecondLevelPageStart == 0) + break; + + outs() << " Second level index[" << i << "]: " + << "offset in section=" + << format("0x%08" PRIx32, IndexEntries[i].SecondLevelPageStart) + << ", " + << "base function offset=" + << format("0x%08" PRIx32, IndexEntries[i].FunctionOffset) << '\n'; + + Pos = Contents.data() + IndexEntries[i].SecondLevelPageStart; + uint32_t Kind = *reinterpret_cast(Pos); + if (Kind == 2) + printRegularSecondLevelUnwindPage(Pos); + else if (Kind == 3) + printCompressedSecondLevelUnwindPage(Pos, IndexEntries[i].FunctionOffset, + CommonEncodings); + else + outs() << " Skipping 2nd level page with unknown kind " << Kind + << '\n'; + } +} + +void llvm::printMachOUnwindInfo(const MachOObjectFile *Obj) { + std::map Symbols; + for (const SymbolRef &SymRef : Obj->symbols()) { + // Discard any undefined or absolute symbols. They're not going to take part + // in the convenience lookup for unwind info and just take up resources. + auto SectOrErr = SymRef.getSection(); + if (!SectOrErr) { + // TODO: Actually report errors helpfully. + consumeError(SectOrErr.takeError()); + continue; + } + section_iterator Section = *SectOrErr; + if (Section == Obj->section_end()) + continue; + + uint64_t Addr = SymRef.getValue(); + Symbols.insert(std::make_pair(Addr, SymRef)); + } + + for (const SectionRef &Section : Obj->sections()) { + StringRef SectName; + Section.getName(SectName); + if (SectName == "__compact_unwind") + printMachOCompactUnwindSection(Obj, Symbols, Section); + else if (SectName == "__unwind_info") + printMachOUnwindInfoSection(Obj, Symbols, Section); + } +} + +static void PrintMachHeader(uint32_t magic, uint32_t cputype, + uint32_t cpusubtype, uint32_t filetype, + uint32_t ncmds, uint32_t sizeofcmds, uint32_t flags, + bool verbose) { + outs() << "Mach header\n"; + outs() << " magic cputype cpusubtype caps filetype ncmds " + "sizeofcmds flags\n"; + if (verbose) { + if (magic == MachO::MH_MAGIC) + outs() << " MH_MAGIC"; + else if (magic == MachO::MH_MAGIC_64) + outs() << "MH_MAGIC_64"; + else + outs() << format(" 0x%08" PRIx32, magic); + switch (cputype) { + case MachO::CPU_TYPE_I386: + outs() << " I386"; + switch (cpusubtype & ~MachO::CPU_SUBTYPE_MASK) { + case MachO::CPU_SUBTYPE_I386_ALL: + outs() << " ALL"; + break; + default: + outs() << format(" %10d", cpusubtype & ~MachO::CPU_SUBTYPE_MASK); + break; + } + break; + case MachO::CPU_TYPE_X86_64: + outs() << " X86_64"; + switch (cpusubtype & ~MachO::CPU_SUBTYPE_MASK) { + case MachO::CPU_SUBTYPE_X86_64_ALL: + outs() << " ALL"; + break; + case MachO::CPU_SUBTYPE_X86_64_H: + outs() << " Haswell"; + break; + default: + outs() << format(" %10d", cpusubtype & ~MachO::CPU_SUBTYPE_MASK); + break; + } + break; + case MachO::CPU_TYPE_ARM: + outs() << " ARM"; + switch (cpusubtype & ~MachO::CPU_SUBTYPE_MASK) { + case MachO::CPU_SUBTYPE_ARM_ALL: + outs() << " ALL"; + break; + case MachO::CPU_SUBTYPE_ARM_V4T: + outs() << " V4T"; + break; + case MachO::CPU_SUBTYPE_ARM_V5TEJ: + outs() << " V5TEJ"; + break; + case MachO::CPU_SUBTYPE_ARM_XSCALE: + outs() << " XSCALE"; + break; + case MachO::CPU_SUBTYPE_ARM_V6: + outs() << " V6"; + break; + case MachO::CPU_SUBTYPE_ARM_V6M: + outs() << " V6M"; + break; + case MachO::CPU_SUBTYPE_ARM_V7: + outs() << " V7"; + break; + case MachO::CPU_SUBTYPE_ARM_V7EM: + outs() << " V7EM"; + break; + case MachO::CPU_SUBTYPE_ARM_V7K: + outs() << " V7K"; + break; + case MachO::CPU_SUBTYPE_ARM_V7M: + outs() << " V7M"; + break; + case MachO::CPU_SUBTYPE_ARM_V7S: + outs() << " V7S"; + break; + default: + outs() << format(" %10d", cpusubtype & ~MachO::CPU_SUBTYPE_MASK); + break; + } + break; + case MachO::CPU_TYPE_ARM64: + outs() << " ARM64"; + switch (cpusubtype & ~MachO::CPU_SUBTYPE_MASK) { + case MachO::CPU_SUBTYPE_ARM64_ALL: + outs() << " ALL"; + break; + default: + outs() << format(" %10d", cpusubtype & ~MachO::CPU_SUBTYPE_MASK); + break; + } + break; + case MachO::CPU_TYPE_POWERPC: + outs() << " PPC"; + switch (cpusubtype & ~MachO::CPU_SUBTYPE_MASK) { + case MachO::CPU_SUBTYPE_POWERPC_ALL: + outs() << " ALL"; + break; + default: + outs() << format(" %10d", cpusubtype & ~MachO::CPU_SUBTYPE_MASK); + break; + } + break; + case MachO::CPU_TYPE_POWERPC64: + outs() << " PPC64"; + switch (cpusubtype & ~MachO::CPU_SUBTYPE_MASK) { + case MachO::CPU_SUBTYPE_POWERPC_ALL: + outs() << " ALL"; + break; + default: + outs() << format(" %10d", cpusubtype & ~MachO::CPU_SUBTYPE_MASK); + break; + } + break; + default: + outs() << format(" %7d", cputype); + outs() << format(" %10d", cpusubtype & ~MachO::CPU_SUBTYPE_MASK); + break; + } + if ((cpusubtype & MachO::CPU_SUBTYPE_MASK) == MachO::CPU_SUBTYPE_LIB64) { + outs() << " LIB64"; + } else { + outs() << format(" 0x%02" PRIx32, + (cpusubtype & MachO::CPU_SUBTYPE_MASK) >> 24); + } + switch (filetype) { + case MachO::MH_OBJECT: + outs() << " OBJECT"; + break; + case MachO::MH_EXECUTE: + outs() << " EXECUTE"; + break; + case MachO::MH_FVMLIB: + outs() << " FVMLIB"; + break; + case MachO::MH_CORE: + outs() << " CORE"; + break; + case MachO::MH_PRELOAD: + outs() << " PRELOAD"; + break; + case MachO::MH_DYLIB: + outs() << " DYLIB"; + break; + case MachO::MH_DYLIB_STUB: + outs() << " DYLIB_STUB"; + break; + case MachO::MH_DYLINKER: + outs() << " DYLINKER"; + break; + case MachO::MH_BUNDLE: + outs() << " BUNDLE"; + break; + case MachO::MH_DSYM: + outs() << " DSYM"; + break; + case MachO::MH_KEXT_BUNDLE: + outs() << " KEXTBUNDLE"; + break; + default: + outs() << format(" %10u", filetype); + break; + } + outs() << format(" %5u", ncmds); + outs() << format(" %10u", sizeofcmds); + uint32_t f = flags; + if (f & MachO::MH_NOUNDEFS) { + outs() << " NOUNDEFS"; + f &= ~MachO::MH_NOUNDEFS; + } + if (f & MachO::MH_INCRLINK) { + outs() << " INCRLINK"; + f &= ~MachO::MH_INCRLINK; + } + if (f & MachO::MH_DYLDLINK) { + outs() << " DYLDLINK"; + f &= ~MachO::MH_DYLDLINK; + } + if (f & MachO::MH_BINDATLOAD) { + outs() << " BINDATLOAD"; + f &= ~MachO::MH_BINDATLOAD; + } + if (f & MachO::MH_PREBOUND) { + outs() << " PREBOUND"; + f &= ~MachO::MH_PREBOUND; + } + if (f & MachO::MH_SPLIT_SEGS) { + outs() << " SPLIT_SEGS"; + f &= ~MachO::MH_SPLIT_SEGS; + } + if (f & MachO::MH_LAZY_INIT) { + outs() << " LAZY_INIT"; + f &= ~MachO::MH_LAZY_INIT; + } + if (f & MachO::MH_TWOLEVEL) { + outs() << " TWOLEVEL"; + f &= ~MachO::MH_TWOLEVEL; + } + if (f & MachO::MH_FORCE_FLAT) { + outs() << " FORCE_FLAT"; + f &= ~MachO::MH_FORCE_FLAT; + } + if (f & MachO::MH_NOMULTIDEFS) { + outs() << " NOMULTIDEFS"; + f &= ~MachO::MH_NOMULTIDEFS; + } + if (f & MachO::MH_NOFIXPREBINDING) { + outs() << " NOFIXPREBINDING"; + f &= ~MachO::MH_NOFIXPREBINDING; + } + if (f & MachO::MH_PREBINDABLE) { + outs() << " PREBINDABLE"; + f &= ~MachO::MH_PREBINDABLE; + } + if (f & MachO::MH_ALLMODSBOUND) { + outs() << " ALLMODSBOUND"; + f &= ~MachO::MH_ALLMODSBOUND; + } + if (f & MachO::MH_SUBSECTIONS_VIA_SYMBOLS) { + outs() << " SUBSECTIONS_VIA_SYMBOLS"; + f &= ~MachO::MH_SUBSECTIONS_VIA_SYMBOLS; + } + if (f & MachO::MH_CANONICAL) { + outs() << " CANONICAL"; + f &= ~MachO::MH_CANONICAL; + } + if (f & MachO::MH_WEAK_DEFINES) { + outs() << " WEAK_DEFINES"; + f &= ~MachO::MH_WEAK_DEFINES; + } + if (f & MachO::MH_BINDS_TO_WEAK) { + outs() << " BINDS_TO_WEAK"; + f &= ~MachO::MH_BINDS_TO_WEAK; + } + if (f & MachO::MH_ALLOW_STACK_EXECUTION) { + outs() << " ALLOW_STACK_EXECUTION"; + f &= ~MachO::MH_ALLOW_STACK_EXECUTION; + } + if (f & MachO::MH_DEAD_STRIPPABLE_DYLIB) { + outs() << " DEAD_STRIPPABLE_DYLIB"; + f &= ~MachO::MH_DEAD_STRIPPABLE_DYLIB; + } + if (f & MachO::MH_PIE) { + outs() << " PIE"; + f &= ~MachO::MH_PIE; + } + if (f & MachO::MH_NO_REEXPORTED_DYLIBS) { + outs() << " NO_REEXPORTED_DYLIBS"; + f &= ~MachO::MH_NO_REEXPORTED_DYLIBS; + } + if (f & MachO::MH_HAS_TLV_DESCRIPTORS) { + outs() << " MH_HAS_TLV_DESCRIPTORS"; + f &= ~MachO::MH_HAS_TLV_DESCRIPTORS; + } + if (f & MachO::MH_NO_HEAP_EXECUTION) { + outs() << " MH_NO_HEAP_EXECUTION"; + f &= ~MachO::MH_NO_HEAP_EXECUTION; + } + if (f & MachO::MH_APP_EXTENSION_SAFE) { + outs() << " APP_EXTENSION_SAFE"; + f &= ~MachO::MH_APP_EXTENSION_SAFE; + } + if (f & MachO::MH_NLIST_OUTOFSYNC_WITH_DYLDINFO) { + outs() << " NLIST_OUTOFSYNC_WITH_DYLDINFO"; + f &= ~MachO::MH_NLIST_OUTOFSYNC_WITH_DYLDINFO; + } + if (f != 0 || flags == 0) + outs() << format(" 0x%08" PRIx32, f); + } else { + outs() << format(" 0x%08" PRIx32, magic); + outs() << format(" %7d", cputype); + outs() << format(" %10d", cpusubtype & ~MachO::CPU_SUBTYPE_MASK); + outs() << format(" 0x%02" PRIx32, + (cpusubtype & MachO::CPU_SUBTYPE_MASK) >> 24); + outs() << format(" %10u", filetype); + outs() << format(" %5u", ncmds); + outs() << format(" %10u", sizeofcmds); + outs() << format(" 0x%08" PRIx32, flags); + } + outs() << "\n"; +} + +static void PrintSegmentCommand(uint32_t cmd, uint32_t cmdsize, + StringRef SegName, uint64_t vmaddr, + uint64_t vmsize, uint64_t fileoff, + uint64_t filesize, uint32_t maxprot, + uint32_t initprot, uint32_t nsects, + uint32_t flags, uint32_t object_size, + bool verbose) { + uint64_t expected_cmdsize; + if (cmd == MachO::LC_SEGMENT) { + outs() << " cmd LC_SEGMENT\n"; + expected_cmdsize = nsects; + expected_cmdsize *= sizeof(struct MachO::section); + expected_cmdsize += sizeof(struct MachO::segment_command); + } else { + outs() << " cmd LC_SEGMENT_64\n"; + expected_cmdsize = nsects; + expected_cmdsize *= sizeof(struct MachO::section_64); + expected_cmdsize += sizeof(struct MachO::segment_command_64); + } + outs() << " cmdsize " << cmdsize; + if (cmdsize != expected_cmdsize) + outs() << " Inconsistent size\n"; + else + outs() << "\n"; + outs() << " segname " << SegName << "\n"; + if (cmd == MachO::LC_SEGMENT_64) { + outs() << " vmaddr " << format("0x%016" PRIx64, vmaddr) << "\n"; + outs() << " vmsize " << format("0x%016" PRIx64, vmsize) << "\n"; + } else { + outs() << " vmaddr " << format("0x%08" PRIx64, vmaddr) << "\n"; + outs() << " vmsize " << format("0x%08" PRIx64, vmsize) << "\n"; + } + outs() << " fileoff " << fileoff; + if (fileoff > object_size) + outs() << " (past end of file)\n"; + else + outs() << "\n"; + outs() << " filesize " << filesize; + if (fileoff + filesize > object_size) + outs() << " (past end of file)\n"; + else + outs() << "\n"; + if (verbose) { + if ((maxprot & ~(MachO::VM_PROT_READ | MachO::VM_PROT_WRITE | + MachO::VM_PROT_EXECUTE)) != 0) + outs() << " maxprot ?" << format("0x%08" PRIx32, maxprot) << "\n"; + else { + outs() << " maxprot "; + outs() << ((maxprot & MachO::VM_PROT_READ) ? "r" : "-"); + outs() << ((maxprot & MachO::VM_PROT_WRITE) ? "w" : "-"); + outs() << ((maxprot & MachO::VM_PROT_EXECUTE) ? "x\n" : "-\n"); + } + if ((initprot & ~(MachO::VM_PROT_READ | MachO::VM_PROT_WRITE | + MachO::VM_PROT_EXECUTE)) != 0) + outs() << " initprot ?" << format("0x%08" PRIx32, initprot) << "\n"; + else { + outs() << " initprot "; + outs() << ((initprot & MachO::VM_PROT_READ) ? "r" : "-"); + outs() << ((initprot & MachO::VM_PROT_WRITE) ? "w" : "-"); + outs() << ((initprot & MachO::VM_PROT_EXECUTE) ? "x\n" : "-\n"); + } + } else { + outs() << " maxprot " << format("0x%08" PRIx32, maxprot) << "\n"; + outs() << " initprot " << format("0x%08" PRIx32, initprot) << "\n"; + } + outs() << " nsects " << nsects << "\n"; + if (verbose) { + outs() << " flags"; + if (flags == 0) + outs() << " (none)\n"; + else { + if (flags & MachO::SG_HIGHVM) { + outs() << " HIGHVM"; + flags &= ~MachO::SG_HIGHVM; + } + if (flags & MachO::SG_FVMLIB) { + outs() << " FVMLIB"; + flags &= ~MachO::SG_FVMLIB; + } + if (flags & MachO::SG_NORELOC) { + outs() << " NORELOC"; + flags &= ~MachO::SG_NORELOC; + } + if (flags & MachO::SG_PROTECTED_VERSION_1) { + outs() << " PROTECTED_VERSION_1"; + flags &= ~MachO::SG_PROTECTED_VERSION_1; + } + if (flags) + outs() << format(" 0x%08" PRIx32, flags) << " (unknown flags)\n"; + else + outs() << "\n"; + } + } else { + outs() << " flags " << format("0x%" PRIx32, flags) << "\n"; + } +} + +static void PrintSection(const char *sectname, const char *segname, + uint64_t addr, uint64_t size, uint32_t offset, + uint32_t align, uint32_t reloff, uint32_t nreloc, + uint32_t flags, uint32_t reserved1, uint32_t reserved2, + uint32_t cmd, const char *sg_segname, + uint32_t filetype, uint32_t object_size, + bool verbose) { + outs() << "Section\n"; + outs() << " sectname " << format("%.16s\n", sectname); + outs() << " segname " << format("%.16s", segname); + if (filetype != MachO::MH_OBJECT && strncmp(sg_segname, segname, 16) != 0) + outs() << " (does not match segment)\n"; + else + outs() << "\n"; + if (cmd == MachO::LC_SEGMENT_64) { + outs() << " addr " << format("0x%016" PRIx64, addr) << "\n"; + outs() << " size " << format("0x%016" PRIx64, size); + } else { + outs() << " addr " << format("0x%08" PRIx64, addr) << "\n"; + outs() << " size " << format("0x%08" PRIx64, size); + } + if ((flags & MachO::S_ZEROFILL) != 0 && offset + size > object_size) + outs() << " (past end of file)\n"; + else + outs() << "\n"; + outs() << " offset " << offset; + if (offset > object_size) + outs() << " (past end of file)\n"; + else + outs() << "\n"; + uint32_t align_shifted = 1 << align; + outs() << " align 2^" << align << " (" << align_shifted << ")\n"; + outs() << " reloff " << reloff; + if (reloff > object_size) + outs() << " (past end of file)\n"; + else + outs() << "\n"; + outs() << " nreloc " << nreloc; + if (reloff + nreloc * sizeof(struct MachO::relocation_info) > object_size) + outs() << " (past end of file)\n"; + else + outs() << "\n"; + uint32_t section_type = flags & MachO::SECTION_TYPE; + if (verbose) { + outs() << " type"; + if (section_type == MachO::S_REGULAR) + outs() << " S_REGULAR\n"; + else if (section_type == MachO::S_ZEROFILL) + outs() << " S_ZEROFILL\n"; + else if (section_type == MachO::S_CSTRING_LITERALS) + outs() << " S_CSTRING_LITERALS\n"; + else if (section_type == MachO::S_4BYTE_LITERALS) + outs() << " S_4BYTE_LITERALS\n"; + else if (section_type == MachO::S_8BYTE_LITERALS) + outs() << " S_8BYTE_LITERALS\n"; + else if (section_type == MachO::S_16BYTE_LITERALS) + outs() << " S_16BYTE_LITERALS\n"; + else if (section_type == MachO::S_LITERAL_POINTERS) + outs() << " S_LITERAL_POINTERS\n"; + else if (section_type == MachO::S_NON_LAZY_SYMBOL_POINTERS) + outs() << " S_NON_LAZY_SYMBOL_POINTERS\n"; + else if (section_type == MachO::S_LAZY_SYMBOL_POINTERS) + outs() << " S_LAZY_SYMBOL_POINTERS\n"; + else if (section_type == MachO::S_SYMBOL_STUBS) + outs() << " S_SYMBOL_STUBS\n"; + else if (section_type == MachO::S_MOD_INIT_FUNC_POINTERS) + outs() << " S_MOD_INIT_FUNC_POINTERS\n"; + else if (section_type == MachO::S_MOD_TERM_FUNC_POINTERS) + outs() << " S_MOD_TERM_FUNC_POINTERS\n"; + else if (section_type == MachO::S_COALESCED) + outs() << " S_COALESCED\n"; + else if (section_type == MachO::S_INTERPOSING) + outs() << " S_INTERPOSING\n"; + else if (section_type == MachO::S_DTRACE_DOF) + outs() << " S_DTRACE_DOF\n"; + else if (section_type == MachO::S_LAZY_DYLIB_SYMBOL_POINTERS) + outs() << " S_LAZY_DYLIB_SYMBOL_POINTERS\n"; + else if (section_type == MachO::S_THREAD_LOCAL_REGULAR) + outs() << " S_THREAD_LOCAL_REGULAR\n"; + else if (section_type == MachO::S_THREAD_LOCAL_ZEROFILL) + outs() << " S_THREAD_LOCAL_ZEROFILL\n"; + else if (section_type == MachO::S_THREAD_LOCAL_VARIABLES) + outs() << " S_THREAD_LOCAL_VARIABLES\n"; + else if (section_type == MachO::S_THREAD_LOCAL_VARIABLE_POINTERS) + outs() << " S_THREAD_LOCAL_VARIABLE_POINTERS\n"; + else if (section_type == MachO::S_THREAD_LOCAL_INIT_FUNCTION_POINTERS) + outs() << " S_THREAD_LOCAL_INIT_FUNCTION_POINTERS\n"; + else + outs() << format("0x%08" PRIx32, section_type) << "\n"; + outs() << "attributes"; + uint32_t section_attributes = flags & MachO::SECTION_ATTRIBUTES; + if (section_attributes & MachO::S_ATTR_PURE_INSTRUCTIONS) + outs() << " PURE_INSTRUCTIONS"; + if (section_attributes & MachO::S_ATTR_NO_TOC) + outs() << " NO_TOC"; + if (section_attributes & MachO::S_ATTR_STRIP_STATIC_SYMS) + outs() << " STRIP_STATIC_SYMS"; + if (section_attributes & MachO::S_ATTR_NO_DEAD_STRIP) + outs() << " NO_DEAD_STRIP"; + if (section_attributes & MachO::S_ATTR_LIVE_SUPPORT) + outs() << " LIVE_SUPPORT"; + if (section_attributes & MachO::S_ATTR_SELF_MODIFYING_CODE) + outs() << " SELF_MODIFYING_CODE"; + if (section_attributes & MachO::S_ATTR_DEBUG) + outs() << " DEBUG"; + if (section_attributes & MachO::S_ATTR_SOME_INSTRUCTIONS) + outs() << " SOME_INSTRUCTIONS"; + if (section_attributes & MachO::S_ATTR_EXT_RELOC) + outs() << " EXT_RELOC"; + if (section_attributes & MachO::S_ATTR_LOC_RELOC) + outs() << " LOC_RELOC"; + if (section_attributes == 0) + outs() << " (none)"; + outs() << "\n"; + } else + outs() << " flags " << format("0x%08" PRIx32, flags) << "\n"; + outs() << " reserved1 " << reserved1; + if (section_type == MachO::S_SYMBOL_STUBS || + section_type == MachO::S_LAZY_SYMBOL_POINTERS || + section_type == MachO::S_LAZY_DYLIB_SYMBOL_POINTERS || + section_type == MachO::S_NON_LAZY_SYMBOL_POINTERS || + section_type == MachO::S_THREAD_LOCAL_VARIABLE_POINTERS) + outs() << " (index into indirect symbol table)\n"; + else + outs() << "\n"; + outs() << " reserved2 " << reserved2; + if (section_type == MachO::S_SYMBOL_STUBS) + outs() << " (size of stubs)\n"; + else + outs() << "\n"; +} + +static void PrintSymtabLoadCommand(MachO::symtab_command st, bool Is64Bit, + uint32_t object_size) { + outs() << " cmd LC_SYMTAB\n"; + outs() << " cmdsize " << st.cmdsize; + if (st.cmdsize != sizeof(struct MachO::symtab_command)) + outs() << " Incorrect size\n"; + else + outs() << "\n"; + outs() << " symoff " << st.symoff; + if (st.symoff > object_size) + outs() << " (past end of file)\n"; + else + outs() << "\n"; + outs() << " nsyms " << st.nsyms; + uint64_t big_size; + if (Is64Bit) { + big_size = st.nsyms; + big_size *= sizeof(struct MachO::nlist_64); + big_size += st.symoff; + if (big_size > object_size) + outs() << " (past end of file)\n"; + else + outs() << "\n"; + } else { + big_size = st.nsyms; + big_size *= sizeof(struct MachO::nlist); + big_size += st.symoff; + if (big_size > object_size) + outs() << " (past end of file)\n"; + else + outs() << "\n"; + } + outs() << " stroff " << st.stroff; + if (st.stroff > object_size) + outs() << " (past end of file)\n"; + else + outs() << "\n"; + outs() << " strsize " << st.strsize; + big_size = st.stroff; + big_size += st.strsize; + if (big_size > object_size) + outs() << " (past end of file)\n"; + else + outs() << "\n"; +} + +static void PrintDysymtabLoadCommand(MachO::dysymtab_command dyst, + uint32_t nsyms, uint32_t object_size, + bool Is64Bit) { + outs() << " cmd LC_DYSYMTAB\n"; + outs() << " cmdsize " << dyst.cmdsize; + if (dyst.cmdsize != sizeof(struct MachO::dysymtab_command)) + outs() << " Incorrect size\n"; + else + outs() << "\n"; + outs() << " ilocalsym " << dyst.ilocalsym; + if (dyst.ilocalsym > nsyms) + outs() << " (greater than the number of symbols)\n"; + else + outs() << "\n"; + outs() << " nlocalsym " << dyst.nlocalsym; + uint64_t big_size; + big_size = dyst.ilocalsym; + big_size += dyst.nlocalsym; + if (big_size > nsyms) + outs() << " (past the end of the symbol table)\n"; + else + outs() << "\n"; + outs() << " iextdefsym " << dyst.iextdefsym; + if (dyst.iextdefsym > nsyms) + outs() << " (greater than the number of symbols)\n"; + else + outs() << "\n"; + outs() << " nextdefsym " << dyst.nextdefsym; + big_size = dyst.iextdefsym; + big_size += dyst.nextdefsym; + if (big_size > nsyms) + outs() << " (past the end of the symbol table)\n"; + else + outs() << "\n"; + outs() << " iundefsym " << dyst.iundefsym; + if (dyst.iundefsym > nsyms) + outs() << " (greater than the number of symbols)\n"; + else + outs() << "\n"; + outs() << " nundefsym " << dyst.nundefsym; + big_size = dyst.iundefsym; + big_size += dyst.nundefsym; + if (big_size > nsyms) + outs() << " (past the end of the symbol table)\n"; + else + outs() << "\n"; + outs() << " tocoff " << dyst.tocoff; + if (dyst.tocoff > object_size) + outs() << " (past end of file)\n"; + else + outs() << "\n"; + outs() << " ntoc " << dyst.ntoc; + big_size = dyst.ntoc; + big_size *= sizeof(struct MachO::dylib_table_of_contents); + big_size += dyst.tocoff; + if (big_size > object_size) + outs() << " (past end of file)\n"; + else + outs() << "\n"; + outs() << " modtaboff " << dyst.modtaboff; + if (dyst.modtaboff > object_size) + outs() << " (past end of file)\n"; + else + outs() << "\n"; + outs() << " nmodtab " << dyst.nmodtab; + uint64_t modtabend; + if (Is64Bit) { + modtabend = dyst.nmodtab; + modtabend *= sizeof(struct MachO::dylib_module_64); + modtabend += dyst.modtaboff; + } else { + modtabend = dyst.nmodtab; + modtabend *= sizeof(struct MachO::dylib_module); + modtabend += dyst.modtaboff; + } + if (modtabend > object_size) + outs() << " (past end of file)\n"; + else + outs() << "\n"; + outs() << " extrefsymoff " << dyst.extrefsymoff; + if (dyst.extrefsymoff > object_size) + outs() << " (past end of file)\n"; + else + outs() << "\n"; + outs() << " nextrefsyms " << dyst.nextrefsyms; + big_size = dyst.nextrefsyms; + big_size *= sizeof(struct MachO::dylib_reference); + big_size += dyst.extrefsymoff; + if (big_size > object_size) + outs() << " (past end of file)\n"; + else + outs() << "\n"; + outs() << " indirectsymoff " << dyst.indirectsymoff; + if (dyst.indirectsymoff > object_size) + outs() << " (past end of file)\n"; + else + outs() << "\n"; + outs() << " nindirectsyms " << dyst.nindirectsyms; + big_size = dyst.nindirectsyms; + big_size *= sizeof(uint32_t); + big_size += dyst.indirectsymoff; + if (big_size > object_size) + outs() << " (past end of file)\n"; + else + outs() << "\n"; + outs() << " extreloff " << dyst.extreloff; + if (dyst.extreloff > object_size) + outs() << " (past end of file)\n"; + else + outs() << "\n"; + outs() << " nextrel " << dyst.nextrel; + big_size = dyst.nextrel; + big_size *= sizeof(struct MachO::relocation_info); + big_size += dyst.extreloff; + if (big_size > object_size) + outs() << " (past end of file)\n"; + else + outs() << "\n"; + outs() << " locreloff " << dyst.locreloff; + if (dyst.locreloff > object_size) + outs() << " (past end of file)\n"; + else + outs() << "\n"; + outs() << " nlocrel " << dyst.nlocrel; + big_size = dyst.nlocrel; + big_size *= sizeof(struct MachO::relocation_info); + big_size += dyst.locreloff; + if (big_size > object_size) + outs() << " (past end of file)\n"; + else + outs() << "\n"; +} + +static void PrintDyldInfoLoadCommand(MachO::dyld_info_command dc, + uint32_t object_size) { + if (dc.cmd == MachO::LC_DYLD_INFO) + outs() << " cmd LC_DYLD_INFO\n"; + else + outs() << " cmd LC_DYLD_INFO_ONLY\n"; + outs() << " cmdsize " << dc.cmdsize; + if (dc.cmdsize != sizeof(struct MachO::dyld_info_command)) + outs() << " Incorrect size\n"; + else + outs() << "\n"; + outs() << " rebase_off " << dc.rebase_off; + if (dc.rebase_off > object_size) + outs() << " (past end of file)\n"; + else + outs() << "\n"; + outs() << " rebase_size " << dc.rebase_size; + uint64_t big_size; + big_size = dc.rebase_off; + big_size += dc.rebase_size; + if (big_size > object_size) + outs() << " (past end of file)\n"; + else + outs() << "\n"; + outs() << " bind_off " << dc.bind_off; + if (dc.bind_off > object_size) + outs() << " (past end of file)\n"; + else + outs() << "\n"; + outs() << " bind_size " << dc.bind_size; + big_size = dc.bind_off; + big_size += dc.bind_size; + if (big_size > object_size) + outs() << " (past end of file)\n"; + else + outs() << "\n"; + outs() << " weak_bind_off " << dc.weak_bind_off; + if (dc.weak_bind_off > object_size) + outs() << " (past end of file)\n"; + else + outs() << "\n"; + outs() << " weak_bind_size " << dc.weak_bind_size; + big_size = dc.weak_bind_off; + big_size += dc.weak_bind_size; + if (big_size > object_size) + outs() << " (past end of file)\n"; + else + outs() << "\n"; + outs() << " lazy_bind_off " << dc.lazy_bind_off; + if (dc.lazy_bind_off > object_size) + outs() << " (past end of file)\n"; + else + outs() << "\n"; + outs() << " lazy_bind_size " << dc.lazy_bind_size; + big_size = dc.lazy_bind_off; + big_size += dc.lazy_bind_size; + if (big_size > object_size) + outs() << " (past end of file)\n"; + else + outs() << "\n"; + outs() << " export_off " << dc.export_off; + if (dc.export_off > object_size) + outs() << " (past end of file)\n"; + else + outs() << "\n"; + outs() << " export_size " << dc.export_size; + big_size = dc.export_off; + big_size += dc.export_size; + if (big_size > object_size) + outs() << " (past end of file)\n"; + else + outs() << "\n"; +} + +static void PrintDyldLoadCommand(MachO::dylinker_command dyld, + const char *Ptr) { + if (dyld.cmd == MachO::LC_ID_DYLINKER) + outs() << " cmd LC_ID_DYLINKER\n"; + else if (dyld.cmd == MachO::LC_LOAD_DYLINKER) + outs() << " cmd LC_LOAD_DYLINKER\n"; + else if (dyld.cmd == MachO::LC_DYLD_ENVIRONMENT) + outs() << " cmd LC_DYLD_ENVIRONMENT\n"; + else + outs() << " cmd ?(" << dyld.cmd << ")\n"; + outs() << " cmdsize " << dyld.cmdsize; + if (dyld.cmdsize < sizeof(struct MachO::dylinker_command)) + outs() << " Incorrect size\n"; + else + outs() << "\n"; + if (dyld.name >= dyld.cmdsize) + outs() << " name ?(bad offset " << dyld.name << ")\n"; + else { + const char *P = (const char *)(Ptr) + dyld.name; + outs() << " name " << P << " (offset " << dyld.name << ")\n"; + } +} + +static void PrintUuidLoadCommand(MachO::uuid_command uuid) { + outs() << " cmd LC_UUID\n"; + outs() << " cmdsize " << uuid.cmdsize; + if (uuid.cmdsize != sizeof(struct MachO::uuid_command)) + outs() << " Incorrect size\n"; + else + outs() << "\n"; + outs() << " uuid "; + for (int i = 0; i < 16; ++i) { + outs() << format("%02" PRIX32, uuid.uuid[i]); + if (i == 3 || i == 5 || i == 7 || i == 9) + outs() << "-"; + } + outs() << "\n"; +} + +static void PrintRpathLoadCommand(MachO::rpath_command rpath, const char *Ptr) { + outs() << " cmd LC_RPATH\n"; + outs() << " cmdsize " << rpath.cmdsize; + if (rpath.cmdsize < sizeof(struct MachO::rpath_command)) + outs() << " Incorrect size\n"; + else + outs() << "\n"; + if (rpath.path >= rpath.cmdsize) + outs() << " path ?(bad offset " << rpath.path << ")\n"; + else { + const char *P = (const char *)(Ptr) + rpath.path; + outs() << " path " << P << " (offset " << rpath.path << ")\n"; + } +} + +static void PrintVersionMinLoadCommand(MachO::version_min_command vd) { + StringRef LoadCmdName; + switch (vd.cmd) { + case MachO::LC_VERSION_MIN_MACOSX: + LoadCmdName = "LC_VERSION_MIN_MACOSX"; + break; + case MachO::LC_VERSION_MIN_IPHONEOS: + LoadCmdName = "LC_VERSION_MIN_IPHONEOS"; + break; + case MachO::LC_VERSION_MIN_TVOS: + LoadCmdName = "LC_VERSION_MIN_TVOS"; + break; + case MachO::LC_VERSION_MIN_WATCHOS: + LoadCmdName = "LC_VERSION_MIN_WATCHOS"; + break; + default: + llvm_unreachable("Unknown version min load command"); + } + + outs() << " cmd " << LoadCmdName << '\n'; + outs() << " cmdsize " << vd.cmdsize; + if (vd.cmdsize != sizeof(struct MachO::version_min_command)) + outs() << " Incorrect size\n"; + else + outs() << "\n"; + outs() << " version " << MachOObjectFile::getVersionMinMajor(vd, false) + << "." << MachOObjectFile::getVersionMinMinor(vd, false); + uint32_t Update = MachOObjectFile::getVersionMinUpdate(vd, false); + if (Update != 0) + outs() << "." << Update; + outs() << "\n"; + if (vd.sdk == 0) + outs() << " sdk n/a"; + else { + outs() << " sdk " << MachOObjectFile::getVersionMinMajor(vd, true) + << "." << MachOObjectFile::getVersionMinMinor(vd, true); + } + Update = MachOObjectFile::getVersionMinUpdate(vd, true); + if (Update != 0) + outs() << "." << Update; + outs() << "\n"; +} + +static void PrintNoteLoadCommand(MachO::note_command Nt) { + outs() << " cmd LC_NOTE\n"; + outs() << " cmdsize " << Nt.cmdsize; + if (Nt.cmdsize != sizeof(struct MachO::note_command)) + outs() << " Incorrect size\n"; + else + outs() << "\n"; + const char *d = Nt.data_owner; + outs() << "data_owner " << format("%.16s\n", d); + outs() << " offset " << Nt.offset << "\n"; + outs() << " size " << Nt.size << "\n"; +} + +static void PrintBuildToolVersion(MachO::build_tool_version bv) { + outs() << " tool " << MachOObjectFile::getBuildTool(bv.tool) << "\n"; + outs() << " version " << MachOObjectFile::getVersionString(bv.version) + << "\n"; +} + +static void PrintBuildVersionLoadCommand(const MachOObjectFile *obj, + MachO::build_version_command bd) { + outs() << " cmd LC_BUILD_VERSION\n"; + outs() << " cmdsize " << bd.cmdsize; + if (bd.cmdsize != sizeof(struct MachO::build_version_command) + + bd.ntools * sizeof(struct MachO::build_tool_version)) + outs() << " Incorrect size\n"; + else + outs() << "\n"; + outs() << " platform " << MachOObjectFile::getBuildPlatform(bd.platform) + << "\n"; + if (bd.sdk) + outs() << " sdk " << MachOObjectFile::getVersionString(bd.sdk) + << "\n"; + else + outs() << " sdk n/a\n"; + outs() << " minos " << MachOObjectFile::getVersionString(bd.minos) + << "\n"; + outs() << " ntools " << bd.ntools << "\n"; + for (unsigned i = 0; i < bd.ntools; ++i) { + MachO::build_tool_version bv = obj->getBuildToolVersion(i); + PrintBuildToolVersion(bv); + } +} + +static void PrintSourceVersionCommand(MachO::source_version_command sd) { + outs() << " cmd LC_SOURCE_VERSION\n"; + outs() << " cmdsize " << sd.cmdsize; + if (sd.cmdsize != sizeof(struct MachO::source_version_command)) + outs() << " Incorrect size\n"; + else + outs() << "\n"; + uint64_t a = (sd.version >> 40) & 0xffffff; + uint64_t b = (sd.version >> 30) & 0x3ff; + uint64_t c = (sd.version >> 20) & 0x3ff; + uint64_t d = (sd.version >> 10) & 0x3ff; + uint64_t e = sd.version & 0x3ff; + outs() << " version " << a << "." << b; + if (e != 0) + outs() << "." << c << "." << d << "." << e; + else if (d != 0) + outs() << "." << c << "." << d; + else if (c != 0) + outs() << "." << c; + outs() << "\n"; +} + +static void PrintEntryPointCommand(MachO::entry_point_command ep) { + outs() << " cmd LC_MAIN\n"; + outs() << " cmdsize " << ep.cmdsize; + if (ep.cmdsize != sizeof(struct MachO::entry_point_command)) + outs() << " Incorrect size\n"; + else + outs() << "\n"; + outs() << " entryoff " << ep.entryoff << "\n"; + outs() << " stacksize " << ep.stacksize << "\n"; +} + +static void PrintEncryptionInfoCommand(MachO::encryption_info_command ec, + uint32_t object_size) { + outs() << " cmd LC_ENCRYPTION_INFO\n"; + outs() << " cmdsize " << ec.cmdsize; + if (ec.cmdsize != sizeof(struct MachO::encryption_info_command)) + outs() << " Incorrect size\n"; + else + outs() << "\n"; + outs() << " cryptoff " << ec.cryptoff; + if (ec.cryptoff > object_size) + outs() << " (past end of file)\n"; + else + outs() << "\n"; + outs() << " cryptsize " << ec.cryptsize; + if (ec.cryptsize > object_size) + outs() << " (past end of file)\n"; + else + outs() << "\n"; + outs() << " cryptid " << ec.cryptid << "\n"; +} + +static void PrintEncryptionInfoCommand64(MachO::encryption_info_command_64 ec, + uint32_t object_size) { + outs() << " cmd LC_ENCRYPTION_INFO_64\n"; + outs() << " cmdsize " << ec.cmdsize; + if (ec.cmdsize != sizeof(struct MachO::encryption_info_command_64)) + outs() << " Incorrect size\n"; + else + outs() << "\n"; + outs() << " cryptoff " << ec.cryptoff; + if (ec.cryptoff > object_size) + outs() << " (past end of file)\n"; + else + outs() << "\n"; + outs() << " cryptsize " << ec.cryptsize; + if (ec.cryptsize > object_size) + outs() << " (past end of file)\n"; + else + outs() << "\n"; + outs() << " cryptid " << ec.cryptid << "\n"; + outs() << " pad " << ec.pad << "\n"; +} + +static void PrintLinkerOptionCommand(MachO::linker_option_command lo, + const char *Ptr) { + outs() << " cmd LC_LINKER_OPTION\n"; + outs() << " cmdsize " << lo.cmdsize; + if (lo.cmdsize < sizeof(struct MachO::linker_option_command)) + outs() << " Incorrect size\n"; + else + outs() << "\n"; + outs() << " count " << lo.count << "\n"; + const char *string = Ptr + sizeof(struct MachO::linker_option_command); + uint32_t left = lo.cmdsize - sizeof(struct MachO::linker_option_command); + uint32_t i = 0; + while (left > 0) { + while (*string == '\0' && left > 0) { + string++; + left--; + } + if (left > 0) { + i++; + outs() << " string #" << i << " " << format("%.*s\n", left, string); + uint32_t NullPos = StringRef(string, left).find('\0'); + uint32_t len = std::min(NullPos, left) + 1; + string += len; + left -= len; + } + } + if (lo.count != i) + outs() << " count " << lo.count << " does not match number of strings " + << i << "\n"; +} + +static void PrintSubFrameworkCommand(MachO::sub_framework_command sub, + const char *Ptr) { + outs() << " cmd LC_SUB_FRAMEWORK\n"; + outs() << " cmdsize " << sub.cmdsize; + if (sub.cmdsize < sizeof(struct MachO::sub_framework_command)) + outs() << " Incorrect size\n"; + else + outs() << "\n"; + if (sub.umbrella < sub.cmdsize) { + const char *P = Ptr + sub.umbrella; + outs() << " umbrella " << P << " (offset " << sub.umbrella << ")\n"; + } else { + outs() << " umbrella ?(bad offset " << sub.umbrella << ")\n"; + } +} + +static void PrintSubUmbrellaCommand(MachO::sub_umbrella_command sub, + const char *Ptr) { + outs() << " cmd LC_SUB_UMBRELLA\n"; + outs() << " cmdsize " << sub.cmdsize; + if (sub.cmdsize < sizeof(struct MachO::sub_umbrella_command)) + outs() << " Incorrect size\n"; + else + outs() << "\n"; + if (sub.sub_umbrella < sub.cmdsize) { + const char *P = Ptr + sub.sub_umbrella; + outs() << " sub_umbrella " << P << " (offset " << sub.sub_umbrella << ")\n"; + } else { + outs() << " sub_umbrella ?(bad offset " << sub.sub_umbrella << ")\n"; + } +} + +static void PrintSubLibraryCommand(MachO::sub_library_command sub, + const char *Ptr) { + outs() << " cmd LC_SUB_LIBRARY\n"; + outs() << " cmdsize " << sub.cmdsize; + if (sub.cmdsize < sizeof(struct MachO::sub_library_command)) + outs() << " Incorrect size\n"; + else + outs() << "\n"; + if (sub.sub_library < sub.cmdsize) { + const char *P = Ptr + sub.sub_library; + outs() << " sub_library " << P << " (offset " << sub.sub_library << ")\n"; + } else { + outs() << " sub_library ?(bad offset " << sub.sub_library << ")\n"; + } +} + +static void PrintSubClientCommand(MachO::sub_client_command sub, + const char *Ptr) { + outs() << " cmd LC_SUB_CLIENT\n"; + outs() << " cmdsize " << sub.cmdsize; + if (sub.cmdsize < sizeof(struct MachO::sub_client_command)) + outs() << " Incorrect size\n"; + else + outs() << "\n"; + if (sub.client < sub.cmdsize) { + const char *P = Ptr + sub.client; + outs() << " client " << P << " (offset " << sub.client << ")\n"; + } else { + outs() << " client ?(bad offset " << sub.client << ")\n"; + } +} + +static void PrintRoutinesCommand(MachO::routines_command r) { + outs() << " cmd LC_ROUTINES\n"; + outs() << " cmdsize " << r.cmdsize; + if (r.cmdsize != sizeof(struct MachO::routines_command)) + outs() << " Incorrect size\n"; + else + outs() << "\n"; + outs() << " init_address " << format("0x%08" PRIx32, r.init_address) << "\n"; + outs() << " init_module " << r.init_module << "\n"; + outs() << " reserved1 " << r.reserved1 << "\n"; + outs() << " reserved2 " << r.reserved2 << "\n"; + outs() << " reserved3 " << r.reserved3 << "\n"; + outs() << " reserved4 " << r.reserved4 << "\n"; + outs() << " reserved5 " << r.reserved5 << "\n"; + outs() << " reserved6 " << r.reserved6 << "\n"; +} + +static void PrintRoutinesCommand64(MachO::routines_command_64 r) { + outs() << " cmd LC_ROUTINES_64\n"; + outs() << " cmdsize " << r.cmdsize; + if (r.cmdsize != sizeof(struct MachO::routines_command_64)) + outs() << " Incorrect size\n"; + else + outs() << "\n"; + outs() << " init_address " << format("0x%016" PRIx64, r.init_address) << "\n"; + outs() << " init_module " << r.init_module << "\n"; + outs() << " reserved1 " << r.reserved1 << "\n"; + outs() << " reserved2 " << r.reserved2 << "\n"; + outs() << " reserved3 " << r.reserved3 << "\n"; + outs() << " reserved4 " << r.reserved4 << "\n"; + outs() << " reserved5 " << r.reserved5 << "\n"; + outs() << " reserved6 " << r.reserved6 << "\n"; +} + +static void Print_x86_thread_state32_t(MachO::x86_thread_state32_t &cpu32) { + outs() << "\t eax " << format("0x%08" PRIx32, cpu32.eax); + outs() << " ebx " << format("0x%08" PRIx32, cpu32.ebx); + outs() << " ecx " << format("0x%08" PRIx32, cpu32.ecx); + outs() << " edx " << format("0x%08" PRIx32, cpu32.edx) << "\n"; + outs() << "\t edi " << format("0x%08" PRIx32, cpu32.edi); + outs() << " esi " << format("0x%08" PRIx32, cpu32.esi); + outs() << " ebp " << format("0x%08" PRIx32, cpu32.ebp); + outs() << " esp " << format("0x%08" PRIx32, cpu32.esp) << "\n"; + outs() << "\t ss " << format("0x%08" PRIx32, cpu32.ss); + outs() << " eflags " << format("0x%08" PRIx32, cpu32.eflags); + outs() << " eip " << format("0x%08" PRIx32, cpu32.eip); + outs() << " cs " << format("0x%08" PRIx32, cpu32.cs) << "\n"; + outs() << "\t ds " << format("0x%08" PRIx32, cpu32.ds); + outs() << " es " << format("0x%08" PRIx32, cpu32.es); + outs() << " fs " << format("0x%08" PRIx32, cpu32.fs); + outs() << " gs " << format("0x%08" PRIx32, cpu32.gs) << "\n"; +} + +static void Print_x86_thread_state64_t(MachO::x86_thread_state64_t &cpu64) { + outs() << " rax " << format("0x%016" PRIx64, cpu64.rax); + outs() << " rbx " << format("0x%016" PRIx64, cpu64.rbx); + outs() << " rcx " << format("0x%016" PRIx64, cpu64.rcx) << "\n"; + outs() << " rdx " << format("0x%016" PRIx64, cpu64.rdx); + outs() << " rdi " << format("0x%016" PRIx64, cpu64.rdi); + outs() << " rsi " << format("0x%016" PRIx64, cpu64.rsi) << "\n"; + outs() << " rbp " << format("0x%016" PRIx64, cpu64.rbp); + outs() << " rsp " << format("0x%016" PRIx64, cpu64.rsp); + outs() << " r8 " << format("0x%016" PRIx64, cpu64.r8) << "\n"; + outs() << " r9 " << format("0x%016" PRIx64, cpu64.r9); + outs() << " r10 " << format("0x%016" PRIx64, cpu64.r10); + outs() << " r11 " << format("0x%016" PRIx64, cpu64.r11) << "\n"; + outs() << " r12 " << format("0x%016" PRIx64, cpu64.r12); + outs() << " r13 " << format("0x%016" PRIx64, cpu64.r13); + outs() << " r14 " << format("0x%016" PRIx64, cpu64.r14) << "\n"; + outs() << " r15 " << format("0x%016" PRIx64, cpu64.r15); + outs() << " rip " << format("0x%016" PRIx64, cpu64.rip) << "\n"; + outs() << "rflags " << format("0x%016" PRIx64, cpu64.rflags); + outs() << " cs " << format("0x%016" PRIx64, cpu64.cs); + outs() << " fs " << format("0x%016" PRIx64, cpu64.fs) << "\n"; + outs() << " gs " << format("0x%016" PRIx64, cpu64.gs) << "\n"; +} + +static void Print_mmst_reg(MachO::mmst_reg_t &r) { + uint32_t f; + outs() << "\t mmst_reg "; + for (f = 0; f < 10; f++) + outs() << format("%02" PRIx32, (r.mmst_reg[f] & 0xff)) << " "; + outs() << "\n"; + outs() << "\t mmst_rsrv "; + for (f = 0; f < 6; f++) + outs() << format("%02" PRIx32, (r.mmst_rsrv[f] & 0xff)) << " "; + outs() << "\n"; +} + +static void Print_xmm_reg(MachO::xmm_reg_t &r) { + uint32_t f; + outs() << "\t xmm_reg "; + for (f = 0; f < 16; f++) + outs() << format("%02" PRIx32, (r.xmm_reg[f] & 0xff)) << " "; + outs() << "\n"; +} + +static void Print_x86_float_state_t(MachO::x86_float_state64_t &fpu) { + outs() << "\t fpu_reserved[0] " << fpu.fpu_reserved[0]; + outs() << " fpu_reserved[1] " << fpu.fpu_reserved[1] << "\n"; + outs() << "\t control: invalid " << fpu.fpu_fcw.invalid; + outs() << " denorm " << fpu.fpu_fcw.denorm; + outs() << " zdiv " << fpu.fpu_fcw.zdiv; + outs() << " ovrfl " << fpu.fpu_fcw.ovrfl; + outs() << " undfl " << fpu.fpu_fcw.undfl; + outs() << " precis " << fpu.fpu_fcw.precis << "\n"; + outs() << "\t\t pc "; + if (fpu.fpu_fcw.pc == MachO::x86_FP_PREC_24B) + outs() << "FP_PREC_24B "; + else if (fpu.fpu_fcw.pc == MachO::x86_FP_PREC_53B) + outs() << "FP_PREC_53B "; + else if (fpu.fpu_fcw.pc == MachO::x86_FP_PREC_64B) + outs() << "FP_PREC_64B "; + else + outs() << fpu.fpu_fcw.pc << " "; + outs() << "rc "; + if (fpu.fpu_fcw.rc == MachO::x86_FP_RND_NEAR) + outs() << "FP_RND_NEAR "; + else if (fpu.fpu_fcw.rc == MachO::x86_FP_RND_DOWN) + outs() << "FP_RND_DOWN "; + else if (fpu.fpu_fcw.rc == MachO::x86_FP_RND_UP) + outs() << "FP_RND_UP "; + else if (fpu.fpu_fcw.rc == MachO::x86_FP_CHOP) + outs() << "FP_CHOP "; + outs() << "\n"; + outs() << "\t status: invalid " << fpu.fpu_fsw.invalid; + outs() << " denorm " << fpu.fpu_fsw.denorm; + outs() << " zdiv " << fpu.fpu_fsw.zdiv; + outs() << " ovrfl " << fpu.fpu_fsw.ovrfl; + outs() << " undfl " << fpu.fpu_fsw.undfl; + outs() << " precis " << fpu.fpu_fsw.precis; + outs() << " stkflt " << fpu.fpu_fsw.stkflt << "\n"; + outs() << "\t errsumm " << fpu.fpu_fsw.errsumm; + outs() << " c0 " << fpu.fpu_fsw.c0; + outs() << " c1 " << fpu.fpu_fsw.c1; + outs() << " c2 " << fpu.fpu_fsw.c2; + outs() << " tos " << fpu.fpu_fsw.tos; + outs() << " c3 " << fpu.fpu_fsw.c3; + outs() << " busy " << fpu.fpu_fsw.busy << "\n"; + outs() << "\t fpu_ftw " << format("0x%02" PRIx32, fpu.fpu_ftw); + outs() << " fpu_rsrv1 " << format("0x%02" PRIx32, fpu.fpu_rsrv1); + outs() << " fpu_fop " << format("0x%04" PRIx32, fpu.fpu_fop); + outs() << " fpu_ip " << format("0x%08" PRIx32, fpu.fpu_ip) << "\n"; + outs() << "\t fpu_cs " << format("0x%04" PRIx32, fpu.fpu_cs); + outs() << " fpu_rsrv2 " << format("0x%04" PRIx32, fpu.fpu_rsrv2); + outs() << " fpu_dp " << format("0x%08" PRIx32, fpu.fpu_dp); + outs() << " fpu_ds " << format("0x%04" PRIx32, fpu.fpu_ds) << "\n"; + outs() << "\t fpu_rsrv3 " << format("0x%04" PRIx32, fpu.fpu_rsrv3); + outs() << " fpu_mxcsr " << format("0x%08" PRIx32, fpu.fpu_mxcsr); + outs() << " fpu_mxcsrmask " << format("0x%08" PRIx32, fpu.fpu_mxcsrmask); + outs() << "\n"; + outs() << "\t fpu_stmm0:\n"; + Print_mmst_reg(fpu.fpu_stmm0); + outs() << "\t fpu_stmm1:\n"; + Print_mmst_reg(fpu.fpu_stmm1); + outs() << "\t fpu_stmm2:\n"; + Print_mmst_reg(fpu.fpu_stmm2); + outs() << "\t fpu_stmm3:\n"; + Print_mmst_reg(fpu.fpu_stmm3); + outs() << "\t fpu_stmm4:\n"; + Print_mmst_reg(fpu.fpu_stmm4); + outs() << "\t fpu_stmm5:\n"; + Print_mmst_reg(fpu.fpu_stmm5); + outs() << "\t fpu_stmm6:\n"; + Print_mmst_reg(fpu.fpu_stmm6); + outs() << "\t fpu_stmm7:\n"; + Print_mmst_reg(fpu.fpu_stmm7); + outs() << "\t fpu_xmm0:\n"; + Print_xmm_reg(fpu.fpu_xmm0); + outs() << "\t fpu_xmm1:\n"; + Print_xmm_reg(fpu.fpu_xmm1); + outs() << "\t fpu_xmm2:\n"; + Print_xmm_reg(fpu.fpu_xmm2); + outs() << "\t fpu_xmm3:\n"; + Print_xmm_reg(fpu.fpu_xmm3); + outs() << "\t fpu_xmm4:\n"; + Print_xmm_reg(fpu.fpu_xmm4); + outs() << "\t fpu_xmm5:\n"; + Print_xmm_reg(fpu.fpu_xmm5); + outs() << "\t fpu_xmm6:\n"; + Print_xmm_reg(fpu.fpu_xmm6); + outs() << "\t fpu_xmm7:\n"; + Print_xmm_reg(fpu.fpu_xmm7); + outs() << "\t fpu_xmm8:\n"; + Print_xmm_reg(fpu.fpu_xmm8); + outs() << "\t fpu_xmm9:\n"; + Print_xmm_reg(fpu.fpu_xmm9); + outs() << "\t fpu_xmm10:\n"; + Print_xmm_reg(fpu.fpu_xmm10); + outs() << "\t fpu_xmm11:\n"; + Print_xmm_reg(fpu.fpu_xmm11); + outs() << "\t fpu_xmm12:\n"; + Print_xmm_reg(fpu.fpu_xmm12); + outs() << "\t fpu_xmm13:\n"; + Print_xmm_reg(fpu.fpu_xmm13); + outs() << "\t fpu_xmm14:\n"; + Print_xmm_reg(fpu.fpu_xmm14); + outs() << "\t fpu_xmm15:\n"; + Print_xmm_reg(fpu.fpu_xmm15); + outs() << "\t fpu_rsrv4:\n"; + for (uint32_t f = 0; f < 6; f++) { + outs() << "\t "; + for (uint32_t g = 0; g < 16; g++) + outs() << format("%02" PRIx32, fpu.fpu_rsrv4[f * g]) << " "; + outs() << "\n"; + } + outs() << "\t fpu_reserved1 " << format("0x%08" PRIx32, fpu.fpu_reserved1); + outs() << "\n"; +} + +static void Print_x86_exception_state_t(MachO::x86_exception_state64_t &exc64) { + outs() << "\t trapno " << format("0x%08" PRIx32, exc64.trapno); + outs() << " err " << format("0x%08" PRIx32, exc64.err); + outs() << " faultvaddr " << format("0x%016" PRIx64, exc64.faultvaddr) << "\n"; +} + +static void Print_arm_thread_state32_t(MachO::arm_thread_state32_t &cpu32) { + outs() << "\t r0 " << format("0x%08" PRIx32, cpu32.r[0]); + outs() << " r1 " << format("0x%08" PRIx32, cpu32.r[1]); + outs() << " r2 " << format("0x%08" PRIx32, cpu32.r[2]); + outs() << " r3 " << format("0x%08" PRIx32, cpu32.r[3]) << "\n"; + outs() << "\t r4 " << format("0x%08" PRIx32, cpu32.r[4]); + outs() << " r5 " << format("0x%08" PRIx32, cpu32.r[5]); + outs() << " r6 " << format("0x%08" PRIx32, cpu32.r[6]); + outs() << " r7 " << format("0x%08" PRIx32, cpu32.r[7]) << "\n"; + outs() << "\t r8 " << format("0x%08" PRIx32, cpu32.r[8]); + outs() << " r9 " << format("0x%08" PRIx32, cpu32.r[9]); + outs() << " r10 " << format("0x%08" PRIx32, cpu32.r[10]); + outs() << " r11 " << format("0x%08" PRIx32, cpu32.r[11]) << "\n"; + outs() << "\t r12 " << format("0x%08" PRIx32, cpu32.r[12]); + outs() << " sp " << format("0x%08" PRIx32, cpu32.sp); + outs() << " lr " << format("0x%08" PRIx32, cpu32.lr); + outs() << " pc " << format("0x%08" PRIx32, cpu32.pc) << "\n"; + outs() << "\t cpsr " << format("0x%08" PRIx32, cpu32.cpsr) << "\n"; +} + +static void Print_arm_thread_state64_t(MachO::arm_thread_state64_t &cpu64) { + outs() << "\t x0 " << format("0x%016" PRIx64, cpu64.x[0]); + outs() << " x1 " << format("0x%016" PRIx64, cpu64.x[1]); + outs() << " x2 " << format("0x%016" PRIx64, cpu64.x[2]) << "\n"; + outs() << "\t x3 " << format("0x%016" PRIx64, cpu64.x[3]); + outs() << " x4 " << format("0x%016" PRIx64, cpu64.x[4]); + outs() << " x5 " << format("0x%016" PRIx64, cpu64.x[5]) << "\n"; + outs() << "\t x6 " << format("0x%016" PRIx64, cpu64.x[6]); + outs() << " x7 " << format("0x%016" PRIx64, cpu64.x[7]); + outs() << " x8 " << format("0x%016" PRIx64, cpu64.x[8]) << "\n"; + outs() << "\t x9 " << format("0x%016" PRIx64, cpu64.x[9]); + outs() << " x10 " << format("0x%016" PRIx64, cpu64.x[10]); + outs() << " x11 " << format("0x%016" PRIx64, cpu64.x[11]) << "\n"; + outs() << "\t x12 " << format("0x%016" PRIx64, cpu64.x[12]); + outs() << " x13 " << format("0x%016" PRIx64, cpu64.x[13]); + outs() << " x14 " << format("0x%016" PRIx64, cpu64.x[14]) << "\n"; + outs() << "\t x15 " << format("0x%016" PRIx64, cpu64.x[15]); + outs() << " x16 " << format("0x%016" PRIx64, cpu64.x[16]); + outs() << " x17 " << format("0x%016" PRIx64, cpu64.x[17]) << "\n"; + outs() << "\t x18 " << format("0x%016" PRIx64, cpu64.x[18]); + outs() << " x19 " << format("0x%016" PRIx64, cpu64.x[19]); + outs() << " x20 " << format("0x%016" PRIx64, cpu64.x[20]) << "\n"; + outs() << "\t x21 " << format("0x%016" PRIx64, cpu64.x[21]); + outs() << " x22 " << format("0x%016" PRIx64, cpu64.x[22]); + outs() << " x23 " << format("0x%016" PRIx64, cpu64.x[23]) << "\n"; + outs() << "\t x24 " << format("0x%016" PRIx64, cpu64.x[24]); + outs() << " x25 " << format("0x%016" PRIx64, cpu64.x[25]); + outs() << " x26 " << format("0x%016" PRIx64, cpu64.x[26]) << "\n"; + outs() << "\t x27 " << format("0x%016" PRIx64, cpu64.x[27]); + outs() << " x28 " << format("0x%016" PRIx64, cpu64.x[28]); + outs() << " fp " << format("0x%016" PRIx64, cpu64.fp) << "\n"; + outs() << "\t lr " << format("0x%016" PRIx64, cpu64.lr); + outs() << " sp " << format("0x%016" PRIx64, cpu64.sp); + outs() << " pc " << format("0x%016" PRIx64, cpu64.pc) << "\n"; + outs() << "\t cpsr " << format("0x%08" PRIx32, cpu64.cpsr) << "\n"; +} + +static void PrintThreadCommand(MachO::thread_command t, const char *Ptr, + bool isLittleEndian, uint32_t cputype) { + if (t.cmd == MachO::LC_THREAD) + outs() << " cmd LC_THREAD\n"; + else if (t.cmd == MachO::LC_UNIXTHREAD) + outs() << " cmd LC_UNIXTHREAD\n"; + else + outs() << " cmd " << t.cmd << " (unknown)\n"; + outs() << " cmdsize " << t.cmdsize; + if (t.cmdsize < sizeof(struct MachO::thread_command) + 2 * sizeof(uint32_t)) + outs() << " Incorrect size\n"; + else + outs() << "\n"; + + const char *begin = Ptr + sizeof(struct MachO::thread_command); + const char *end = Ptr + t.cmdsize; + uint32_t flavor, count, left; + if (cputype == MachO::CPU_TYPE_I386) { + while (begin < end) { + if (end - begin > (ptrdiff_t)sizeof(uint32_t)) { + memcpy((char *)&flavor, begin, sizeof(uint32_t)); + begin += sizeof(uint32_t); + } else { + flavor = 0; + begin = end; + } + if (isLittleEndian != sys::IsLittleEndianHost) + sys::swapByteOrder(flavor); + if (end - begin > (ptrdiff_t)sizeof(uint32_t)) { + memcpy((char *)&count, begin, sizeof(uint32_t)); + begin += sizeof(uint32_t); + } else { + count = 0; + begin = end; + } + if (isLittleEndian != sys::IsLittleEndianHost) + sys::swapByteOrder(count); + if (flavor == MachO::x86_THREAD_STATE32) { + outs() << " flavor i386_THREAD_STATE\n"; + if (count == MachO::x86_THREAD_STATE32_COUNT) + outs() << " count i386_THREAD_STATE_COUNT\n"; + else + outs() << " count " << count + << " (not x86_THREAD_STATE32_COUNT)\n"; + MachO::x86_thread_state32_t cpu32; + left = end - begin; + if (left >= sizeof(MachO::x86_thread_state32_t)) { + memcpy(&cpu32, begin, sizeof(MachO::x86_thread_state32_t)); + begin += sizeof(MachO::x86_thread_state32_t); + } else { + memset(&cpu32, '\0', sizeof(MachO::x86_thread_state32_t)); + memcpy(&cpu32, begin, left); + begin += left; + } + if (isLittleEndian != sys::IsLittleEndianHost) + swapStruct(cpu32); + Print_x86_thread_state32_t(cpu32); + } else if (flavor == MachO::x86_THREAD_STATE) { + outs() << " flavor x86_THREAD_STATE\n"; + if (count == MachO::x86_THREAD_STATE_COUNT) + outs() << " count x86_THREAD_STATE_COUNT\n"; + else + outs() << " count " << count + << " (not x86_THREAD_STATE_COUNT)\n"; + struct MachO::x86_thread_state_t ts; + left = end - begin; + if (left >= sizeof(MachO::x86_thread_state_t)) { + memcpy(&ts, begin, sizeof(MachO::x86_thread_state_t)); + begin += sizeof(MachO::x86_thread_state_t); + } else { + memset(&ts, '\0', sizeof(MachO::x86_thread_state_t)); + memcpy(&ts, begin, left); + begin += left; + } + if (isLittleEndian != sys::IsLittleEndianHost) + swapStruct(ts); + if (ts.tsh.flavor == MachO::x86_THREAD_STATE32) { + outs() << "\t tsh.flavor x86_THREAD_STATE32 "; + if (ts.tsh.count == MachO::x86_THREAD_STATE32_COUNT) + outs() << "tsh.count x86_THREAD_STATE32_COUNT\n"; + else + outs() << "tsh.count " << ts.tsh.count + << " (not x86_THREAD_STATE32_COUNT\n"; + Print_x86_thread_state32_t(ts.uts.ts32); + } else { + outs() << "\t tsh.flavor " << ts.tsh.flavor << " tsh.count " + << ts.tsh.count << "\n"; + } + } else { + outs() << " flavor " << flavor << " (unknown)\n"; + outs() << " count " << count << "\n"; + outs() << " state (unknown)\n"; + begin += count * sizeof(uint32_t); + } + } + } else if (cputype == MachO::CPU_TYPE_X86_64) { + while (begin < end) { + if (end - begin > (ptrdiff_t)sizeof(uint32_t)) { + memcpy((char *)&flavor, begin, sizeof(uint32_t)); + begin += sizeof(uint32_t); + } else { + flavor = 0; + begin = end; + } + if (isLittleEndian != sys::IsLittleEndianHost) + sys::swapByteOrder(flavor); + if (end - begin > (ptrdiff_t)sizeof(uint32_t)) { + memcpy((char *)&count, begin, sizeof(uint32_t)); + begin += sizeof(uint32_t); + } else { + count = 0; + begin = end; + } + if (isLittleEndian != sys::IsLittleEndianHost) + sys::swapByteOrder(count); + if (flavor == MachO::x86_THREAD_STATE64) { + outs() << " flavor x86_THREAD_STATE64\n"; + if (count == MachO::x86_THREAD_STATE64_COUNT) + outs() << " count x86_THREAD_STATE64_COUNT\n"; + else + outs() << " count " << count + << " (not x86_THREAD_STATE64_COUNT)\n"; + MachO::x86_thread_state64_t cpu64; + left = end - begin; + if (left >= sizeof(MachO::x86_thread_state64_t)) { + memcpy(&cpu64, begin, sizeof(MachO::x86_thread_state64_t)); + begin += sizeof(MachO::x86_thread_state64_t); + } else { + memset(&cpu64, '\0', sizeof(MachO::x86_thread_state64_t)); + memcpy(&cpu64, begin, left); + begin += left; + } + if (isLittleEndian != sys::IsLittleEndianHost) + swapStruct(cpu64); + Print_x86_thread_state64_t(cpu64); + } else if (flavor == MachO::x86_THREAD_STATE) { + outs() << " flavor x86_THREAD_STATE\n"; + if (count == MachO::x86_THREAD_STATE_COUNT) + outs() << " count x86_THREAD_STATE_COUNT\n"; + else + outs() << " count " << count + << " (not x86_THREAD_STATE_COUNT)\n"; + struct MachO::x86_thread_state_t ts; + left = end - begin; + if (left >= sizeof(MachO::x86_thread_state_t)) { + memcpy(&ts, begin, sizeof(MachO::x86_thread_state_t)); + begin += sizeof(MachO::x86_thread_state_t); + } else { + memset(&ts, '\0', sizeof(MachO::x86_thread_state_t)); + memcpy(&ts, begin, left); + begin += left; + } + if (isLittleEndian != sys::IsLittleEndianHost) + swapStruct(ts); + if (ts.tsh.flavor == MachO::x86_THREAD_STATE64) { + outs() << "\t tsh.flavor x86_THREAD_STATE64 "; + if (ts.tsh.count == MachO::x86_THREAD_STATE64_COUNT) + outs() << "tsh.count x86_THREAD_STATE64_COUNT\n"; + else + outs() << "tsh.count " << ts.tsh.count + << " (not x86_THREAD_STATE64_COUNT\n"; + Print_x86_thread_state64_t(ts.uts.ts64); + } else { + outs() << "\t tsh.flavor " << ts.tsh.flavor << " tsh.count " + << ts.tsh.count << "\n"; + } + } else if (flavor == MachO::x86_FLOAT_STATE) { + outs() << " flavor x86_FLOAT_STATE\n"; + if (count == MachO::x86_FLOAT_STATE_COUNT) + outs() << " count x86_FLOAT_STATE_COUNT\n"; + else + outs() << " count " << count << " (not x86_FLOAT_STATE_COUNT)\n"; + struct MachO::x86_float_state_t fs; + left = end - begin; + if (left >= sizeof(MachO::x86_float_state_t)) { + memcpy(&fs, begin, sizeof(MachO::x86_float_state_t)); + begin += sizeof(MachO::x86_float_state_t); + } else { + memset(&fs, '\0', sizeof(MachO::x86_float_state_t)); + memcpy(&fs, begin, left); + begin += left; + } + if (isLittleEndian != sys::IsLittleEndianHost) + swapStruct(fs); + if (fs.fsh.flavor == MachO::x86_FLOAT_STATE64) { + outs() << "\t fsh.flavor x86_FLOAT_STATE64 "; + if (fs.fsh.count == MachO::x86_FLOAT_STATE64_COUNT) + outs() << "fsh.count x86_FLOAT_STATE64_COUNT\n"; + else + outs() << "fsh.count " << fs.fsh.count + << " (not x86_FLOAT_STATE64_COUNT\n"; + Print_x86_float_state_t(fs.ufs.fs64); + } else { + outs() << "\t fsh.flavor " << fs.fsh.flavor << " fsh.count " + << fs.fsh.count << "\n"; + } + } else if (flavor == MachO::x86_EXCEPTION_STATE) { + outs() << " flavor x86_EXCEPTION_STATE\n"; + if (count == MachO::x86_EXCEPTION_STATE_COUNT) + outs() << " count x86_EXCEPTION_STATE_COUNT\n"; + else + outs() << " count " << count + << " (not x86_EXCEPTION_STATE_COUNT)\n"; + struct MachO::x86_exception_state_t es; + left = end - begin; + if (left >= sizeof(MachO::x86_exception_state_t)) { + memcpy(&es, begin, sizeof(MachO::x86_exception_state_t)); + begin += sizeof(MachO::x86_exception_state_t); + } else { + memset(&es, '\0', sizeof(MachO::x86_exception_state_t)); + memcpy(&es, begin, left); + begin += left; + } + if (isLittleEndian != sys::IsLittleEndianHost) + swapStruct(es); + if (es.esh.flavor == MachO::x86_EXCEPTION_STATE64) { + outs() << "\t esh.flavor x86_EXCEPTION_STATE64\n"; + if (es.esh.count == MachO::x86_EXCEPTION_STATE64_COUNT) + outs() << "\t esh.count x86_EXCEPTION_STATE64_COUNT\n"; + else + outs() << "\t esh.count " << es.esh.count + << " (not x86_EXCEPTION_STATE64_COUNT\n"; + Print_x86_exception_state_t(es.ues.es64); + } else { + outs() << "\t esh.flavor " << es.esh.flavor << " esh.count " + << es.esh.count << "\n"; + } + } else { + outs() << " flavor " << flavor << " (unknown)\n"; + outs() << " count " << count << "\n"; + outs() << " state (unknown)\n"; + begin += count * sizeof(uint32_t); + } + } + } else if (cputype == MachO::CPU_TYPE_ARM) { + while (begin < end) { + if (end - begin > (ptrdiff_t)sizeof(uint32_t)) { + memcpy((char *)&flavor, begin, sizeof(uint32_t)); + begin += sizeof(uint32_t); + } else { + flavor = 0; + begin = end; + } + if (isLittleEndian != sys::IsLittleEndianHost) + sys::swapByteOrder(flavor); + if (end - begin > (ptrdiff_t)sizeof(uint32_t)) { + memcpy((char *)&count, begin, sizeof(uint32_t)); + begin += sizeof(uint32_t); + } else { + count = 0; + begin = end; + } + if (isLittleEndian != sys::IsLittleEndianHost) + sys::swapByteOrder(count); + if (flavor == MachO::ARM_THREAD_STATE) { + outs() << " flavor ARM_THREAD_STATE\n"; + if (count == MachO::ARM_THREAD_STATE_COUNT) + outs() << " count ARM_THREAD_STATE_COUNT\n"; + else + outs() << " count " << count + << " (not ARM_THREAD_STATE_COUNT)\n"; + MachO::arm_thread_state32_t cpu32; + left = end - begin; + if (left >= sizeof(MachO::arm_thread_state32_t)) { + memcpy(&cpu32, begin, sizeof(MachO::arm_thread_state32_t)); + begin += sizeof(MachO::arm_thread_state32_t); + } else { + memset(&cpu32, '\0', sizeof(MachO::arm_thread_state32_t)); + memcpy(&cpu32, begin, left); + begin += left; + } + if (isLittleEndian != sys::IsLittleEndianHost) + swapStruct(cpu32); + Print_arm_thread_state32_t(cpu32); + } else { + outs() << " flavor " << flavor << " (unknown)\n"; + outs() << " count " << count << "\n"; + outs() << " state (unknown)\n"; + begin += count * sizeof(uint32_t); + } + } + } else if (cputype == MachO::CPU_TYPE_ARM64) { + while (begin < end) { + if (end - begin > (ptrdiff_t)sizeof(uint32_t)) { + memcpy((char *)&flavor, begin, sizeof(uint32_t)); + begin += sizeof(uint32_t); + } else { + flavor = 0; + begin = end; + } + if (isLittleEndian != sys::IsLittleEndianHost) + sys::swapByteOrder(flavor); + if (end - begin > (ptrdiff_t)sizeof(uint32_t)) { + memcpy((char *)&count, begin, sizeof(uint32_t)); + begin += sizeof(uint32_t); + } else { + count = 0; + begin = end; + } + if (isLittleEndian != sys::IsLittleEndianHost) + sys::swapByteOrder(count); + if (flavor == MachO::ARM_THREAD_STATE64) { + outs() << " flavor ARM_THREAD_STATE64\n"; + if (count == MachO::ARM_THREAD_STATE64_COUNT) + outs() << " count ARM_THREAD_STATE64_COUNT\n"; + else + outs() << " count " << count + << " (not ARM_THREAD_STATE64_COUNT)\n"; + MachO::arm_thread_state64_t cpu64; + left = end - begin; + if (left >= sizeof(MachO::arm_thread_state64_t)) { + memcpy(&cpu64, begin, sizeof(MachO::arm_thread_state64_t)); + begin += sizeof(MachO::arm_thread_state64_t); + } else { + memset(&cpu64, '\0', sizeof(MachO::arm_thread_state64_t)); + memcpy(&cpu64, begin, left); + begin += left; + } + if (isLittleEndian != sys::IsLittleEndianHost) + swapStruct(cpu64); + Print_arm_thread_state64_t(cpu64); + } else { + outs() << " flavor " << flavor << " (unknown)\n"; + outs() << " count " << count << "\n"; + outs() << " state (unknown)\n"; + begin += count * sizeof(uint32_t); + } + } + } else { + while (begin < end) { + if (end - begin > (ptrdiff_t)sizeof(uint32_t)) { + memcpy((char *)&flavor, begin, sizeof(uint32_t)); + begin += sizeof(uint32_t); + } else { + flavor = 0; + begin = end; + } + if (isLittleEndian != sys::IsLittleEndianHost) + sys::swapByteOrder(flavor); + if (end - begin > (ptrdiff_t)sizeof(uint32_t)) { + memcpy((char *)&count, begin, sizeof(uint32_t)); + begin += sizeof(uint32_t); + } else { + count = 0; + begin = end; + } + if (isLittleEndian != sys::IsLittleEndianHost) + sys::swapByteOrder(count); + outs() << " flavor " << flavor << "\n"; + outs() << " count " << count << "\n"; + outs() << " state (Unknown cputype/cpusubtype)\n"; + begin += count * sizeof(uint32_t); + } + } +} + +static void PrintDylibCommand(MachO::dylib_command dl, const char *Ptr) { + if (dl.cmd == MachO::LC_ID_DYLIB) + outs() << " cmd LC_ID_DYLIB\n"; + else if (dl.cmd == MachO::LC_LOAD_DYLIB) + outs() << " cmd LC_LOAD_DYLIB\n"; + else if (dl.cmd == MachO::LC_LOAD_WEAK_DYLIB) + outs() << " cmd LC_LOAD_WEAK_DYLIB\n"; + else if (dl.cmd == MachO::LC_REEXPORT_DYLIB) + outs() << " cmd LC_REEXPORT_DYLIB\n"; + else if (dl.cmd == MachO::LC_LAZY_LOAD_DYLIB) + outs() << " cmd LC_LAZY_LOAD_DYLIB\n"; + else if (dl.cmd == MachO::LC_LOAD_UPWARD_DYLIB) + outs() << " cmd LC_LOAD_UPWARD_DYLIB\n"; + else + outs() << " cmd " << dl.cmd << " (unknown)\n"; + outs() << " cmdsize " << dl.cmdsize; + if (dl.cmdsize < sizeof(struct MachO::dylib_command)) + outs() << " Incorrect size\n"; + else + outs() << "\n"; + if (dl.dylib.name < dl.cmdsize) { + const char *P = (const char *)(Ptr) + dl.dylib.name; + outs() << " name " << P << " (offset " << dl.dylib.name << ")\n"; + } else { + outs() << " name ?(bad offset " << dl.dylib.name << ")\n"; + } + outs() << " time stamp " << dl.dylib.timestamp << " "; + time_t t = dl.dylib.timestamp; + outs() << ctime(&t); + outs() << " current version "; + if (dl.dylib.current_version == 0xffffffff) + outs() << "n/a\n"; + else + outs() << ((dl.dylib.current_version >> 16) & 0xffff) << "." + << ((dl.dylib.current_version >> 8) & 0xff) << "." + << (dl.dylib.current_version & 0xff) << "\n"; + outs() << "compatibility version "; + if (dl.dylib.compatibility_version == 0xffffffff) + outs() << "n/a\n"; + else + outs() << ((dl.dylib.compatibility_version >> 16) & 0xffff) << "." + << ((dl.dylib.compatibility_version >> 8) & 0xff) << "." + << (dl.dylib.compatibility_version & 0xff) << "\n"; +} + +static void PrintLinkEditDataCommand(MachO::linkedit_data_command ld, + uint32_t object_size) { + if (ld.cmd == MachO::LC_CODE_SIGNATURE) + outs() << " cmd LC_CODE_SIGNATURE\n"; + else if (ld.cmd == MachO::LC_SEGMENT_SPLIT_INFO) + outs() << " cmd LC_SEGMENT_SPLIT_INFO\n"; + else if (ld.cmd == MachO::LC_FUNCTION_STARTS) + outs() << " cmd LC_FUNCTION_STARTS\n"; + else if (ld.cmd == MachO::LC_DATA_IN_CODE) + outs() << " cmd LC_DATA_IN_CODE\n"; + else if (ld.cmd == MachO::LC_DYLIB_CODE_SIGN_DRS) + outs() << " cmd LC_DYLIB_CODE_SIGN_DRS\n"; + else if (ld.cmd == MachO::LC_LINKER_OPTIMIZATION_HINT) + outs() << " cmd LC_LINKER_OPTIMIZATION_HINT\n"; + else + outs() << " cmd " << ld.cmd << " (?)\n"; + outs() << " cmdsize " << ld.cmdsize; + if (ld.cmdsize != sizeof(struct MachO::linkedit_data_command)) + outs() << " Incorrect size\n"; + else + outs() << "\n"; + outs() << " dataoff " << ld.dataoff; + if (ld.dataoff > object_size) + outs() << " (past end of file)\n"; + else + outs() << "\n"; + outs() << " datasize " << ld.datasize; + uint64_t big_size = ld.dataoff; + big_size += ld.datasize; + if (big_size > object_size) + outs() << " (past end of file)\n"; + else + outs() << "\n"; +} + +static void PrintLoadCommands(const MachOObjectFile *Obj, uint32_t filetype, + uint32_t cputype, bool verbose) { + StringRef Buf = Obj->getData(); + unsigned Index = 0; + for (const auto &Command : Obj->load_commands()) { + outs() << "Load command " << Index++ << "\n"; + if (Command.C.cmd == MachO::LC_SEGMENT) { + MachO::segment_command SLC = Obj->getSegmentLoadCommand(Command); + const char *sg_segname = SLC.segname; + PrintSegmentCommand(SLC.cmd, SLC.cmdsize, SLC.segname, SLC.vmaddr, + SLC.vmsize, SLC.fileoff, SLC.filesize, SLC.maxprot, + SLC.initprot, SLC.nsects, SLC.flags, Buf.size(), + verbose); + for (unsigned j = 0; j < SLC.nsects; j++) { + MachO::section S = Obj->getSection(Command, j); + PrintSection(S.sectname, S.segname, S.addr, S.size, S.offset, S.align, + S.reloff, S.nreloc, S.flags, S.reserved1, S.reserved2, + SLC.cmd, sg_segname, filetype, Buf.size(), verbose); + } + } else if (Command.C.cmd == MachO::LC_SEGMENT_64) { + MachO::segment_command_64 SLC_64 = Obj->getSegment64LoadCommand(Command); + const char *sg_segname = SLC_64.segname; + PrintSegmentCommand(SLC_64.cmd, SLC_64.cmdsize, SLC_64.segname, + SLC_64.vmaddr, SLC_64.vmsize, SLC_64.fileoff, + SLC_64.filesize, SLC_64.maxprot, SLC_64.initprot, + SLC_64.nsects, SLC_64.flags, Buf.size(), verbose); + for (unsigned j = 0; j < SLC_64.nsects; j++) { + MachO::section_64 S_64 = Obj->getSection64(Command, j); + PrintSection(S_64.sectname, S_64.segname, S_64.addr, S_64.size, + S_64.offset, S_64.align, S_64.reloff, S_64.nreloc, + S_64.flags, S_64.reserved1, S_64.reserved2, SLC_64.cmd, + sg_segname, filetype, Buf.size(), verbose); + } + } else if (Command.C.cmd == MachO::LC_SYMTAB) { + MachO::symtab_command Symtab = Obj->getSymtabLoadCommand(); + PrintSymtabLoadCommand(Symtab, Obj->is64Bit(), Buf.size()); + } else if (Command.C.cmd == MachO::LC_DYSYMTAB) { + MachO::dysymtab_command Dysymtab = Obj->getDysymtabLoadCommand(); + MachO::symtab_command Symtab = Obj->getSymtabLoadCommand(); + PrintDysymtabLoadCommand(Dysymtab, Symtab.nsyms, Buf.size(), + Obj->is64Bit()); + } else if (Command.C.cmd == MachO::LC_DYLD_INFO || + Command.C.cmd == MachO::LC_DYLD_INFO_ONLY) { + MachO::dyld_info_command DyldInfo = Obj->getDyldInfoLoadCommand(Command); + PrintDyldInfoLoadCommand(DyldInfo, Buf.size()); + } else if (Command.C.cmd == MachO::LC_LOAD_DYLINKER || + Command.C.cmd == MachO::LC_ID_DYLINKER || + Command.C.cmd == MachO::LC_DYLD_ENVIRONMENT) { + MachO::dylinker_command Dyld = Obj->getDylinkerCommand(Command); + PrintDyldLoadCommand(Dyld, Command.Ptr); + } else if (Command.C.cmd == MachO::LC_UUID) { + MachO::uuid_command Uuid = Obj->getUuidCommand(Command); + PrintUuidLoadCommand(Uuid); + } else if (Command.C.cmd == MachO::LC_RPATH) { + MachO::rpath_command Rpath = Obj->getRpathCommand(Command); + PrintRpathLoadCommand(Rpath, Command.Ptr); + } else if (Command.C.cmd == MachO::LC_VERSION_MIN_MACOSX || + Command.C.cmd == MachO::LC_VERSION_MIN_IPHONEOS || + Command.C.cmd == MachO::LC_VERSION_MIN_TVOS || + Command.C.cmd == MachO::LC_VERSION_MIN_WATCHOS) { + MachO::version_min_command Vd = Obj->getVersionMinLoadCommand(Command); + PrintVersionMinLoadCommand(Vd); + } else if (Command.C.cmd == MachO::LC_NOTE) { + MachO::note_command Nt = Obj->getNoteLoadCommand(Command); + PrintNoteLoadCommand(Nt); + } else if (Command.C.cmd == MachO::LC_BUILD_VERSION) { + MachO::build_version_command Bv = + Obj->getBuildVersionLoadCommand(Command); + PrintBuildVersionLoadCommand(Obj, Bv); + } else if (Command.C.cmd == MachO::LC_SOURCE_VERSION) { + MachO::source_version_command Sd = Obj->getSourceVersionCommand(Command); + PrintSourceVersionCommand(Sd); + } else if (Command.C.cmd == MachO::LC_MAIN) { + MachO::entry_point_command Ep = Obj->getEntryPointCommand(Command); + PrintEntryPointCommand(Ep); + } else if (Command.C.cmd == MachO::LC_ENCRYPTION_INFO) { + MachO::encryption_info_command Ei = + Obj->getEncryptionInfoCommand(Command); + PrintEncryptionInfoCommand(Ei, Buf.size()); + } else if (Command.C.cmd == MachO::LC_ENCRYPTION_INFO_64) { + MachO::encryption_info_command_64 Ei = + Obj->getEncryptionInfoCommand64(Command); + PrintEncryptionInfoCommand64(Ei, Buf.size()); + } else if (Command.C.cmd == MachO::LC_LINKER_OPTION) { + MachO::linker_option_command Lo = + Obj->getLinkerOptionLoadCommand(Command); + PrintLinkerOptionCommand(Lo, Command.Ptr); + } else if (Command.C.cmd == MachO::LC_SUB_FRAMEWORK) { + MachO::sub_framework_command Sf = Obj->getSubFrameworkCommand(Command); + PrintSubFrameworkCommand(Sf, Command.Ptr); + } else if (Command.C.cmd == MachO::LC_SUB_UMBRELLA) { + MachO::sub_umbrella_command Sf = Obj->getSubUmbrellaCommand(Command); + PrintSubUmbrellaCommand(Sf, Command.Ptr); + } else if (Command.C.cmd == MachO::LC_SUB_LIBRARY) { + MachO::sub_library_command Sl = Obj->getSubLibraryCommand(Command); + PrintSubLibraryCommand(Sl, Command.Ptr); + } else if (Command.C.cmd == MachO::LC_SUB_CLIENT) { + MachO::sub_client_command Sc = Obj->getSubClientCommand(Command); + PrintSubClientCommand(Sc, Command.Ptr); + } else if (Command.C.cmd == MachO::LC_ROUTINES) { + MachO::routines_command Rc = Obj->getRoutinesCommand(Command); + PrintRoutinesCommand(Rc); + } else if (Command.C.cmd == MachO::LC_ROUTINES_64) { + MachO::routines_command_64 Rc = Obj->getRoutinesCommand64(Command); + PrintRoutinesCommand64(Rc); + } else if (Command.C.cmd == MachO::LC_THREAD || + Command.C.cmd == MachO::LC_UNIXTHREAD) { + MachO::thread_command Tc = Obj->getThreadCommand(Command); + PrintThreadCommand(Tc, Command.Ptr, Obj->isLittleEndian(), cputype); + } else if (Command.C.cmd == MachO::LC_LOAD_DYLIB || + Command.C.cmd == MachO::LC_ID_DYLIB || + Command.C.cmd == MachO::LC_LOAD_WEAK_DYLIB || + Command.C.cmd == MachO::LC_REEXPORT_DYLIB || + Command.C.cmd == MachO::LC_LAZY_LOAD_DYLIB || + Command.C.cmd == MachO::LC_LOAD_UPWARD_DYLIB) { + MachO::dylib_command Dl = Obj->getDylibIDLoadCommand(Command); + PrintDylibCommand(Dl, Command.Ptr); + } else if (Command.C.cmd == MachO::LC_CODE_SIGNATURE || + Command.C.cmd == MachO::LC_SEGMENT_SPLIT_INFO || + Command.C.cmd == MachO::LC_FUNCTION_STARTS || + Command.C.cmd == MachO::LC_DATA_IN_CODE || + Command.C.cmd == MachO::LC_DYLIB_CODE_SIGN_DRS || + Command.C.cmd == MachO::LC_LINKER_OPTIMIZATION_HINT) { + MachO::linkedit_data_command Ld = + Obj->getLinkeditDataLoadCommand(Command); + PrintLinkEditDataCommand(Ld, Buf.size()); + } else { + outs() << " cmd ?(" << format("0x%08" PRIx32, Command.C.cmd) + << ")\n"; + outs() << " cmdsize " << Command.C.cmdsize << "\n"; + // TODO: get and print the raw bytes of the load command. + } + // TODO: print all the other kinds of load commands. + } +} + +static void PrintMachHeader(const MachOObjectFile *Obj, bool verbose) { + if (Obj->is64Bit()) { + MachO::mach_header_64 H_64; + H_64 = Obj->getHeader64(); + PrintMachHeader(H_64.magic, H_64.cputype, H_64.cpusubtype, H_64.filetype, + H_64.ncmds, H_64.sizeofcmds, H_64.flags, verbose); + } else { + MachO::mach_header H; + H = Obj->getHeader(); + PrintMachHeader(H.magic, H.cputype, H.cpusubtype, H.filetype, H.ncmds, + H.sizeofcmds, H.flags, verbose); + } +} + +void llvm::printMachOFileHeader(const object::ObjectFile *Obj) { + const MachOObjectFile *file = dyn_cast(Obj); + PrintMachHeader(file, !NonVerbose); +} + +void llvm::printMachOLoadCommands(const object::ObjectFile *Obj) { + const MachOObjectFile *file = dyn_cast(Obj); + uint32_t filetype = 0; + uint32_t cputype = 0; + if (file->is64Bit()) { + MachO::mach_header_64 H_64; + H_64 = file->getHeader64(); + filetype = H_64.filetype; + cputype = H_64.cputype; + } else { + MachO::mach_header H; + H = file->getHeader(); + filetype = H.filetype; + cputype = H.cputype; + } + PrintLoadCommands(file, filetype, cputype, !NonVerbose); +} + +//===----------------------------------------------------------------------===// +// export trie dumping +//===----------------------------------------------------------------------===// + +void llvm::printMachOExportsTrie(const object::MachOObjectFile *Obj) { + uint64_t BaseSegmentAddress = 0; + for (const auto &Command : Obj->load_commands()) { + if (Command.C.cmd == MachO::LC_SEGMENT) { + MachO::segment_command Seg = Obj->getSegmentLoadCommand(Command); + if (Seg.fileoff == 0 && Seg.filesize != 0) { + BaseSegmentAddress = Seg.vmaddr; + break; + } + } else if (Command.C.cmd == MachO::LC_SEGMENT_64) { + MachO::segment_command_64 Seg = Obj->getSegment64LoadCommand(Command); + if (Seg.fileoff == 0 && Seg.filesize != 0) { + BaseSegmentAddress = Seg.vmaddr; + break; + } + } + } + Error Err = Error::success(); + for (const llvm::object::ExportEntry &Entry : Obj->exports(Err)) { + uint64_t Flags = Entry.flags(); + bool ReExport = (Flags & MachO::EXPORT_SYMBOL_FLAGS_REEXPORT); + bool WeakDef = (Flags & MachO::EXPORT_SYMBOL_FLAGS_WEAK_DEFINITION); + bool ThreadLocal = ((Flags & MachO::EXPORT_SYMBOL_FLAGS_KIND_MASK) == + MachO::EXPORT_SYMBOL_FLAGS_KIND_THREAD_LOCAL); + bool Abs = ((Flags & MachO::EXPORT_SYMBOL_FLAGS_KIND_MASK) == + MachO::EXPORT_SYMBOL_FLAGS_KIND_ABSOLUTE); + bool Resolver = (Flags & MachO::EXPORT_SYMBOL_FLAGS_STUB_AND_RESOLVER); + if (ReExport) + outs() << "[re-export] "; + else + outs() << format("0x%08llX ", Entry.address() + BaseSegmentAddress); + outs() << Entry.name(); + if (WeakDef || ThreadLocal || Resolver || Abs) { + bool NeedsComma = false; + outs() << " ["; + if (WeakDef) { + outs() << "weak_def"; + NeedsComma = true; + } + if (ThreadLocal) { + if (NeedsComma) + outs() << ", "; + outs() << "per-thread"; + NeedsComma = true; + } + if (Abs) { + if (NeedsComma) + outs() << ", "; + outs() << "absolute"; + NeedsComma = true; + } + if (Resolver) { + if (NeedsComma) + outs() << ", "; + outs() << format("resolver=0x%08llX", Entry.other()); + NeedsComma = true; + } + outs() << "]"; + } + if (ReExport) { + StringRef DylibName = "unknown"; + int Ordinal = Entry.other() - 1; + Obj->getLibraryShortNameByIndex(Ordinal, DylibName); + if (Entry.otherName().empty()) + outs() << " (from " << DylibName << ")"; + else + outs() << " (" << Entry.otherName() << " from " << DylibName << ")"; + } + outs() << "\n"; + } + if (Err) + report_error(Obj->getFileName(), std::move(Err)); +} + +//===----------------------------------------------------------------------===// +// rebase table dumping +//===----------------------------------------------------------------------===// + +void llvm::printMachORebaseTable(object::MachOObjectFile *Obj) { + outs() << "segment section address type\n"; + Error Err = Error::success(); + for (const llvm::object::MachORebaseEntry &Entry : Obj->rebaseTable(Err)) { + StringRef SegmentName = Entry.segmentName(); + StringRef SectionName = Entry.sectionName(); + uint64_t Address = Entry.address(); + + // Table lines look like: __DATA __nl_symbol_ptr 0x0000F00C pointer + outs() << format("%-8s %-18s 0x%08" PRIX64 " %s\n", + SegmentName.str().c_str(), SectionName.str().c_str(), + Address, Entry.typeName().str().c_str()); + } + if (Err) + report_error(Obj->getFileName(), std::move(Err)); +} + +static StringRef ordinalName(const object::MachOObjectFile *Obj, int Ordinal) { + StringRef DylibName; + switch (Ordinal) { + case MachO::BIND_SPECIAL_DYLIB_SELF: + return "this-image"; + case MachO::BIND_SPECIAL_DYLIB_MAIN_EXECUTABLE: + return "main-executable"; + case MachO::BIND_SPECIAL_DYLIB_FLAT_LOOKUP: + return "flat-namespace"; + default: + if (Ordinal > 0) { + std::error_code EC = + Obj->getLibraryShortNameByIndex(Ordinal - 1, DylibName); + if (EC) + return "<>"; + return DylibName; + } + } + return "<>"; +} + +//===----------------------------------------------------------------------===// +// bind table dumping +//===----------------------------------------------------------------------===// + +void llvm::printMachOBindTable(object::MachOObjectFile *Obj) { + // Build table of sections so names can used in final output. + outs() << "segment section address type " + "addend dylib symbol\n"; + Error Err = Error::success(); + for (const llvm::object::MachOBindEntry &Entry : Obj->bindTable(Err)) { + StringRef SegmentName = Entry.segmentName(); + StringRef SectionName = Entry.sectionName(); + uint64_t Address = Entry.address(); + + // Table lines look like: + // __DATA __got 0x00012010 pointer 0 libSystem ___stack_chk_guard + StringRef Attr; + if (Entry.flags() & MachO::BIND_SYMBOL_FLAGS_WEAK_IMPORT) + Attr = " (weak_import)"; + outs() << left_justify(SegmentName, 8) << " " + << left_justify(SectionName, 18) << " " + << format_hex(Address, 10, true) << " " + << left_justify(Entry.typeName(), 8) << " " + << format_decimal(Entry.addend(), 8) << " " + << left_justify(ordinalName(Obj, Entry.ordinal()), 16) << " " + << Entry.symbolName() << Attr << "\n"; + } + if (Err) + report_error(Obj->getFileName(), std::move(Err)); +} + +//===----------------------------------------------------------------------===// +// lazy bind table dumping +//===----------------------------------------------------------------------===// + +void llvm::printMachOLazyBindTable(object::MachOObjectFile *Obj) { + outs() << "segment section address " + "dylib symbol\n"; + Error Err = Error::success(); + for (const llvm::object::MachOBindEntry &Entry : Obj->lazyBindTable(Err)) { + StringRef SegmentName = Entry.segmentName(); + StringRef SectionName = Entry.sectionName(); + uint64_t Address = Entry.address(); + + // Table lines look like: + // __DATA __got 0x00012010 libSystem ___stack_chk_guard + outs() << left_justify(SegmentName, 8) << " " + << left_justify(SectionName, 18) << " " + << format_hex(Address, 10, true) << " " + << left_justify(ordinalName(Obj, Entry.ordinal()), 16) << " " + << Entry.symbolName() << "\n"; + } + if (Err) + report_error(Obj->getFileName(), std::move(Err)); +} + +//===----------------------------------------------------------------------===// +// weak bind table dumping +//===----------------------------------------------------------------------===// + +void llvm::printMachOWeakBindTable(object::MachOObjectFile *Obj) { + outs() << "segment section address " + "type addend symbol\n"; + Error Err = Error::success(); + for (const llvm::object::MachOBindEntry &Entry : Obj->weakBindTable(Err)) { + // Strong symbols don't have a location to update. + if (Entry.flags() & MachO::BIND_SYMBOL_FLAGS_NON_WEAK_DEFINITION) { + outs() << " strong " + << Entry.symbolName() << "\n"; + continue; + } + StringRef SegmentName = Entry.segmentName(); + StringRef SectionName = Entry.sectionName(); + uint64_t Address = Entry.address(); + + // Table lines look like: + // __DATA __data 0x00001000 pointer 0 _foo + outs() << left_justify(SegmentName, 8) << " " + << left_justify(SectionName, 18) << " " + << format_hex(Address, 10, true) << " " + << left_justify(Entry.typeName(), 8) << " " + << format_decimal(Entry.addend(), 8) << " " << Entry.symbolName() + << "\n"; + } + if (Err) + report_error(Obj->getFileName(), std::move(Err)); +} + +// get_dyld_bind_info_symbolname() is used for disassembly and passed an +// address, ReferenceValue, in the Mach-O file and looks in the dyld bind +// information for that address. If the address is found its binding symbol +// name is returned. If not nullptr is returned. +static const char *get_dyld_bind_info_symbolname(uint64_t ReferenceValue, + struct DisassembleInfo *info) { + if (info->bindtable == nullptr) { + info->bindtable = llvm::make_unique(); + Error Err = Error::success(); + for (const llvm::object::MachOBindEntry &Entry : info->O->bindTable(Err)) { + uint64_t Address = Entry.address(); + StringRef name = Entry.symbolName(); + if (!name.empty()) + (*info->bindtable)[Address] = name; + } + if (Err) + report_error(info->O->getFileName(), std::move(Err)); + } + auto name = info->bindtable->lookup(ReferenceValue); + return !name.empty() ? name.data() : nullptr; +} Index: tools/llvm-mctoll/MachineFunctionRaiser.h =================================================================== --- /dev/null +++ tools/llvm-mctoll/MachineFunctionRaiser.h @@ -0,0 +1,75 @@ +//===-- MachineFunctionRaiser.h - Binary raiser utility llvm-mctoll -------===// +// +// The LLVM Compiler Infrastructure +// +// This file is distributed under the University of Illinois Open Source +// License. See LICENSE.TXT for details. +// +//===----------------------------------------------------------------------===// +// +// This file contains the declaration of the MachineFunctionRaiser class used +// by llvm-mctoll. This class encapsulates the context in which an assembly +// function is raised. +// +//===----------------------------------------------------------------------===// + +#ifndef LLVM_TOOLS_LLVM_MCTOLL_FUNCTIONRAISER_H +#define LLVM_TOOLS_LLVM_MCTOLL_FUNCTIONRAISER_H + +#include "MachineInstructionRaiser.h" +#include "ModuleRaiser.h" +#include "llvm/CodeGen/MachineFunction.h" +#include "llvm/CodeGen/MachineModuleInfo.h" +#include "llvm/MC/MCInstrAnalysis.h" +#include "llvm/MC/MCInstrInfo.h" + +using namespace llvm; +using IndexedData32 = std::pair; + +class MachineFunctionRaiser { +public: + MachineFunctionRaiser(Module &m, MachineFunction &mf, const ModuleRaiser *mr, + uint64_t start, uint64_t end) + : MF(mf), module(m), MR(mr) { + init(start, end); + // The new MachineFunction is not in SSA form, yet + MF.getProperties().reset(MachineFunctionProperties::Property::IsSSA); + }; + + bool runRaiserPasses(); + MachineFunction &getMachineFunction() const { return MF; } + + // Getters + MCInstRaiser *getMCInstRaiser() { return mcInstRaiser; } + Module &getModule() { return module; } + MachineInstructionRaiser *getMachineInstrRaiser() { + return machineInstRaiser; + } + Function *getRaisedFunction() { + return machineInstRaiser->getRaisedFunction(); + } + const ModuleRaiser *getModuleRaiser() { return MR; } + + virtual ~MachineFunctionRaiser() { + delete mcInstRaiser; + } + +private: + MachineFunction &MF; + Module &module; + + // Data members built and used by this class + MCInstRaiser *mcInstRaiser; + MachineInstructionRaiser *machineInstRaiser; + // A vector of data blobs found in the instruction stream + // of this function. A data blob is a sequence of data bytes. + // Multiple such data blobs may be found while disassembling + // the instruction stream of a function symbol. + std::vector dataBlobVector; + const ModuleRaiser *MR; + + // Functions + void init(uint64_t funcStart, uint64_t funcEnd); +}; + +#endif // LLVM_TOOLS_LLVM_MCTOLL_FUNCTIONRAISER_H Index: tools/llvm-mctoll/MachineFunctionRaiser.cpp =================================================================== --- /dev/null +++ tools/llvm-mctoll/MachineFunctionRaiser.cpp @@ -0,0 +1,303 @@ +//===-- MachineFunctionRaiser.cpp - Binary raiser utility llvm-mctoll -----===// +// +// The LLVM Compiler Infrastructure +// +// This file is distributed under the University of Illinois Open Source +// License. See LICENSE.TXT for details. +// +//===----------------------------------------------------------------------===// +// +// This file contains the implementaion of MachineFunctionRaiser class for use +// by llvm-mctoll. +// +//===----------------------------------------------------------------------===// + +#include "MachineFunctionRaiser.h" +#include "llvm/Object/ELFObjectFile.h" +#include "llvm/Target/TargetMachine.h" + +#ifdef __cplusplus +extern "C" { +#endif + +// ARM Raiser passes +MachineInstructionRaiser * +InitializeARMMachineInstructionRaiser(MachineFunction &machFunc, Module &m, + const ModuleRaiser *mr, + MCInstRaiser *mcir); + +// X86 Raiser passes +MachineInstructionRaiser * +InitializeX86MachineInstructionRaiser(MachineFunction &machFunc, Module &m, + const ModuleRaiser *mr, + MCInstRaiser *mcir); +#ifdef __cplusplus +} +#endif + +void MachineFunctionRaiser::init(uint64_t start, uint64_t end) { + mcInstRaiser = new MCInstRaiser(start, end); + machineInstRaiser = nullptr; + auto arch = MR->getTargetMachine()->getTargetTriple().getArch(); + + // Double check supported architecture. + if (!MR->isSupportedArch()) { + outs() << arch << "Unsupported architecture\n"; + return; + } + + switch (arch) { + case Triple::x86_64: + machineInstRaiser = + InitializeX86MachineInstructionRaiser(MF, module, MR, mcInstRaiser); + break; + case Triple::arm: + machineInstRaiser = + InitializeARMMachineInstructionRaiser(MF, module, MR, mcInstRaiser); + break; + // Add default case to pacify the compiler warnings. + default: + outs() << "\n" << arch << " not yet supported for raising\n"; + } +} + +bool MachineFunctionRaiser::runRaiserPasses() { + bool success = false; + // Do not run raise binaries of an unsupported architecture. + if (!MR->isSupportedArch()) + return false; + + // Raise MCInst to MachineInstr and Build CFG + if (machineInstRaiser != nullptr) { + // Raise MachineInstr to Instruction + success = machineInstRaiser->raise(); + } + return success; +} + +/* NOTE : The following ModuleRaiser class functions are defined here as they + * reference MachineFunctionRaiser class that has a forward declaration in + * ModuleRaiser.h. + */ +// Create a new MachineFunctionRaiser object and add it to the list of +// MachineFunction raiser objects of this module. +MachineFunctionRaiser *ModuleRaiser::CreateAndAddMachineFunctionRaiser( + Function *f, const ModuleRaiser *mr, uint64_t start, uint64_t end) { + MachineFunctionRaiser *mfRaiser = new MachineFunctionRaiser( + M, mr->getMachineModuleInfo()->getOrCreateMachineFunction(*f), mr, start, + end); + mfRaiserVector.push_back(mfRaiser); + return mfRaiser; +} + +Function *ModuleRaiser::getFunctionAt(uint64_t Index) const { + int64_t TextSecAddr = getTextSectionAddress(); + for (auto MFR : mfRaiserVector) { + if ((MFR->getMCInstRaiser()->getFuncStart() + TextSecAddr) == Index) { + return MFR->getRaisedFunction(); + } + } + return nullptr; +} + +const RelocationRef *ModuleRaiser::getDynRelocAtOffset(uint64_t Loc) const { + if (DynRelocs.empty()) { + return nullptr; + } + auto relocIter = std::find_if( + DynRelocs.begin(), DynRelocs.end(), + [Loc](const RelocationRef &a) -> bool { return (a.getOffset() == Loc); }); + if (relocIter != DynRelocs.end()) { + return &(*relocIter); + } else { + return nullptr; + } +} + +// Return relocation whose offset is in the range [Index, Index+Size) +const RelocationRef *ModuleRaiser::getTextRelocAtOffset(uint64_t Index, + uint64_t Size) const { + if (TextRelocs.empty()) { + return nullptr; + } + auto relocIter = std::find_if(TextRelocs.begin(), TextRelocs.end(), + [Index, Size](const RelocationRef &a) -> bool { + return ((a.getOffset() >= Index) && + (a.getOffset() < (Index + Size))); + }); + if (relocIter != TextRelocs.end()) { + return &(*relocIter); + } else { + return nullptr; + } +} + +Function *ModuleRaiser::getCalledFunctionUsingTextReloc(uint64_t Loc, + uint64_t Size) const { + // Find the text relocation with offset in the range [Loc, Loc+Size) + const RelocationRef *textReloc = getTextRelocAtOffset(Loc, Loc + Size); + if (textReloc != nullptr) { + Expected sym = textReloc->getSymbol()->getName(); + assert(sym && "Failed to find call target symbol"); + for (auto MFR : mfRaiserVector) { + Function *FP = MFR->getRaisedFunction(); + assert(FP && "Unexpected null function pointer encountered"); + if (sym->equals(FP->getName())) + return FP; + } + } + return nullptr; +} + +bool ModuleRaiser::runMachineFunctionPasses() { + bool success = true; + + // For each of the functions, run passes to + // set up for instruction raising. + for (auto MFR : mfRaiserVector) { + // 1. Build CFG + MCInstRaiser *MCIR = MFR->getMCInstRaiser(); + // Populates the MachineFunction with CFG. + MCIR->buildCFG(MFR->getMachineFunction(), MIA, MII); + + // 2. Construct function prototype. + // Knowing the function prototypes prior to raising the instructions + // facilitates raising of call instructions whose targets are within + // the current module. + // TODO : Adjust this when raising multiple modules. + Function *RF = MFR->getRaisedFunction(); + if (RF == nullptr) { + FunctionType *FT = + MFR->getMachineInstrRaiser()->getRaisedFunctionPrototype(); + assert(FT != nullptr && "Failed to build function prototype"); + } + } + // Run instruction raiser passes. + for (auto MFR : mfRaiserVector) { + success |= MFR->runRaiserPasses(); + } + return success; +} + +// Get the MachineFunction associated with the placeholder +// function corresponding to raised function. +MachineFunction *ModuleRaiser::getMachineFunction(Function *RF) { + auto V = PlaceholderRaisedFunctionMap.find(RF); + assert(V != PlaceholderRaisedFunctionMap.end() && + "Failed to find place-holder function"); + return MMI->getMachineFunction(*V->getSecond()); +} + +bool ModuleRaiser::collectTextSectionRelocs(const SectionRef &TextSec) { + // Assuming only one .text section in the binary + assert(TextSectionIndex == -1 && + "Relocations for .text section already collected"); + TextSectionIndex = TextSec.getIndex(); + // Find the section whose relocated section index is TextSecIndex. + // That section is the one with relocations corresponding to the + // section with index TextSecIndex. + for (const SectionRef &CandRelocSection : Obj->sections()) { + section_iterator RelocatedSecIter = CandRelocSection.getRelocatedSection(); + // If the CandRelocSection has a corresponding relocated section + if (RelocatedSecIter != Obj->section_end()) { + // If the corresponding relocated section is TextSec, CandRelocSection + // is the section with relocation information for TextSec. + if (RelocatedSecIter->getIndex() == (uint64_t)TextSectionIndex) { + for (const RelocationRef &reloc : CandRelocSection.relocations()) { + TextRelocs.push_back(reloc); + } + // Sort the relocations + std::sort(TextRelocs.begin(), TextRelocs.end(), + [](const RelocationRef &a, const RelocationRef &b) -> bool { + return a.getOffset() < b.getOffset(); + }); + break; + } + } + } + return true; +} + +bool ModuleRaiser::collectDynamicRelocations() { + + if (!Obj->isELF()) { + return false; + } + + const ELF64LEObjectFile *Elf64LEObjFile = dyn_cast(Obj); + if (!Elf64LEObjFile) { + return false; + } + + std::vector DynRelSec = Obj->dynamic_relocation_sections(); + + for (const SectionRef &Section : DynRelSec) { + for (const RelocationRef &Reloc : Section.relocations()) { + DynRelocs.push_back(Reloc); + } + } + + // Get relocations of .got.plt section from .rela.plt if it exists. I do not + // see an API in ObjectFile class to get at these. + + // Find .got.plt and .rela.plt sections Note: A lot of verification and double + // checking done in the following code. + const ELFFile *ElfFile = Elf64LEObjFile->getELFFile(); + // Find .rela.plt + SectionRef DotGotDotPltSec, DotRelaDotPltSec; + for (const SectionRef Section : Obj->sections()) { + StringRef SecName; + Section.getName(SecName); + if (SecName.equals(".rela.plt")) { + DotRelaDotPltSec = Section; + } else if (SecName.equals(".got.plt")) { + DotGotDotPltSec = Section; + } + } + if (DotRelaDotPltSec.getObject() != nullptr) { + // Do some additional sanity checks + assert((DotGotDotPltSec.getObject() != nullptr) && + "Failed to find .got.plt section"); + auto DotRelaDotPltShdr = ElfFile->getSection(DotRelaDotPltSec.getIndex()); + assert(DotRelaDotPltShdr && "Failed to find .rela.plt section"); + assert((DotRelaDotPltShdr.get()->sh_info == DotGotDotPltSec.getIndex()) && + ".rela.plt does not refer .got.plt section"); + assert((DotRelaDotPltShdr.get()->sh_type == ELF::SHT_RELA) && + "Unexpected type of section .rela.plt"); + for (const RelocationRef &Reloc : DotRelaDotPltSec.relocations()) { + DynRelocs.push_back(Reloc); + } + } + return true; +} + +// Return text section address; or -1 if text section is not found +int64_t ModuleRaiser::getTextSectionAddress() const { + if (!Obj->isELF()) { + return -1; + } + assert(TextSectionIndex >= 0 && "Unexpected negative index of text section"); + for (SectionRef Sec : Obj->sections()) { + if (Sec.getIndex() == (unsigned)TextSectionIndex) { + return Sec.getAddress(); + } + } + assert(false && "Failed to locate text section."); + return -1; +} + +const Value *ModuleRaiser::getRODataValueAt(uint64_t offset) const { + Value *V = nullptr; + auto iter = GlobalRODataValues.find(offset); + if (iter != GlobalRODataValues.end()) { + V = iter->second; + } + return V; +} + +void ModuleRaiser::addRODataValueAt(Value *v, uint64_t offset) const { + assert((GlobalRODataValues.find(offset) == GlobalRODataValues.end()) && + "Attempt to insert value for already existing rodata location"); + GlobalRODataValues.emplace(offset, v); + return; +} Index: tools/llvm-mctoll/MachineInstructionRaiser.h =================================================================== --- /dev/null +++ tools/llvm-mctoll/MachineInstructionRaiser.h @@ -0,0 +1,80 @@ +//===-- MachineInstructionRaiser.h - Binary raiser utility llvm-mctoll ----===// +// +// The LLVM Compiler Infrastructure +// +// This file is distributed under the University of Illinois Open Source +// License. See LICENSE.TXT for details. +// +//===----------------------------------------------------------------------===// +// +// This file contains the declaration of MachineInstructionRaiser class used +// by llvm-mctoll. This class encapsulates the raising of MachineInstruction +// to LLVM Instruction +// +//===----------------------------------------------------------------------===// + +#ifndef LLVM_TOOLS_LLVM_MCTOLL_MACHINEINSTRUCTIONRAISER_H +#define LLVM_TOOLS_LLVM_MCTOLL_MACHINEINSTRUCTIONRAISER_H + +#include "MCInstRaiser.h" +#include "ModuleRaiser.h" +#include "llvm/CodeGen/MachineFunction.h" + +using namespace llvm; + +// Structure holding all necesssary information to raise control +// transfer (i.e., branch) instructions during a post-processing +// phase. + +typedef struct { + BasicBlock *CandidateBlock; + // This is the MachineInstr that needs to be raised + const MachineInstr *CandidateMachineInstr; + // A vector of values that could be of use while raising + // CandidateMachineInstr. If it is a call instruction, + // This vector has the Values corresponding to argument + // registers (TODO : need to handles arguments passed on stack) + std::vector RegValues; + // Flag to indicate that CandidateMachineInstr has been raised + bool Raised; +} ControlTransferInfo; + +class MachineInstructionRaiser { +public: + MachineInstructionRaiser() = delete; + MachineInstructionRaiser(MachineFunction &machFunc, Module &m, + const ModuleRaiser *mr, MCInstRaiser *mcir = nullptr) + : MF(machFunc), raisedFunction(nullptr), mcInstRaiser(mcir), MR(mr), + PrintPass(false) {} + virtual ~MachineInstructionRaiser(){}; + + virtual bool raise() { return true; }; + virtual FunctionType *getRaisedFunctionPrototype() = 0; + virtual int getArgumentNumber(unsigned PReg) = 0; + virtual Value *getRegValue(unsigned PReg) = 0; + virtual bool buildFuncArgTypeVector(const std::set &, + std::vector &) = 0; + + Function *getRaisedFunction() { return raisedFunction; } + MCInstRaiser *getMCInstRaiser() { return mcInstRaiser; } + + std::vector getControlTransferInfo() { + return CTInfo; + }; + +protected: + MachineFunction &MF; + // This is the Function object that holds the raised abstraction of MF. + // Not the the fucntion associated with MF should not be referenced or + // updated. It was created just to enable the creation of MF. + Function *raisedFunction; + MCInstRaiser *mcInstRaiser; + const ModuleRaiser *MR; + + // A vector of information to be used for raising of control transfer + // (i.e., Call and Terminator) instructions. + std::vector CTInfo; + + bool PrintPass; +}; +#endif // LLVM_TOOLS_LLVM_MCTOLL_MACHINEINSTRUCTIONRAISER_H Index: tools/llvm-mctoll/ModuleRaiser.h =================================================================== --- /dev/null +++ tools/llvm-mctoll/ModuleRaiser.h @@ -0,0 +1,155 @@ +//===-- ModuleRaiser.h - Object file dumping utility for llvm -------------===// +// +// The LLVM Compiler Infrastructure +// +// This file is distributed under the University of Illinois Open Source +// License. See LICENSE.TXT for details. +// +//===----------------------------------------------------------------------===// +// +// This file contains the declaration of ModuleRaiser class for use by +// llvm-mctoll. +// +//===----------------------------------------------------------------------===// + +#ifndef LLVM_TOOLS_LLVM_MCTOLL_MODULERAISER_H +#define LLVM_TOOLS_LLVM_MCTOLL_MODULERAISER_H + +#include "llvm/CodeGen/MachineModuleInfo.h" +#include "llvm/MC/MCDisassembler/MCDisassembler.h" +#include "llvm/MC/MCInstrAnalysis.h" +#include "llvm/Object/ObjectFile.h" +#include "llvm/Target/TargetMachine.h" +#include + +using namespace llvm; +using namespace std; + +class MachineFunctionRaiser; + +using namespace object; + +// The ModuleRaiser class encapsulates information needed to raise a given +// module. +class ModuleRaiser { +public: + ModuleRaiser(Module &m, const TargetMachine *tm, MachineModuleInfo *mmi, + const MCInstrAnalysis *mia, const MCInstrInfo *mii, + const ObjectFile *o, MCDisassembler *dis) + : M(m), TM(tm), MMI(mmi), MIA(mia), MII(mii), Obj(o), DisAsm(dis), + TextSectionIndex(-1) { + supportedArch = false; + auto arch = tm->getTargetTriple().getArch(); + switch (arch) { + case Triple::x86_64: + supportedArch = true; + break; + case Triple::arm: + supportedArch = true; + break; + default: + outs() << "\n" << arch << " not yet supported for raising\n"; + } + // Collect dynamic relocations. + collectDynamicRelocations(); + } + + // Function to create a MachineFunctionRaiser corresponding to Function f. + // As noted elsewhere (llvm-mctoll.cpp), f is a place holder to allow for + // creation of MachineFunction. The Function object representing raising + // of MachineFunction is accessible by calling getRaisedFunction() + // on the MachineFunctionRaiser object. + MachineFunctionRaiser *CreateAndAddMachineFunctionRaiser(Function *f, + const ModuleRaiser *, + uint64_t start, + uint64_t end); + + MachineFunctionRaiser *getCurrentMachineFunctionRaiser() { + if (mfRaiserVector.size() > 0) { + return mfRaiserVector.back(); + } + return nullptr; + } + + // Insert the map of raised function R to place-holder function PH pointer + // that inturn has the to corresponding MachineFunction. + + bool insertPlaceholderRaisedFunctionMap(Function *R, Function *PH) { + auto V = PlaceholderRaisedFunctionMap.insert(std::make_pair(R, PH)); + return V.second; + } + + bool collectTextSectionRelocs(const SectionRef &); + bool collectDynamicRelocations(); + + MachineFunction *getMachineFunction(Function *); + + // Member getters + Module &getModule() const { return M; } + const TargetMachine *getTargetMachine() const { return TM; } + MachineModuleInfo *getMachineModuleInfo() const { return MMI; } + const MCInstrAnalysis *getMCInstrAnalysis() const { return MIA; } + const MCInstrInfo *getMCInstrInfo() const { return MII; } + const ObjectFile *getObjectFile() const { return Obj; } + const MCDisassembler *getMCDisassembler() const { return DisAsm; } + + bool isSupportedArch() const { return supportedArch; } + + bool runMachineFunctionPasses(); + + // Return the Function * corresponding to input binary function with + // start offset equal to that specified as argument. + Function *getFunctionAt(uint64_t) const; + + // Return the Function * corresponding to input binary function from + // text relocation record with off set in the range [Loc, Loc+Size]. + Function *getCalledFunctionUsingTextReloc(uint64_t Loc, uint64_t Size) const; + + // Get dynamic relocation with offset 'O' + const RelocationRef *getDynRelocAtOffset(uint64_t O) const; + // Return text relocation of instruction at index 'I'. 'S' is the size of the + // instruction at index 'I'. + const RelocationRef *getTextRelocAtOffset(uint64_t I, uint64_t S) const; + int64_t getTextSectionAddress() const; + + const Value *getRODataValueAt(uint64_t) const; + void addRODataValueAt(Value *, uint64_t) const; + + virtual ~ModuleRaiser() {} + +private: + // A sequential list of MachineFunctionRaiser objects created + // as the instructions of the input binary are parsed. Each of + // these correspond to a "machine function". A machine function + // corresponds to a sequence of instructions (possibly interspersed + // by data bytes) whose start is denoted by a function symbol in + // the binary. + std::vector mfRaiserVector; + // A map of raised function pointer to place-holder function pointer + // that links to the MachineFunction. + DenseMap PlaceholderRaisedFunctionMap; + // Sorted vector of text relocations + std::vector TextRelocs; + // Vector of dynamic relocation records + std::vector DynRelocs; + // Map of read-only data (i.e., from .rodata) to its corresponding global + // value. + // NOTE: A const version of ModuleRaiser object is constructed during the + // raising process. Making this map mutable since this map is expected to be + // updated throughout the raising process. + mutable std::map GlobalRODataValues; + + // Commonly used data structures + Module &M; + const TargetMachine *TM; + MachineModuleInfo *MMI; + const MCInstrAnalysis *MIA; + const MCInstrInfo *MII; + bool supportedArch; + const ObjectFile *Obj; + MCDisassembler *DisAsm; + // Index of text section whose instructions are raised + int64_t TextSectionIndex; +}; + +#endif // LLVM_TOOLS_LLVM_MCTOLL_MODULERAISER_H Index: tools/llvm-mctoll/README.md =================================================================== --- /dev/null +++ tools/llvm-mctoll/README.md @@ -0,0 +1,101 @@ +# Introduction +Tool to statically (AOT) translate binaries to LLVM IR. + +A tool to raise (or lift) compiled binaries to LLVM IR. + +The implementation uses disassembly functionality implemented in +llvm-objdump. + +# Getting Started (Linux/Mac) +## Building as part of LLVM tree + +1. `mkdir $PWD/src && mkdir -p $PWD/build/llvm && cd src` +2. `git clone https://edgetools.visualstudio.com/DefaultCollection/llvm/_git/llvm && pushd llvm && git checkout master && popd` +3. `pushd llvm/tools && git clone https://edgetools.visualstudio.com/DefaultCollection/llvm/_git/clang && git checkout master && popd` +4. `pushd llvm/tools && git clone https://edgetools.visualstudio.com/DefaultCollection/llvm/_git/llvm-mctoll && git checkout master && popd` +7. `cd ../build/llvm` +7. Run cmake command that you usually use to build llvm +8. Run `make llvm-mctoll` or `ninja llvm-mctoll` + +## Building as standalone project (not as part of LLVM tree) +(**NOTE** : _Support for this needs to be updated. Please build llvm-mctoll as part of LLVM tree as described above_.) + +The source files of this project include LLVM target-specific headers +from the LLVM source directory and LLVM build directory. Hence LLVM +sources need to be downloaded and built. At least, the following LLVM +targets need to be built so that all dependencies of llvm-mctoll are +available prior creating build files for llvm-mctoll (i.e., prior to +running `cmake` on llvm-mctoll tree). + + * llc + * llvm-objdump + * llvm-config + +Building the targets llc and llvm-objdump will build all the necessary +libraries and include files to enable building of llvm-mctoll. + +At present llvm-mctoll is being developed to handle X86_64 and ARM +binaries. So the above targets need to be built at least for these two +targets. + +CMake script of llvm-mctoll uses `llvm-config` from the build tree to +discover the following information of the LLVM build used to build +llvm-mctoll. + + * assertion mode, + * location of build and object directories, + * location of LLVM source directory + * compiler flags to be used, + * location of cmake script directory + +`llvm-config` from the LLVM build directory needs to be specified in the +cmake command that creates build files for llvm-mctoll. + +If you also want to run the tests for llvm-mctoll, the following +additional dependencies from LLVM need to be built: + + * clang + * count + * not + * FileCheck + +Following assumes that llvm build dir is `` and an +install directory `` of your choice. + +1. `mkdir $PWD/src; mkdir -p $PWD/build/llvm-mctoll; cd src` +2. `git clone https://edgetools.visualstudio.com/DefaultCollection/_git/rawbits` +3. `cd ../build/llvm-mctoll` +4. Run cmake command as follows + + `cmake -G ["Unix Makefiles"|"Ninja"] -DLLVM_CONFIG_PATH=/bin/llvm-config -DCMAKE_INSTALL_PREFIX= ../../src/rawbits/llvm-mctoll` + +5. Run `make` or `ninja`. Resulting binary `llvm-mctoll` is in current directory. +6. (Optional) Run `make install` or `ninja install` + + +# Usage instructions: + +`llvm-mctoll -d ` + +or + +To print debug output: + +`llvm-mctoll -d -print-after-all ` + +To view Pass: +`llvm-mctoll -d -debug-pass=Structure ` + +# Current Status + +The tool is currently able to raise Linux x86_64 shared libraries and executables with `printf` calls. + +TODO : +1. Cleanup llvm-objdump related functionality that is not relevant to this tool. + +# Build and Test + +Run the tests by invoking 'make check-mctoll' or 'ninja check-mctoll' + +# Contribute +TODO: Explain how other users and developers can contribute to make your code better. Index: tools/llvm-mctoll/WasmDump.cpp =================================================================== --- /dev/null +++ tools/llvm-mctoll/WasmDump.cpp @@ -0,0 +1,28 @@ +//===-- WasmDump.cpp - wasm-specific dumper ---------------------*- C++ -*-===// +// +// The LLVM Compiler Infrastructure +// +// This file is distributed under the University of Illinois Open Source +// License. See LICENSE.TXT for details. +// +//===----------------------------------------------------------------------===// +/// +/// \file +/// \brief This file implements the wasm-specific dumper for llvm-objdump. +/// +//===----------------------------------------------------------------------===// + +#include "llvm-mctoll.h" +#include "llvm/Object/Wasm.h" + +using namespace llvm; +using namespace object; + +void llvm::printWasmFileHeader(const object::ObjectFile *Obj) { + const WasmObjectFile *File = dyn_cast(Obj); + + outs() << "Program Header:\n"; + outs() << "Version: 0x"; + outs().write_hex(File->getHeader().Version); + outs() << "\n"; +} Index: tools/llvm-mctoll/X86/CMakeLists.txt =================================================================== --- /dev/null +++ tools/llvm-mctoll/X86/CMakeLists.txt @@ -0,0 +1,16 @@ +include_directories( + ${LLVM_MAIN_SRC_DIR}/lib/Target/X86 + ${LLVM_BINARY_DIR}/lib/Target/X86 + ${CMAKE_CURRENT_SOURCE_DIR}/.. +) + +if(NOT LLVM_MCTOLL_BUILT_STANDALONE) + set(LLVM_MCTOLL_DEPS intrinsics_gen X86CommonTableGen) +endif() + +add_llvm_library(X86Raiser + X86MachineInstructionRaiser.cpp + + DEPENDS + ${LLVM_MCTOLL_DEPS} + ) Index: tools/llvm-mctoll/X86/X86AdditionalInstrInfo.h =================================================================== --- /dev/null +++ tools/llvm-mctoll/X86/X86AdditionalInstrInfo.h @@ -0,0 +1,14636 @@ +//==-- X86AdditionalInstrInfo.h - Binary raiser utility llvm-mctoll =====// +// +// The LLVM Compiler Infrastructure +// +// This file is distributed under the University of Illinois Open Source +// License. See LICENSE.TXT for details. +// +//===----------------------------------------------------------------------===// +// +// This file contains the declaration of X86AdditionalInstrInfo.h +// class for use by llvm-mctoll. +// It contains all information about X86 instructions that are not available +// from tblgen generated tables. +// +//===----------------------------------------------------------------------===// +#ifndef LLVM_TOOLS_LLVM_MCTOLL_X86_X86ADDITIONALINSTRINFO_H +#define LLVM_TOOLS_LLVM_MCTOLL_X86_X86ADDITIONALINSTRINFO_H + +#include "X86InstrBuilder.h" +#include "X86Subtarget.h" + +namespace mctoll { +// Instruction Kinds + +typedef enum { + Unknown = 0, + BINARY_OP_RM, + BINARY_OP_RR, + BINARY_OP_WITH_IMM, + COMPARE, + CONVERT_BWWDDQ, + CONVERT_WDDQQO, + DIVIDE_OP, + FPU_REG_OP, + LEA_OP, + LEAVE_OP, + LOAD_FPU_REG, + MOV_RR, + MOV_RI, + MOV_TO_MEM, + MOV_FROM_MEM, + NOOP, + SETCC, + STORE_FPU_REG, +} InstructionKind; + +typedef struct { + // A vaue of 8 or 4 or 2 or 1 indicates the size of memory an instruction + // operates on. A value of 0 indicates that the instruction doess not have + // memory operands. + unsigned short MemOpSize; + // Instruction kind + InstructionKind InstKind; + // Add any necessary additional instruction related data as fields of this + // structure. +} X86AdditionalInstrInfo; + +using const_addl_instr_info = const std::map; +using const_addl_instr_info_iteartor = const_addl_instr_info::iterator; + +static const_addl_instr_info X86AddlInstrInfo = { + {X86::AAA, {0, Unknown}}, + {X86::AAD8i8, {0, Unknown}}, + {X86::AAM8i8, {0, Unknown}}, + {X86::AAS, {0, Unknown}}, + {X86::ABS_F, {0, Unknown}}, + {X86::ABS_Fp32, {0, Unknown}}, + {X86::ABS_Fp64, {0, Unknown}}, + {X86::ABS_Fp80, {0, Unknown}}, + {X86::ADC16i16, {0, Unknown}}, + {X86::ADC16mi, {2, Unknown}}, + {X86::ADC16mi8, {2, Unknown}}, + {X86::ADC16mr, {2, Unknown}}, + {X86::ADC16ri, {0, Unknown}}, + {X86::ADC16ri8, {0, Unknown}}, + {X86::ADC16rm, {2, Unknown}}, + {X86::ADC16rr, {0, Unknown}}, + {X86::ADC16rr_REV, {0, Unknown}}, + {X86::ADC32i32, {0, Unknown}}, + {X86::ADC32mi, {4, Unknown}}, + {X86::ADC32mi8, {4, Unknown}}, + {X86::ADC32mr, {4, Unknown}}, + {X86::ADC32ri, {0, Unknown}}, + {X86::ADC32ri8, {0, Unknown}}, + {X86::ADC32rm, {4, Unknown}}, + {X86::ADC32rr, {0, Unknown}}, + {X86::ADC32rr_REV, {0, Unknown}}, + {X86::ADC64i32, {0, Unknown}}, + {X86::ADC64mi32, {8, Unknown}}, + {X86::ADC64mi8, {8, Unknown}}, + {X86::ADC64mr, {8, Unknown}}, + {X86::ADC64ri32, {0, Unknown}}, + {X86::ADC64ri8, {0, Unknown}}, + {X86::ADC64rm, {8, Unknown}}, + {X86::ADC64rr, {0, Unknown}}, + {X86::ADC64rr_REV, {0, Unknown}}, + {X86::ADC8i8, {0, Unknown}}, + {X86::ADC8mi, {1, Unknown}}, + {X86::ADC8mi8, {1, Unknown}}, + {X86::ADC8mr, {1, Unknown}}, + {X86::ADC8ri, {0, Unknown}}, + {X86::ADC8ri8, {0, Unknown}}, + {X86::ADC8rm, {1, Unknown}}, + {X86::ADC8rr, {0, Unknown}}, + {X86::ADC8rr_REV, {0, Unknown}}, + {X86::ADCX32rm, {4, Unknown}}, + {X86::ADCX32rr, {0, Unknown}}, + {X86::ADCX64rm, {8, Unknown}}, + {X86::ADCX64rr, {0, Unknown}}, + {X86::ADD16i16, {0, Unknown}}, + {X86::ADD16mi, {2, Unknown}}, + {X86::ADD16mi8, {2, Unknown}}, + {X86::ADD16mr, {2, Unknown}}, + {X86::ADD16ri, {0, Unknown}}, + {X86::ADD16ri8, {0, Unknown}}, + {X86::ADD16ri8_DB, {0, Unknown}}, + {X86::ADD16ri_DB, {0, Unknown}}, + {X86::ADD16rm, {2, Unknown}}, + {X86::ADD16rr, {0, Unknown}}, + {X86::ADD16rr_DB, {0, Unknown}}, + {X86::ADD16rr_REV, {0, Unknown}}, + {X86::ADD32i32, {0, Unknown}}, + {X86::ADD32mi, {4, Unknown}}, + {X86::ADD32mi8, {4, Unknown}}, + {X86::ADD32mr, {4, Unknown}}, + {X86::ADD32ri, {0, BINARY_OP_WITH_IMM}}, + {X86::ADD32ri8, {0, BINARY_OP_WITH_IMM}}, + {X86::ADD32ri8_DB, {0, Unknown}}, + {X86::ADD32ri_DB, {0, Unknown}}, + {X86::ADD32rm, {4, BINARY_OP_RM}}, + {X86::ADD32rr, {0, BINARY_OP_RR}}, + {X86::ADD32rr_DB, {0, Unknown}}, + {X86::ADD32rr_REV, {0, Unknown}}, + {X86::ADD64i32, {0, Unknown}}, + {X86::ADD64mi32, {8, Unknown}}, + {X86::ADD64mi8, {8, Unknown}}, + {X86::ADD64mr, {8, Unknown}}, + {X86::ADD64ri32, {0, BINARY_OP_WITH_IMM}}, + {X86::ADD64ri32_DB, {0, Unknown}}, + {X86::ADD64ri8, {0, BINARY_OP_WITH_IMM}}, + {X86::ADD64ri8_DB, {0, Unknown}}, + {X86::ADD64rm, {8, BINARY_OP_RM}}, + {X86::ADD64rr, {0, BINARY_OP_RR}}, + {X86::ADD64rr_DB, {0, Unknown}}, + {X86::ADD64rr_REV, {0, Unknown}}, + {X86::ADD8i8, {0, BINARY_OP_WITH_IMM}}, + {X86::ADD8mi, {1, Unknown}}, + {X86::ADD8mi8, {1, Unknown}}, + {X86::ADD8mr, {1, Unknown}}, + {X86::ADD8ri, {0, Unknown}}, + {X86::ADD8ri8, {0, Unknown}}, + {X86::ADD8rm, {1, Unknown}}, + {X86::ADD8rr, {0, Unknown}}, + {X86::ADD8rr_REV, {0, Unknown}}, + {X86::ADDPDrm, {0, Unknown}}, + {X86::ADDPDrr, {0, Unknown}}, + {X86::ADDPSrm, {0, Unknown}}, + {X86::ADDPSrr, {0, Unknown}}, + {X86::ADDSDrm, {0, Unknown}}, + {X86::ADDSDrm_Int, {0, Unknown}}, + {X86::ADDSDrr, {0, Unknown}}, + {X86::ADDSDrr_Int, {0, Unknown}}, + {X86::ADDSSrm, {0, Unknown}}, + {X86::ADDSSrm_Int, {0, Unknown}}, + {X86::ADDSSrr, {0, Unknown}}, + {X86::ADDSSrr_Int, {0, Unknown}}, + {X86::ADDSUBPDrm, {0, Unknown}}, + {X86::ADDSUBPDrr, {0, Unknown}}, + {X86::ADDSUBPSrm, {0, Unknown}}, + {X86::ADDSUBPSrr, {0, Unknown}}, + {X86::ADD_F32m, {0, Unknown}}, + {X86::ADD_F64m, {0, Unknown}}, + {X86::ADD_FI16m, {0, Unknown}}, + {X86::ADD_FI32m, {0, Unknown}}, + {X86::ADD_FPrST0, {0, Unknown}}, + {X86::ADD_FST0r, {0, Unknown}}, + {X86::ADD_Fp32, {0, Unknown}}, + {X86::ADD_Fp32m, {0, Unknown}}, + {X86::ADD_Fp64, {0, Unknown}}, + {X86::ADD_Fp64m, {0, Unknown}}, + {X86::ADD_Fp64m32, {0, Unknown}}, + {X86::ADD_Fp80, {0, Unknown}}, + {X86::ADD_Fp80m32, {0, Unknown}}, + {X86::ADD_Fp80m64, {0, Unknown}}, + {X86::ADD_FpI16m32, {0, Unknown}}, + {X86::ADD_FpI16m64, {0, Unknown}}, + {X86::ADD_FpI16m80, {0, Unknown}}, + {X86::ADD_FpI32m32, {0, Unknown}}, + {X86::ADD_FpI32m64, {0, Unknown}}, + {X86::ADD_FpI32m80, {0, Unknown}}, + {X86::ADD_FrST0, {0, Unknown}}, + {X86::ADJCALLSTACKDOWN32, {0, Unknown}}, + {X86::ADJCALLSTACKDOWN64, {0, Unknown}}, + {X86::ADJCALLSTACKUP32, {0, Unknown}}, + {X86::ADJCALLSTACKUP64, {0, Unknown}}, + {X86::ADOX32rm, {4, Unknown}}, + {X86::ADOX32rr, {0, Unknown}}, + {X86::ADOX64rm, {8, Unknown}}, + {X86::ADOX64rr, {0, Unknown}}, + {X86::AESDECLASTrm, {0, Unknown}}, + {X86::AESDECLASTrr, {0, Unknown}}, + {X86::AESDECrm, {0, Unknown}}, + {X86::AESDECrr, {0, Unknown}}, + {X86::AESENCLASTrm, {0, Unknown}}, + {X86::AESENCLASTrr, {0, Unknown}}, + {X86::AESENCrm, {0, Unknown}}, + {X86::AESENCrr, {0, Unknown}}, + {X86::AESIMCrm, {0, Unknown}}, + {X86::AESIMCrr, {0, Unknown}}, + {X86::AESKEYGENASSIST128rm, {1, Unknown}}, + {X86::AESKEYGENASSIST128rr, {0, Unknown}}, + {X86::AND16i16, {0, Unknown}}, + {X86::AND16mi, {2, Unknown}}, + {X86::AND16mi8, {2, Unknown}}, + {X86::AND16mr, {2, Unknown}}, + {X86::AND16ri, {0, BINARY_OP_WITH_IMM}}, + {X86::AND16ri8, {0, Unknown}}, + {X86::AND16rm, {2, Unknown}}, + {X86::AND16rr, {0, Unknown}}, + {X86::AND16rr_REV, {0, Unknown}}, + {X86::AND32i32, {0, Unknown}}, + {X86::AND32mi, {4, Unknown}}, + {X86::AND32mi8, {4, Unknown}}, + {X86::AND32mr, {4, Unknown}}, + {X86::AND32ri, {0, BINARY_OP_WITH_IMM}}, + {X86::AND32ri8, {0, Unknown}}, + {X86::AND32rm, {4, Unknown}}, + {X86::AND32rr, {0, Unknown}}, + {X86::AND32rr_REV, {0, Unknown}}, + {X86::AND64i32, {0, Unknown}}, + {X86::AND64mi32, {8, Unknown}}, + {X86::AND64mi8, {8, Unknown}}, + {X86::AND64mr, {8, Unknown}}, + {X86::AND64ri32, {0, BINARY_OP_WITH_IMM}}, + {X86::AND64ri8, {0, BINARY_OP_WITH_IMM}}, + {X86::AND64rm, {8, Unknown}}, + {X86::AND64rr, {0, Unknown}}, + {X86::AND64rr_REV, {0, Unknown}}, + {X86::AND8i8, {0, BINARY_OP_WITH_IMM}}, + {X86::AND8mi, {1, Unknown}}, + {X86::AND8mi8, {1, Unknown}}, + {X86::AND8mr, {1, Unknown}}, + {X86::AND8ri, {0, BINARY_OP_WITH_IMM}}, + {X86::AND8ri8, {0, Unknown}}, + {X86::AND8rm, {1, Unknown}}, + {X86::AND8rr, {0, Unknown}}, + {X86::AND8rr_REV, {0, Unknown}}, + {X86::ANDN32rm, {4, Unknown}}, + {X86::ANDN32rr, {0, Unknown}}, + {X86::ANDN64rm, {8, Unknown}}, + {X86::ANDN64rr, {0, Unknown}}, + {X86::ANDNPDrm, {0, Unknown}}, + {X86::ANDNPDrr, {0, Unknown}}, + {X86::ANDNPSrm, {0, Unknown}}, + {X86::ANDNPSrr, {0, Unknown}}, + {X86::ANDPDrm, {0, Unknown}}, + {X86::ANDPDrr, {0, Unknown}}, + {X86::ANDPSrm, {0, Unknown}}, + {X86::ANDPSrr, {0, Unknown}}, + {X86::ANNOTATION_LABEL, {0, Unknown}}, + {X86::ARPL16mr, {2, Unknown}}, + {X86::ARPL16rr, {0, Unknown}}, + {X86::AVX1_SETALLONES, {0, Unknown}}, + {X86::AVX2_SETALLONES, {0, Unknown}}, + {X86::AVX512_128_SET0, {0, Unknown}}, + {X86::AVX512_256_SET0, {0, Unknown}}, + {X86::AVX512_512_SET0, {0, Unknown}}, + {X86::AVX512_512_SETALLONES, {0, Unknown}}, + {X86::AVX512_512_SEXT_MASK_32, {0, Unknown}}, + {X86::AVX512_512_SEXT_MASK_64, {0, Unknown}}, + {X86::AVX512_FsFLD0SD, {0, Unknown}}, + {X86::AVX512_FsFLD0SS, {0, Unknown}}, + {X86::AVX_SET0, {0, Unknown}}, + {X86::BEXTR32rm, {4, Unknown}}, + {X86::BEXTR32rr, {0, Unknown}}, + {X86::BEXTR64rm, {8, Unknown}}, + {X86::BEXTR64rr, {0, Unknown}}, + {X86::BEXTRI32mi, {4, Unknown}}, + {X86::BEXTRI32ri, {0, Unknown}}, + {X86::BEXTRI64mi, {8, Unknown}}, + {X86::BEXTRI64ri, {0, Unknown}}, + {X86::BLCFILL32rm, {4, Unknown}}, + {X86::BLCFILL32rr, {0, Unknown}}, + {X86::BLCFILL64rm, {8, Unknown}}, + {X86::BLCFILL64rr, {0, Unknown}}, + {X86::BLCI32rm, {4, Unknown}}, + {X86::BLCI32rr, {0, Unknown}}, + {X86::BLCI64rm, {8, Unknown}}, + {X86::BLCI64rr, {0, Unknown}}, + {X86::BLCIC32rm, {4, Unknown}}, + {X86::BLCIC32rr, {0, Unknown}}, + {X86::BLCIC64rm, {8, Unknown}}, + {X86::BLCIC64rr, {0, Unknown}}, + {X86::BLCMSK32rm, {4, Unknown}}, + {X86::BLCMSK32rr, {0, Unknown}}, + {X86::BLCMSK64rm, {8, Unknown}}, + {X86::BLCMSK64rr, {0, Unknown}}, + {X86::BLCS32rm, {4, Unknown}}, + {X86::BLCS32rr, {0, Unknown}}, + {X86::BLCS64rm, {8, Unknown}}, + {X86::BLCS64rr, {0, Unknown}}, + {X86::BLENDPDrmi, {0, Unknown}}, + {X86::BLENDPDrri, {0, Unknown}}, + {X86::BLENDPSrmi, {0, Unknown}}, + {X86::BLENDPSrri, {0, Unknown}}, + {X86::BLENDVPDrm0, {0, Unknown}}, + {X86::BLENDVPDrr0, {0, Unknown}}, + {X86::BLENDVPSrm0, {0, Unknown}}, + {X86::BLENDVPSrr0, {0, Unknown}}, + {X86::BLSFILL32rm, {4, Unknown}}, + {X86::BLSFILL32rr, {0, Unknown}}, + {X86::BLSFILL64rm, {8, Unknown}}, + {X86::BLSFILL64rr, {0, Unknown}}, + {X86::BLSI32rm, {4, Unknown}}, + {X86::BLSI32rr, {0, Unknown}}, + {X86::BLSI64rm, {8, Unknown}}, + {X86::BLSI64rr, {0, Unknown}}, + {X86::BLSIC32rm, {4, Unknown}}, + {X86::BLSIC32rr, {0, Unknown}}, + {X86::BLSIC64rm, {8, Unknown}}, + {X86::BLSIC64rr, {0, Unknown}}, + {X86::BLSMSK32rm, {4, Unknown}}, + {X86::BLSMSK32rr, {0, Unknown}}, + {X86::BLSMSK64rm, {8, Unknown}}, + {X86::BLSMSK64rr, {0, Unknown}}, + {X86::BLSR32rm, {4, Unknown}}, + {X86::BLSR32rr, {0, Unknown}}, + {X86::BLSR64rm, {8, Unknown}}, + {X86::BLSR64rr, {0, Unknown}}, + {X86::BNDCL32rm, {4, Unknown}}, + {X86::BNDCL32rr, {0, Unknown}}, + {X86::BNDCL64rm, {8, Unknown}}, + {X86::BNDCL64rr, {0, Unknown}}, + {X86::BNDCN32rm, {4, Unknown}}, + {X86::BNDCN32rr, {0, Unknown}}, + {X86::BNDCN64rm, {8, Unknown}}, + {X86::BNDCN64rr, {0, Unknown}}, + {X86::BNDCU32rm, {4, Unknown}}, + {X86::BNDCU32rr, {0, Unknown}}, + {X86::BNDCU64rm, {8, Unknown}}, + {X86::BNDCU64rr, {0, Unknown}}, + {X86::BNDLDXrm, {0, Unknown}}, + {X86::BNDMK32rm, {4, Unknown}}, + {X86::BNDMK64rm, {8, Unknown}}, + {X86::BNDMOV32mr, {4, Unknown}}, + {X86::BNDMOV64mr, {8, Unknown}}, + {X86::BNDMOVrr, {0, Unknown}}, + {X86::BNDMOV32rm, {4, Unknown}}, + {X86::BNDMOV64rm, {8, Unknown}}, + {X86::BNDMOVrr_REV, {0, Unknown}}, + {X86::BNDSTXmr, {0, Unknown}}, + {X86::BOUNDS16rm, {2, Unknown}}, + {X86::BOUNDS32rm, {4, Unknown}}, + {X86::BSF16rm, {2, Unknown}}, + {X86::BSF16rr, {0, Unknown}}, + {X86::BSF32rm, {4, Unknown}}, + {X86::BSF32rr, {0, Unknown}}, + {X86::BSF64rm, {8, Unknown}}, + {X86::BSF64rr, {0, Unknown}}, + {X86::BSR16rm, {2, Unknown}}, + {X86::BSR16rr, {0, Unknown}}, + {X86::BSR32rm, {4, Unknown}}, + {X86::BSR32rr, {0, Unknown}}, + {X86::BSR64rm, {8, Unknown}}, + {X86::BSR64rr, {0, Unknown}}, + {X86::BSWAP32r, {0, Unknown}}, + {X86::BSWAP64r, {0, Unknown}}, + {X86::BT16mi8, {2, Unknown}}, + {X86::BT16mr, {2, Unknown}}, + {X86::BT16ri8, {0, Unknown}}, + {X86::BT16rr, {0, Unknown}}, + {X86::BT32mi8, {4, Unknown}}, + {X86::BT32mr, {4, Unknown}}, + {X86::BT32ri8, {0, Unknown}}, + {X86::BT32rr, {0, Unknown}}, + {X86::BT64mi8, {8, Unknown}}, + {X86::BT64mr, {8, Unknown}}, + {X86::BT64ri8, {0, Unknown}}, + {X86::BT64rr, {0, Unknown}}, + {X86::BTC16mi8, {2, Unknown}}, + {X86::BTC16mr, {2, Unknown}}, + {X86::BTC16ri8, {0, Unknown}}, + {X86::BTC16rr, {0, Unknown}}, + {X86::BTC32mi8, {4, Unknown}}, + {X86::BTC32mr, {4, Unknown}}, + {X86::BTC32ri8, {0, Unknown}}, + {X86::BTC32rr, {0, Unknown}}, + {X86::BTC64mi8, {8, Unknown}}, + {X86::BTC64mr, {8, Unknown}}, + {X86::BTC64ri8, {0, Unknown}}, + {X86::BTC64rr, {0, Unknown}}, + {X86::BTR16mi8, {2, Unknown}}, + {X86::BTR16mr, {2, Unknown}}, + {X86::BTR16ri8, {0, Unknown}}, + {X86::BTR16rr, {0, Unknown}}, + {X86::BTR32mi8, {4, Unknown}}, + {X86::BTR32mr, {4, Unknown}}, + {X86::BTR32ri8, {0, Unknown}}, + {X86::BTR32rr, {0, Unknown}}, + {X86::BTR64mi8, {8, Unknown}}, + {X86::BTR64mr, {8, Unknown}}, + {X86::BTR64ri8, {0, Unknown}}, + {X86::BTR64rr, {0, Unknown}}, + {X86::BTS16mi8, {2, Unknown}}, + {X86::BTS16mr, {2, Unknown}}, + {X86::BTS16ri8, {0, Unknown}}, + {X86::BTS16rr, {0, Unknown}}, + {X86::BTS32mi8, {4, Unknown}}, + {X86::BTS32mr, {4, Unknown}}, + {X86::BTS32ri8, {0, Unknown}}, + {X86::BTS32rr, {0, Unknown}}, + {X86::BTS64mi8, {8, Unknown}}, + {X86::BTS64mr, {8, Unknown}}, + {X86::BTS64ri8, {0, Unknown}}, + {X86::BTS64rr, {0, Unknown}}, + {X86::BUNDLE, {0, Unknown}}, + {X86::BZHI32rm, {4, Unknown}}, + {X86::BZHI32rr, {0, Unknown}}, + {X86::BZHI64rm, {8, Unknown}}, + {X86::BZHI64rr, {0, Unknown}}, + {X86::CALL16m, {0, Unknown}}, + {X86::CALL16m_NT, {0, Unknown}}, + {X86::CALL16r, {0, Unknown}}, + {X86::CALL16r_NT, {0, Unknown}}, + {X86::CALL32m, {0, Unknown}}, + {X86::CALL32m_NT, {0, Unknown}}, + {X86::CALL32r, {0, Unknown}}, + {X86::CALL32r_NT, {0, Unknown}}, + {X86::CALL64m, {0, Unknown}}, + {X86::CALL64m_NT, {0, Unknown}}, + {X86::CALL64pcrel32, {0, Unknown}}, + {X86::CALL64r, {0, Unknown}}, + {X86::CALL64r_NT, {0, Unknown}}, + {X86::CALLpcrel16, {0, Unknown}}, + {X86::CALLpcrel32, {0, Unknown}}, + {X86::CATCHPAD, {0, Unknown}}, + {X86::CATCHRET, {0, Unknown}}, + {X86::CBW, {0, CONVERT_BWWDDQ}}, + {X86::CDQ, {0, CONVERT_WDDQQO}}, + {X86::CDQE, {0, CONVERT_BWWDDQ}}, + {X86::CFI_INSTRUCTION, {0, Unknown}}, + {X86::CHS_F, {0, Unknown}}, + {X86::CHS_Fp32, {0, Unknown}}, + {X86::CHS_Fp64, {0, Unknown}}, + {X86::CHS_Fp80, {0, Unknown}}, + {X86::CLAC, {0, Unknown}}, + {X86::CLC, {0, Unknown}}, + {X86::CLD, {0, Unknown}}, + {X86::CLEANUPRET, {0, Unknown}}, + {X86::CLFLUSH, {0, Unknown}}, + {X86::CLFLUSHOPT, {0, Unknown}}, + {X86::CLGI, {0, Unknown}}, + {X86::CLI, {0, Unknown}}, + {X86::CLRSSBSY, {0, Unknown}}, + {X86::CLTS, {0, Unknown}}, + {X86::CLWB, {0, Unknown}}, + {X86::CLZERO, {0, Unknown}}, + {X86::CLZEROr, {0, Unknown}}, + {X86::CMC, {0, Unknown}}, + {X86::CMOVA16rm, {2, Unknown}}, + {X86::CMOVA16rr, {0, Unknown}}, + {X86::CMOVA32rm, {4, Unknown}}, + {X86::CMOVA32rr, {0, Unknown}}, + {X86::CMOVA64rm, {8, Unknown}}, + {X86::CMOVA64rr, {0, Unknown}}, + {X86::CMOVAE16rm, {2, Unknown}}, + {X86::CMOVAE16rr, {0, Unknown}}, + {X86::CMOVAE32rm, {4, Unknown}}, + {X86::CMOVAE32rr, {0, Unknown}}, + {X86::CMOVAE64rm, {8, Unknown}}, + {X86::CMOVAE64rr, {0, Unknown}}, + {X86::CMOVB16rm, {2, Unknown}}, + {X86::CMOVB16rr, {0, Unknown}}, + {X86::CMOVB32rm, {4, Unknown}}, + {X86::CMOVB32rr, {0, Unknown}}, + {X86::CMOVB64rm, {8, Unknown}}, + {X86::CMOVB64rr, {0, Unknown}}, + {X86::CMOVBE16rm, {2, Unknown}}, + {X86::CMOVBE16rr, {0, Unknown}}, + {X86::CMOVBE32rm, {4, Unknown}}, + {X86::CMOVBE32rr, {0, Unknown}}, + {X86::CMOVBE64rm, {8, Unknown}}, + {X86::CMOVBE64rr, {0, Unknown}}, + {X86::CMOVBE_F, {0, Unknown}}, + {X86::CMOVBE_Fp32, {0, Unknown}}, + {X86::CMOVBE_Fp64, {0, Unknown}}, + {X86::CMOVBE_Fp80, {0, Unknown}}, + {X86::CMOVB_F, {0, Unknown}}, + {X86::CMOVB_Fp32, {0, Unknown}}, + {X86::CMOVB_Fp64, {0, Unknown}}, + {X86::CMOVB_Fp80, {0, Unknown}}, + {X86::CMOVE16rm, {2, Unknown}}, + {X86::CMOVE16rr, {0, Unknown}}, + {X86::CMOVE32rm, {4, Unknown}}, + {X86::CMOVE32rr, {0, Unknown}}, + {X86::CMOVE64rm, {8, Unknown}}, + {X86::CMOVE64rr, {0, Unknown}}, + {X86::CMOVE_F, {0, Unknown}}, + {X86::CMOVE_Fp32, {0, Unknown}}, + {X86::CMOVE_Fp64, {0, Unknown}}, + {X86::CMOVE_Fp80, {0, Unknown}}, + {X86::CMOVG16rm, {2, Unknown}}, + {X86::CMOVG16rr, {0, Unknown}}, + {X86::CMOVG32rm, {4, Unknown}}, + {X86::CMOVG32rr, {0, Unknown}}, + {X86::CMOVG64rm, {8, Unknown}}, + {X86::CMOVG64rr, {0, Unknown}}, + {X86::CMOVGE16rm, {2, Unknown}}, + {X86::CMOVGE16rr, {0, Unknown}}, + {X86::CMOVGE32rm, {4, Unknown}}, + {X86::CMOVGE32rr, {0, Unknown}}, + {X86::CMOVGE64rm, {8, Unknown}}, + {X86::CMOVGE64rr, {0, Unknown}}, + {X86::CMOVL16rm, {2, Unknown}}, + {X86::CMOVL16rr, {0, Unknown}}, + {X86::CMOVL32rm, {4, Unknown}}, + {X86::CMOVL32rr, {0, Unknown}}, + {X86::CMOVL64rm, {8, Unknown}}, + {X86::CMOVL64rr, {0, Unknown}}, + {X86::CMOVLE16rm, {2, Unknown}}, + {X86::CMOVLE16rr, {0, Unknown}}, + {X86::CMOVLE32rm, {4, Unknown}}, + {X86::CMOVLE32rr, {0, Unknown}}, + {X86::CMOVLE64rm, {8, Unknown}}, + {X86::CMOVLE64rr, {0, Unknown}}, + {X86::CMOVNBE_F, {0, Unknown}}, + {X86::CMOVNBE_Fp32, {0, Unknown}}, + {X86::CMOVNBE_Fp64, {0, Unknown}}, + {X86::CMOVNBE_Fp80, {0, Unknown}}, + {X86::CMOVNB_F, {0, Unknown}}, + {X86::CMOVNB_Fp32, {0, Unknown}}, + {X86::CMOVNB_Fp64, {0, Unknown}}, + {X86::CMOVNB_Fp80, {0, Unknown}}, + {X86::CMOVNE16rm, {2, Unknown}}, + {X86::CMOVNE16rr, {0, Unknown}}, + {X86::CMOVNE32rm, {4, Unknown}}, + {X86::CMOVNE32rr, {0, Unknown}}, + {X86::CMOVNE64rm, {8, Unknown}}, + {X86::CMOVNE64rr, {0, Unknown}}, + {X86::CMOVNE_F, {0, Unknown}}, + {X86::CMOVNE_Fp32, {0, Unknown}}, + {X86::CMOVNE_Fp64, {0, Unknown}}, + {X86::CMOVNE_Fp80, {0, Unknown}}, + {X86::CMOVNO16rm, {2, Unknown}}, + {X86::CMOVNO16rr, {0, Unknown}}, + {X86::CMOVNO32rm, {4, Unknown}}, + {X86::CMOVNO32rr, {0, Unknown}}, + {X86::CMOVNO64rm, {8, Unknown}}, + {X86::CMOVNO64rr, {0, Unknown}}, + {X86::CMOVNP16rm, {2, Unknown}}, + {X86::CMOVNP16rr, {0, Unknown}}, + {X86::CMOVNP32rm, {4, Unknown}}, + {X86::CMOVNP32rr, {0, Unknown}}, + {X86::CMOVNP64rm, {8, Unknown}}, + {X86::CMOVNP64rr, {0, Unknown}}, + {X86::CMOVNP_F, {0, Unknown}}, + {X86::CMOVNP_Fp32, {0, Unknown}}, + {X86::CMOVNP_Fp64, {0, Unknown}}, + {X86::CMOVNP_Fp80, {0, Unknown}}, + {X86::CMOVNS16rm, {2, Unknown}}, + {X86::CMOVNS16rr, {0, Unknown}}, + {X86::CMOVNS32rm, {4, Unknown}}, + {X86::CMOVNS32rr, {0, Unknown}}, + {X86::CMOVNS64rm, {8, Unknown}}, + {X86::CMOVNS64rr, {0, Unknown}}, + {X86::CMOVO16rm, {2, Unknown}}, + {X86::CMOVO16rr, {0, Unknown}}, + {X86::CMOVO32rm, {4, Unknown}}, + {X86::CMOVO32rr, {0, Unknown}}, + {X86::CMOVO64rm, {8, Unknown}}, + {X86::CMOVO64rr, {0, Unknown}}, + {X86::CMOVP16rm, {2, Unknown}}, + {X86::CMOVP16rr, {0, Unknown}}, + {X86::CMOVP32rm, {4, Unknown}}, + {X86::CMOVP32rr, {0, Unknown}}, + {X86::CMOVP64rm, {8, Unknown}}, + {X86::CMOVP64rr, {0, Unknown}}, + {X86::CMOVP_F, {0, Unknown}}, + {X86::CMOVP_Fp32, {0, Unknown}}, + {X86::CMOVP_Fp64, {0, Unknown}}, + {X86::CMOVP_Fp80, {0, Unknown}}, + {X86::CMOVS16rm, {2, Unknown}}, + {X86::CMOVS16rr, {0, Unknown}}, + {X86::CMOVS32rm, {4, Unknown}}, + {X86::CMOVS32rr, {0, Unknown}}, + {X86::CMOVS64rm, {8, Unknown}}, + {X86::CMOVS64rr, {0, Unknown}}, + {X86::CMOV_F128, {0, Unknown}}, + {X86::CMOV_FR32, {0, Unknown}}, + {X86::CMOV_FR64, {0, Unknown}}, + {X86::CMOV_GR16, {0, Unknown}}, + {X86::CMOV_GR32, {0, Unknown}}, + {X86::CMOV_GR8, {0, Unknown}}, + {X86::CMOV_RFP32, {0, Unknown}}, + {X86::CMOV_RFP64, {0, Unknown}}, + {X86::CMOV_RFP80, {0, Unknown}}, + {X86::CMOV_V16F32, {0, Unknown}}, + {X86::CMOV_V16I1, {0, Unknown}}, + {X86::CMOV_V2F64, {0, Unknown}}, + {X86::CMOV_V2I64, {0, Unknown}}, + {X86::CMOV_V32I1, {0, Unknown}}, + {X86::CMOV_V4F32, {0, Unknown}}, + {X86::CMOV_V4F64, {0, Unknown}}, + {X86::CMOV_V4I64, {0, Unknown}}, + {X86::CMOV_V64I1, {0, Unknown}}, + {X86::CMOV_V8F32, {0, Unknown}}, + {X86::CMOV_V8F64, {0, Unknown}}, + {X86::CMOV_V8I1, {0, Unknown}}, + {X86::CMOV_V8I64, {0, Unknown}}, + {X86::CMP16i16, {0, Unknown}}, + {X86::CMP16mi, {2, Unknown}}, + {X86::CMP16mi8, {2, Unknown}}, + {X86::CMP16mr, {2, Unknown}}, + {X86::CMP16ri, {0, Unknown}}, + {X86::CMP16ri8, {0, Unknown}}, + {X86::CMP16rm, {2, Unknown}}, + {X86::CMP16rr, {0, Unknown}}, + {X86::CMP16rr_REV, {0, Unknown}}, + {X86::CMP32i32, {0, Unknown}}, + {X86::CMP32mi, {4, Unknown}}, + {X86::CMP32mi8, {4, Unknown}}, + {X86::CMP32mr, {4, Unknown}}, + {X86::CMP32ri, {0, Unknown}}, + {X86::CMP32ri8, {0, COMPARE}}, + {X86::CMP32rm, {4, Unknown}}, + {X86::CMP32rr, {0, COMPARE}}, + {X86::CMP32rr_REV, {0, Unknown}}, + {X86::CMP64i32, {0, Unknown}}, + {X86::CMP64mi32, {8, Unknown}}, + {X86::CMP64mi8, {8, Unknown}}, + {X86::CMP64mr, {8, Unknown}}, + {X86::CMP64ri32, {0, Unknown}}, + {X86::CMP64ri8, {0, Unknown}}, + {X86::CMP64rm, {8, Unknown}}, + {X86::CMP64rr, {0, Unknown}}, + {X86::CMP64rr_REV, {0, Unknown}}, + {X86::CMP8i8, {0, Unknown}}, + {X86::CMP8mi, {1, Unknown}}, + {X86::CMP8mi8, {1, Unknown}}, + {X86::CMP8mr, {1, Unknown}}, + {X86::CMP8ri, {0, Unknown}}, + {X86::CMP8ri8, {0, Unknown}}, + {X86::CMP8rm, {1, Unknown}}, + {X86::CMP8rr, {0, Unknown}}, + {X86::CMP8rr_REV, {0, Unknown}}, + {X86::CMPPDrmi, {0, Unknown}}, + {X86::CMPPDrmi_alt, {0, Unknown}}, + {X86::CMPPDrri, {0, Unknown}}, + {X86::CMPPDrri_alt, {0, Unknown}}, + {X86::CMPPSrmi, {0, Unknown}}, + {X86::CMPPSrmi_alt, {0, Unknown}}, + {X86::CMPPSrri, {0, Unknown}}, + {X86::CMPPSrri_alt, {0, Unknown}}, + {X86::CMPSB, {0, Unknown}}, + {X86::CMPSDrm, {0, Unknown}}, + {X86::CMPSDrm_Int, {0, Unknown}}, + {X86::CMPSDrm_alt, {0, Unknown}}, + {X86::CMPSDrr, {0, Unknown}}, + {X86::CMPSDrr_Int, {0, Unknown}}, + {X86::CMPSDrr_alt, {0, Unknown}}, + {X86::CMPSL, {0, Unknown}}, + {X86::CMPSQ, {0, Unknown}}, + {X86::CMPSSrm, {0, Unknown}}, + {X86::CMPSSrm_Int, {0, Unknown}}, + {X86::CMPSSrm_alt, {0, Unknown}}, + {X86::CMPSSrr, {0, Unknown}}, + {X86::CMPSSrr_Int, {0, Unknown}}, + {X86::CMPSSrr_alt, {0, Unknown}}, + {X86::CMPSW, {0, Unknown}}, + {X86::CMPXCHG16B, {0, Unknown}}, + {X86::CMPXCHG16rm, {2, Unknown}}, + {X86::CMPXCHG16rr, {0, Unknown}}, + {X86::CMPXCHG32rm, {4, Unknown}}, + {X86::CMPXCHG32rr, {0, Unknown}}, + {X86::CMPXCHG64rm, {8, Unknown}}, + {X86::CMPXCHG64rr, {0, Unknown}}, + {X86::CMPXCHG8B, {0, Unknown}}, + {X86::CMPXCHG8rm, {1, Unknown}}, + {X86::CMPXCHG8rr, {0, Unknown}}, + {X86::COMISDrm, {0, Unknown}}, + {X86::COMISDrm_Int, {0, Unknown}}, + {X86::COMISDrr, {0, Unknown}}, + {X86::COMISDrr_Int, {0, Unknown}}, + {X86::COMISSrm, {0, Unknown}}, + {X86::COMISSrm_Int, {0, Unknown}}, + {X86::COMISSrr, {0, Unknown}}, + {X86::COMISSrr_Int, {0, Unknown}}, + {X86::COMP_FST0r, {0, Unknown}}, + {X86::COM_FIPr, {0, Unknown}}, + {X86::COM_FIr, {0, Unknown}}, + {X86::COM_FST0r, {0, Unknown}}, + {X86::COPY, {0, Unknown}}, + {X86::COPY_TO_REGCLASS, {0, Unknown}}, + {X86::COS_F, {0, Unknown}}, + {X86::COS_Fp32, {0, Unknown}}, + {X86::COS_Fp64, {0, Unknown}}, + {X86::COS_Fp80, {0, Unknown}}, + {X86::CPUID, {0, Unknown}}, + {X86::CQO, {0, CONVERT_WDDQQO}}, + {X86::CRC32r32m16, {0, Unknown}}, + {X86::CRC32r32m32, {0, Unknown}}, + {X86::CRC32r32m8, {0, Unknown}}, + {X86::CRC32r32r16, {0, Unknown}}, + {X86::CRC32r32r32, {0, Unknown}}, + {X86::CRC32r32r8, {0, Unknown}}, + {X86::CRC32r64m64, {0, Unknown}}, + {X86::CRC32r64m8, {0, Unknown}}, + {X86::CRC32r64r64, {0, Unknown}}, + {X86::CRC32r64r8, {0, Unknown}}, + {X86::CS_PREFIX, {0, Unknown}}, + {X86::CVTDQ2PDrm, {0, Unknown}}, + {X86::CVTDQ2PDrr, {0, Unknown}}, + {X86::CVTDQ2PSrm, {0, Unknown}}, + {X86::CVTDQ2PSrr, {0, Unknown}}, + {X86::CVTPD2DQrm, {0, Unknown}}, + {X86::CVTPD2DQrr, {0, Unknown}}, + {X86::CVTPD2PSrm, {0, Unknown}}, + {X86::CVTPD2PSrr, {0, Unknown}}, + {X86::CVTPS2DQrm, {0, Unknown}}, + {X86::CVTPS2DQrr, {0, Unknown}}, + {X86::CVTPS2PDrm, {0, Unknown}}, + {X86::CVTPS2PDrr, {0, Unknown}}, + {X86::CVTSD2SI64rm_Int, {8, Unknown}}, + {X86::CVTSD2SI64rr_Int, {0, Unknown}}, + {X86::CVTSD2SIrm_Int, {0, Unknown}}, + {X86::CVTSD2SIrr_Int, {0, Unknown}}, + {X86::CVTSD2SSrm, {0, Unknown}}, + {X86::CVTSD2SSrm_Int, {0, Unknown}}, + {X86::CVTSD2SSrr, {0, Unknown}}, + {X86::CVTSD2SSrr_Int, {0, Unknown}}, + {X86::CVTSI2SDrm, {0, Unknown}}, + {X86::CVTSI2SDrm_Int, {0, Unknown}}, + {X86::CVTSI2SDrr, {0, Unknown}}, + {X86::CVTSI2SDrr_Int, {0, Unknown}}, + {X86::CVTSI2SSrm, {0, Unknown}}, + {X86::CVTSI2SSrm_Int, {0, Unknown}}, + {X86::CVTSI2SSrr, {0, Unknown}}, + {X86::CVTSI2SSrr_Int, {0, Unknown}}, + {X86::CVTSI642SDrm, {0, Unknown}}, + {X86::CVTSI642SDrm_Int, {0, Unknown}}, + {X86::CVTSI642SDrr, {0, Unknown}}, + {X86::CVTSI642SDrr_Int, {0, Unknown}}, + {X86::CVTSI642SSrm, {0, Unknown}}, + {X86::CVTSI642SSrm_Int, {0, Unknown}}, + {X86::CVTSI642SSrr, {0, Unknown}}, + {X86::CVTSI642SSrr_Int, {0, Unknown}}, + {X86::CVTSS2SDrm, {0, Unknown}}, + {X86::CVTSS2SDrm_Int, {0, Unknown}}, + {X86::CVTSS2SDrr, {0, Unknown}}, + {X86::CVTSS2SDrr_Int, {0, Unknown}}, + {X86::CVTSS2SI64rm_Int, {8, Unknown}}, + {X86::CVTSS2SI64rr_Int, {0, Unknown}}, + {X86::CVTSS2SIrm_Int, {0, Unknown}}, + {X86::CVTSS2SIrr_Int, {0, Unknown}}, + {X86::CVTTPD2DQrm, {0, Unknown}}, + {X86::CVTTPD2DQrr, {0, Unknown}}, + {X86::CVTTPS2DQrm, {0, Unknown}}, + {X86::CVTTPS2DQrr, {0, Unknown}}, + {X86::CVTTSD2SI64rm, {8, Unknown}}, + {X86::CVTTSD2SI64rm_Int, {8, Unknown}}, + {X86::CVTTSD2SI64rr, {0, Unknown}}, + {X86::CVTTSD2SI64rr_Int, {0, Unknown}}, + {X86::CVTTSD2SIrm, {0, Unknown}}, + {X86::CVTTSD2SIrm_Int, {0, Unknown}}, + {X86::CVTTSD2SIrr, {0, Unknown}}, + {X86::CVTTSD2SIrr_Int, {0, Unknown}}, + {X86::CVTTSS2SI64rm, {8, Unknown}}, + {X86::CVTTSS2SI64rm_Int, {8, Unknown}}, + {X86::CVTTSS2SI64rr, {0, Unknown}}, + {X86::CVTTSS2SI64rr_Int, {0, Unknown}}, + {X86::CVTTSS2SIrm, {0, Unknown}}, + {X86::CVTTSS2SIrm_Int, {0, Unknown}}, + {X86::CVTTSS2SIrr, {0, Unknown}}, + {X86::CVTTSS2SIrr_Int, {0, Unknown}}, + {X86::CWD, {0, CONVERT_WDDQQO}}, + {X86::CWDE, {0, CONVERT_BWWDDQ}}, + {X86::DAA, {0, Unknown}}, + {X86::DAS, {0, Unknown}}, + {X86::DATA16_PREFIX, {0, Unknown}}, + {X86::DBG_VALUE, {0, Unknown}}, + {X86::DEC16m, {0, Unknown}}, + {X86::DEC16r, {0, Unknown}}, + {X86::DEC16r_alt, {0, Unknown}}, + {X86::DEC32m, {0, Unknown}}, + {X86::DEC32r, {0, Unknown}}, + {X86::DEC32r_alt, {0, Unknown}}, + {X86::DEC64m, {0, Unknown}}, + {X86::DEC64r, {0, Unknown}}, + {X86::DEC8m, {0, Unknown}}, + {X86::DEC8r, {0, Unknown}}, + {X86::DIV16m, {0, Unknown}}, + {X86::DIV16r, {0, Unknown}}, + {X86::DIV32m, {0, Unknown}}, + {X86::DIV32r, {0, Unknown}}, + {X86::DIV64m, {0, Unknown}}, + {X86::DIV64r, {0, Unknown}}, + {X86::DIV8m, {0, Unknown}}, + {X86::DIV8r, {0, Unknown}}, + {X86::DIVPDrm, {0, Unknown}}, + {X86::DIVPDrr, {0, Unknown}}, + {X86::DIVPSrm, {0, Unknown}}, + {X86::DIVPSrr, {0, Unknown}}, + {X86::DIVR_F32m, {0, Unknown}}, + {X86::DIVR_F64m, {0, Unknown}}, + {X86::DIVR_FI16m, {0, Unknown}}, + {X86::DIVR_FI32m, {0, Unknown}}, + {X86::DIVR_FPrST0, {0, FPU_REG_OP}}, + {X86::DIVR_FST0r, {0, Unknown}}, + {X86::DIVR_Fp32m, {0, Unknown}}, + {X86::DIVR_Fp64m, {0, Unknown}}, + {X86::DIVR_Fp64m32, {0, Unknown}}, + {X86::DIVR_Fp80m32, {0, Unknown}}, + {X86::DIVR_Fp80m64, {0, Unknown}}, + {X86::DIVR_FpI16m32, {0, Unknown}}, + {X86::DIVR_FpI16m64, {0, Unknown}}, + {X86::DIVR_FpI16m80, {0, Unknown}}, + {X86::DIVR_FpI32m32, {0, Unknown}}, + {X86::DIVR_FpI32m64, {0, Unknown}}, + {X86::DIVR_FpI32m80, {0, Unknown}}, + {X86::DIVR_FrST0, {0, Unknown}}, + {X86::DIVSDrm, {0, Unknown}}, + {X86::DIVSDrm_Int, {0, Unknown}}, + {X86::DIVSDrr, {0, Unknown}}, + {X86::DIVSDrr_Int, {0, Unknown}}, + {X86::DIVSSrm, {0, Unknown}}, + {X86::DIVSSrm_Int, {0, Unknown}}, + {X86::DIVSSrr, {0, Unknown}}, + {X86::DIVSSrr_Int, {0, Unknown}}, + {X86::DIV_F32m, {0, Unknown}}, + {X86::DIV_F64m, {0, Unknown}}, + {X86::DIV_FI16m, {0, Unknown}}, + {X86::DIV_FI32m, {0, Unknown}}, + {X86::DIV_FPrST0, {0, FPU_REG_OP}}, + {X86::DIV_FST0r, {0, Unknown}}, + {X86::DIV_Fp32, {0, Unknown}}, + {X86::DIV_Fp32m, {0, Unknown}}, + {X86::DIV_Fp64, {0, Unknown}}, + {X86::DIV_Fp64m, {0, Unknown}}, + {X86::DIV_Fp64m32, {0, Unknown}}, + {X86::DIV_Fp80, {0, Unknown}}, + {X86::DIV_Fp80m32, {0, Unknown}}, + {X86::DIV_Fp80m64, {0, Unknown}}, + {X86::DIV_FpI16m32, {0, Unknown}}, + {X86::DIV_FpI16m64, {0, Unknown}}, + {X86::DIV_FpI16m80, {0, Unknown}}, + {X86::DIV_FpI32m32, {0, Unknown}}, + {X86::DIV_FpI32m64, {0, Unknown}}, + {X86::DIV_FpI32m80, {0, Unknown}}, + {X86::DIV_FrST0, {0, Unknown}}, + {X86::DPPDrmi, {0, Unknown}}, + {X86::DPPDrri, {0, Unknown}}, + {X86::DPPSrmi, {0, Unknown}}, + {X86::DPPSrri, {0, Unknown}}, + {X86::DS_PREFIX, {0, Unknown}}, + {X86::EH_LABEL, {0, Unknown}}, + {X86::EH_RESTORE, {0, Unknown}}, + {X86::EH_RETURN, {0, Unknown}}, + {X86::EH_RETURN64, {0, Unknown}}, + {X86::EH_SjLj_LongJmp32, {0, Unknown}}, + {X86::EH_SjLj_LongJmp64, {0, Unknown}}, + {X86::EH_SjLj_SetJmp32, {0, Unknown}}, + {X86::EH_SjLj_SetJmp64, {0, Unknown}}, + {X86::EH_SjLj_Setup, {0, Unknown}}, + {X86::ENCLS, {0, Unknown}}, + {X86::ENCLU, {0, Unknown}}, + {X86::ENDBR32, {0, Unknown}}, + {X86::ENDBR64, {0, Unknown}}, + {X86::ENTER, {0, Unknown}}, + {X86::ES_PREFIX, {0, Unknown}}, + {X86::EXTRACTPSmr, {0, Unknown}}, + {X86::EXTRACTPSrr, {0, Unknown}}, + {X86::EXTRACT_SUBREG, {0, Unknown}}, + {X86::EXTRQ, {0, Unknown}}, + {X86::EXTRQI, {0, Unknown}}, + {X86::F2XM1, {0, Unknown}}, + {X86::FARCALL16i, {0, Unknown}}, + {X86::FARCALL16m, {0, Unknown}}, + {X86::FARCALL32i, {0, Unknown}}, + {X86::FARCALL32m, {0, Unknown}}, + {X86::FARCALL64, {0, Unknown}}, + {X86::FARJMP16i, {0, Unknown}}, + {X86::FARJMP16m, {0, Unknown}}, + {X86::FARJMP32i, {0, Unknown}}, + {X86::FARJMP32m, {0, Unknown}}, + {X86::FARJMP64, {0, Unknown}}, + {X86::FAULTING_OP, {0, Unknown}}, + {X86::FBLDm, {0, Unknown}}, + {X86::FBSTPm, {0, Unknown}}, + {X86::FCOM32m, {0, Unknown}}, + {X86::FCOM64m, {0, Unknown}}, + {X86::FCOMP32m, {0, Unknown}}, + {X86::FCOMP64m, {0, Unknown}}, + {X86::FCOMPP, {0, Unknown}}, + {X86::FDECSTP, {0, Unknown}}, + {X86::FEMMS, {0, Unknown}}, + {X86::FENTRY_CALL, {0, Unknown}}, + {X86::FFREE, {0, Unknown}}, + {X86::FFREEP, {0, Unknown}}, + {X86::FICOM16m, {0, Unknown}}, + {X86::FICOM32m, {0, Unknown}}, + {X86::FICOMP16m, {0, Unknown}}, + {X86::FICOMP32m, {0, Unknown}}, + {X86::FINCSTP, {0, Unknown}}, + {X86::FLDCW16m, {0, Unknown}}, + {X86::FLDENVm, {0, Unknown}}, + {X86::FLDL2E, {0, Unknown}}, + {X86::FLDL2T, {0, Unknown}}, + {X86::FLDLG2, {0, Unknown}}, + {X86::FLDLN2, {0, Unknown}}, + {X86::FLDPI, {0, Unknown}}, + {X86::FNCLEX, {0, Unknown}}, + {X86::FNINIT, {0, Unknown}}, + {X86::FNOP, {0, Unknown}}, + {X86::FNSTCW16m, {0, Unknown}}, + {X86::FNSTSW16r, {0, Unknown}}, + {X86::FNSTSWm, {0, Unknown}}, + {X86::FP32_TO_INT16_IN_MEM, {0, Unknown}}, + {X86::FP32_TO_INT32_IN_MEM, {0, Unknown}}, + {X86::FP32_TO_INT64_IN_MEM, {0, Unknown}}, + {X86::FP64_TO_INT16_IN_MEM, {0, Unknown}}, + {X86::FP64_TO_INT32_IN_MEM, {0, Unknown}}, + {X86::FP64_TO_INT64_IN_MEM, {0, Unknown}}, + {X86::FP80_TO_INT16_IN_MEM, {0, Unknown}}, + {X86::FP80_TO_INT32_IN_MEM, {0, Unknown}}, + {X86::FP80_TO_INT64_IN_MEM, {0, Unknown}}, + {X86::FPATAN, {0, Unknown}}, + {X86::FPREM, {0, Unknown}}, + {X86::FPREM1, {0, Unknown}}, + {X86::FPTAN, {0, Unknown}}, + {X86::FRNDINT, {0, Unknown}}, + {X86::FRSTORm, {0, Unknown}}, + {X86::FSAVEm, {0, Unknown}}, + {X86::FSCALE, {0, Unknown}}, + {X86::FSINCOS, {0, Unknown}}, + {X86::FSTENVm, {0, Unknown}}, + {X86::FS_PREFIX, {0, Unknown}}, + {X86::FXAM, {0, Unknown}}, + {X86::FXRSTOR, {0, Unknown}}, + {X86::FXRSTOR64, {0, Unknown}}, + {X86::FXSAVE, {0, Unknown}}, + {X86::FXSAVE64, {0, Unknown}}, + {X86::FXTRACT, {0, Unknown}}, + {X86::FYL2X, {0, Unknown}}, + {X86::FYL2XP1, {0, Unknown}}, + {X86::FsFLD0SD, {0, Unknown}}, + {X86::FsFLD0SS, {0, Unknown}}, + {X86::GC_LABEL, {0, Unknown}}, + {X86::GETSEC, {0, Unknown}}, + {X86::GF2P8AFFINEINVQBrmi, {0, Unknown}}, + {X86::GF2P8AFFINEINVQBrri, {0, Unknown}}, + {X86::GF2P8AFFINEQBrmi, {0, Unknown}}, + {X86::GF2P8AFFINEQBrri, {0, Unknown}}, + {X86::GF2P8MULBrm, {0, Unknown}}, + {X86::GF2P8MULBrr, {0, Unknown}}, + {X86::GS_PREFIX, {0, Unknown}}, + {X86::G_ADD, {0, Unknown}}, + {X86::G_AND, {0, Unknown}}, + {X86::G_ANYEXT, {0, Unknown}}, + {X86::G_ASHR, {0, Unknown}}, + {X86::G_ATOMICRMW_ADD, {0, Unknown}}, + {X86::G_ATOMICRMW_AND, {0, Unknown}}, + {X86::G_ATOMICRMW_MAX, {0, Unknown}}, + {X86::G_ATOMICRMW_MIN, {0, Unknown}}, + {X86::G_ATOMICRMW_NAND, {0, Unknown}}, + {X86::G_ATOMICRMW_OR, {0, Unknown}}, + {X86::G_ATOMICRMW_SUB, {0, Unknown}}, + {X86::G_ATOMICRMW_UMAX, {0, Unknown}}, + {X86::G_ATOMICRMW_UMIN, {0, Unknown}}, + {X86::G_ATOMICRMW_XCHG, {0, Unknown}}, + {X86::G_ATOMICRMW_XOR, {0, Unknown}}, + {X86::G_ATOMIC_CMPXCHG, {0, Unknown}}, + {X86::G_ATOMIC_CMPXCHG_WITH_SUCCESS, {0, Unknown}}, + {X86::G_BITCAST, {0, Unknown}}, + {X86::G_BR, {0, Unknown}}, + {X86::G_BRCOND, {0, Unknown}}, + {X86::G_BRINDIRECT, {0, Unknown}}, + {X86::G_BSWAP, {0, Unknown}}, + {X86::G_CONSTANT, {0, Unknown}}, + {X86::G_EXTRACT, {0, Unknown}}, + {X86::G_EXTRACT_VECTOR_ELT, {0, Unknown}}, + {X86::G_FABS, {0, Unknown}}, + {X86::G_FADD, {0, Unknown}}, + {X86::G_FCMP, {0, Unknown}}, + {X86::G_FCONSTANT, {0, Unknown}}, + {X86::G_FDIV, {0, Unknown}}, + {X86::G_FEXP, {0, Unknown}}, + {X86::G_FEXP2, {0, Unknown}}, + {X86::G_FLOG, {0, Unknown}}, + {X86::G_FLOG2, {0, Unknown}}, + {X86::G_FMA, {0, Unknown}}, + {X86::G_FMUL, {0, Unknown}}, + {X86::G_FNEG, {0, Unknown}}, + {X86::G_FPEXT, {0, Unknown}}, + {X86::G_FPOW, {0, Unknown}}, + {X86::G_FPTOSI, {0, Unknown}}, + {X86::G_FPTOUI, {0, Unknown}}, + {X86::G_FPTRUNC, {0, Unknown}}, + {X86::G_FRAME_INDEX, {0, Unknown}}, + {X86::G_FREM, {0, Unknown}}, + {X86::G_FSUB, {0, Unknown}}, + {X86::G_GEP, {0, Unknown}}, + {X86::G_GLOBAL_VALUE, {0, Unknown}}, + {X86::G_ICMP, {0, Unknown}}, + {X86::G_IMPLICIT_DEF, {0, Unknown}}, + {X86::G_INSERT, {0, Unknown}}, + {X86::G_INSERT_VECTOR_ELT, {0, Unknown}}, + {X86::G_INTRINSIC, {0, Unknown}}, + {X86::G_INTRINSIC_W_SIDE_EFFECTS, {0, Unknown}}, + {X86::G_INTTOPTR, {0, Unknown}}, + {X86::G_LOAD, {0, Unknown}}, + {X86::G_LSHR, {0, Unknown}}, + {X86::G_MERGE_VALUES, {0, Unknown}}, + {X86::G_MUL, {0, Unknown}}, + {X86::G_OR, {0, Unknown}}, + {X86::G_PHI, {0, Unknown}}, + {X86::G_PTRTOINT, {0, Unknown}}, + {X86::G_PTR_MASK, {0, Unknown}}, + {X86::G_SADDO, {0, Unknown}}, + {X86::G_SDIV, {0, Unknown}}, + {X86::G_SELECT, {0, Unknown}}, + {X86::G_SEXT, {0, Unknown}}, + {X86::G_SHL, {0, Unknown}}, + {X86::G_SHUFFLE_VECTOR, {0, Unknown}}, + {X86::G_SITOFP, {0, Unknown}}, + {X86::G_SMULH, {0, Unknown}}, + {X86::G_SMULO, {0, Unknown}}, + {X86::G_SREM, {0, Unknown}}, + {X86::G_SSUBO, {0, Unknown}}, + {X86::G_STORE, {0, Unknown}}, + {X86::G_SUB, {0, Unknown}}, + {X86::G_TRUNC, {0, Unknown}}, + {X86::G_UADDE, {0, Unknown}}, + {X86::G_UDIV, {0, Unknown}}, + {X86::G_UITOFP, {0, Unknown}}, + {X86::G_UMULH, {0, Unknown}}, + {X86::G_UMULO, {0, Unknown}}, + {X86::G_UNMERGE_VALUES, {0, Unknown}}, + {X86::G_UREM, {0, Unknown}}, + {X86::G_USUBE, {0, Unknown}}, + {X86::G_VAARG, {0, Unknown}}, + {X86::G_VASTART, {0, Unknown}}, + {X86::G_XOR, {0, Unknown}}, + {X86::G_ZEXT, {0, Unknown}}, + {X86::HADDPDrm, {0, Unknown}}, + {X86::HADDPDrr, {0, Unknown}}, + {X86::HADDPSrm, {0, Unknown}}, + {X86::HADDPSrr, {0, Unknown}}, + {X86::HLT, {0, Unknown}}, + {X86::HSUBPDrm, {0, Unknown}}, + {X86::HSUBPDrr, {0, Unknown}}, + {X86::HSUBPSrm, {0, Unknown}}, + {X86::HSUBPSrr, {0, Unknown}}, + {X86::ICALL_BRANCH_FUNNEL, {0, Unknown}}, + {X86::IDIV16m, {2, DIVIDE_OP}}, + {X86::IDIV16r, {0, Unknown}}, + {X86::IDIV32m, {4, DIVIDE_OP}}, + {X86::IDIV32r, {0, Unknown}}, + {X86::IDIV64m, {8, DIVIDE_OP}}, + {X86::IDIV64r, {0, Unknown}}, + {X86::IDIV8m, {1, DIVIDE_OP}}, + {X86::IDIV8r, {0, Unknown}}, + {X86::ILD_F16m, {0, Unknown}}, + {X86::ILD_F32m, {4, LOAD_FPU_REG}}, + {X86::ILD_F64m, {8, LOAD_FPU_REG}}, + {X86::ILD_Fp16m32, {0, Unknown}}, + {X86::ILD_Fp16m64, {0, Unknown}}, + {X86::ILD_Fp16m80, {0, Unknown}}, + {X86::ILD_Fp32m32, {0, Unknown}}, + {X86::ILD_Fp32m64, {0, Unknown}}, + {X86::ILD_Fp32m80, {0, Unknown}}, + {X86::ILD_Fp64m32, {0, Unknown}}, + {X86::ILD_Fp64m64, {0, Unknown}}, + {X86::ILD_Fp64m80, {0, Unknown}}, + {X86::IMPLICIT_DEF, {0, Unknown}}, + {X86::IMUL16m, {0, Unknown}}, + {X86::IMUL16r, {0, Unknown}}, + {X86::IMUL16rm, {2, Unknown}}, + {X86::IMUL16rmi, {2, Unknown}}, + {X86::IMUL16rmi8, {2, Unknown}}, + {X86::IMUL16rr, {0, Unknown}}, + {X86::IMUL16rri, {0, Unknown}}, + {X86::IMUL16rri8, {0, Unknown}}, + {X86::IMUL32m, {0, Unknown}}, + {X86::IMUL32r, {0, Unknown}}, + {X86::IMUL32rm, {4, BINARY_OP_RM}}, + {X86::IMUL32rmi, {4, Unknown}}, + {X86::IMUL32rmi8, {4, BINARY_OP_RM}}, + {X86::IMUL32rr, {0, BINARY_OP_RR}}, + {X86::IMUL32rri, {0, Unknown}}, + {X86::IMUL32rri8, {0, BINARY_OP_WITH_IMM}}, + {X86::IMUL64m, {0, Unknown}}, + {X86::IMUL64r, {0, Unknown}}, + {X86::IMUL64rm, {8, Unknown}}, + {X86::IMUL64rmi32, {8, Unknown}}, + {X86::IMUL64rmi8, {8, Unknown}}, + {X86::IMUL64rr, {0, BINARY_OP_RR}}, + {X86::IMUL64rri32, {0, BINARY_OP_WITH_IMM}}, + {X86::IMUL64rri8, {0, Unknown}}, + {X86::IMUL8m, {0, Unknown}}, + {X86::IMUL8r, {0, Unknown}}, + {X86::IN16ri, {0, Unknown}}, + {X86::IN16rr, {0, Unknown}}, + {X86::IN32ri, {0, Unknown}}, + {X86::IN32rr, {0, Unknown}}, + {X86::IN8ri, {0, Unknown}}, + {X86::IN8rr, {0, Unknown}}, + {X86::INC16m, {0, Unknown}}, + {X86::INC16r, {0, Unknown}}, + {X86::INC16r_alt, {0, Unknown}}, + {X86::INC32m, {0, Unknown}}, + {X86::INC32r, {0, Unknown}}, + {X86::INC32r_alt, {0, Unknown}}, + {X86::INC64m, {0, Unknown}}, + {X86::INC64r, {0, Unknown}}, + {X86::INC8m, {0, Unknown}}, + {X86::INC8r, {0, Unknown}}, + {X86::INCSSPD, {0, Unknown}}, + {X86::INCSSPQ, {0, Unknown}}, + {X86::INLINEASM, {0, Unknown}}, + {X86::INSB, {0, Unknown}}, + {X86::INSERTPSrm, {0, Unknown}}, + {X86::INSERTPSrr, {0, Unknown}}, + {X86::INSERTQ, {0, Unknown}}, + {X86::INSERTQI, {0, Unknown}}, + {X86::INSERT_SUBREG, {0, Unknown}}, + {X86::INSL, {0, Unknown}}, + {X86::INSW, {0, Unknown}}, + {X86::INT, {0, Unknown}}, + {X86::INT3, {0, Unknown}}, + {X86::INTO, {0, Unknown}}, + {X86::INVD, {0, Unknown}}, + {X86::INVEPT32, {0, Unknown}}, + {X86::INVEPT64, {0, Unknown}}, + {X86::INVLPG, {0, Unknown}}, + {X86::INVLPGA32, {0, Unknown}}, + {X86::INVLPGA64, {0, Unknown}}, + {X86::INVPCID32, {0, Unknown}}, + {X86::INVPCID64, {0, Unknown}}, + {X86::INVVPID32, {0, Unknown}}, + {X86::INVVPID64, {0, Unknown}}, + {X86::IRET, {0, Unknown}}, + {X86::IRET16, {0, Unknown}}, + {X86::IRET32, {0, Unknown}}, + {X86::IRET64, {0, Unknown}}, + {X86::ISTT_FP16m, {0, Unknown}}, + {X86::ISTT_FP32m, {0, Unknown}}, + {X86::ISTT_FP64m, {0, Unknown}}, + {X86::ISTT_Fp16m32, {0, Unknown}}, + {X86::ISTT_Fp16m64, {0, Unknown}}, + {X86::ISTT_Fp16m80, {0, Unknown}}, + {X86::ISTT_Fp32m32, {0, Unknown}}, + {X86::ISTT_Fp32m64, {0, Unknown}}, + {X86::ISTT_Fp32m80, {0, Unknown}}, + {X86::ISTT_Fp64m32, {0, Unknown}}, + {X86::ISTT_Fp64m64, {0, Unknown}}, + {X86::ISTT_Fp64m80, {0, Unknown}}, + {X86::IST_F16m, {0, Unknown}}, + {X86::IST_F32m, {0, Unknown}}, + {X86::IST_FP16m, {0, Unknown}}, + {X86::IST_FP32m, {0, Unknown}}, + {X86::IST_FP64m, {0, Unknown}}, + {X86::IST_Fp16m32, {0, Unknown}}, + {X86::IST_Fp16m64, {0, Unknown}}, + {X86::IST_Fp16m80, {0, Unknown}}, + {X86::IST_Fp32m32, {0, Unknown}}, + {X86::IST_Fp32m64, {0, Unknown}}, + {X86::IST_Fp32m80, {0, Unknown}}, + {X86::IST_Fp64m32, {0, Unknown}}, + {X86::IST_Fp64m64, {0, Unknown}}, + {X86::IST_Fp64m80, {0, Unknown}}, + {X86::Int_MemBarrier, {0, Unknown}}, + {X86::Int_eh_sjlj_setup_dispatch, {0, Unknown}}, + {X86::JAE_1, {0, Unknown}}, + {X86::JAE_2, {0, Unknown}}, + {X86::JAE_4, {0, Unknown}}, + {X86::JA_1, {0, Unknown}}, + {X86::JA_2, {0, Unknown}}, + {X86::JA_4, {0, Unknown}}, + {X86::JBE_1, {0, Unknown}}, + {X86::JBE_2, {0, Unknown}}, + {X86::JBE_4, {0, Unknown}}, + {X86::JB_1, {0, Unknown}}, + {X86::JB_2, {0, Unknown}}, + {X86::JB_4, {0, Unknown}}, + {X86::JCXZ, {0, Unknown}}, + {X86::JECXZ, {0, Unknown}}, + {X86::JE_1, {0, Unknown}}, + {X86::JE_2, {0, Unknown}}, + {X86::JE_4, {0, Unknown}}, + {X86::JGE_1, {0, Unknown}}, + {X86::JGE_2, {0, Unknown}}, + {X86::JGE_4, {0, Unknown}}, + {X86::JG_1, {0, Unknown}}, + {X86::JG_2, {0, Unknown}}, + {X86::JG_4, {0, Unknown}}, + {X86::JLE_1, {0, Unknown}}, + {X86::JLE_2, {0, Unknown}}, + {X86::JLE_4, {0, Unknown}}, + {X86::JL_1, {0, Unknown}}, + {X86::JL_2, {0, Unknown}}, + {X86::JL_4, {0, Unknown}}, + {X86::JMP16m, {0, Unknown}}, + {X86::JMP16m_NT, {0, Unknown}}, + {X86::JMP16r, {0, Unknown}}, + {X86::JMP16r_NT, {0, Unknown}}, + {X86::JMP32m, {0, Unknown}}, + {X86::JMP32m_NT, {0, Unknown}}, + {X86::JMP32r, {0, Unknown}}, + {X86::JMP32r_NT, {0, Unknown}}, + {X86::JMP64m, {0, Unknown}}, + {X86::JMP64m_NT, {0, Unknown}}, + {X86::JMP64r, {0, Unknown}}, + {X86::JMP64r_NT, {0, Unknown}}, + {X86::JMP_1, {0, Unknown}}, + {X86::JMP_2, {0, Unknown}}, + {X86::JMP_4, {0, Unknown}}, + {X86::JNE_1, {0, Unknown}}, + {X86::JNE_2, {0, Unknown}}, + {X86::JNE_4, {0, Unknown}}, + {X86::JNO_1, {0, Unknown}}, + {X86::JNO_2, {0, Unknown}}, + {X86::JNO_4, {0, Unknown}}, + {X86::JNP_1, {0, Unknown}}, + {X86::JNP_2, {0, Unknown}}, + {X86::JNP_4, {0, Unknown}}, + {X86::JNS_1, {0, Unknown}}, + {X86::JNS_2, {0, Unknown}}, + {X86::JNS_4, {0, Unknown}}, + {X86::JO_1, {0, Unknown}}, + {X86::JO_2, {0, Unknown}}, + {X86::JO_4, {0, Unknown}}, + {X86::JP_1, {0, Unknown}}, + {X86::JP_2, {0, Unknown}}, + {X86::JP_4, {0, Unknown}}, + {X86::JRCXZ, {0, Unknown}}, + {X86::JS_1, {0, Unknown}}, + {X86::JS_2, {0, Unknown}}, + {X86::JS_4, {0, Unknown}}, + {X86::KADDBrr, {0, Unknown}}, + {X86::KADDDrr, {0, Unknown}}, + {X86::KADDQrr, {0, Unknown}}, + {X86::KADDWrr, {0, Unknown}}, + {X86::KANDBrr, {0, Unknown}}, + {X86::KANDDrr, {0, Unknown}}, + {X86::KANDNBrr, {0, Unknown}}, + {X86::KANDNDrr, {0, Unknown}}, + {X86::KANDNQrr, {0, Unknown}}, + {X86::KANDNWrr, {0, Unknown}}, + {X86::KANDQrr, {0, Unknown}}, + {X86::KANDWrr, {0, Unknown}}, + {X86::KILL, {0, Unknown}}, + {X86::KMOVBkk, {0, Unknown}}, + {X86::KMOVBkm, {0, Unknown}}, + {X86::KMOVBkr, {0, Unknown}}, + {X86::KMOVBmk, {0, Unknown}}, + {X86::KMOVBrk, {0, Unknown}}, + {X86::KMOVDkk, {0, Unknown}}, + {X86::KMOVDkm, {0, Unknown}}, + {X86::KMOVDkr, {0, Unknown}}, + {X86::KMOVDmk, {0, Unknown}}, + {X86::KMOVDrk, {0, Unknown}}, + {X86::KMOVQkk, {0, Unknown}}, + {X86::KMOVQkm, {0, Unknown}}, + {X86::KMOVQkr, {0, Unknown}}, + {X86::KMOVQmk, {0, Unknown}}, + {X86::KMOVQrk, {0, Unknown}}, + {X86::KMOVWkk, {0, Unknown}}, + {X86::KMOVWkm, {0, Unknown}}, + {X86::KMOVWkr, {0, Unknown}}, + {X86::KMOVWmk, {0, Unknown}}, + {X86::KMOVWrk, {0, Unknown}}, + {X86::KNOTBrr, {0, Unknown}}, + {X86::KNOTDrr, {0, Unknown}}, + {X86::KNOTQrr, {0, Unknown}}, + {X86::KNOTWrr, {0, Unknown}}, + {X86::KORBrr, {0, Unknown}}, + {X86::KORDrr, {0, Unknown}}, + {X86::KORQrr, {0, Unknown}}, + {X86::KORTESTBrr, {0, Unknown}}, + {X86::KORTESTDrr, {0, Unknown}}, + {X86::KORTESTQrr, {0, Unknown}}, + {X86::KORTESTWrr, {0, Unknown}}, + {X86::KORWrr, {0, Unknown}}, + {X86::KSET0D, {0, Unknown}}, + {X86::KSET0Q, {0, Unknown}}, + {X86::KSET0W, {0, Unknown}}, + {X86::KSET1D, {0, Unknown}}, + {X86::KSET1Q, {0, Unknown}}, + {X86::KSET1W, {0, Unknown}}, + {X86::KSHIFTLBri, {0, Unknown}}, + {X86::KSHIFTLDri, {0, Unknown}}, + {X86::KSHIFTLQri, {0, Unknown}}, + {X86::KSHIFTLWri, {0, Unknown}}, + {X86::KSHIFTRBri, {0, Unknown}}, + {X86::KSHIFTRDri, {0, Unknown}}, + {X86::KSHIFTRQri, {0, Unknown}}, + {X86::KSHIFTRWri, {0, Unknown}}, + {X86::KTESTBrr, {0, Unknown}}, + {X86::KTESTDrr, {0, Unknown}}, + {X86::KTESTQrr, {0, Unknown}}, + {X86::KTESTWrr, {0, Unknown}}, + {X86::KUNPCKBWrr, {0, Unknown}}, + {X86::KUNPCKDQrr, {0, Unknown}}, + {X86::KUNPCKWDrr, {0, Unknown}}, + {X86::KXNORBrr, {0, Unknown}}, + {X86::KXNORDrr, {0, Unknown}}, + {X86::KXNORQrr, {0, Unknown}}, + {X86::KXNORWrr, {0, Unknown}}, + {X86::KXORBrr, {0, Unknown}}, + {X86::KXORDrr, {0, Unknown}}, + {X86::KXORQrr, {0, Unknown}}, + {X86::KXORWrr, {0, Unknown}}, + {X86::LAHF, {0, Unknown}}, + {X86::LAR16rm, {2, Unknown}}, + {X86::LAR16rr, {0, Unknown}}, + {X86::LAR32rm, {4, Unknown}}, + {X86::LAR32rr, {0, Unknown}}, + {X86::LAR64rm, {8, Unknown}}, + {X86::LAR64rr, {0, Unknown}}, + {X86::LCMPXCHG16, {0, Unknown}}, + {X86::LCMPXCHG16B, {0, Unknown}}, + {X86::LCMPXCHG16B_SAVE_RBX, {0, Unknown}}, + {X86::LCMPXCHG32, {0, Unknown}}, + {X86::LCMPXCHG64, {0, Unknown}}, + {X86::LCMPXCHG8, {0, Unknown}}, + {X86::LCMPXCHG8B, {0, Unknown}}, + {X86::LCMPXCHG8B_SAVE_EBX, {0, Unknown}}, + {X86::LDDQUrm, {0, Unknown}}, + {X86::LDMXCSR, {0, Unknown}}, + {X86::LDS16rm, {2, Unknown}}, + {X86::LDS32rm, {4, Unknown}}, + {X86::LD_F0, {0, Unknown}}, + {X86::LD_F1, {0, Unknown}}, + {X86::LD_F32m, {8, LOAD_FPU_REG}}, + {X86::LD_F64m, {0, Unknown}}, + {X86::LD_F80m, {0, Unknown}}, + {X86::LD_Fp032, {0, Unknown}}, + {X86::LD_Fp064, {0, Unknown}}, + {X86::LD_Fp080, {0, Unknown}}, + {X86::LD_Fp132, {0, Unknown}}, + {X86::LD_Fp164, {0, Unknown}}, + {X86::LD_Fp180, {0, Unknown}}, + {X86::LD_Fp32m, {0, Unknown}}, + {X86::LD_Fp32m64, {0, Unknown}}, + {X86::LD_Fp32m80, {0, Unknown}}, + {X86::LD_Fp64m, {0, Unknown}}, + {X86::LD_Fp64m80, {0, Unknown}}, + {X86::LD_Fp80m, {0, Unknown}}, + {X86::LD_Frr, {0, Unknown}}, + {X86::LEA16r, {2, LEA_OP}}, // Memory address size 2 bytes + {X86::LEA32r, {4, LEA_OP}}, // Memory address size 4 bytes + {X86::LEA64_32r, {8, LEA_OP}}, // Memory address size 8 bytes + {X86::LEA64r, {8, LEA_OP}}, // Memory address size 8 bytes + {X86::LEAVE, {0, LEAVE_OP}}, + {X86::LEAVE64, {0, LEAVE_OP}}, + {X86::LES16rm, {2, Unknown}}, + {X86::LES32rm, {4, Unknown}}, + {X86::LFENCE, {0, Unknown}}, + {X86::LFS16rm, {2, Unknown}}, + {X86::LFS32rm, {4, Unknown}}, + {X86::LFS64rm, {8, Unknown}}, + {X86::LGDT16m, {0, Unknown}}, + {X86::LGDT32m, {0, Unknown}}, + {X86::LGDT64m, {0, Unknown}}, + {X86::LGS16rm, {2, Unknown}}, + {X86::LGS32rm, {4, Unknown}}, + {X86::LGS64rm, {8, Unknown}}, + {X86::LIDT16m, {0, Unknown}}, + {X86::LIDT32m, {0, Unknown}}, + {X86::LIDT64m, {0, Unknown}}, + {X86::LIFETIME_END, {0, Unknown}}, + {X86::LIFETIME_START, {0, Unknown}}, + {X86::LLDT16m, {0, Unknown}}, + {X86::LLDT16r, {0, Unknown}}, + {X86::LLWPCB, {0, Unknown}}, + {X86::LLWPCB64, {0, Unknown}}, + {X86::LMSW16m, {0, Unknown}}, + {X86::LMSW16r, {0, Unknown}}, + {X86::LOAD_STACK_GUARD, {0, Unknown}}, + {X86::LOCAL_ESCAPE, {0, Unknown}}, + {X86::LOCK_ADD16mi, {2, Unknown}}, + {X86::LOCK_ADD16mi8, {2, Unknown}}, + {X86::LOCK_ADD16mr, {2, Unknown}}, + {X86::LOCK_ADD32mi, {4, Unknown}}, + {X86::LOCK_ADD32mi8, {4, Unknown}}, + {X86::LOCK_ADD32mr, {4, Unknown}}, + {X86::LOCK_ADD64mi32, {8, Unknown}}, + {X86::LOCK_ADD64mi8, {8, Unknown}}, + {X86::LOCK_ADD64mr, {8, Unknown}}, + {X86::LOCK_ADD8mi, {1, Unknown}}, + {X86::LOCK_ADD8mr, {1, Unknown}}, + {X86::LOCK_AND16mi, {2, Unknown}}, + {X86::LOCK_AND16mi8, {2, Unknown}}, + {X86::LOCK_AND16mr, {2, Unknown}}, + {X86::LOCK_AND32mi, {4, Unknown}}, + {X86::LOCK_AND32mi8, {4, Unknown}}, + {X86::LOCK_AND32mr, {4, Unknown}}, + {X86::LOCK_AND64mi32, {8, Unknown}}, + {X86::LOCK_AND64mi8, {8, Unknown}}, + {X86::LOCK_AND64mr, {8, Unknown}}, + {X86::LOCK_AND8mi, {1, Unknown}}, + {X86::LOCK_AND8mr, {1, Unknown}}, + {X86::LOCK_DEC16m, {0, Unknown}}, + {X86::LOCK_DEC32m, {0, Unknown}}, + {X86::LOCK_DEC64m, {0, Unknown}}, + {X86::LOCK_DEC8m, {0, Unknown}}, + {X86::LOCK_INC16m, {0, Unknown}}, + {X86::LOCK_INC32m, {0, Unknown}}, + {X86::LOCK_INC64m, {0, Unknown}}, + {X86::LOCK_INC8m, {0, Unknown}}, + {X86::LOCK_OR16mi, {2, Unknown}}, + {X86::LOCK_OR16mi8, {2, Unknown}}, + {X86::LOCK_OR16mr, {2, Unknown}}, + {X86::LOCK_OR32mi, {4, Unknown}}, + {X86::LOCK_OR32mi8, {4, Unknown}}, + {X86::LOCK_OR32mr, {4, Unknown}}, + {X86::LOCK_OR64mi32, {8, Unknown}}, + {X86::LOCK_OR64mi8, {8, Unknown}}, + {X86::LOCK_OR64mr, {8, Unknown}}, + {X86::LOCK_OR8mi, {1, Unknown}}, + {X86::LOCK_OR8mr, {1, Unknown}}, + {X86::LOCK_PREFIX, {0, Unknown}}, + {X86::LOCK_SUB16mi, {2, Unknown}}, + {X86::LOCK_SUB16mi8, {2, Unknown}}, + {X86::LOCK_SUB16mr, {2, Unknown}}, + {X86::LOCK_SUB32mi, {4, Unknown}}, + {X86::LOCK_SUB32mi8, {4, Unknown}}, + {X86::LOCK_SUB32mr, {4, Unknown}}, + {X86::LOCK_SUB64mi32, {8, Unknown}}, + {X86::LOCK_SUB64mi8, {8, Unknown}}, + {X86::LOCK_SUB64mr, {8, Unknown}}, + {X86::LOCK_SUB8mi, {1, Unknown}}, + {X86::LOCK_SUB8mr, {1, Unknown}}, + {X86::LOCK_XOR16mi, {2, Unknown}}, + {X86::LOCK_XOR16mi8, {2, Unknown}}, + {X86::LOCK_XOR16mr, {2, Unknown}}, + {X86::LOCK_XOR32mi, {4, Unknown}}, + {X86::LOCK_XOR32mi8, {4, Unknown}}, + {X86::LOCK_XOR32mr, {4, Unknown}}, + {X86::LOCK_XOR64mi32, {8, Unknown}}, + {X86::LOCK_XOR64mi8, {8, Unknown}}, + {X86::LOCK_XOR64mr, {8, Unknown}}, + {X86::LOCK_XOR8mi, {1, Unknown}}, + {X86::LOCK_XOR8mr, {1, Unknown}}, + {X86::LODSB, {0, Unknown}}, + {X86::LODSL, {0, Unknown}}, + {X86::LODSQ, {0, Unknown}}, + {X86::LODSW, {0, Unknown}}, + {X86::LOOP, {0, Unknown}}, + {X86::LOOPE, {0, Unknown}}, + {X86::LOOPNE, {0, Unknown}}, + {X86::LRETIL, {0, Unknown}}, + {X86::LRETIQ, {0, Unknown}}, + {X86::LRETIW, {0, Unknown}}, + {X86::LRETL, {0, Unknown}}, + {X86::LRETQ, {0, Unknown}}, + {X86::LRETW, {0, Unknown}}, + {X86::LSL16rm, {2, Unknown}}, + {X86::LSL16rr, {0, Unknown}}, + {X86::LSL32rm, {4, Unknown}}, + {X86::LSL32rr, {0, Unknown}}, + {X86::LSL64rm, {8, Unknown}}, + {X86::LSL64rr, {0, Unknown}}, + {X86::LSS16rm, {2, Unknown}}, + {X86::LSS32rm, {4, Unknown}}, + {X86::LSS64rm, {8, Unknown}}, + {X86::LTRm, {0, Unknown}}, + {X86::LTRr, {0, Unknown}}, + {X86::LWPINS32rmi, {4, Unknown}}, + {X86::LWPINS32rri, {0, Unknown}}, + {X86::LWPINS64rmi, {8, Unknown}}, + {X86::LWPINS64rri, {0, Unknown}}, + {X86::LWPVAL32rmi, {4, Unknown}}, + {X86::LWPVAL32rri, {0, Unknown}}, + {X86::LWPVAL64rmi, {8, Unknown}}, + {X86::LWPVAL64rri, {0, Unknown}}, + {X86::LXADD16, {0, Unknown}}, + {X86::LXADD32, {0, Unknown}}, + {X86::LXADD64, {0, Unknown}}, + {X86::LXADD8, {0, Unknown}}, + {X86::LZCNT16rm, {2, Unknown}}, + {X86::LZCNT16rr, {0, Unknown}}, + {X86::LZCNT32rm, {4, Unknown}}, + {X86::LZCNT32rr, {0, Unknown}}, + {X86::LZCNT64rm, {8, Unknown}}, + {X86::LZCNT64rr, {0, Unknown}}, + {X86::MASKMOVDQU, {0, Unknown}}, + {X86::MASKMOVDQU64, {0, Unknown}}, + {X86::MAXCPDrm, {0, Unknown}}, + {X86::MAXCPDrr, {0, Unknown}}, + {X86::MAXCPSrm, {0, Unknown}}, + {X86::MAXCPSrr, {0, Unknown}}, + {X86::MAXCSDrm, {0, Unknown}}, + {X86::MAXCSDrr, {0, Unknown}}, + {X86::MAXCSSrm, {0, Unknown}}, + {X86::MAXCSSrr, {0, Unknown}}, + {X86::MAXPDrm, {0, Unknown}}, + {X86::MAXPDrr, {0, Unknown}}, + {X86::MAXPSrm, {0, Unknown}}, + {X86::MAXPSrr, {0, Unknown}}, + {X86::MAXSDrm, {0, Unknown}}, + {X86::MAXSDrm_Int, {0, Unknown}}, + {X86::MAXSDrr, {0, Unknown}}, + {X86::MAXSDrr_Int, {0, Unknown}}, + {X86::MAXSSrm, {0, Unknown}}, + {X86::MAXSSrm_Int, {0, Unknown}}, + {X86::MAXSSrr, {0, Unknown}}, + {X86::MAXSSrr_Int, {0, Unknown}}, + {X86::MFENCE, {0, Unknown}}, + {X86::MINCPDrm, {0, Unknown}}, + {X86::MINCPDrr, {0, Unknown}}, + {X86::MINCPSrm, {0, Unknown}}, + {X86::MINCPSrr, {0, Unknown}}, + {X86::MINCSDrm, {0, Unknown}}, + {X86::MINCSDrr, {0, Unknown}}, + {X86::MINCSSrm, {0, Unknown}}, + {X86::MINCSSrr, {0, Unknown}}, + {X86::MINPDrm, {0, Unknown}}, + {X86::MINPDrr, {0, Unknown}}, + {X86::MINPSrm, {0, Unknown}}, + {X86::MINPSrr, {0, Unknown}}, + {X86::MINSDrm, {0, Unknown}}, + {X86::MINSDrm_Int, {0, Unknown}}, + {X86::MINSDrr, {0, Unknown}}, + {X86::MINSDrr_Int, {0, Unknown}}, + {X86::MINSSrm, {0, Unknown}}, + {X86::MINSSrm_Int, {0, Unknown}}, + {X86::MINSSrr, {0, Unknown}}, + {X86::MINSSrr_Int, {0, Unknown}}, + {X86::MMX_CVTPD2PIirm, {0, Unknown}}, + {X86::MMX_CVTPD2PIirr, {0, Unknown}}, + {X86::MMX_CVTPI2PDirm, {0, Unknown}}, + {X86::MMX_CVTPI2PDirr, {0, Unknown}}, + {X86::MMX_CVTPI2PSirm, {0, Unknown}}, + {X86::MMX_CVTPI2PSirr, {0, Unknown}}, + {X86::MMX_CVTPS2PIirm, {0, Unknown}}, + {X86::MMX_CVTPS2PIirr, {0, Unknown}}, + {X86::MMX_CVTTPD2PIirm, {0, Unknown}}, + {X86::MMX_CVTTPD2PIirr, {0, Unknown}}, + {X86::MMX_CVTTPS2PIirm, {0, Unknown}}, + {X86::MMX_CVTTPS2PIirr, {0, Unknown}}, + {X86::MMX_EMMS, {0, Unknown}}, + {X86::MMX_MASKMOVQ, {0, Unknown}}, + {X86::MMX_MASKMOVQ64, {0, Unknown}}, + {X86::MMX_MOVD64from64rm, {8, Unknown}}, + {X86::MMX_MOVD64from64rr, {0, Unknown}}, + {X86::MMX_MOVD64grr, {0, Unknown}}, + {X86::MMX_MOVD64mr, {8, Unknown}}, + {X86::MMX_MOVD64rm, {8, Unknown}}, + {X86::MMX_MOVD64rr, {0, Unknown}}, + {X86::MMX_MOVD64to64rm, {8, Unknown}}, + {X86::MMX_MOVD64to64rr, {0, Unknown}}, + {X86::MMX_MOVDQ2Qrr, {0, Unknown}}, + {X86::MMX_MOVFR642Qrr, {0, Unknown}}, + {X86::MMX_MOVNTQmr, {0, Unknown}}, + {X86::MMX_MOVQ2DQrr, {0, Unknown}}, + {X86::MMX_MOVQ2FR64rr, {0, Unknown}}, + {X86::MMX_MOVQ64mr, {8, Unknown}}, + {X86::MMX_MOVQ64rm, {8, Unknown}}, + {X86::MMX_MOVQ64rr, {0, Unknown}}, + {X86::MMX_MOVQ64rr_REV, {0, Unknown}}, + {X86::MMX_PABSBrm, {0, Unknown}}, + {X86::MMX_PABSBrr, {0, Unknown}}, + {X86::MMX_PABSDrm, {0, Unknown}}, + {X86::MMX_PABSDrr, {0, Unknown}}, + {X86::MMX_PABSWrm, {0, Unknown}}, + {X86::MMX_PABSWrr, {0, Unknown}}, + {X86::MMX_PACKSSDWirm, {0, Unknown}}, + {X86::MMX_PACKSSDWirr, {0, Unknown}}, + {X86::MMX_PACKSSWBirm, {0, Unknown}}, + {X86::MMX_PACKSSWBirr, {0, Unknown}}, + {X86::MMX_PACKUSWBirm, {0, Unknown}}, + {X86::MMX_PACKUSWBirr, {0, Unknown}}, + {X86::MMX_PADDBirm, {0, Unknown}}, + {X86::MMX_PADDBirr, {0, Unknown}}, + {X86::MMX_PADDDirm, {0, Unknown}}, + {X86::MMX_PADDDirr, {0, Unknown}}, + {X86::MMX_PADDQirm, {0, Unknown}}, + {X86::MMX_PADDQirr, {0, Unknown}}, + {X86::MMX_PADDSBirm, {0, Unknown}}, + {X86::MMX_PADDSBirr, {0, Unknown}}, + {X86::MMX_PADDSWirm, {0, Unknown}}, + {X86::MMX_PADDSWirr, {0, Unknown}}, + {X86::MMX_PADDUSBirm, {0, Unknown}}, + {X86::MMX_PADDUSBirr, {0, Unknown}}, + {X86::MMX_PADDUSWirm, {0, Unknown}}, + {X86::MMX_PADDUSWirr, {0, Unknown}}, + {X86::MMX_PADDWirm, {0, Unknown}}, + {X86::MMX_PADDWirr, {0, Unknown}}, + {X86::MMX_PALIGNRrmi, {0, Unknown}}, + {X86::MMX_PALIGNRrri, {0, Unknown}}, + {X86::MMX_PANDNirm, {0, Unknown}}, + {X86::MMX_PANDNirr, {0, Unknown}}, + {X86::MMX_PANDirm, {0, Unknown}}, + {X86::MMX_PANDirr, {0, Unknown}}, + {X86::MMX_PAVGBirm, {0, Unknown}}, + {X86::MMX_PAVGBirr, {0, Unknown}}, + {X86::MMX_PAVGWirm, {0, Unknown}}, + {X86::MMX_PAVGWirr, {0, Unknown}}, + {X86::MMX_PCMPEQBirm, {0, Unknown}}, + {X86::MMX_PCMPEQBirr, {0, Unknown}}, + {X86::MMX_PCMPEQDirm, {0, Unknown}}, + {X86::MMX_PCMPEQDirr, {0, Unknown}}, + {X86::MMX_PCMPEQWirm, {0, Unknown}}, + {X86::MMX_PCMPEQWirr, {0, Unknown}}, + {X86::MMX_PCMPGTBirm, {0, Unknown}}, + {X86::MMX_PCMPGTBirr, {0, Unknown}}, + {X86::MMX_PCMPGTDirm, {0, Unknown}}, + {X86::MMX_PCMPGTDirr, {0, Unknown}}, + {X86::MMX_PCMPGTWirm, {0, Unknown}}, + {X86::MMX_PCMPGTWirr, {0, Unknown}}, + {X86::MMX_PEXTRWrr, {0, Unknown}}, + {X86::MMX_PHADDDrm, {0, Unknown}}, + {X86::MMX_PHADDDrr, {0, Unknown}}, + {X86::MMX_PHADDSWrm, {0, Unknown}}, + {X86::MMX_PHADDSWrr, {0, Unknown}}, + {X86::MMX_PHADDWrm, {0, Unknown}}, + {X86::MMX_PHADDWrr, {0, Unknown}}, + {X86::MMX_PHSUBDrm, {0, Unknown}}, + {X86::MMX_PHSUBDrr, {0, Unknown}}, + {X86::MMX_PHSUBSWrm, {0, Unknown}}, + {X86::MMX_PHSUBSWrr, {0, Unknown}}, + {X86::MMX_PHSUBWrm, {0, Unknown}}, + {X86::MMX_PHSUBWrr, {0, Unknown}}, + {X86::MMX_PINSRWrm, {0, Unknown}}, + {X86::MMX_PINSRWrr, {0, Unknown}}, + {X86::MMX_PMADDUBSWrm, {0, Unknown}}, + {X86::MMX_PMADDUBSWrr, {0, Unknown}}, + {X86::MMX_PMADDWDirm, {0, Unknown}}, + {X86::MMX_PMADDWDirr, {0, Unknown}}, + {X86::MMX_PMAXSWirm, {0, Unknown}}, + {X86::MMX_PMAXSWirr, {0, Unknown}}, + {X86::MMX_PMAXUBirm, {0, Unknown}}, + {X86::MMX_PMAXUBirr, {0, Unknown}}, + {X86::MMX_PMINSWirm, {0, Unknown}}, + {X86::MMX_PMINSWirr, {0, Unknown}}, + {X86::MMX_PMINUBirm, {0, Unknown}}, + {X86::MMX_PMINUBirr, {0, Unknown}}, + {X86::MMX_PMOVMSKBrr, {0, Unknown}}, + {X86::MMX_PMULHRSWrm, {0, Unknown}}, + {X86::MMX_PMULHRSWrr, {0, Unknown}}, + {X86::MMX_PMULHUWirm, {0, Unknown}}, + {X86::MMX_PMULHUWirr, {0, Unknown}}, + {X86::MMX_PMULHWirm, {0, Unknown}}, + {X86::MMX_PMULHWirr, {0, Unknown}}, + {X86::MMX_PMULLWirm, {0, Unknown}}, + {X86::MMX_PMULLWirr, {0, Unknown}}, + {X86::MMX_PMULUDQirm, {0, Unknown}}, + {X86::MMX_PMULUDQirr, {0, Unknown}}, + {X86::MMX_PORirm, {0, Unknown}}, + {X86::MMX_PORirr, {0, Unknown}}, + {X86::MMX_PSADBWirm, {0, Unknown}}, + {X86::MMX_PSADBWirr, {0, Unknown}}, + {X86::MMX_PSHUFBrm, {0, Unknown}}, + {X86::MMX_PSHUFBrr, {0, Unknown}}, + {X86::MMX_PSHUFWmi, {0, Unknown}}, + {X86::MMX_PSHUFWri, {0, Unknown}}, + {X86::MMX_PSIGNBrm, {0, Unknown}}, + {X86::MMX_PSIGNBrr, {0, Unknown}}, + {X86::MMX_PSIGNDrm, {0, Unknown}}, + {X86::MMX_PSIGNDrr, {0, Unknown}}, + {X86::MMX_PSIGNWrm, {0, Unknown}}, + {X86::MMX_PSIGNWrr, {0, Unknown}}, + {X86::MMX_PSLLDri, {0, Unknown}}, + {X86::MMX_PSLLDrm, {0, Unknown}}, + {X86::MMX_PSLLDrr, {0, Unknown}}, + {X86::MMX_PSLLQri, {0, Unknown}}, + {X86::MMX_PSLLQrm, {0, Unknown}}, + {X86::MMX_PSLLQrr, {0, Unknown}}, + {X86::MMX_PSLLWri, {0, Unknown}}, + {X86::MMX_PSLLWrm, {0, Unknown}}, + {X86::MMX_PSLLWrr, {0, Unknown}}, + {X86::MMX_PSRADri, {0, Unknown}}, + {X86::MMX_PSRADrm, {0, Unknown}}, + {X86::MMX_PSRADrr, {0, Unknown}}, + {X86::MMX_PSRAWri, {0, Unknown}}, + {X86::MMX_PSRAWrm, {0, Unknown}}, + {X86::MMX_PSRAWrr, {0, Unknown}}, + {X86::MMX_PSRLDri, {0, Unknown}}, + {X86::MMX_PSRLDrm, {0, Unknown}}, + {X86::MMX_PSRLDrr, {0, Unknown}}, + {X86::MMX_PSRLQri, {0, Unknown}}, + {X86::MMX_PSRLQrm, {0, Unknown}}, + {X86::MMX_PSRLQrr, {0, Unknown}}, + {X86::MMX_PSRLWri, {0, Unknown}}, + {X86::MMX_PSRLWrm, {0, Unknown}}, + {X86::MMX_PSRLWrr, {0, Unknown}}, + {X86::MMX_PSUBBirm, {0, Unknown}}, + {X86::MMX_PSUBBirr, {0, Unknown}}, + {X86::MMX_PSUBDirm, {0, Unknown}}, + {X86::MMX_PSUBDirr, {0, Unknown}}, + {X86::MMX_PSUBQirm, {0, Unknown}}, + {X86::MMX_PSUBQirr, {0, Unknown}}, + {X86::MMX_PSUBSBirm, {0, Unknown}}, + {X86::MMX_PSUBSBirr, {0, Unknown}}, + {X86::MMX_PSUBSWirm, {0, Unknown}}, + {X86::MMX_PSUBSWirr, {0, Unknown}}, + {X86::MMX_PSUBUSBirm, {0, Unknown}}, + {X86::MMX_PSUBUSBirr, {0, Unknown}}, + {X86::MMX_PSUBUSWirm, {0, Unknown}}, + {X86::MMX_PSUBUSWirr, {0, Unknown}}, + {X86::MMX_PSUBWirm, {0, Unknown}}, + {X86::MMX_PSUBWirr, {0, Unknown}}, + {X86::MMX_PUNPCKHBWirm, {0, Unknown}}, + {X86::MMX_PUNPCKHBWirr, {0, Unknown}}, + {X86::MMX_PUNPCKHDQirm, {0, Unknown}}, + {X86::MMX_PUNPCKHDQirr, {0, Unknown}}, + {X86::MMX_PUNPCKHWDirm, {0, Unknown}}, + {X86::MMX_PUNPCKHWDirr, {0, Unknown}}, + {X86::MMX_PUNPCKLBWirm, {0, Unknown}}, + {X86::MMX_PUNPCKLBWirr, {0, Unknown}}, + {X86::MMX_PUNPCKLDQirm, {0, Unknown}}, + {X86::MMX_PUNPCKLDQirr, {0, Unknown}}, + {X86::MMX_PUNPCKLWDirm, {0, Unknown}}, + {X86::MMX_PUNPCKLWDirr, {0, Unknown}}, + {X86::MMX_PXORirm, {0, Unknown}}, + {X86::MMX_PXORirr, {0, Unknown}}, + {X86::MMX_SET0, {0, Unknown}}, + {X86::MONITOR, {0, Unknown}}, + {X86::MONITORX, {0, Unknown}}, + {X86::MONITORXrrr, {0, Unknown}}, + {X86::MONITORrrr, {0, Unknown}}, + {X86::MONTMUL, {0, Unknown}}, + {X86::MORESTACK_RET, {0, Unknown}}, + {X86::MORESTACK_RET_RESTORE_R10, {0, Unknown}}, + {X86::MOV16ao16, {0, Unknown}}, + {X86::MOV16ao32, {0, Unknown}}, + {X86::MOV16ao64, {0, Unknown}}, + {X86::MOV16mi, {2, Unknown}}, + {X86::MOV16mr, {2, Unknown}}, + {X86::MOV16ms, {0, Unknown}}, + {X86::MOV16o16a, {0, Unknown}}, + {X86::MOV16o32a, {0, Unknown}}, + {X86::MOV16o64a, {0, Unknown}}, + {X86::MOV16ri, {0, MOV_RI}}, + {X86::MOV16ri_alt, {0, Unknown}}, + {X86::MOV16rm, {2, MOV_FROM_MEM}}, + {X86::MOV16rr, {0, MOV_RR}}, + {X86::MOV16rr_REV, {0, Unknown}}, + {X86::MOV16rs, {0, Unknown}}, + {X86::MOV16sm, {0, Unknown}}, + {X86::MOV16sr, {0, Unknown}}, + {X86::MOV32ImmSExti8, {0, Unknown}}, + {X86::MOV32ao16, {0, Unknown}}, + {X86::MOV32ao32, {0, Unknown}}, + {X86::MOV32ao64, {0, Unknown}}, + {X86::MOV32cr, {0, Unknown}}, + {X86::MOV32dr, {0, Unknown}}, + {X86::MOV32mi, {4, MOV_TO_MEM}}, + {X86::MOV32mr, {4, MOV_TO_MEM}}, + {X86::MOV32o16a, {0, Unknown}}, + {X86::MOV32o32a, {0, Unknown}}, + {X86::MOV32o64a, {0, Unknown}}, + {X86::MOV32r0, {0, Unknown}}, + {X86::MOV32r1, {0, Unknown}}, + {X86::MOV32r_1, {0, Unknown}}, + {X86::MOV32rc, {0, Unknown}}, + {X86::MOV32rd, {0, Unknown}}, + {X86::MOV32ri, {0, MOV_RI}}, + {X86::MOV32ri64, {0, Unknown}}, + {X86::MOV32ri_alt, {0, Unknown}}, + {X86::MOV32rm, {4, MOV_FROM_MEM}}, + {X86::MOV32rr, {0, MOV_RR}}, + {X86::MOV32rr_REV, {0, Unknown}}, + {X86::MOV32rs, {0, Unknown}}, + {X86::MOV32sr, {0, Unknown}}, + {X86::MOV64ImmSExti8, {0, Unknown}}, + {X86::MOV64ao32, {0, Unknown}}, + {X86::MOV64ao64, {0, Unknown}}, + {X86::MOV64cr, {0, Unknown}}, + {X86::MOV64dr, {0, Unknown}}, + {X86::MOV64mi32, {8, MOV_TO_MEM}}, + {X86::MOV64mr, {8, MOV_TO_MEM}}, + {X86::MOV64o32a, {0, Unknown}}, + {X86::MOV64o64a, {0, Unknown}}, + {X86::MOV64rc, {0, Unknown}}, + {X86::MOV64rd, {0, Unknown}}, + {X86::MOV64ri, {0, MOV_RI}}, + {X86::MOV64ri32, {0, Unknown}}, + {X86::MOV64rm, {8, MOV_FROM_MEM}}, + {X86::MOV64rr, {0, MOV_RR}}, + {X86::MOV64rr_REV, {0, Unknown}}, + {X86::MOV64rs, {0, Unknown}}, + {X86::MOV64sr, {0, Unknown}}, + {X86::MOV64toPQIrm, {0, Unknown}}, + {X86::MOV64toPQIrr, {0, Unknown}}, + {X86::MOV64toSDrm, {0, Unknown}}, + {X86::MOV64toSDrr, {0, Unknown}}, + {X86::MOV8ao16, {0, Unknown}}, + {X86::MOV8ao32, {0, Unknown}}, + {X86::MOV8ao64, {0, Unknown}}, + {X86::MOV8mi, {1, MOV_TO_MEM}}, + {X86::MOV8mr, {1, MOV_TO_MEM}}, + {X86::MOV8mr_NOREX, {1, Unknown}}, + {X86::MOV8o16a, {0, Unknown}}, + {X86::MOV8o32a, {0, Unknown}}, + {X86::MOV8o64a, {0, Unknown}}, + {X86::MOV8ri, {0, MOV_RI}}, + {X86::MOV8ri_alt, {0, Unknown}}, + {X86::MOV8rm, {1, MOV_FROM_MEM}}, + {X86::MOV8rm_NOREX, {1, Unknown}}, + {X86::MOV8rr, {0, MOV_RR}}, + {X86::MOV8rr_NOREX, {0, Unknown}}, + {X86::MOV8rr_REV, {0, Unknown}}, + {X86::MOVAPDmr, {0, Unknown}}, + {X86::MOVAPDrm, {0, Unknown}}, + {X86::MOVAPDrr, {0, Unknown}}, + {X86::MOVAPDrr_REV, {0, Unknown}}, + {X86::MOVAPSmr, {0, Unknown}}, + {X86::MOVAPSrm, {0, Unknown}}, + {X86::MOVAPSrr, {0, Unknown}}, + {X86::MOVAPSrr_REV, {0, Unknown}}, + {X86::MOVBE16mr, {2, Unknown}}, + {X86::MOVBE16rm, {2, Unknown}}, + {X86::MOVBE32mr, {4, Unknown}}, + {X86::MOVBE32rm, {4, Unknown}}, + {X86::MOVBE64mr, {8, Unknown}}, + {X86::MOVBE64rm, {8, Unknown}}, + {X86::MOVDDUPrm, {0, Unknown}}, + {X86::MOVDDUPrr, {0, Unknown}}, + {X86::MOVDI2PDIrm, {0, Unknown}}, + {X86::MOVDI2PDIrr, {0, Unknown}}, + {X86::MOVDI2SSrm, {0, Unknown}}, + {X86::MOVDI2SSrr, {0, Unknown}}, + {X86::MOVDQAmr, {0, Unknown}}, + {X86::MOVDQArm, {0, Unknown}}, + {X86::MOVDQArr, {0, Unknown}}, + {X86::MOVDQArr_REV, {0, Unknown}}, + {X86::MOVDQUmr, {0, Unknown}}, + {X86::MOVDQUrm, {0, Unknown}}, + {X86::MOVDQUrr, {0, Unknown}}, + {X86::MOVDQUrr_REV, {0, Unknown}}, + {X86::MOVHLPSrr, {0, Unknown}}, + {X86::MOVHPDmr, {0, Unknown}}, + {X86::MOVHPDrm, {0, Unknown}}, + {X86::MOVHPSmr, {0, Unknown}}, + {X86::MOVHPSrm, {0, Unknown}}, + {X86::MOVLHPSrr, {0, Unknown}}, + {X86::MOVLPDmr, {0, Unknown}}, + {X86::MOVLPDrm, {0, Unknown}}, + {X86::MOVLPSmr, {0, Unknown}}, + {X86::MOVLPSrm, {0, Unknown}}, + {X86::MOVMSKPDrr, {0, Unknown}}, + {X86::MOVMSKPSrr, {0, Unknown}}, + {X86::MOVNTDQArm, {0, Unknown}}, + {X86::MOVNTDQmr, {0, Unknown}}, + {X86::MOVNTI_64mr, {8, Unknown}}, + {X86::MOVNTImr, {0, Unknown}}, + {X86::MOVNTPDmr, {0, Unknown}}, + {X86::MOVNTPSmr, {0, Unknown}}, + {X86::MOVNTSD, {0, Unknown}}, + {X86::MOVNTSS, {0, Unknown}}, + {X86::MOVPC32r, {0, Unknown}}, + {X86::MOVPDI2DImr, {0, Unknown}}, + {X86::MOVPDI2DIrr, {0, Unknown}}, + {X86::MOVPQI2QImr, {0, Unknown}}, + {X86::MOVPQI2QIrr, {0, Unknown}}, + {X86::MOVPQIto64mr, {8, Unknown}}, + {X86::MOVPQIto64rr, {0, Unknown}}, + {X86::MOVQI2PQIrm, {0, Unknown}}, + {X86::MOVSB, {0, Unknown}}, + {X86::MOVSDmr, {0, Unknown}}, + {X86::MOVSDrm, {0, Unknown}}, + {X86::MOVSDrr, {0, Unknown}}, + {X86::MOVSDrr_REV, {0, Unknown}}, + {X86::MOVSDto64mr, {8, Unknown}}, + {X86::MOVSDto64rr, {0, Unknown}}, + + {X86::MOVSHDUPrm, {0, Unknown}}, + {X86::MOVSHDUPrr, {0, Unknown}}, + {X86::MOVSL, {0, Unknown}}, + {X86::MOVSLDUPrm, {0, Unknown}}, + {X86::MOVSLDUPrr, {0, Unknown}}, + {X86::MOVSQ, {0, Unknown}}, + {X86::MOVSS2DImr, {0, Unknown}}, + {X86::MOVSS2DIrr, {0, Unknown}}, + {X86::MOVSSmr, {0, Unknown}}, + {X86::MOVSSrm, {0, Unknown}}, + {X86::MOVSSrr, {0, Unknown}}, + {X86::MOVSSrr_REV, {0, Unknown}}, + {X86::MOVSW, {0, Unknown}}, + {X86::MOVSX16rm8, {2, Unknown}}, + {X86::MOVSX16rr8, {0, MOV_RR}}, + {X86::MOVSX32rm16, {4, Unknown}}, + {X86::MOVSX32rm8, {4, MOV_FROM_MEM}}, + {X86::MOVSX32rm8_NOREX, {4, Unknown}}, + {X86::MOVSX32rr16, {0, MOV_RR}}, + {X86::MOVSX32rr8, {0, MOV_RR}}, + {X86::MOVSX32rr8_NOREX, {0, Unknown}}, + {X86::MOVSX64rm16, {2, Unknown}}, + {X86::MOVSX64rm32, {4, MOV_FROM_MEM}}, + {X86::MOVSX64rm8, {1, Unknown}}, + {X86::MOVSX64rr16, {0, MOV_RR}}, + {X86::MOVSX64rr32, {0, MOV_RR}}, + {X86::MOVSX64rr8, {0, MOV_RR}}, + {X86::MOVUPDmr, {0, Unknown}}, + {X86::MOVUPDrm, {0, Unknown}}, + {X86::MOVUPDrr, {0, Unknown}}, + {X86::MOVUPDrr_REV, {0, Unknown}}, + {X86::MOVUPSmr, {0, Unknown}}, + {X86::MOVUPSrm, {0, Unknown}}, + {X86::MOVUPSrr, {0, Unknown}}, + {X86::MOVUPSrr_REV, {0, Unknown}}, + {X86::MOVZPQILo2PQIrr, {0, Unknown}}, + {X86::MOVZX16rm8, {2, Unknown}}, + {X86::MOVZX16rr8, {0, MOV_RR}}, + {X86::MOVZX32rm16, {4, Unknown}}, + {X86::MOVZX32rm8, {4, MOV_FROM_MEM}}, + {X86::MOVZX32rm8_NOREX, {4, Unknown}}, + {X86::MOVZX32rr16, {0, MOV_RR}}, + {X86::MOVZX32rr8, {0, MOV_RR}}, + {X86::MOVZX32rr8_NOREX, {0, Unknown}}, + {X86::MOVZX64rm16, {8, Unknown}}, + {X86::MOVZX64rm8, {8, Unknown}}, + {X86::MOVZX64rr16, {0, MOV_RR}}, + {X86::MOVZX64rr8, {0, MOV_RR}}, + {X86::MPSADBWrmi, {0, Unknown}}, + {X86::MPSADBWrri, {0, Unknown}}, + {X86::MUL16m, {0, Unknown}}, + {X86::MUL16r, {0, Unknown}}, + {X86::MUL32m, {0, Unknown}}, + {X86::MUL32r, {0, Unknown}}, + {X86::MUL64m, {0, Unknown}}, + {X86::MUL64r, {0, Unknown}}, + {X86::MUL8m, {0, Unknown}}, + {X86::MUL8r, {0, Unknown}}, + {X86::MULPDrm, {0, Unknown}}, + {X86::MULPDrr, {0, Unknown}}, + {X86::MULPSrm, {0, Unknown}}, + {X86::MULPSrr, {0, Unknown}}, + {X86::MULSDrm, {0, Unknown}}, + {X86::MULSDrm_Int, {0, Unknown}}, + {X86::MULSDrr, {0, Unknown}}, + {X86::MULSDrr_Int, {0, Unknown}}, + {X86::MULSSrm, {0, Unknown}}, + {X86::MULSSrm_Int, {0, Unknown}}, + {X86::MULSSrr, {0, Unknown}}, + {X86::MULSSrr_Int, {0, Unknown}}, + {X86::MULX32rm, {4, Unknown}}, + {X86::MULX32rr, {0, Unknown}}, + {X86::MULX64rm, {8, Unknown}}, + {X86::MULX64rr, {0, Unknown}}, + {X86::MUL_F32m, {0, Unknown}}, + {X86::MUL_F64m, {0, Unknown}}, + {X86::MUL_FI16m, {0, Unknown}}, + {X86::MUL_FI32m, {0, Unknown}}, + {X86::MUL_FPrST0, {0, FPU_REG_OP}}, + {X86::MUL_FST0r, {0, Unknown}}, + {X86::MUL_Fp32, {0, Unknown}}, + {X86::MUL_Fp32m, {0, Unknown}}, + {X86::MUL_Fp64, {0, Unknown}}, + {X86::MUL_Fp64m, {0, Unknown}}, + {X86::MUL_Fp64m32, {0, Unknown}}, + {X86::MUL_Fp80, {0, Unknown}}, + {X86::MUL_Fp80m32, {0, Unknown}}, + {X86::MUL_Fp80m64, {0, Unknown}}, + {X86::MUL_FpI16m32, {0, Unknown}}, + {X86::MUL_FpI16m64, {0, Unknown}}, + {X86::MUL_FpI16m80, {0, Unknown}}, + {X86::MUL_FpI32m32, {0, Unknown}}, + {X86::MUL_FpI32m64, {0, Unknown}}, + {X86::MUL_FpI32m80, {0, Unknown}}, + {X86::MUL_FrST0, {0, Unknown}}, + {X86::MWAITXrrr, {0, Unknown}}, + {X86::MWAITrr, {0, Unknown}}, + {X86::NEG16m, {0, Unknown}}, + {X86::NEG16r, {0, Unknown}}, + {X86::NEG32m, {0, Unknown}}, + {X86::NEG32r, {0, Unknown}}, + {X86::NEG64m, {0, Unknown}}, + {X86::NEG64r, {0, Unknown}}, + {X86::NEG8m, {0, Unknown}}, + {X86::NEG8r, {0, Unknown}}, + {X86::NOOP, {0, NOOP}}, + {X86::NOOPL, {0, NOOP}}, + {X86::NOOPLr, {0, NOOP}}, + {X86::NOOPQ, {0, NOOP}}, + {X86::NOOPQr, {0, NOOP}}, + {X86::NOOPW, {0, NOOP}}, + {X86::NOOPWr, {0, NOOP}}, + {X86::NOT16m, {0, Unknown}}, + {X86::NOT16r, {0, Unknown}}, + {X86::NOT32m, {0, Unknown}}, + {X86::NOT32r, {0, Unknown}}, + {X86::NOT64m, {0, Unknown}}, + {X86::NOT64r, {0, Unknown}}, + {X86::NOT8m, {0, Unknown}}, + {X86::NOT8r, {0, Unknown}}, + {X86::OR16i16, {0, Unknown}}, + {X86::OR16mi, {2, Unknown}}, + {X86::OR16mi8, {2, Unknown}}, + {X86::OR16mr, {2, Unknown}}, + {X86::OR16ri, {0, Unknown}}, + {X86::OR16ri8, {0, Unknown}}, + {X86::OR16rm, {2, Unknown}}, + {X86::OR16rr, {0, Unknown}}, + {X86::OR16rr_REV, {0, Unknown}}, + {X86::OR32i32, {0, Unknown}}, + {X86::OR32mi, {4, Unknown}}, + {X86::OR32mi8, {4, Unknown}}, + {X86::OR32mr, {4, Unknown}}, + {X86::OR32mrLocked, {4, Unknown}}, + {X86::OR32ri, {0, Unknown}}, + {X86::OR32ri8, {0, Unknown}}, + {X86::OR32rm, {4, BINARY_OP_RM}}, + {X86::OR32rr, {0, Unknown}}, + {X86::OR32rr_REV, {0, Unknown}}, + {X86::OR64i32, {0, Unknown}}, + {X86::OR64mi32, {8, Unknown}}, + {X86::OR64mi8, {8, Unknown}}, + {X86::OR64mr, {8, Unknown}}, + {X86::OR64ri32, {0, Unknown}}, + {X86::OR64ri8, {0, Unknown}}, + {X86::OR64rm, {8, Unknown}}, + {X86::OR64rr, {0, Unknown}}, + {X86::OR64rr_REV, {0, Unknown}}, + {X86::OR8i8, {0, Unknown}}, + {X86::OR8mi, {1, Unknown}}, + {X86::OR8mi8, {1, Unknown}}, + {X86::OR8mr, {1, Unknown}}, + {X86::OR8ri, {0, Unknown}}, + {X86::OR8ri8, {0, Unknown}}, + {X86::OR8rm, {1, Unknown}}, + {X86::OR8rr, {0, Unknown}}, + {X86::OR8rr_REV, {0, Unknown}}, + {X86::ORPDrm, {0, Unknown}}, + {X86::ORPDrr, {0, Unknown}}, + {X86::ORPSrm, {0, Unknown}}, + {X86::ORPSrr, {0, Unknown}}, + {X86::OUT16ir, {0, Unknown}}, + {X86::OUT16rr, {0, Unknown}}, + {X86::OUT32ir, {0, Unknown}}, + {X86::OUT32rr, {0, Unknown}}, + {X86::OUT8ir, {0, Unknown}}, + {X86::OUT8rr, {0, Unknown}}, + {X86::OUTSB, {0, Unknown}}, + {X86::OUTSL, {0, Unknown}}, + {X86::OUTSW, {0, Unknown}}, + {X86::PABSBrm, {0, Unknown}}, + {X86::PABSBrr, {0, Unknown}}, + {X86::PABSDrm, {0, Unknown}}, + {X86::PABSDrr, {0, Unknown}}, + {X86::PABSWrm, {0, Unknown}}, + {X86::PABSWrr, {0, Unknown}}, + {X86::PACKSSDWrm, {0, Unknown}}, + {X86::PACKSSDWrr, {0, Unknown}}, + {X86::PACKSSWBrm, {0, Unknown}}, + {X86::PACKSSWBrr, {0, Unknown}}, + {X86::PACKUSDWrm, {0, Unknown}}, + {X86::PACKUSDWrr, {0, Unknown}}, + {X86::PACKUSWBrm, {0, Unknown}}, + {X86::PACKUSWBrr, {0, Unknown}}, + {X86::PADDBrm, {0, Unknown}}, + {X86::PADDBrr, {0, Unknown}}, + {X86::PADDDrm, {0, Unknown}}, + {X86::PADDDrr, {0, Unknown}}, + {X86::PADDQrm, {0, Unknown}}, + {X86::PADDQrr, {0, Unknown}}, + {X86::PADDSBrm, {0, Unknown}}, + {X86::PADDSBrr, {0, Unknown}}, + {X86::PADDSWrm, {0, Unknown}}, + {X86::PADDSWrr, {0, Unknown}}, + {X86::PADDUSBrm, {0, Unknown}}, + {X86::PADDUSBrr, {0, Unknown}}, + {X86::PADDUSWrm, {0, Unknown}}, + {X86::PADDUSWrr, {0, Unknown}}, + {X86::PADDWrm, {0, Unknown}}, + {X86::PADDWrr, {0, Unknown}}, + {X86::PALIGNRrmi, {0, Unknown}}, + {X86::PALIGNRrri, {0, Unknown}}, + {X86::PANDNrm, {0, Unknown}}, + {X86::PANDNrr, {0, Unknown}}, + {X86::PANDrm, {0, Unknown}}, + {X86::PANDrr, {0, Unknown}}, + {X86::PATCHABLE_EVENT_CALL, {0, Unknown}}, + {X86::PATCHABLE_FUNCTION_ENTER, {0, Unknown}}, + {X86::PATCHABLE_FUNCTION_EXIT, {0, Unknown}}, + {X86::PATCHABLE_OP, {0, Unknown}}, + {X86::PATCHABLE_RET, {0, Unknown}}, + {X86::PATCHABLE_TAIL_CALL, {0, Unknown}}, + {X86::PATCHPOINT, {0, Unknown}}, + {X86::PAUSE, {0, Unknown}}, + {X86::PAVGBrm, {0, Unknown}}, + {X86::PAVGBrr, {0, Unknown}}, + {X86::PAVGUSBrm, {0, Unknown}}, + {X86::PAVGUSBrr, {0, Unknown}}, + {X86::PAVGWrm, {0, Unknown}}, + {X86::PAVGWrr, {0, Unknown}}, + {X86::PBLENDVBrm0, {0, Unknown}}, + {X86::PBLENDVBrr0, {0, Unknown}}, + {X86::PBLENDWrmi, {0, Unknown}}, + {X86::PBLENDWrri, {0, Unknown}}, + {X86::PCLMULQDQrm, {0, Unknown}}, + {X86::PCLMULQDQrr, {0, Unknown}}, + {X86::PDEP32rm, {4, Unknown}}, + {X86::PDEP32rr, {0, Unknown}}, + {X86::PDEP64rm, {8, Unknown}}, + {X86::PDEP64rr, {0, Unknown}}, + {X86::PEXT32rm, {4, Unknown}}, + {X86::PEXT32rr, {0, Unknown}}, + {X86::PEXT64rm, {8, Unknown}}, + {X86::PEXT64rr, {0, Unknown}}, + {X86::PEXTRBmr, {0, Unknown}}, + {X86::PEXTRBrr, {0, Unknown}}, + {X86::PEXTRDmr, {0, Unknown}}, + {X86::PEXTRDrr, {0, Unknown}}, + {X86::PEXTRQmr, {0, Unknown}}, + {X86::PEXTRQrr, {0, Unknown}}, + {X86::PEXTRWmr, {0, Unknown}}, + {X86::PEXTRWrr, {0, Unknown}}, + {X86::PEXTRWrr_REV, {0, Unknown}}, + {X86::PF2IDrm, {0, Unknown}}, + {X86::PF2IDrr, {0, Unknown}}, + {X86::PF2IWrm, {0, Unknown}}, + {X86::PF2IWrr, {0, Unknown}}, + {X86::PFACCrm, {0, Unknown}}, + {X86::PFACCrr, {0, Unknown}}, + {X86::PFADDrm, {0, Unknown}}, + {X86::PFADDrr, {0, Unknown}}, + {X86::PFCMPEQrm, {0, Unknown}}, + {X86::PFCMPEQrr, {0, Unknown}}, + {X86::PFCMPGErm, {0, Unknown}}, + {X86::PFCMPGErr, {0, Unknown}}, + {X86::PFCMPGTrm, {0, Unknown}}, + {X86::PFCMPGTrr, {0, Unknown}}, + {X86::PFMAXrm, {0, Unknown}}, + {X86::PFMAXrr, {0, Unknown}}, + {X86::PFMINrm, {0, Unknown}}, + {X86::PFMINrr, {0, Unknown}}, + {X86::PFMULrm, {0, Unknown}}, + {X86::PFMULrr, {0, Unknown}}, + {X86::PFNACCrm, {0, Unknown}}, + {X86::PFNACCrr, {0, Unknown}}, + {X86::PFPNACCrm, {0, Unknown}}, + {X86::PFPNACCrr, {0, Unknown}}, + {X86::PFRCPIT1rm, {0, Unknown}}, + {X86::PFRCPIT1rr, {0, Unknown}}, + {X86::PFRCPIT2rm, {0, Unknown}}, + {X86::PFRCPIT2rr, {0, Unknown}}, + {X86::PFRCPrm, {0, Unknown}}, + {X86::PFRCPrr, {0, Unknown}}, + {X86::PFRSQIT1rm, {0, Unknown}}, + {X86::PFRSQIT1rr, {0, Unknown}}, + {X86::PFRSQRTrm, {0, Unknown}}, + {X86::PFRSQRTrr, {0, Unknown}}, + {X86::PFSUBRrm, {0, Unknown}}, + {X86::PFSUBRrr, {0, Unknown}}, + {X86::PFSUBrm, {0, Unknown}}, + {X86::PFSUBrr, {0, Unknown}}, + {X86::PHADDDrm, {0, Unknown}}, + {X86::PHADDDrr, {0, Unknown}}, + {X86::PHADDSWrm, {0, Unknown}}, + {X86::PHADDSWrr, {0, Unknown}}, + {X86::PHADDWrm, {0, Unknown}}, + {X86::PHADDWrr, {0, Unknown}}, + {X86::PHI, {0, Unknown}}, + {X86::PHMINPOSUWrm, {0, Unknown}}, + {X86::PHMINPOSUWrr, {0, Unknown}}, + {X86::PHSUBDrm, {0, Unknown}}, + {X86::PHSUBDrr, {0, Unknown}}, + {X86::PHSUBSWrm, {0, Unknown}}, + {X86::PHSUBSWrr, {0, Unknown}}, + {X86::PHSUBWrm, {0, Unknown}}, + {X86::PHSUBWrr, {0, Unknown}}, + {X86::PI2FDrm, {0, Unknown}}, + {X86::PI2FDrr, {0, Unknown}}, + {X86::PI2FWrm, {0, Unknown}}, + {X86::PI2FWrr, {0, Unknown}}, + {X86::PINSRBrm, {0, Unknown}}, + {X86::PINSRBrr, {0, Unknown}}, + {X86::PINSRDrm, {0, Unknown}}, + {X86::PINSRDrr, {0, Unknown}}, + {X86::PINSRQrm, {0, Unknown}}, + {X86::PINSRQrr, {0, Unknown}}, + {X86::PINSRWrm, {0, Unknown}}, + {X86::PINSRWrr, {0, Unknown}}, + {X86::PMADDUBSWrm, {0, Unknown}}, + {X86::PMADDUBSWrr, {0, Unknown}}, + {X86::PMADDWDrm, {0, Unknown}}, + {X86::PMADDWDrr, {0, Unknown}}, + {X86::PMAXSBrm, {0, Unknown}}, + {X86::PMAXSBrr, {0, Unknown}}, + {X86::PMAXSDrm, {0, Unknown}}, + {X86::PMAXSDrr, {0, Unknown}}, + {X86::PMAXSWrm, {0, Unknown}}, + {X86::PMAXSWrr, {0, Unknown}}, + {X86::PMAXUBrm, {0, Unknown}}, + {X86::PMAXUBrr, {0, Unknown}}, + {X86::PMAXUDrm, {0, Unknown}}, + {X86::PMAXUDrr, {0, Unknown}}, + {X86::PMAXUWrm, {0, Unknown}}, + {X86::PMAXUWrr, {0, Unknown}}, + {X86::PMINSBrm, {0, Unknown}}, + {X86::PMINSBrr, {0, Unknown}}, + {X86::PMINSDrm, {0, Unknown}}, + {X86::PMINSDrr, {0, Unknown}}, + {X86::PMINSWrm, {0, Unknown}}, + {X86::PMINSWrr, {0, Unknown}}, + {X86::PMINUBrm, {0, Unknown}}, + {X86::PMINUBrr, {0, Unknown}}, + {X86::PMINUDrm, {0, Unknown}}, + {X86::PMINUDrr, {0, Unknown}}, + {X86::PMINUWrm, {0, Unknown}}, + {X86::PMINUWrr, {0, Unknown}}, + {X86::PMOVMSKBrr, {0, Unknown}}, + {X86::PMOVSXBDrm, {0, Unknown}}, + {X86::PMOVSXBDrr, {0, Unknown}}, + {X86::PMOVSXBQrm, {0, Unknown}}, + {X86::PMOVSXBQrr, {0, Unknown}}, + {X86::PMOVSXBWrm, {0, Unknown}}, + {X86::PMOVSXBWrr, {0, Unknown}}, + {X86::PMOVSXDQrm, {0, Unknown}}, + {X86::PMOVSXDQrr, {0, Unknown}}, + {X86::PMOVSXWDrm, {0, Unknown}}, + {X86::PMOVSXWDrr, {0, Unknown}}, + {X86::PMOVSXWQrm, {0, Unknown}}, + {X86::PMOVSXWQrr, {0, Unknown}}, + {X86::PMOVZXBDrm, {0, Unknown}}, + {X86::PMOVZXBDrr, {0, Unknown}}, + {X86::PMOVZXBQrm, {0, Unknown}}, + {X86::PMOVZXBQrr, {0, Unknown}}, + {X86::PMOVZXBWrm, {0, Unknown}}, + {X86::PMOVZXBWrr, {0, Unknown}}, + {X86::PMOVZXDQrm, {0, Unknown}}, + {X86::PMOVZXDQrr, {0, Unknown}}, + {X86::PMOVZXWDrm, {0, Unknown}}, + {X86::PMOVZXWDrr, {0, Unknown}}, + {X86::PMOVZXWQrm, {0, Unknown}}, + {X86::PMOVZXWQrr, {0, Unknown}}, + {X86::PMULDQrm, {0, Unknown}}, + {X86::PMULDQrr, {0, Unknown}}, + {X86::PMULHRSWrm, {0, Unknown}}, + {X86::PMULHRSWrr, {0, Unknown}}, + {X86::PMULHRWrm, {0, Unknown}}, + {X86::PMULHRWrr, {0, Unknown}}, + {X86::PMULHUWrm, {0, Unknown}}, + {X86::PMULHUWrr, {0, Unknown}}, + {X86::PMULHWrm, {0, Unknown}}, + {X86::PMULHWrr, {0, Unknown}}, + {X86::PMULLDrm, {0, Unknown}}, + {X86::PMULLDrr, {0, Unknown}}, + {X86::PMULLWrm, {0, Unknown}}, + {X86::PMULLWrr, {0, Unknown}}, + {X86::PMULUDQrm, {0, Unknown}}, + {X86::PMULUDQrr, {0, Unknown}}, + {X86::POP16r, {0, Unknown}}, + {X86::POP16rmm, {2, Unknown}}, + {X86::POP16rmr, {2, Unknown}}, + {X86::POP32r, {0, Unknown}}, + {X86::POP32rmm, {4, Unknown}}, + {X86::POP32rmr, {4, Unknown}}, + {X86::POP64r, {0, Unknown}}, + {X86::POP64rmm, {8, Unknown}}, + {X86::POP64rmr, {8, Unknown}}, + {X86::POPA16, {0, Unknown}}, + {X86::POPA32, {0, Unknown}}, + {X86::POPCNT16rm, {2, Unknown}}, + {X86::POPCNT16rr, {0, Unknown}}, + {X86::POPCNT32rm, {4, Unknown}}, + {X86::POPCNT32rr, {0, Unknown}}, + {X86::POPCNT64rm, {8, Unknown}}, + {X86::POPCNT64rr, {0, Unknown}}, + {X86::POPDS16, {0, Unknown}}, + {X86::POPDS32, {0, Unknown}}, + {X86::POPES16, {0, Unknown}}, + {X86::POPES32, {0, Unknown}}, + {X86::POPF16, {0, Unknown}}, + {X86::POPF32, {0, Unknown}}, + {X86::POPF64, {0, Unknown}}, + {X86::POPFS16, {0, Unknown}}, + {X86::POPFS32, {0, Unknown}}, + {X86::POPFS64, {0, Unknown}}, + {X86::POPGS16, {0, Unknown}}, + {X86::POPGS32, {0, Unknown}}, + {X86::POPGS64, {0, Unknown}}, + {X86::POPSS16, {0, Unknown}}, + {X86::POPSS32, {0, Unknown}}, + {X86::PORrm, {0, Unknown}}, + {X86::PORrr, {0, Unknown}}, + {X86::PREFETCH, {0, Unknown}}, + {X86::PREFETCHNTA, {0, Unknown}}, + {X86::PREFETCHT0, {0, Unknown}}, + {X86::PREFETCHT1, {0, Unknown}}, + {X86::PREFETCHT2, {0, Unknown}}, + {X86::PREFETCHW, {0, Unknown}}, + {X86::PREFETCHWT1, {0, Unknown}}, + {X86::PSADBWrm, {0, Unknown}}, + {X86::PSADBWrr, {0, Unknown}}, + {X86::PSHUFBrm, {0, Unknown}}, + {X86::PSHUFBrr, {0, Unknown}}, + {X86::PSHUFDmi, {0, Unknown}}, + {X86::PSHUFDri, {0, Unknown}}, + {X86::PSHUFHWmi, {0, Unknown}}, + {X86::PSHUFHWri, {0, Unknown}}, + {X86::PSHUFLWmi, {0, Unknown}}, + {X86::PSHUFLWri, {0, Unknown}}, + {X86::PSIGNBrm, {0, Unknown}}, + {X86::PSIGNBrr, {0, Unknown}}, + {X86::PSIGNDrm, {0, Unknown}}, + {X86::PSIGNDrr, {0, Unknown}}, + {X86::PSIGNWrm, {0, Unknown}}, + {X86::PSIGNWrr, {0, Unknown}}, + {X86::PSLLDQri, {0, Unknown}}, + {X86::PSLLDri, {0, Unknown}}, + {X86::PSLLDrm, {0, Unknown}}, + {X86::PSLLDrr, {0, Unknown}}, + {X86::PSLLQri, {0, Unknown}}, + {X86::PSLLQrm, {0, Unknown}}, + {X86::PSLLQrr, {0, Unknown}}, + {X86::PSLLWri, {0, Unknown}}, + {X86::PSLLWrm, {0, Unknown}}, + {X86::PSLLWrr, {0, Unknown}}, + {X86::PSRADri, {0, Unknown}}, + {X86::PSRADrm, {0, Unknown}}, + {X86::PSRADrr, {0, Unknown}}, + {X86::PSRAWri, {0, Unknown}}, + {X86::PSRAWrm, {0, Unknown}}, + {X86::PSRAWrr, {0, Unknown}}, + {X86::PSRLDQri, {0, Unknown}}, + {X86::PSRLDri, {0, Unknown}}, + {X86::PSRLDrm, {0, Unknown}}, + {X86::PSRLDrr, {0, Unknown}}, + {X86::PSRLQri, {0, Unknown}}, + {X86::PSRLQrm, {0, Unknown}}, + {X86::PSRLQrr, {0, Unknown}}, + {X86::PSRLWri, {0, Unknown}}, + {X86::PSRLWrm, {0, Unknown}}, + {X86::PSRLWrr, {0, Unknown}}, + {X86::PSUBBrm, {0, Unknown}}, + {X86::PSUBBrr, {0, Unknown}}, + {X86::PSUBDrm, {0, Unknown}}, + {X86::PSUBDrr, {0, Unknown}}, + {X86::PSUBQrm, {0, Unknown}}, + {X86::PSUBQrr, {0, Unknown}}, + {X86::PSUBSBrm, {0, Unknown}}, + {X86::PSUBSBrr, {0, Unknown}}, + {X86::PSUBSWrm, {0, Unknown}}, + {X86::PSUBSWrr, {0, Unknown}}, + {X86::PSUBUSBrm, {0, Unknown}}, + {X86::PSUBUSBrr, {0, Unknown}}, + {X86::PSUBUSWrm, {0, Unknown}}, + {X86::PSUBUSWrr, {0, Unknown}}, + {X86::PSUBWrm, {0, Unknown}}, + {X86::PSUBWrr, {0, Unknown}}, + {X86::PSWAPDrm, {0, Unknown}}, + {X86::PSWAPDrr, {0, Unknown}}, + {X86::PTESTrm, {0, Unknown}}, + {X86::PTESTrr, {0, Unknown}}, + {X86::PTWRITE64m, {0, Unknown}}, + {X86::PTWRITE64r, {0, Unknown}}, + {X86::PTWRITEm, {0, Unknown}}, + {X86::PTWRITEr, {0, Unknown}}, + {X86::PUNPCKHBWrm, {0, Unknown}}, + {X86::PUNPCKHBWrr, {0, Unknown}}, + {X86::PUNPCKHDQrm, {0, Unknown}}, + {X86::PUNPCKHDQrr, {0, Unknown}}, + {X86::PUNPCKHQDQrm, {0, Unknown}}, + {X86::PUNPCKHQDQrr, {0, Unknown}}, + {X86::PUNPCKHWDrm, {0, Unknown}}, + {X86::PUNPCKHWDrr, {0, Unknown}}, + {X86::PUNPCKLBWrm, {0, Unknown}}, + {X86::PUNPCKLBWrr, {0, Unknown}}, + {X86::PUNPCKLDQrm, {0, Unknown}}, + {X86::PUNPCKLDQrr, {0, Unknown}}, + {X86::PUNPCKLQDQrm, {0, Unknown}}, + {X86::PUNPCKLQDQrr, {0, Unknown}}, + {X86::PUNPCKLWDrm, {0, Unknown}}, + {X86::PUNPCKLWDrr, {0, Unknown}}, + {X86::PUSH16i8, {0, Unknown}}, + {X86::PUSH16r, {0, Unknown}}, + {X86::PUSH16rmm, {2, Unknown}}, + {X86::PUSH16rmr, {2, Unknown}}, + {X86::PUSH32i8, {0, Unknown}}, + {X86::PUSH32r, {0, Unknown}}, + {X86::PUSH32rmm, {4, Unknown}}, + {X86::PUSH32rmr, {4, Unknown}}, + {X86::PUSH64i32, {0, Unknown}}, + {X86::PUSH64i8, {0, Unknown}}, + {X86::PUSH64r, {0, Unknown}}, + {X86::PUSH64rmm, {8, Unknown}}, + {X86::PUSH64rmr, {8, Unknown}}, + {X86::PUSHA16, {0, Unknown}}, + {X86::PUSHA32, {0, Unknown}}, + {X86::PUSHCS16, {0, Unknown}}, + {X86::PUSHCS32, {0, Unknown}}, + {X86::PUSHDS16, {0, Unknown}}, + {X86::PUSHDS32, {0, Unknown}}, + {X86::PUSHES16, {0, Unknown}}, + {X86::PUSHES32, {0, Unknown}}, + {X86::PUSHF16, {0, Unknown}}, + {X86::PUSHF32, {0, Unknown}}, + {X86::PUSHF64, {0, Unknown}}, + {X86::PUSHFS16, {0, Unknown}}, + {X86::PUSHFS32, {0, Unknown}}, + {X86::PUSHFS64, {0, Unknown}}, + {X86::PUSHGS16, {0, Unknown}}, + {X86::PUSHGS32, {0, Unknown}}, + {X86::PUSHGS64, {0, Unknown}}, + {X86::PUSHSS16, {0, Unknown}}, + {X86::PUSHSS32, {0, Unknown}}, + {X86::PUSHi16, {0, Unknown}}, + {X86::PUSHi32, {0, Unknown}}, + {X86::PXORrm, {0, Unknown}}, + {X86::PXORrr, {0, Unknown}}, + {X86::RCL16m1, {0, Unknown}}, + {X86::RCL16mCL, {0, Unknown}}, + {X86::RCL16mi, {2, Unknown}}, + {X86::RCL16r1, {0, Unknown}}, + {X86::RCL16rCL, {0, Unknown}}, + {X86::RCL16ri, {0, Unknown}}, + {X86::RCL32m1, {0, Unknown}}, + {X86::RCL32mCL, {0, Unknown}}, + {X86::RCL32mi, {4, Unknown}}, + {X86::RCL32r1, {0, Unknown}}, + {X86::RCL32rCL, {0, Unknown}}, + {X86::RCL32ri, {0, Unknown}}, + {X86::RCL64m1, {0, Unknown}}, + {X86::RCL64mCL, {0, Unknown}}, + {X86::RCL64mi, {8, Unknown}}, + {X86::RCL64r1, {0, Unknown}}, + {X86::RCL64rCL, {0, Unknown}}, + {X86::RCL64ri, {0, Unknown}}, + {X86::RCL8m1, {0, Unknown}}, + {X86::RCL8mCL, {0, Unknown}}, + {X86::RCL8mi, {1, Unknown}}, + {X86::RCL8r1, {0, Unknown}}, + {X86::RCL8rCL, {0, Unknown}}, + {X86::RCL8ri, {0, Unknown}}, + {X86::RCPPSm, {0, Unknown}}, + {X86::RCPPSr, {0, Unknown}}, + {X86::RCPSSm, {0, Unknown}}, + {X86::RCPSSm_Int, {0, Unknown}}, + {X86::RCPSSr, {0, Unknown}}, + {X86::RCPSSr_Int, {0, Unknown}}, + {X86::RCR16m1, {0, Unknown}}, + {X86::RCR16mCL, {0, Unknown}}, + {X86::RCR16mi, {2, Unknown}}, + {X86::RCR16r1, {0, Unknown}}, + {X86::RCR16rCL, {0, Unknown}}, + {X86::RCR16ri, {0, Unknown}}, + {X86::RCR32m1, {0, Unknown}}, + {X86::RCR32mCL, {0, Unknown}}, + {X86::RCR32mi, {4, Unknown}}, + {X86::RCR32r1, {0, Unknown}}, + {X86::RCR32rCL, {0, Unknown}}, + {X86::RCR32ri, {0, Unknown}}, + {X86::RCR64m1, {0, Unknown}}, + {X86::RCR64mCL, {0, Unknown}}, + {X86::RCR64mi, {8, Unknown}}, + {X86::RCR64r1, {0, Unknown}}, + {X86::RCR64rCL, {0, Unknown}}, + {X86::RCR64ri, {0, Unknown}}, + {X86::RCR8m1, {0, Unknown}}, + {X86::RCR8mCL, {0, Unknown}}, + {X86::RCR8mi, {1, Unknown}}, + {X86::RCR8r1, {0, Unknown}}, + {X86::RCR8rCL, {0, Unknown}}, + {X86::RCR8ri, {0, Unknown}}, + {X86::RDFLAGS32, {0, Unknown}}, + {X86::RDFLAGS64, {0, Unknown}}, + {X86::RDFSBASE, {0, Unknown}}, + {X86::RDFSBASE64, {0, Unknown}}, + {X86::RDGSBASE, {0, Unknown}}, + {X86::RDGSBASE64, {0, Unknown}}, + {X86::RDMSR, {0, Unknown}}, + {X86::RDPID32, {0, Unknown}}, + {X86::RDPID64, {0, Unknown}}, + {X86::RDPKRU, {0, Unknown}}, + {X86::RDPKRUr, {0, Unknown}}, + {X86::RDPMC, {0, Unknown}}, + {X86::RDRAND16r, {0, Unknown}}, + {X86::RDRAND32r, {0, Unknown}}, + {X86::RDRAND64r, {0, Unknown}}, + {X86::RDSEED16r, {0, Unknown}}, + {X86::RDSEED32r, {0, Unknown}}, + {X86::RDSEED64r, {0, Unknown}}, + {X86::RDSSPD, {0, Unknown}}, + {X86::RDSSPQ, {0, Unknown}}, + {X86::RDTSC, {0, Unknown}}, + {X86::RDTSCP, {0, Unknown}}, + {X86::REG_SEQUENCE, {0, Unknown}}, + {X86::RELEASE_FADD32mr, {4, Unknown}}, + {X86::RELEASE_FADD64mr, {8, Unknown}}, + {X86::REPNE_PREFIX, {0, Unknown}}, + {X86::REP_MOVSB_32, {0, Unknown}}, + {X86::REP_MOVSB_64, {0, Unknown}}, + {X86::REP_MOVSD_32, {0, Unknown}}, + {X86::REP_MOVSD_64, {0, Unknown}}, + {X86::REP_MOVSQ_64, {0, Unknown}}, + {X86::REP_MOVSW_32, {0, Unknown}}, + {X86::REP_MOVSW_64, {0, Unknown}}, + {X86::REP_PREFIX, {0, Unknown}}, + {X86::REP_STOSB_32, {0, Unknown}}, + {X86::REP_STOSB_64, {0, Unknown}}, + {X86::REP_STOSD_32, {0, Unknown}}, + {X86::REP_STOSD_64, {0, Unknown}}, + {X86::REP_STOSQ_64, {0, Unknown}}, + {X86::REP_STOSW_32, {0, Unknown}}, + {X86::REP_STOSW_64, {0, Unknown}}, + {X86::RET, {0, Unknown}}, + {X86::RETIL, {0, Unknown}}, + {X86::RETIQ, {0, Unknown}}, + {X86::RETIW, {0, Unknown}}, + {X86::RETL, {0, Unknown}}, + {X86::RETPOLINE_CALL32, {0, Unknown}}, + {X86::RETPOLINE_CALL64, {0, Unknown}}, + {X86::RETPOLINE_TCRETURN32, {0, Unknown}}, + {X86::RETPOLINE_TCRETURN64, {0, Unknown}}, + {X86::RETQ, {0, Unknown}}, + {X86::RETW, {0, Unknown}}, + {X86::REX64_PREFIX, {0, Unknown}}, + {X86::ROL16m1, {0, Unknown}}, + {X86::ROL16mCL, {0, Unknown}}, + {X86::ROL16mi, {2, Unknown}}, + {X86::ROL16r1, {0, Unknown}}, + {X86::ROL16rCL, {0, Unknown}}, + {X86::ROL16ri, {0, Unknown}}, + {X86::ROL32m1, {0, Unknown}}, + {X86::ROL32mCL, {0, Unknown}}, + {X86::ROL32mi, {4, Unknown}}, + {X86::ROL32r1, {0, Unknown}}, + {X86::ROL32rCL, {0, Unknown}}, + {X86::ROL32ri, {0, Unknown}}, + {X86::ROL64m1, {0, Unknown}}, + {X86::ROL64mCL, {0, Unknown}}, + {X86::ROL64mi, {8, Unknown}}, + {X86::ROL64r1, {0, Unknown}}, + {X86::ROL64rCL, {0, Unknown}}, + {X86::ROL64ri, {0, Unknown}}, + {X86::ROL8m1, {0, Unknown}}, + {X86::ROL8mCL, {0, Unknown}}, + {X86::ROL8mi, {1, Unknown}}, + {X86::ROL8r1, {0, Unknown}}, + {X86::ROL8rCL, {0, Unknown}}, + {X86::ROL8ri, {0, Unknown}}, + {X86::ROR16m1, {0, Unknown}}, + {X86::ROR16mCL, {0, Unknown}}, + {X86::ROR16mi, {2, Unknown}}, + {X86::ROR16r1, {0, Unknown}}, + {X86::ROR16rCL, {0, Unknown}}, + {X86::ROR16ri, {0, Unknown}}, + {X86::ROR32m1, {0, Unknown}}, + {X86::ROR32mCL, {0, Unknown}}, + {X86::ROR32mi, {4, Unknown}}, + {X86::ROR32r1, {0, Unknown}}, + {X86::ROR32rCL, {0, Unknown}}, + {X86::ROR32ri, {0, Unknown}}, + {X86::ROR64m1, {0, Unknown}}, + {X86::ROR64mCL, {0, Unknown}}, + {X86::ROR64mi, {8, Unknown}}, + {X86::ROR64r1, {0, Unknown}}, + {X86::ROR64rCL, {0, Unknown}}, + {X86::ROR64ri, {0, Unknown}}, + {X86::ROR8m1, {0, Unknown}}, + {X86::ROR8mCL, {0, Unknown}}, + {X86::ROR8mi, {1, Unknown}}, + {X86::ROR8r1, {0, Unknown}}, + {X86::ROR8rCL, {0, Unknown}}, + {X86::ROR8ri, {0, Unknown}}, + {X86::RORX32mi, {4, Unknown}}, + {X86::RORX32ri, {0, Unknown}}, + {X86::RORX64mi, {8, Unknown}}, + {X86::RORX64ri, {0, Unknown}}, + {X86::ROUNDPDm, {0, Unknown}}, + {X86::ROUNDPDr, {0, Unknown}}, + {X86::ROUNDPSm, {0, Unknown}}, + {X86::ROUNDPSr, {0, Unknown}}, + {X86::ROUNDSDm, {0, Unknown}}, + {X86::ROUNDSDm_Int, {0, Unknown}}, + {X86::ROUNDSDr, {0, Unknown}}, + {X86::ROUNDSDr_Int, {0, Unknown}}, + {X86::ROUNDSSm, {0, Unknown}}, + {X86::ROUNDSSm_Int, {0, Unknown}}, + {X86::ROUNDSSr, {0, Unknown}}, + {X86::ROUNDSSr_Int, {0, Unknown}}, + {X86::RSM, {0, Unknown}}, + {X86::RSQRTPSm, {0, Unknown}}, + {X86::RSQRTPSr, {0, Unknown}}, + {X86::RSQRTSSm, {0, Unknown}}, + {X86::RSQRTSSm_Int, {0, Unknown}}, + {X86::RSQRTSSr, {0, Unknown}}, + {X86::RSQRTSSr_Int, {0, Unknown}}, + {X86::RSTORSSP, {0, Unknown}}, + {X86::SAHF, {0, Unknown}}, + {X86::SALC, {0, Unknown}}, + {X86::SAR16m1, {0, Unknown}}, + {X86::SAR16mCL, {0, Unknown}}, + {X86::SAR16mi, {2, Unknown}}, + {X86::SAR16r1, {0, Unknown}}, + {X86::SAR16rCL, {0, Unknown}}, + {X86::SAR16ri, {0, Unknown}}, + {X86::SAR32m1, {0, Unknown}}, + {X86::SAR32mCL, {0, Unknown}}, + {X86::SAR32mi, {4, Unknown}}, + {X86::SAR32r1, {0, Unknown}}, + {X86::SAR32rCL, {0, Unknown}}, + {X86::SAR32ri, {0, Unknown}}, + {X86::SAR64m1, {0, Unknown}}, + {X86::SAR64mCL, {0, Unknown}}, + {X86::SAR64mi, {8, Unknown}}, + {X86::SAR64r1, {0, Unknown}}, + {X86::SAR64rCL, {0, Unknown}}, + {X86::SAR64ri, {0, Unknown}}, + {X86::SAR8m1, {0, Unknown}}, + {X86::SAR8mCL, {0, Unknown}}, + {X86::SAR8mi, {1, Unknown}}, + {X86::SAR8r1, {0, Unknown}}, + {X86::SAR8rCL, {0, Unknown}}, + {X86::SAR8ri, {0, Unknown}}, + {X86::SARX32rm, {4, Unknown}}, + {X86::SARX32rr, {0, Unknown}}, + {X86::SARX64rm, {8, Unknown}}, + {X86::SARX64rr, {0, Unknown}}, + {X86::SAVEPREVSSP, {0, Unknown}}, + {X86::SBB16i16, {0, Unknown}}, + {X86::SBB16mi, {2, Unknown}}, + {X86::SBB16mi8, {2, Unknown}}, + {X86::SBB16mr, {2, Unknown}}, + {X86::SBB16ri, {0, Unknown}}, + {X86::SBB16ri8, {0, Unknown}}, + {X86::SBB16rm, {2, Unknown}}, + {X86::SBB16rr, {0, Unknown}}, + {X86::SBB16rr_REV, {0, Unknown}}, + {X86::SBB32i32, {0, Unknown}}, + {X86::SBB32mi, {4, Unknown}}, + {X86::SBB32mi8, {4, Unknown}}, + {X86::SBB32mr, {4, Unknown}}, + {X86::SBB32ri, {0, Unknown}}, + {X86::SBB32ri8, {0, Unknown}}, + {X86::SBB32rm, {4, Unknown}}, + {X86::SBB32rr, {0, Unknown}}, + {X86::SBB32rr_REV, {0, Unknown}}, + {X86::SBB64i32, {0, Unknown}}, + {X86::SBB64mi32, {8, Unknown}}, + {X86::SBB64mi8, {8, Unknown}}, + {X86::SBB64mr, {8, Unknown}}, + {X86::SBB64ri32, {0, Unknown}}, + {X86::SBB64ri8, {0, Unknown}}, + {X86::SBB64rm, {8, Unknown}}, + {X86::SBB64rr, {0, Unknown}}, + {X86::SBB64rr_REV, {0, Unknown}}, + {X86::SBB8i8, {0, Unknown}}, + {X86::SBB8mi, {1, Unknown}}, + {X86::SBB8mi8, {1, Unknown}}, + {X86::SBB8mr, {1, Unknown}}, + {X86::SBB8ri, {0, Unknown}}, + {X86::SBB8ri8, {0, Unknown}}, + {X86::SBB8rm, {1, Unknown}}, + {X86::SBB8rr, {0, Unknown}}, + {X86::SBB8rr_REV, {0, Unknown}}, + {X86::SCASB, {0, Unknown}}, + {X86::SCASL, {0, Unknown}}, + {X86::SCASQ, {0, Unknown}}, + {X86::SCASW, {0, Unknown}}, + {X86::SEG_ALLOCA_32, {0, Unknown}}, + {X86::SEG_ALLOCA_64, {0, Unknown}}, + {X86::SEH_EndPrologue, {0, Unknown}}, + {X86::SEH_Epilogue, {0, Unknown}}, + {X86::SEH_PushFrame, {0, Unknown}}, + {X86::SEH_PushReg, {0, Unknown}}, + {X86::SEH_SaveReg, {0, Unknown}}, + {X86::SEH_SaveXMM, {0, Unknown}}, + {X86::SEH_SetFrame, {0, Unknown}}, + {X86::SEH_StackAlloc, {0, Unknown}}, + {X86::SETAEm, {0, SETCC}}, + {X86::SETAEr, {0, SETCC}}, + {X86::SETAm, {0, SETCC}}, + {X86::SETAr, {0, SETCC}}, + {X86::SETBEm, {0, SETCC}}, + {X86::SETBEr, {0, SETCC}}, + {X86::SETB_C16r, {0, SETCC}}, + {X86::SETB_C32r, {0, SETCC}}, + {X86::SETB_C64r, {0, SETCC}}, + {X86::SETB_C8r, {0, SETCC}}, + {X86::SETBm, {0, SETCC}}, + {X86::SETBr, {0, SETCC}}, + {X86::SETEm, {0, SETCC}}, + {X86::SETEr, {0, SETCC}}, + {X86::SETGEm, {0, SETCC}}, + {X86::SETGEr, {0, SETCC}}, + {X86::SETGm, {0, SETCC}}, + {X86::SETGr, {0, SETCC}}, + {X86::SETLEm, {0, SETCC}}, + {X86::SETLEr, {0, SETCC}}, + {X86::SETLm, {0, SETCC}}, + {X86::SETLr, {0, SETCC}}, + {X86::SETNEm, {0, SETCC}}, + {X86::SETNEr, {0, SETCC}}, + {X86::SETNOm, {0, SETCC}}, + {X86::SETNOr, {0, SETCC}}, + {X86::SETNPm, {0, SETCC}}, + {X86::SETNPr, {0, SETCC}}, + {X86::SETNSm, {0, SETCC}}, + {X86::SETNSr, {0, SETCC}}, + {X86::SETOm, {0, SETCC}}, + {X86::SETOr, {0, SETCC}}, + {X86::SETPm, {0, SETCC}}, + {X86::SETPr, {0, SETCC}}, + {X86::SETSSBSY, {0, SETCC}}, + {X86::SETSm, {0, SETCC}}, + {X86::SETSr, {0, SETCC}}, + {X86::SFENCE, {0, Unknown}}, + {X86::SGDT16m, {0, Unknown}}, + {X86::SGDT32m, {0, Unknown}}, + {X86::SGDT64m, {0, Unknown}}, + {X86::SHA1MSG1rm, {0, Unknown}}, + {X86::SHA1MSG1rr, {0, Unknown}}, + {X86::SHA1MSG2rm, {0, Unknown}}, + {X86::SHA1MSG2rr, {0, Unknown}}, + {X86::SHA1NEXTErm, {0, Unknown}}, + {X86::SHA1NEXTErr, {0, Unknown}}, + {X86::SHA1RNDS4rmi, {0, Unknown}}, + {X86::SHA1RNDS4rri, {0, Unknown}}, + {X86::SHA256MSG1rm, {0, Unknown}}, + {X86::SHA256MSG1rr, {0, Unknown}}, + {X86::SHA256MSG2rm, {0, Unknown}}, + {X86::SHA256MSG2rr, {0, Unknown}}, + {X86::SHA256RNDS2rm, {0, Unknown}}, + {X86::SHA256RNDS2rr, {0, Unknown}}, + {X86::SHL16m1, {0, Unknown}}, + {X86::SHL16mCL, {0, Unknown}}, + {X86::SHL16mi, {2, Unknown}}, + {X86::SHL16r1, {0, Unknown}}, + {X86::SHL16rCL, {0, Unknown}}, + {X86::SHL16ri, {0, Unknown}}, + {X86::SHL32m1, {0, Unknown}}, + {X86::SHL32mCL, {0, Unknown}}, + {X86::SHL32mi, {4, Unknown}}, + {X86::SHL32r1, {0, Unknown}}, + {X86::SHL32rCL, {0, Unknown}}, + {X86::SHL32ri, {0, Unknown}}, + {X86::SHL64m1, {0, Unknown}}, + {X86::SHL64mCL, {0, Unknown}}, + {X86::SHL64mi, {8, Unknown}}, + {X86::SHL64r1, {0, Unknown}}, + {X86::SHL64rCL, {0, Unknown}}, + {X86::SHL64ri, {0, Unknown}}, + {X86::SHL8m1, {0, Unknown}}, + {X86::SHL8mCL, {0, Unknown}}, + {X86::SHL8mi, {1, Unknown}}, + {X86::SHL8r1, {0, Unknown}}, + {X86::SHL8rCL, {0, Unknown}}, + {X86::SHL8ri, {0, Unknown}}, + {X86::SHLD16mrCL, {2, Unknown}}, + {X86::SHLD16mri8, {2, Unknown}}, + {X86::SHLD16rrCL, {0, Unknown}}, + {X86::SHLD16rri8, {0, Unknown}}, + {X86::SHLD32mrCL, {4, Unknown}}, + {X86::SHLD32mri8, {4, Unknown}}, + {X86::SHLD32rrCL, {0, Unknown}}, + {X86::SHLD32rri8, {0, Unknown}}, + {X86::SHLD64mrCL, {8, Unknown}}, + {X86::SHLD64mri8, {8, Unknown}}, + {X86::SHLD64rrCL, {0, Unknown}}, + {X86::SHLD64rri8, {0, Unknown}}, + {X86::SHLX32rm, {4, Unknown}}, + {X86::SHLX32rr, {0, Unknown}}, + {X86::SHLX64rm, {8, Unknown}}, + {X86::SHLX64rr, {0, Unknown}}, + {X86::SHR16m1, {0, Unknown}}, + {X86::SHR16mCL, {0, Unknown}}, + {X86::SHR16mi, {2, Unknown}}, + {X86::SHR16r1, {0, Unknown}}, + {X86::SHR16rCL, {0, Unknown}}, + {X86::SHR16ri, {0, Unknown}}, + {X86::SHR32m1, {0, Unknown}}, + {X86::SHR32mCL, {0, Unknown}}, + {X86::SHR32mi, {4, Unknown}}, + {X86::SHR32r1, {0, Unknown}}, + {X86::SHR32rCL, {0, Unknown}}, + {X86::SHR32ri, {0, Unknown}}, + {X86::SHR64m1, {0, Unknown}}, + {X86::SHR64mCL, {0, Unknown}}, + {X86::SHR64mi, {8, Unknown}}, + {X86::SHR64r1, {0, Unknown}}, + {X86::SHR64rCL, {0, Unknown}}, + {X86::SHR64ri, {0, Unknown}}, + {X86::SHR8m1, {0, Unknown}}, + {X86::SHR8mCL, {0, Unknown}}, + {X86::SHR8mi, {1, Unknown}}, + {X86::SHR8r1, {0, Unknown}}, + {X86::SHR8rCL, {0, Unknown}}, + {X86::SHR8ri, {0, Unknown}}, + {X86::SHRD16mrCL, {2, Unknown}}, + {X86::SHRD16mri8, {2, Unknown}}, + {X86::SHRD16rrCL, {0, Unknown}}, + {X86::SHRD16rri8, {0, Unknown}}, + {X86::SHRD32mrCL, {4, Unknown}}, + {X86::SHRD32mri8, {4, Unknown}}, + {X86::SHRD32rrCL, {0, Unknown}}, + {X86::SHRD32rri8, {0, Unknown}}, + {X86::SHRD64mrCL, {8, Unknown}}, + {X86::SHRD64mri8, {8, Unknown}}, + {X86::SHRD64rrCL, {0, Unknown}}, + {X86::SHRD64rri8, {0, Unknown}}, + {X86::SHRX32rm, {4, Unknown}}, + {X86::SHRX32rr, {0, Unknown}}, + {X86::SHRX64rm, {8, Unknown}}, + {X86::SHRX64rr, {0, Unknown}}, + {X86::SHUFPDrmi, {0, Unknown}}, + {X86::SHUFPDrri, {0, Unknown}}, + {X86::SHUFPSrmi, {0, Unknown}}, + {X86::SHUFPSrri, {0, Unknown}}, + {X86::SIDT16m, {0, Unknown}}, + {X86::SIDT32m, {0, Unknown}}, + {X86::SIDT64m, {0, Unknown}}, + {X86::SIN_F, {0, Unknown}}, + {X86::SIN_Fp32, {0, Unknown}}, + {X86::SIN_Fp64, {0, Unknown}}, + {X86::SIN_Fp80, {0, Unknown}}, + {X86::SKINIT, {0, Unknown}}, + {X86::SLDT16m, {0, Unknown}}, + {X86::SLDT16r, {0, Unknown}}, + {X86::SLDT32r, {0, Unknown}}, + {X86::SLWPCB, {0, Unknown}}, + {X86::SLWPCB64, {0, Unknown}}, + {X86::SMSW16m, {0, Unknown}}, + {X86::SMSW16r, {0, Unknown}}, + {X86::SMSW32r, {0, Unknown}}, + {X86::SMSW64r, {0, Unknown}}, + {X86::SQRTPDm, {0, Unknown}}, + {X86::SQRTPDr, {0, Unknown}}, + {X86::SQRTPSm, {0, Unknown}}, + {X86::SQRTPSr, {0, Unknown}}, + {X86::SQRTSDm, {0, Unknown}}, + {X86::SQRTSDm_Int, {0, Unknown}}, + {X86::SQRTSDr, {0, Unknown}}, + {X86::SQRTSDr_Int, {0, Unknown}}, + {X86::SQRTSSm, {0, Unknown}}, + {X86::SQRTSSm_Int, {0, Unknown}}, + {X86::SQRTSSr, {0, Unknown}}, + {X86::SQRTSSr_Int, {0, Unknown}}, + {X86::SQRT_F, {0, Unknown}}, + {X86::SQRT_Fp32, {0, Unknown}}, + {X86::SQRT_Fp64, {0, Unknown}}, + {X86::SQRT_Fp80, {0, Unknown}}, + {X86::SS_PREFIX, {0, Unknown}}, + {X86::STAC, {0, Unknown}}, + {X86::STACKMAP, {0, Unknown}}, + {X86::STATEPOINT, {0, Unknown}}, + {X86::STC, {0, Unknown}}, + {X86::STD, {0, Unknown}}, + {X86::STGI, {0, Unknown}}, + {X86::STI, {0, Unknown}}, + {X86::STMXCSR, {0, Unknown}}, + {X86::STOSB, {0, Unknown}}, + {X86::STOSL, {0, Unknown}}, + {X86::STOSQ, {0, Unknown}}, + {X86::STOSW, {0, Unknown}}, + {X86::STR16r, {0, Unknown}}, + {X86::STR32r, {0, Unknown}}, + {X86::STR64r, {0, Unknown}}, + {X86::STRm, {0, Unknown}}, + {X86::ST_F32m, {0, Unknown}}, + {X86::ST_F64m, {0, Unknown}}, + {X86::ST_FP32m, {4, STORE_FPU_REG}}, + {X86::ST_FP64m, {8, STORE_FPU_REG}}, + {X86::ST_FP80m, {0, Unknown}}, + {X86::ST_FPrr, {0, Unknown}}, + {X86::ST_Fp32m, {0, Unknown}}, + {X86::ST_Fp64m, {0, Unknown}}, + {X86::ST_Fp64m32, {0, Unknown}}, + {X86::ST_Fp80m32, {0, Unknown}}, + {X86::ST_Fp80m64, {0, Unknown}}, + {X86::ST_FpP32m, {0, Unknown}}, + {X86::ST_FpP64m, {0, Unknown}}, + {X86::ST_FpP64m32, {0, Unknown}}, + {X86::ST_FpP80m, {0, Unknown}}, + {X86::ST_FpP80m32, {0, Unknown}}, + {X86::ST_FpP80m64, {0, Unknown}}, + {X86::ST_Frr, {0, Unknown}}, + {X86::SUB16i16, {0, Unknown}}, + {X86::SUB16mi, {2, Unknown}}, + {X86::SUB16mi8, {2, Unknown}}, + {X86::SUB16mr, {2, Unknown}}, + {X86::SUB16ri, {0, Unknown}}, + {X86::SUB16ri8, {0, Unknown}}, + {X86::SUB16rm, {2, Unknown}}, + {X86::SUB16rr, {0, Unknown}}, + {X86::SUB16rr_REV, {0, Unknown}}, + {X86::SUB32i32, {0, Unknown}}, + {X86::SUB32mi, {4, Unknown}}, + {X86::SUB32mi8, {4, Unknown}}, + {X86::SUB32mr, {4, Unknown}}, + {X86::SUB32ri, {0, BINARY_OP_WITH_IMM}}, + {X86::SUB32ri8, {0, BINARY_OP_WITH_IMM}}, + {X86::SUB32rm, {4, Unknown}}, + {X86::SUB32rr, {0, COMPARE}}, + {X86::SUB32rr_REV, {0, Unknown}}, + {X86::SUB64i32, {0, Unknown}}, + {X86::SUB64mi32, {8, Unknown}}, + {X86::SUB64mi8, {8, Unknown}}, + {X86::SUB64mr, {8, Unknown}}, + {X86::SUB64ri32, {0, BINARY_OP_WITH_IMM}}, + {X86::SUB64ri8, {0, BINARY_OP_WITH_IMM}}, + {X86::SUB64rm, {8, Unknown}}, + {X86::SUB64rr, {0, Unknown}}, + {X86::SUB64rr_REV, {0, Unknown}}, + {X86::SUB8i8, {0, Unknown}}, + {X86::SUB8mi, {1, Unknown}}, + {X86::SUB8mi8, {1, Unknown}}, + {X86::SUB8mr, {1, Unknown}}, + {X86::SUB8ri, {0, Unknown}}, + {X86::SUB8ri8, {0, Unknown}}, + {X86::SUB8rm, {1, Unknown}}, + {X86::SUB8rr, {0, Unknown}}, + {X86::SUB8rr_REV, {0, Unknown}}, + {X86::SUBPDrm, {0, Unknown}}, + {X86::SUBPDrr, {0, Unknown}}, + {X86::SUBPSrm, {0, Unknown}}, + {X86::SUBPSrr, {0, Unknown}}, + {X86::SUBREG_TO_REG, {0, Unknown}}, + {X86::SUBR_F32m, {0, Unknown}}, + {X86::SUBR_F64m, {0, Unknown}}, + {X86::SUBR_FI16m, {0, Unknown}}, + {X86::SUBR_FI32m, {0, Unknown}}, + {X86::SUBR_FPrST0, {0, Unknown}}, + {X86::SUBR_FST0r, {0, Unknown}}, + {X86::SUBR_Fp32m, {0, Unknown}}, + {X86::SUBR_Fp64m, {0, Unknown}}, + {X86::SUBR_Fp64m32, {0, Unknown}}, + {X86::SUBR_Fp80m32, {0, Unknown}}, + {X86::SUBR_Fp80m64, {0, Unknown}}, + {X86::SUBR_FpI16m32, {0, Unknown}}, + {X86::SUBR_FpI16m64, {0, Unknown}}, + {X86::SUBR_FpI16m80, {0, Unknown}}, + {X86::SUBR_FpI32m32, {0, Unknown}}, + {X86::SUBR_FpI32m64, {0, Unknown}}, + {X86::SUBR_FpI32m80, {0, Unknown}}, + {X86::SUBR_FrST0, {0, Unknown}}, + {X86::SUBSDrm, {0, Unknown}}, + {X86::SUBSDrm_Int, {0, Unknown}}, + {X86::SUBSDrr, {0, Unknown}}, + {X86::SUBSDrr_Int, {0, Unknown}}, + {X86::SUBSSrm, {0, Unknown}}, + {X86::SUBSSrm_Int, {0, Unknown}}, + {X86::SUBSSrr, {0, Unknown}}, + {X86::SUBSSrr_Int, {0, Unknown}}, + {X86::SUB_F32m, {0, Unknown}}, + {X86::SUB_F64m, {0, Unknown}}, + {X86::SUB_FI16m, {0, Unknown}}, + {X86::SUB_FI32m, {0, Unknown}}, + {X86::SUB_FPrST0, {0, Unknown}}, + {X86::SUB_FST0r, {0, Unknown}}, + {X86::SUB_Fp32, {0, Unknown}}, + {X86::SUB_Fp32m, {0, Unknown}}, + {X86::SUB_Fp64, {0, Unknown}}, + {X86::SUB_Fp64m, {0, Unknown}}, + {X86::SUB_Fp64m32, {0, Unknown}}, + {X86::SUB_Fp80, {0, Unknown}}, + {X86::SUB_Fp80m32, {0, Unknown}}, + {X86::SUB_Fp80m64, {0, Unknown}}, + {X86::SUB_FpI16m32, {0, Unknown}}, + {X86::SUB_FpI16m64, {0, Unknown}}, + {X86::SUB_FpI16m80, {0, Unknown}}, + {X86::SUB_FpI32m32, {0, Unknown}}, + {X86::SUB_FpI32m64, {0, Unknown}}, + {X86::SUB_FpI32m80, {0, Unknown}}, + {X86::SUB_FrST0, {0, Unknown}}, + {X86::SWAPGS, {0, Unknown}}, + {X86::SYSCALL, {0, Unknown}}, + {X86::SYSENTER, {0, Unknown}}, + {X86::SYSEXIT, {0, Unknown}}, + {X86::SYSEXIT64, {0, Unknown}}, + {X86::SYSRET, {0, Unknown}}, + {X86::SYSRET64, {0, Unknown}}, + {X86::T1MSKC32rm, {4, Unknown}}, + {X86::T1MSKC32rr, {0, Unknown}}, + {X86::T1MSKC64rm, {8, Unknown}}, + {X86::T1MSKC64rr, {0, Unknown}}, + {X86::TAILJMPd, {0, Unknown}}, + {X86::TAILJMPd64, {0, Unknown}}, + {X86::TAILJMPd64_CC, {0, Unknown}}, + {X86::TAILJMPd_CC, {0, Unknown}}, + {X86::TAILJMPm, {0, Unknown}}, + {X86::TAILJMPm64, {0, Unknown}}, + {X86::TAILJMPm64_REX, {0, Unknown}}, + {X86::TAILJMPr, {0, Unknown}}, + {X86::TAILJMPr64, {0, Unknown}}, + {X86::TAILJMPr64_REX, {0, Unknown}}, + {X86::TCRETURNdi, {0, Unknown}}, + {X86::TCRETURNdi64, {0, Unknown}}, + {X86::TCRETURNdi64cc, {0, Unknown}}, + {X86::TCRETURNdicc, {0, Unknown}}, + {X86::TCRETURNmi, {0, Unknown}}, + {X86::TCRETURNmi64, {0, Unknown}}, + {X86::TCRETURNri, {0, Unknown}}, + {X86::TCRETURNri64, {0, Unknown}}, + {X86::TEST16i16, {0, Unknown}}, + {X86::TEST16mi, {2, Unknown}}, + {X86::TEST16mr, {2, Unknown}}, + {X86::TEST16ri, {0, Unknown}}, + {X86::TEST16rr, {0, Unknown}}, + {X86::TEST32i32, {0, Unknown}}, + {X86::TEST32mi, {4, Unknown}}, + {X86::TEST32mr, {4, Unknown}}, + {X86::TEST32ri, {0, Unknown}}, + {X86::TEST32rr, {0, BINARY_OP_RR}}, + {X86::TEST64i32, {0, Unknown}}, + {X86::TEST64mi32, {8, Unknown}}, + {X86::TEST64mr, {8, Unknown}}, + {X86::TEST64ri32, {0, Unknown}}, + {X86::TEST64rr, {0, BINARY_OP_RR}}, + {X86::TEST8i8, {0, Unknown}}, + {X86::TEST8mi, {1, Unknown}}, + {X86::TEST8mr, {1, Unknown}}, + {X86::TEST8ri, {0, Unknown}}, + {X86::TEST8rr, {0, Unknown}}, + {X86::TLSCall_32, {0, Unknown}}, + {X86::TLSCall_64, {0, Unknown}}, + {X86::TLS_addr32, {0, Unknown}}, + {X86::TLS_addr64, {0, Unknown}}, + {X86::TLS_base_addr32, {0, Unknown}}, + {X86::TLS_base_addr64, {0, Unknown}}, + {X86::TRAP, {0, Unknown}}, + {X86::TST_F, {0, Unknown}}, + {X86::TST_Fp32, {0, Unknown}}, + {X86::TST_Fp64, {0, Unknown}}, + {X86::TST_Fp80, {0, Unknown}}, + {X86::TZCNT16rm, {2, Unknown}}, + {X86::TZCNT16rr, {0, Unknown}}, + {X86::TZCNT32rm, {4, Unknown}}, + {X86::TZCNT32rr, {0, Unknown}}, + {X86::TZCNT64rm, {8, Unknown}}, + {X86::TZCNT64rr, {0, Unknown}}, + {X86::TZMSK32rm, {4, Unknown}}, + {X86::TZMSK32rr, {0, Unknown}}, + {X86::TZMSK64rm, {8, Unknown}}, + {X86::TZMSK64rr, {0, Unknown}}, + {X86::UCOMISDrm, {0, Unknown}}, + {X86::UCOMISDrm_Int, {0, Unknown}}, + {X86::UCOMISDrr, {0, Unknown}}, + {X86::UCOMISDrr_Int, {0, Unknown}}, + {X86::UCOMISSrm, {0, Unknown}}, + {X86::UCOMISSrm_Int, {0, Unknown}}, + {X86::UCOMISSrr, {0, Unknown}}, + {X86::UCOMISSrr_Int, {0, Unknown}}, + {X86::UCOM_FIPr, {0, Unknown}}, + {X86::UCOM_FIr, {0, Unknown}}, + {X86::UCOM_FPPr, {0, Unknown}}, + {X86::UCOM_FPr, {0, Unknown}}, + {X86::UCOM_FpIr32, {0, Unknown}}, + {X86::UCOM_FpIr64, {0, Unknown}}, + {X86::UCOM_FpIr80, {0, Unknown}}, + {X86::UCOM_Fpr32, {0, Unknown}}, + {X86::UCOM_Fpr64, {0, Unknown}}, + {X86::UCOM_Fpr80, {0, Unknown}}, + {X86::UCOM_Fr, {0, Unknown}}, + {X86::UD2B, {0, Unknown}}, + {X86::UNPCKHPDrm, {0, Unknown}}, + {X86::UNPCKHPDrr, {0, Unknown}}, + {X86::UNPCKHPSrm, {0, Unknown}}, + {X86::UNPCKHPSrr, {0, Unknown}}, + {X86::UNPCKLPDrm, {0, Unknown}}, + {X86::UNPCKLPDrr, {0, Unknown}}, + {X86::UNPCKLPSrm, {0, Unknown}}, + {X86::UNPCKLPSrr, {0, Unknown}}, + {X86::VAARG_64, {0, Unknown}}, + {X86::VADDPDYrm, {0, Unknown}}, + {X86::VADDPDYrr, {0, Unknown}}, + {X86::VADDPDZ128rm, {1, Unknown}}, + {X86::VADDPDZ128rmb, {1, Unknown}}, + {X86::VADDPDZ128rmbk, {1, Unknown}}, + {X86::VADDPDZ128rmbkz, {1, Unknown}}, + {X86::VADDPDZ128rmk, {1, Unknown}}, + {X86::VADDPDZ128rmkz, {1, Unknown}}, + {X86::VADDPDZ128rr, {0, Unknown}}, + {X86::VADDPDZ128rrk, {0, Unknown}}, + {X86::VADDPDZ128rrkz, {0, Unknown}}, + {X86::VADDPDZ256rm, {0, Unknown}}, + {X86::VADDPDZ256rmb, {0, Unknown}}, + {X86::VADDPDZ256rmbk, {0, Unknown}}, + {X86::VADDPDZ256rmbkz, {0, Unknown}}, + {X86::VADDPDZ256rmk, {0, Unknown}}, + {X86::VADDPDZ256rmkz, {0, Unknown}}, + {X86::VADDPDZ256rr, {0, Unknown}}, + {X86::VADDPDZ256rrk, {0, Unknown}}, + {X86::VADDPDZ256rrkz, {0, Unknown}}, + {X86::VADDPDZrm, {0, Unknown}}, + {X86::VADDPDZrmb, {0, Unknown}}, + {X86::VADDPDZrmbk, {0, Unknown}}, + {X86::VADDPDZrmbkz, {0, Unknown}}, + {X86::VADDPDZrmk, {0, Unknown}}, + {X86::VADDPDZrmkz, {0, Unknown}}, + {X86::VADDPDZrr, {0, Unknown}}, + {X86::VADDPDZrrb, {0, Unknown}}, + {X86::VADDPDZrrbk, {0, Unknown}}, + {X86::VADDPDZrrbkz, {0, Unknown}}, + {X86::VADDPDZrrk, {0, Unknown}}, + {X86::VADDPDZrrkz, {0, Unknown}}, + {X86::VADDPDrm, {0, Unknown}}, + {X86::VADDPDrr, {0, Unknown}}, + {X86::VADDPSYrm, {0, Unknown}}, + {X86::VADDPSYrr, {0, Unknown}}, + {X86::VADDPSZ128rm, {1, Unknown}}, + {X86::VADDPSZ128rmb, {1, Unknown}}, + {X86::VADDPSZ128rmbk, {1, Unknown}}, + {X86::VADDPSZ128rmbkz, {1, Unknown}}, + {X86::VADDPSZ128rmk, {1, Unknown}}, + {X86::VADDPSZ128rmkz, {1, Unknown}}, + {X86::VADDPSZ128rr, {0, Unknown}}, + {X86::VADDPSZ128rrk, {0, Unknown}}, + {X86::VADDPSZ128rrkz, {0, Unknown}}, + {X86::VADDPSZ256rm, {0, Unknown}}, + {X86::VADDPSZ256rmb, {0, Unknown}}, + {X86::VADDPSZ256rmbk, {0, Unknown}}, + {X86::VADDPSZ256rmbkz, {0, Unknown}}, + {X86::VADDPSZ256rmk, {0, Unknown}}, + {X86::VADDPSZ256rmkz, {0, Unknown}}, + {X86::VADDPSZ256rr, {0, Unknown}}, + {X86::VADDPSZ256rrk, {0, Unknown}}, + {X86::VADDPSZ256rrkz, {0, Unknown}}, + {X86::VADDPSZrm, {0, Unknown}}, + {X86::VADDPSZrmb, {0, Unknown}}, + {X86::VADDPSZrmbk, {0, Unknown}}, + {X86::VADDPSZrmbkz, {0, Unknown}}, + {X86::VADDPSZrmk, {0, Unknown}}, + {X86::VADDPSZrmkz, {0, Unknown}}, + {X86::VADDPSZrr, {0, Unknown}}, + {X86::VADDPSZrrb, {0, Unknown}}, + {X86::VADDPSZrrbk, {0, Unknown}}, + {X86::VADDPSZrrbkz, {0, Unknown}}, + {X86::VADDPSZrrk, {0, Unknown}}, + {X86::VADDPSZrrkz, {0, Unknown}}, + {X86::VADDPSrm, {0, Unknown}}, + {X86::VADDPSrr, {0, Unknown}}, + {X86::VADDSDZrm, {0, Unknown}}, + {X86::VADDSDZrm_Int, {0, Unknown}}, + {X86::VADDSDZrm_Intk, {0, Unknown}}, + {X86::VADDSDZrm_Intkz, {0, Unknown}}, + {X86::VADDSDZrr, {0, Unknown}}, + {X86::VADDSDZrr_Int, {0, Unknown}}, + {X86::VADDSDZrr_Intk, {0, Unknown}}, + {X86::VADDSDZrr_Intkz, {0, Unknown}}, + {X86::VADDSDZrrb_Int, {0, Unknown}}, + {X86::VADDSDZrrb_Intk, {0, Unknown}}, + {X86::VADDSDZrrb_Intkz, {0, Unknown}}, + {X86::VADDSDrm, {0, Unknown}}, + {X86::VADDSDrm_Int, {0, Unknown}}, + {X86::VADDSDrr, {0, Unknown}}, + {X86::VADDSDrr_Int, {0, Unknown}}, + {X86::VADDSSZrm, {0, Unknown}}, + {X86::VADDSSZrm_Int, {0, Unknown}}, + {X86::VADDSSZrm_Intk, {0, Unknown}}, + {X86::VADDSSZrm_Intkz, {0, Unknown}}, + {X86::VADDSSZrr, {0, Unknown}}, + {X86::VADDSSZrr_Int, {0, Unknown}}, + {X86::VADDSSZrr_Intk, {0, Unknown}}, + {X86::VADDSSZrr_Intkz, {0, Unknown}}, + {X86::VADDSSZrrb_Int, {0, Unknown}}, + {X86::VADDSSZrrb_Intk, {0, Unknown}}, + {X86::VADDSSZrrb_Intkz, {0, Unknown}}, + {X86::VADDSSrm, {0, Unknown}}, + {X86::VADDSSrm_Int, {0, Unknown}}, + {X86::VADDSSrr, {0, Unknown}}, + {X86::VADDSSrr_Int, {0, Unknown}}, + {X86::VADDSUBPDYrm, {0, Unknown}}, + {X86::VADDSUBPDYrr, {0, Unknown}}, + {X86::VADDSUBPDrm, {0, Unknown}}, + {X86::VADDSUBPDrr, {0, Unknown}}, + {X86::VADDSUBPSYrm, {0, Unknown}}, + {X86::VADDSUBPSYrr, {0, Unknown}}, + {X86::VADDSUBPSrm, {0, Unknown}}, + {X86::VADDSUBPSrr, {0, Unknown}}, + {X86::VAESDECLASTYrm, {0, Unknown}}, + {X86::VAESDECLASTYrr, {0, Unknown}}, + {X86::VAESDECLASTZ128rm, {1, Unknown}}, + {X86::VAESDECLASTZ128rr, {0, Unknown}}, + {X86::VAESDECLASTZ256rm, {0, Unknown}}, + {X86::VAESDECLASTZ256rr, {0, Unknown}}, + {X86::VAESDECLASTZrm, {0, Unknown}}, + {X86::VAESDECLASTZrr, {0, Unknown}}, + {X86::VAESDECLASTrm, {0, Unknown}}, + {X86::VAESDECLASTrr, {0, Unknown}}, + {X86::VAESDECYrm, {0, Unknown}}, + {X86::VAESDECYrr, {0, Unknown}}, + {X86::VAESDECZ128rm, {1, Unknown}}, + {X86::VAESDECZ128rr, {0, Unknown}}, + {X86::VAESDECZ256rm, {0, Unknown}}, + {X86::VAESDECZ256rr, {0, Unknown}}, + {X86::VAESDECZrm, {0, Unknown}}, + {X86::VAESDECZrr, {0, Unknown}}, + {X86::VAESDECrm, {0, Unknown}}, + {X86::VAESDECrr, {0, Unknown}}, + {X86::VAESENCLASTYrm, {0, Unknown}}, + {X86::VAESENCLASTYrr, {0, Unknown}}, + {X86::VAESENCLASTZ128rm, {1, Unknown}}, + {X86::VAESENCLASTZ128rr, {0, Unknown}}, + {X86::VAESENCLASTZ256rm, {0, Unknown}}, + {X86::VAESENCLASTZ256rr, {0, Unknown}}, + {X86::VAESENCLASTZrm, {0, Unknown}}, + {X86::VAESENCLASTZrr, {0, Unknown}}, + {X86::VAESENCLASTrm, {0, Unknown}}, + {X86::VAESENCLASTrr, {0, Unknown}}, + {X86::VAESENCYrm, {0, Unknown}}, + {X86::VAESENCYrr, {0, Unknown}}, + {X86::VAESENCZ128rm, {1, Unknown}}, + {X86::VAESENCZ128rr, {0, Unknown}}, + {X86::VAESENCZ256rm, {0, Unknown}}, + {X86::VAESENCZ256rr, {0, Unknown}}, + {X86::VAESENCZrm, {0, Unknown}}, + {X86::VAESENCZrr, {0, Unknown}}, + {X86::VAESENCrm, {0, Unknown}}, + {X86::VAESENCrr, {0, Unknown}}, + {X86::VAESIMCrm, {0, Unknown}}, + {X86::VAESIMCrr, {0, Unknown}}, + {X86::VAESKEYGENASSIST128rm, {1, Unknown}}, + {X86::VAESKEYGENASSIST128rr, {0, Unknown}}, + {X86::VALIGNDZ128rmbi, {1, Unknown}}, + {X86::VALIGNDZ128rmbik, {1, Unknown}}, + {X86::VALIGNDZ128rmbikz, {1, Unknown}}, + {X86::VALIGNDZ128rmi, {1, Unknown}}, + {X86::VALIGNDZ128rmik, {1, Unknown}}, + {X86::VALIGNDZ128rmikz, {1, Unknown}}, + {X86::VALIGNDZ128rri, {0, Unknown}}, + {X86::VALIGNDZ128rrik, {0, Unknown}}, + {X86::VALIGNDZ128rrikz, {0, Unknown}}, + {X86::VALIGNDZ256rmbi, {0, Unknown}}, + {X86::VALIGNDZ256rmbik, {0, Unknown}}, + {X86::VALIGNDZ256rmbikz, {0, Unknown}}, + {X86::VALIGNDZ256rmi, {0, Unknown}}, + {X86::VALIGNDZ256rmik, {0, Unknown}}, + {X86::VALIGNDZ256rmikz, {0, Unknown}}, + {X86::VALIGNDZ256rri, {0, Unknown}}, + {X86::VALIGNDZ256rrik, {0, Unknown}}, + {X86::VALIGNDZ256rrikz, {0, Unknown}}, + {X86::VALIGNDZrmbi, {0, Unknown}}, + {X86::VALIGNDZrmbik, {0, Unknown}}, + {X86::VALIGNDZrmbikz, {0, Unknown}}, + {X86::VALIGNDZrmi, {0, Unknown}}, + {X86::VALIGNDZrmik, {0, Unknown}}, + {X86::VALIGNDZrmikz, {0, Unknown}}, + {X86::VALIGNDZrri, {0, Unknown}}, + {X86::VALIGNDZrrik, {0, Unknown}}, + {X86::VALIGNDZrrikz, {0, Unknown}}, + {X86::VALIGNQZ128rmbi, {1, Unknown}}, + {X86::VALIGNQZ128rmbik, {1, Unknown}}, + {X86::VALIGNQZ128rmbikz, {1, Unknown}}, + {X86::VALIGNQZ128rmi, {1, Unknown}}, + {X86::VALIGNQZ128rmik, {1, Unknown}}, + {X86::VALIGNQZ128rmikz, {1, Unknown}}, + {X86::VALIGNQZ128rri, {0, Unknown}}, + {X86::VALIGNQZ128rrik, {0, Unknown}}, + {X86::VALIGNQZ128rrikz, {0, Unknown}}, + {X86::VALIGNQZ256rmbi, {0, Unknown}}, + {X86::VALIGNQZ256rmbik, {0, Unknown}}, + {X86::VALIGNQZ256rmbikz, {0, Unknown}}, + {X86::VALIGNQZ256rmi, {0, Unknown}}, + {X86::VALIGNQZ256rmik, {0, Unknown}}, + {X86::VALIGNQZ256rmikz, {0, Unknown}}, + {X86::VALIGNQZ256rri, {0, Unknown}}, + {X86::VALIGNQZ256rrik, {0, Unknown}}, + {X86::VALIGNQZ256rrikz, {0, Unknown}}, + {X86::VALIGNQZrmbi, {0, Unknown}}, + {X86::VALIGNQZrmbik, {0, Unknown}}, + {X86::VALIGNQZrmbikz, {0, Unknown}}, + {X86::VALIGNQZrmi, {0, Unknown}}, + {X86::VALIGNQZrmik, {0, Unknown}}, + {X86::VALIGNQZrmikz, {0, Unknown}}, + {X86::VALIGNQZrri, {0, Unknown}}, + {X86::VALIGNQZrrik, {0, Unknown}}, + {X86::VALIGNQZrrikz, {0, Unknown}}, + {X86::VANDNPDYrm, {0, Unknown}}, + {X86::VANDNPDYrr, {0, Unknown}}, + {X86::VANDNPDZ128rm, {1, Unknown}}, + {X86::VANDNPDZ128rmb, {1, Unknown}}, + {X86::VANDNPDZ128rmbk, {1, Unknown}}, + {X86::VANDNPDZ128rmbkz, {1, Unknown}}, + {X86::VANDNPDZ128rmk, {1, Unknown}}, + {X86::VANDNPDZ128rmkz, {1, Unknown}}, + {X86::VANDNPDZ128rr, {0, Unknown}}, + {X86::VANDNPDZ128rrk, {0, Unknown}}, + {X86::VANDNPDZ128rrkz, {0, Unknown}}, + {X86::VANDNPDZ256rm, {0, Unknown}}, + {X86::VANDNPDZ256rmb, {0, Unknown}}, + {X86::VANDNPDZ256rmbk, {0, Unknown}}, + {X86::VANDNPDZ256rmbkz, {0, Unknown}}, + {X86::VANDNPDZ256rmk, {0, Unknown}}, + {X86::VANDNPDZ256rmkz, {0, Unknown}}, + {X86::VANDNPDZ256rr, {0, Unknown}}, + {X86::VANDNPDZ256rrk, {0, Unknown}}, + {X86::VANDNPDZ256rrkz, {0, Unknown}}, + {X86::VANDNPDZrm, {0, Unknown}}, + {X86::VANDNPDZrmb, {0, Unknown}}, + {X86::VANDNPDZrmbk, {0, Unknown}}, + {X86::VANDNPDZrmbkz, {0, Unknown}}, + {X86::VANDNPDZrmk, {0, Unknown}}, + {X86::VANDNPDZrmkz, {0, Unknown}}, + {X86::VANDNPDZrr, {0, Unknown}}, + {X86::VANDNPDZrrk, {0, Unknown}}, + {X86::VANDNPDZrrkz, {0, Unknown}}, + {X86::VANDNPDrm, {0, Unknown}}, + {X86::VANDNPDrr, {0, Unknown}}, + {X86::VANDNPSYrm, {0, Unknown}}, + {X86::VANDNPSYrr, {0, Unknown}}, + {X86::VANDNPSZ128rm, {1, Unknown}}, + {X86::VANDNPSZ128rmb, {1, Unknown}}, + {X86::VANDNPSZ128rmbk, {1, Unknown}}, + {X86::VANDNPSZ128rmbkz, {1, Unknown}}, + {X86::VANDNPSZ128rmk, {1, Unknown}}, + {X86::VANDNPSZ128rmkz, {1, Unknown}}, + {X86::VANDNPSZ128rr, {0, Unknown}}, + {X86::VANDNPSZ128rrk, {0, Unknown}}, + {X86::VANDNPSZ128rrkz, {0, Unknown}}, + {X86::VANDNPSZ256rm, {0, Unknown}}, + {X86::VANDNPSZ256rmb, {0, Unknown}}, + {X86::VANDNPSZ256rmbk, {0, Unknown}}, + {X86::VANDNPSZ256rmbkz, {0, Unknown}}, + {X86::VANDNPSZ256rmk, {0, Unknown}}, + {X86::VANDNPSZ256rmkz, {0, Unknown}}, + {X86::VANDNPSZ256rr, {0, Unknown}}, + {X86::VANDNPSZ256rrk, {0, Unknown}}, + {X86::VANDNPSZ256rrkz, {0, Unknown}}, + {X86::VANDNPSZrm, {0, Unknown}}, + {X86::VANDNPSZrmb, {0, Unknown}}, + {X86::VANDNPSZrmbk, {0, Unknown}}, + {X86::VANDNPSZrmbkz, {0, Unknown}}, + {X86::VANDNPSZrmk, {0, Unknown}}, + {X86::VANDNPSZrmkz, {0, Unknown}}, + {X86::VANDNPSZrr, {0, Unknown}}, + {X86::VANDNPSZrrk, {0, Unknown}}, + {X86::VANDNPSZrrkz, {0, Unknown}}, + {X86::VANDNPSrm, {0, Unknown}}, + {X86::VANDNPSrr, {0, Unknown}}, + {X86::VANDPDYrm, {0, Unknown}}, + {X86::VANDPDYrr, {0, Unknown}}, + {X86::VANDPDZ128rm, {1, Unknown}}, + {X86::VANDPDZ128rmb, {1, Unknown}}, + {X86::VANDPDZ128rmbk, {1, Unknown}}, + {X86::VANDPDZ128rmbkz, {1, Unknown}}, + {X86::VANDPDZ128rmk, {1, Unknown}}, + {X86::VANDPDZ128rmkz, {1, Unknown}}, + {X86::VANDPDZ128rr, {0, Unknown}}, + {X86::VANDPDZ128rrk, {0, Unknown}}, + {X86::VANDPDZ128rrkz, {0, Unknown}}, + {X86::VANDPDZ256rm, {0, Unknown}}, + {X86::VANDPDZ256rmb, {0, Unknown}}, + {X86::VANDPDZ256rmbk, {0, Unknown}}, + {X86::VANDPDZ256rmbkz, {0, Unknown}}, + {X86::VANDPDZ256rmk, {0, Unknown}}, + {X86::VANDPDZ256rmkz, {0, Unknown}}, + {X86::VANDPDZ256rr, {0, Unknown}}, + {X86::VANDPDZ256rrk, {0, Unknown}}, + {X86::VANDPDZ256rrkz, {0, Unknown}}, + {X86::VANDPDZrm, {0, Unknown}}, + {X86::VANDPDZrmb, {0, Unknown}}, + {X86::VANDPDZrmbk, {0, Unknown}}, + {X86::VANDPDZrmbkz, {0, Unknown}}, + {X86::VANDPDZrmk, {0, Unknown}}, + {X86::VANDPDZrmkz, {0, Unknown}}, + {X86::VANDPDZrr, {0, Unknown}}, + {X86::VANDPDZrrk, {0, Unknown}}, + {X86::VANDPDZrrkz, {0, Unknown}}, + {X86::VANDPDrm, {0, Unknown}}, + {X86::VANDPDrr, {0, Unknown}}, + {X86::VANDPSYrm, {0, Unknown}}, + {X86::VANDPSYrr, {0, Unknown}}, + {X86::VANDPSZ128rm, {1, Unknown}}, + {X86::VANDPSZ128rmb, {1, Unknown}}, + {X86::VANDPSZ128rmbk, {1, Unknown}}, + {X86::VANDPSZ128rmbkz, {1, Unknown}}, + {X86::VANDPSZ128rmk, {1, Unknown}}, + {X86::VANDPSZ128rmkz, {1, Unknown}}, + {X86::VANDPSZ128rr, {0, Unknown}}, + {X86::VANDPSZ128rrk, {0, Unknown}}, + {X86::VANDPSZ128rrkz, {0, Unknown}}, + {X86::VANDPSZ256rm, {0, Unknown}}, + {X86::VANDPSZ256rmb, {0, Unknown}}, + {X86::VANDPSZ256rmbk, {0, Unknown}}, + {X86::VANDPSZ256rmbkz, {0, Unknown}}, + {X86::VANDPSZ256rmk, {0, Unknown}}, + {X86::VANDPSZ256rmkz, {0, Unknown}}, + {X86::VANDPSZ256rr, {0, Unknown}}, + {X86::VANDPSZ256rrk, {0, Unknown}}, + {X86::VANDPSZ256rrkz, {0, Unknown}}, + {X86::VANDPSZrm, {0, Unknown}}, + {X86::VANDPSZrmb, {0, Unknown}}, + {X86::VANDPSZrmbk, {0, Unknown}}, + {X86::VANDPSZrmbkz, {0, Unknown}}, + {X86::VANDPSZrmk, {0, Unknown}}, + {X86::VANDPSZrmkz, {0, Unknown}}, + {X86::VANDPSZrr, {0, Unknown}}, + {X86::VANDPSZrrk, {0, Unknown}}, + {X86::VANDPSZrrkz, {0, Unknown}}, + {X86::VANDPSrm, {0, Unknown}}, + {X86::VANDPSrr, {0, Unknown}}, + {X86::VASTART_SAVE_XMM_REGS, {0, Unknown}}, + {X86::VBLENDMPDZ128rm, {1, Unknown}}, + {X86::VBLENDMPDZ128rmb, {1, Unknown}}, + {X86::VBLENDMPDZ128rmbk, {1, Unknown}}, + {X86::VBLENDMPDZ128rmbkz, {1, Unknown}}, + {X86::VBLENDMPDZ128rmk, {1, Unknown}}, + {X86::VBLENDMPDZ128rmkz, {1, Unknown}}, + {X86::VBLENDMPDZ128rr, {0, Unknown}}, + {X86::VBLENDMPDZ128rrk, {0, Unknown}}, + {X86::VBLENDMPDZ128rrkz, {0, Unknown}}, + {X86::VBLENDMPDZ256rm, {0, Unknown}}, + {X86::VBLENDMPDZ256rmb, {0, Unknown}}, + {X86::VBLENDMPDZ256rmbk, {0, Unknown}}, + {X86::VBLENDMPDZ256rmbkz, {0, Unknown}}, + {X86::VBLENDMPDZ256rmk, {0, Unknown}}, + {X86::VBLENDMPDZ256rmkz, {0, Unknown}}, + {X86::VBLENDMPDZ256rr, {0, Unknown}}, + {X86::VBLENDMPDZ256rrk, {0, Unknown}}, + {X86::VBLENDMPDZ256rrkz, {0, Unknown}}, + {X86::VBLENDMPDZrm, {0, Unknown}}, + {X86::VBLENDMPDZrmb, {0, Unknown}}, + {X86::VBLENDMPDZrmbk, {0, Unknown}}, + {X86::VBLENDMPDZrmbkz, {0, Unknown}}, + {X86::VBLENDMPDZrmk, {0, Unknown}}, + {X86::VBLENDMPDZrmkz, {0, Unknown}}, + {X86::VBLENDMPDZrr, {0, Unknown}}, + {X86::VBLENDMPDZrrk, {0, Unknown}}, + {X86::VBLENDMPDZrrkz, {0, Unknown}}, + {X86::VBLENDMPSZ128rm, {1, Unknown}}, + {X86::VBLENDMPSZ128rmb, {1, Unknown}}, + {X86::VBLENDMPSZ128rmbk, {1, Unknown}}, + {X86::VBLENDMPSZ128rmbkz, {1, Unknown}}, + {X86::VBLENDMPSZ128rmk, {1, Unknown}}, + {X86::VBLENDMPSZ128rmkz, {1, Unknown}}, + {X86::VBLENDMPSZ128rr, {0, Unknown}}, + {X86::VBLENDMPSZ128rrk, {0, Unknown}}, + {X86::VBLENDMPSZ128rrkz, {0, Unknown}}, + {X86::VBLENDMPSZ256rm, {0, Unknown}}, + {X86::VBLENDMPSZ256rmb, {0, Unknown}}, + {X86::VBLENDMPSZ256rmbk, {0, Unknown}}, + {X86::VBLENDMPSZ256rmbkz, {0, Unknown}}, + {X86::VBLENDMPSZ256rmk, {0, Unknown}}, + {X86::VBLENDMPSZ256rmkz, {0, Unknown}}, + {X86::VBLENDMPSZ256rr, {0, Unknown}}, + {X86::VBLENDMPSZ256rrk, {0, Unknown}}, + {X86::VBLENDMPSZ256rrkz, {0, Unknown}}, + {X86::VBLENDMPSZrm, {0, Unknown}}, + {X86::VBLENDMPSZrmb, {0, Unknown}}, + {X86::VBLENDMPSZrmbk, {0, Unknown}}, + {X86::VBLENDMPSZrmbkz, {0, Unknown}}, + {X86::VBLENDMPSZrmk, {0, Unknown}}, + {X86::VBLENDMPSZrmkz, {0, Unknown}}, + {X86::VBLENDMPSZrr, {0, Unknown}}, + {X86::VBLENDMPSZrrk, {0, Unknown}}, + {X86::VBLENDMPSZrrkz, {0, Unknown}}, + {X86::VBLENDPDYrmi, {0, Unknown}}, + {X86::VBLENDPDYrri, {0, Unknown}}, + {X86::VBLENDPDrmi, {0, Unknown}}, + {X86::VBLENDPDrri, {0, Unknown}}, + {X86::VBLENDPSYrmi, {0, Unknown}}, + {X86::VBLENDPSYrri, {0, Unknown}}, + {X86::VBLENDPSrmi, {0, Unknown}}, + {X86::VBLENDPSrri, {0, Unknown}}, + {X86::VBLENDVPDYrm, {0, Unknown}}, + {X86::VBLENDVPDYrr, {0, Unknown}}, + {X86::VBLENDVPDrm, {0, Unknown}}, + {X86::VBLENDVPDrr, {0, Unknown}}, + {X86::VBLENDVPSYrm, {0, Unknown}}, + {X86::VBLENDVPSYrr, {0, Unknown}}, + {X86::VBLENDVPSrm, {0, Unknown}}, + {X86::VBLENDVPSrr, {0, Unknown}}, + {X86::VBROADCASTF128, {0, Unknown}}, + {X86::VBROADCASTF32X2Z256m, {0, Unknown}}, + {X86::VBROADCASTF32X2Z256mk, {0, Unknown}}, + {X86::VBROADCASTF32X2Z256mkz, {0, Unknown}}, + {X86::VBROADCASTF32X2Z256r, {0, Unknown}}, + {X86::VBROADCASTF32X2Z256rk, {0, Unknown}}, + {X86::VBROADCASTF32X2Z256rkz, {0, Unknown}}, + {X86::VBROADCASTF32X2Zm, {0, Unknown}}, + {X86::VBROADCASTF32X2Zmk, {0, Unknown}}, + {X86::VBROADCASTF32X2Zmkz, {0, Unknown}}, + {X86::VBROADCASTF32X2Zr, {0, Unknown}}, + {X86::VBROADCASTF32X2Zrk, {0, Unknown}}, + {X86::VBROADCASTF32X2Zrkz, {0, Unknown}}, + {X86::VBROADCASTF32X4Z256rm, {0, Unknown}}, + {X86::VBROADCASTF32X4Z256rmk, {0, Unknown}}, + {X86::VBROADCASTF32X4Z256rmkz, {0, Unknown}}, + {X86::VBROADCASTF32X4rm, {0, Unknown}}, + {X86::VBROADCASTF32X4rmk, {0, Unknown}}, + {X86::VBROADCASTF32X4rmkz, {0, Unknown}}, + {X86::VBROADCASTF32X8rm, {1, Unknown}}, + {X86::VBROADCASTF32X8rmk, {1, Unknown}}, + {X86::VBROADCASTF32X8rmkz, {1, Unknown}}, + {X86::VBROADCASTF64X2Z128rm, {1, Unknown}}, + {X86::VBROADCASTF64X2Z128rmk, {1, Unknown}}, + {X86::VBROADCASTF64X2Z128rmkz, {1, Unknown}}, + {X86::VBROADCASTF64X2rm, {0, Unknown}}, + {X86::VBROADCASTF64X2rmk, {0, Unknown}}, + {X86::VBROADCASTF64X2rmkz, {0, Unknown}}, + {X86::VBROADCASTF64X4rm, {0, Unknown}}, + {X86::VBROADCASTF64X4rmk, {0, Unknown}}, + {X86::VBROADCASTF64X4rmkz, {0, Unknown}}, + {X86::VBROADCASTI128, {0, Unknown}}, + {X86::VBROADCASTI32X2Z128m, {0, Unknown}}, + {X86::VBROADCASTI32X2Z128mk, {0, Unknown}}, + {X86::VBROADCASTI32X2Z128mkz, {0, Unknown}}, + {X86::VBROADCASTI32X2Z128r, {0, Unknown}}, + {X86::VBROADCASTI32X2Z128rk, {0, Unknown}}, + {X86::VBROADCASTI32X2Z128rkz, {0, Unknown}}, + {X86::VBROADCASTI32X2Z256m, {0, Unknown}}, + {X86::VBROADCASTI32X2Z256mk, {0, Unknown}}, + {X86::VBROADCASTI32X2Z256mkz, {0, Unknown}}, + {X86::VBROADCASTI32X2Z256r, {0, Unknown}}, + {X86::VBROADCASTI32X2Z256rk, {0, Unknown}}, + {X86::VBROADCASTI32X2Z256rkz, {0, Unknown}}, + {X86::VBROADCASTI32X2Zm, {0, Unknown}}, + {X86::VBROADCASTI32X2Zmk, {0, Unknown}}, + {X86::VBROADCASTI32X2Zmkz, {0, Unknown}}, + {X86::VBROADCASTI32X2Zr, {0, Unknown}}, + {X86::VBROADCASTI32X2Zrk, {0, Unknown}}, + {X86::VBROADCASTI32X2Zrkz, {0, Unknown}}, + {X86::VBROADCASTI32X4Z256rm, {0, Unknown}}, + {X86::VBROADCASTI32X4Z256rmk, {0, Unknown}}, + {X86::VBROADCASTI32X4Z256rmkz, {0, Unknown}}, + {X86::VBROADCASTI32X4rm, {0, Unknown}}, + {X86::VBROADCASTI32X4rmk, {0, Unknown}}, + {X86::VBROADCASTI32X4rmkz, {0, Unknown}}, + {X86::VBROADCASTI32X8rm, {1, Unknown}}, + {X86::VBROADCASTI32X8rmk, {1, Unknown}}, + {X86::VBROADCASTI32X8rmkz, {1, Unknown}}, + {X86::VBROADCASTI64X2Z128rm, {1, Unknown}}, + {X86::VBROADCASTI64X2Z128rmk, {1, Unknown}}, + {X86::VBROADCASTI64X2Z128rmkz, {1, Unknown}}, + {X86::VBROADCASTI64X2rm, {0, Unknown}}, + {X86::VBROADCASTI64X2rmk, {0, Unknown}}, + {X86::VBROADCASTI64X2rmkz, {0, Unknown}}, + {X86::VBROADCASTI64X4rm, {0, Unknown}}, + {X86::VBROADCASTI64X4rmk, {0, Unknown}}, + {X86::VBROADCASTI64X4rmkz, {0, Unknown}}, + {X86::VBROADCASTSDYrm, {0, Unknown}}, + {X86::VBROADCASTSDYrr, {0, Unknown}}, + {X86::VBROADCASTSDZ256m, {0, Unknown}}, + {X86::VBROADCASTSDZ256mk, {0, Unknown}}, + {X86::VBROADCASTSDZ256mkz, {0, Unknown}}, + {X86::VBROADCASTSDZ256r, {0, Unknown}}, + {X86::VBROADCASTSDZ256rk, {0, Unknown}}, + {X86::VBROADCASTSDZ256rkz, {0, Unknown}}, + {X86::VBROADCASTSDZm, {0, Unknown}}, + {X86::VBROADCASTSDZmk, {0, Unknown}}, + {X86::VBROADCASTSDZmkz, {0, Unknown}}, + {X86::VBROADCASTSDZr, {0, Unknown}}, + {X86::VBROADCASTSDZrk, {0, Unknown}}, + {X86::VBROADCASTSDZrkz, {0, Unknown}}, + {X86::VBROADCASTSSYrm, {0, Unknown}}, + {X86::VBROADCASTSSYrr, {0, Unknown}}, + {X86::VBROADCASTSSZ128m, {0, Unknown}}, + {X86::VBROADCASTSSZ128mk, {0, Unknown}}, + {X86::VBROADCASTSSZ128mkz, {0, Unknown}}, + {X86::VBROADCASTSSZ128r, {0, Unknown}}, + {X86::VBROADCASTSSZ128rk, {0, Unknown}}, + {X86::VBROADCASTSSZ128rkz, {0, Unknown}}, + {X86::VBROADCASTSSZ256m, {0, Unknown}}, + {X86::VBROADCASTSSZ256mk, {0, Unknown}}, + {X86::VBROADCASTSSZ256mkz, {0, Unknown}}, + {X86::VBROADCASTSSZ256r, {0, Unknown}}, + {X86::VBROADCASTSSZ256rk, {0, Unknown}}, + {X86::VBROADCASTSSZ256rkz, {0, Unknown}}, + {X86::VBROADCASTSSZm, {0, Unknown}}, + {X86::VBROADCASTSSZmk, {0, Unknown}}, + {X86::VBROADCASTSSZmkz, {0, Unknown}}, + {X86::VBROADCASTSSZr, {0, Unknown}}, + {X86::VBROADCASTSSZrk, {0, Unknown}}, + {X86::VBROADCASTSSZrkz, {0, Unknown}}, + {X86::VBROADCASTSSrm, {0, Unknown}}, + {X86::VBROADCASTSSrr, {0, Unknown}}, + {X86::VCMPPDYrmi, {0, Unknown}}, + {X86::VCMPPDYrmi_alt, {0, Unknown}}, + {X86::VCMPPDYrri, {0, Unknown}}, + {X86::VCMPPDYrri_alt, {0, Unknown}}, + {X86::VCMPPDZ128rmbi, {1, Unknown}}, + {X86::VCMPPDZ128rmbi_alt, {1, Unknown}}, + {X86::VCMPPDZ128rmbi_altk, {1, Unknown}}, + {X86::VCMPPDZ128rmbik, {1, Unknown}}, + {X86::VCMPPDZ128rmi, {1, Unknown}}, + {X86::VCMPPDZ128rmi_alt, {1, Unknown}}, + {X86::VCMPPDZ128rmi_altk, {1, Unknown}}, + {X86::VCMPPDZ128rmik, {1, Unknown}}, + {X86::VCMPPDZ128rri, {0, Unknown}}, + {X86::VCMPPDZ128rri_alt, {0, Unknown}}, + {X86::VCMPPDZ128rri_altk, {0, Unknown}}, + {X86::VCMPPDZ128rrik, {0, Unknown}}, + {X86::VCMPPDZ256rmbi, {0, Unknown}}, + {X86::VCMPPDZ256rmbi_alt, {0, Unknown}}, + {X86::VCMPPDZ256rmbi_altk, {0, Unknown}}, + {X86::VCMPPDZ256rmbik, {0, Unknown}}, + {X86::VCMPPDZ256rmi, {0, Unknown}}, + {X86::VCMPPDZ256rmi_alt, {0, Unknown}}, + {X86::VCMPPDZ256rmi_altk, {0, Unknown}}, + {X86::VCMPPDZ256rmik, {0, Unknown}}, + {X86::VCMPPDZ256rri, {0, Unknown}}, + {X86::VCMPPDZ256rri_alt, {0, Unknown}}, + {X86::VCMPPDZ256rri_altk, {0, Unknown}}, + {X86::VCMPPDZ256rrik, {0, Unknown}}, + {X86::VCMPPDZrmbi, {0, Unknown}}, + {X86::VCMPPDZrmbi_alt, {0, Unknown}}, + {X86::VCMPPDZrmbi_altk, {0, Unknown}}, + {X86::VCMPPDZrmbik, {0, Unknown}}, + {X86::VCMPPDZrmi, {0, Unknown}}, + {X86::VCMPPDZrmi_alt, {0, Unknown}}, + {X86::VCMPPDZrmi_altk, {0, Unknown}}, + {X86::VCMPPDZrmik, {0, Unknown}}, + {X86::VCMPPDZrri, {0, Unknown}}, + {X86::VCMPPDZrri_alt, {0, Unknown}}, + {X86::VCMPPDZrri_altk, {0, Unknown}}, + {X86::VCMPPDZrrib, {0, Unknown}}, + {X86::VCMPPDZrrib_alt, {0, Unknown}}, + {X86::VCMPPDZrrib_altk, {0, Unknown}}, + {X86::VCMPPDZrribk, {0, Unknown}}, + {X86::VCMPPDZrrik, {0, Unknown}}, + {X86::VCMPPDrmi, {0, Unknown}}, + {X86::VCMPPDrmi_alt, {0, Unknown}}, + {X86::VCMPPDrri, {0, Unknown}}, + {X86::VCMPPDrri_alt, {0, Unknown}}, + {X86::VCMPPSYrmi, {0, Unknown}}, + {X86::VCMPPSYrmi_alt, {0, Unknown}}, + {X86::VCMPPSYrri, {0, Unknown}}, + {X86::VCMPPSYrri_alt, {0, Unknown}}, + {X86::VCMPPSZ128rmbi, {1, Unknown}}, + {X86::VCMPPSZ128rmbi_alt, {1, Unknown}}, + {X86::VCMPPSZ128rmbi_altk, {1, Unknown}}, + {X86::VCMPPSZ128rmbik, {1, Unknown}}, + {X86::VCMPPSZ128rmi, {1, Unknown}}, + {X86::VCMPPSZ128rmi_alt, {1, Unknown}}, + {X86::VCMPPSZ128rmi_altk, {1, Unknown}}, + {X86::VCMPPSZ128rmik, {1, Unknown}}, + {X86::VCMPPSZ128rri, {0, Unknown}}, + {X86::VCMPPSZ128rri_alt, {0, Unknown}}, + {X86::VCMPPSZ128rri_altk, {0, Unknown}}, + {X86::VCMPPSZ128rrik, {0, Unknown}}, + {X86::VCMPPSZ256rmbi, {0, Unknown}}, + {X86::VCMPPSZ256rmbi_alt, {0, Unknown}}, + {X86::VCMPPSZ256rmbi_altk, {0, Unknown}}, + {X86::VCMPPSZ256rmbik, {0, Unknown}}, + {X86::VCMPPSZ256rmi, {0, Unknown}}, + {X86::VCMPPSZ256rmi_alt, {0, Unknown}}, + {X86::VCMPPSZ256rmi_altk, {0, Unknown}}, + {X86::VCMPPSZ256rmik, {0, Unknown}}, + {X86::VCMPPSZ256rri, {0, Unknown}}, + {X86::VCMPPSZ256rri_alt, {0, Unknown}}, + {X86::VCMPPSZ256rri_altk, {0, Unknown}}, + {X86::VCMPPSZ256rrik, {0, Unknown}}, + {X86::VCMPPSZrmbi, {0, Unknown}}, + {X86::VCMPPSZrmbi_alt, {0, Unknown}}, + {X86::VCMPPSZrmbi_altk, {0, Unknown}}, + {X86::VCMPPSZrmbik, {0, Unknown}}, + {X86::VCMPPSZrmi, {0, Unknown}}, + {X86::VCMPPSZrmi_alt, {0, Unknown}}, + {X86::VCMPPSZrmi_altk, {0, Unknown}}, + {X86::VCMPPSZrmik, {0, Unknown}}, + {X86::VCMPPSZrri, {0, Unknown}}, + {X86::VCMPPSZrri_alt, {0, Unknown}}, + {X86::VCMPPSZrri_altk, {0, Unknown}}, + {X86::VCMPPSZrrib, {0, Unknown}}, + {X86::VCMPPSZrrib_alt, {0, Unknown}}, + {X86::VCMPPSZrrib_altk, {0, Unknown}}, + {X86::VCMPPSZrribk, {0, Unknown}}, + {X86::VCMPPSZrrik, {0, Unknown}}, + {X86::VCMPPSrmi, {0, Unknown}}, + {X86::VCMPPSrmi_alt, {0, Unknown}}, + {X86::VCMPPSrri, {0, Unknown}}, + {X86::VCMPPSrri_alt, {0, Unknown}}, + {X86::VCMPSDZrm, {0, Unknown}}, + {X86::VCMPSDZrm_Int, {0, Unknown}}, + {X86::VCMPSDZrm_Intk, {0, Unknown}}, + {X86::VCMPSDZrmi_alt, {0, Unknown}}, + {X86::VCMPSDZrmi_altk, {0, Unknown}}, + {X86::VCMPSDZrr, {0, Unknown}}, + {X86::VCMPSDZrr_Int, {0, Unknown}}, + {X86::VCMPSDZrr_Intk, {0, Unknown}}, + {X86::VCMPSDZrrb_Int, {0, Unknown}}, + {X86::VCMPSDZrrb_Intk, {0, Unknown}}, + {X86::VCMPSDZrrb_alt, {0, Unknown}}, + {X86::VCMPSDZrrb_altk, {0, Unknown}}, + {X86::VCMPSDZrri_alt, {0, Unknown}}, + {X86::VCMPSDZrri_altk, {0, Unknown}}, + {X86::VCMPSDrm, {0, Unknown}}, + {X86::VCMPSDrm_Int, {0, Unknown}}, + {X86::VCMPSDrm_alt, {0, Unknown}}, + {X86::VCMPSDrr, {0, Unknown}}, + {X86::VCMPSDrr_Int, {0, Unknown}}, + {X86::VCMPSDrr_alt, {0, Unknown}}, + {X86::VCMPSSZrm, {0, Unknown}}, + {X86::VCMPSSZrm_Int, {0, Unknown}}, + {X86::VCMPSSZrm_Intk, {0, Unknown}}, + {X86::VCMPSSZrmi_alt, {0, Unknown}}, + {X86::VCMPSSZrmi_altk, {0, Unknown}}, + {X86::VCMPSSZrr, {0, Unknown}}, + {X86::VCMPSSZrr_Int, {0, Unknown}}, + {X86::VCMPSSZrr_Intk, {0, Unknown}}, + {X86::VCMPSSZrrb_Int, {0, Unknown}}, + {X86::VCMPSSZrrb_Intk, {0, Unknown}}, + {X86::VCMPSSZrrb_alt, {0, Unknown}}, + {X86::VCMPSSZrrb_altk, {0, Unknown}}, + {X86::VCMPSSZrri_alt, {0, Unknown}}, + {X86::VCMPSSZrri_altk, {0, Unknown}}, + {X86::VCMPSSrm, {0, Unknown}}, + {X86::VCMPSSrm_Int, {0, Unknown}}, + {X86::VCMPSSrm_alt, {0, Unknown}}, + {X86::VCMPSSrr, {0, Unknown}}, + {X86::VCMPSSrr_Int, {0, Unknown}}, + {X86::VCMPSSrr_alt, {0, Unknown}}, + {X86::VCOMISDZrm, {0, Unknown}}, + {X86::VCOMISDZrm_Int, {0, Unknown}}, + {X86::VCOMISDZrr, {0, Unknown}}, + {X86::VCOMISDZrr_Int, {0, Unknown}}, + {X86::VCOMISDZrrb, {0, Unknown}}, + {X86::VCOMISDrm, {0, Unknown}}, + {X86::VCOMISDrm_Int, {0, Unknown}}, + {X86::VCOMISDrr, {0, Unknown}}, + {X86::VCOMISDrr_Int, {0, Unknown}}, + {X86::VCOMISSZrm, {0, Unknown}}, + {X86::VCOMISSZrm_Int, {0, Unknown}}, + {X86::VCOMISSZrr, {0, Unknown}}, + {X86::VCOMISSZrr_Int, {0, Unknown}}, + {X86::VCOMISSZrrb, {0, Unknown}}, + {X86::VCOMISSrm, {0, Unknown}}, + {X86::VCOMISSrm_Int, {0, Unknown}}, + {X86::VCOMISSrr, {0, Unknown}}, + {X86::VCOMISSrr_Int, {0, Unknown}}, + {X86::VCOMPRESSPDZ128mr, {1, Unknown}}, + {X86::VCOMPRESSPDZ128mrk, {1, Unknown}}, + {X86::VCOMPRESSPDZ128rr, {0, Unknown}}, + {X86::VCOMPRESSPDZ128rrk, {0, Unknown}}, + {X86::VCOMPRESSPDZ128rrkz, {0, Unknown}}, + {X86::VCOMPRESSPDZ256mr, {0, Unknown}}, + {X86::VCOMPRESSPDZ256mrk, {0, Unknown}}, + {X86::VCOMPRESSPDZ256rr, {0, Unknown}}, + {X86::VCOMPRESSPDZ256rrk, {0, Unknown}}, + {X86::VCOMPRESSPDZ256rrkz, {0, Unknown}}, + {X86::VCOMPRESSPDZmr, {0, Unknown}}, + {X86::VCOMPRESSPDZmrk, {0, Unknown}}, + {X86::VCOMPRESSPDZrr, {0, Unknown}}, + {X86::VCOMPRESSPDZrrk, {0, Unknown}}, + {X86::VCOMPRESSPDZrrkz, {0, Unknown}}, + {X86::VCOMPRESSPSZ128mr, {1, Unknown}}, + {X86::VCOMPRESSPSZ128mrk, {1, Unknown}}, + {X86::VCOMPRESSPSZ128rr, {0, Unknown}}, + {X86::VCOMPRESSPSZ128rrk, {0, Unknown}}, + {X86::VCOMPRESSPSZ128rrkz, {0, Unknown}}, + {X86::VCOMPRESSPSZ256mr, {0, Unknown}}, + {X86::VCOMPRESSPSZ256mrk, {0, Unknown}}, + {X86::VCOMPRESSPSZ256rr, {0, Unknown}}, + {X86::VCOMPRESSPSZ256rrk, {0, Unknown}}, + {X86::VCOMPRESSPSZ256rrkz, {0, Unknown}}, + {X86::VCOMPRESSPSZmr, {0, Unknown}}, + {X86::VCOMPRESSPSZmrk, {0, Unknown}}, + {X86::VCOMPRESSPSZrr, {0, Unknown}}, + {X86::VCOMPRESSPSZrrk, {0, Unknown}}, + {X86::VCOMPRESSPSZrrkz, {0, Unknown}}, + {X86::VCVTDQ2PDYrm, {0, Unknown}}, + {X86::VCVTDQ2PDYrr, {0, Unknown}}, + {X86::VCVTDQ2PDZ128rm, {1, Unknown}}, + {X86::VCVTDQ2PDZ128rmb, {1, Unknown}}, + {X86::VCVTDQ2PDZ128rmbk, {1, Unknown}}, + {X86::VCVTDQ2PDZ128rmbkz, {1, Unknown}}, + {X86::VCVTDQ2PDZ128rmk, {1, Unknown}}, + {X86::VCVTDQ2PDZ128rmkz, {1, Unknown}}, + {X86::VCVTDQ2PDZ128rr, {0, Unknown}}, + {X86::VCVTDQ2PDZ128rrk, {0, Unknown}}, + {X86::VCVTDQ2PDZ128rrkz, {0, Unknown}}, + {X86::VCVTDQ2PDZ256rm, {0, Unknown}}, + {X86::VCVTDQ2PDZ256rmb, {0, Unknown}}, + {X86::VCVTDQ2PDZ256rmbk, {0, Unknown}}, + {X86::VCVTDQ2PDZ256rmbkz, {0, Unknown}}, + {X86::VCVTDQ2PDZ256rmk, {0, Unknown}}, + {X86::VCVTDQ2PDZ256rmkz, {0, Unknown}}, + {X86::VCVTDQ2PDZ256rr, {0, Unknown}}, + {X86::VCVTDQ2PDZ256rrk, {0, Unknown}}, + {X86::VCVTDQ2PDZ256rrkz, {0, Unknown}}, + {X86::VCVTDQ2PDZrm, {0, Unknown}}, + {X86::VCVTDQ2PDZrmb, {0, Unknown}}, + {X86::VCVTDQ2PDZrmbk, {0, Unknown}}, + {X86::VCVTDQ2PDZrmbkz, {0, Unknown}}, + {X86::VCVTDQ2PDZrmk, {0, Unknown}}, + {X86::VCVTDQ2PDZrmkz, {0, Unknown}}, + {X86::VCVTDQ2PDZrr, {0, Unknown}}, + {X86::VCVTDQ2PDZrrk, {0, Unknown}}, + {X86::VCVTDQ2PDZrrkz, {0, Unknown}}, + {X86::VCVTDQ2PDrm, {0, Unknown}}, + {X86::VCVTDQ2PDrr, {0, Unknown}}, + {X86::VCVTDQ2PSYrm, {0, Unknown}}, + {X86::VCVTDQ2PSYrr, {0, Unknown}}, + {X86::VCVTDQ2PSZ128rm, {1, Unknown}}, + {X86::VCVTDQ2PSZ128rmb, {1, Unknown}}, + {X86::VCVTDQ2PSZ128rmbk, {1, Unknown}}, + {X86::VCVTDQ2PSZ128rmbkz, {1, Unknown}}, + {X86::VCVTDQ2PSZ128rmk, {1, Unknown}}, + {X86::VCVTDQ2PSZ128rmkz, {1, Unknown}}, + {X86::VCVTDQ2PSZ128rr, {0, Unknown}}, + {X86::VCVTDQ2PSZ128rrk, {0, Unknown}}, + {X86::VCVTDQ2PSZ128rrkz, {0, Unknown}}, + {X86::VCVTDQ2PSZ256rm, {0, Unknown}}, + {X86::VCVTDQ2PSZ256rmb, {0, Unknown}}, + {X86::VCVTDQ2PSZ256rmbk, {0, Unknown}}, + {X86::VCVTDQ2PSZ256rmbkz, {0, Unknown}}, + {X86::VCVTDQ2PSZ256rmk, {0, Unknown}}, + {X86::VCVTDQ2PSZ256rmkz, {0, Unknown}}, + {X86::VCVTDQ2PSZ256rr, {0, Unknown}}, + {X86::VCVTDQ2PSZ256rrk, {0, Unknown}}, + {X86::VCVTDQ2PSZ256rrkz, {0, Unknown}}, + {X86::VCVTDQ2PSZrm, {0, Unknown}}, + {X86::VCVTDQ2PSZrmb, {0, Unknown}}, + {X86::VCVTDQ2PSZrmbk, {0, Unknown}}, + {X86::VCVTDQ2PSZrmbkz, {0, Unknown}}, + {X86::VCVTDQ2PSZrmk, {0, Unknown}}, + {X86::VCVTDQ2PSZrmkz, {0, Unknown}}, + {X86::VCVTDQ2PSZrr, {0, Unknown}}, + {X86::VCVTDQ2PSZrrb, {0, Unknown}}, + {X86::VCVTDQ2PSZrrbk, {0, Unknown}}, + {X86::VCVTDQ2PSZrrbkz, {0, Unknown}}, + {X86::VCVTDQ2PSZrrk, {0, Unknown}}, + {X86::VCVTDQ2PSZrrkz, {0, Unknown}}, + {X86::VCVTDQ2PSrm, {0, Unknown}}, + {X86::VCVTDQ2PSrr, {0, Unknown}}, + {X86::VCVTPD2DQYrm, {0, Unknown}}, + {X86::VCVTPD2DQYrr, {0, Unknown}}, + {X86::VCVTPD2DQZ128rm, {1, Unknown}}, + {X86::VCVTPD2DQZ128rmb, {1, Unknown}}, + {X86::VCVTPD2DQZ128rmbk, {1, Unknown}}, + {X86::VCVTPD2DQZ128rmbkz, {1, Unknown}}, + {X86::VCVTPD2DQZ128rmk, {1, Unknown}}, + {X86::VCVTPD2DQZ128rmkz, {1, Unknown}}, + {X86::VCVTPD2DQZ128rr, {0, Unknown}}, + {X86::VCVTPD2DQZ128rrk, {0, Unknown}}, + {X86::VCVTPD2DQZ128rrkz, {0, Unknown}}, + {X86::VCVTPD2DQZ256rm, {0, Unknown}}, + {X86::VCVTPD2DQZ256rmb, {0, Unknown}}, + {X86::VCVTPD2DQZ256rmbk, {0, Unknown}}, + {X86::VCVTPD2DQZ256rmbkz, {0, Unknown}}, + {X86::VCVTPD2DQZ256rmk, {0, Unknown}}, + {X86::VCVTPD2DQZ256rmkz, {0, Unknown}}, + {X86::VCVTPD2DQZ256rr, {0, Unknown}}, + {X86::VCVTPD2DQZ256rrk, {0, Unknown}}, + {X86::VCVTPD2DQZ256rrkz, {0, Unknown}}, + {X86::VCVTPD2DQZrm, {0, Unknown}}, + {X86::VCVTPD2DQZrmb, {0, Unknown}}, + {X86::VCVTPD2DQZrmbk, {0, Unknown}}, + {X86::VCVTPD2DQZrmbkz, {0, Unknown}}, + {X86::VCVTPD2DQZrmk, {0, Unknown}}, + {X86::VCVTPD2DQZrmkz, {0, Unknown}}, + {X86::VCVTPD2DQZrr, {0, Unknown}}, + {X86::VCVTPD2DQZrrb, {0, Unknown}}, + {X86::VCVTPD2DQZrrbk, {0, Unknown}}, + {X86::VCVTPD2DQZrrbkz, {0, Unknown}}, + {X86::VCVTPD2DQZrrk, {0, Unknown}}, + {X86::VCVTPD2DQZrrkz, {0, Unknown}}, + {X86::VCVTPD2DQrm, {0, Unknown}}, + {X86::VCVTPD2DQrr, {0, Unknown}}, + {X86::VCVTPD2PSYrm, {0, Unknown}}, + {X86::VCVTPD2PSYrr, {0, Unknown}}, + {X86::VCVTPD2PSZ128rm, {1, Unknown}}, + {X86::VCVTPD2PSZ128rmb, {1, Unknown}}, + {X86::VCVTPD2PSZ128rmbk, {1, Unknown}}, + {X86::VCVTPD2PSZ128rmbkz, {1, Unknown}}, + {X86::VCVTPD2PSZ128rmk, {1, Unknown}}, + {X86::VCVTPD2PSZ128rmkz, {1, Unknown}}, + {X86::VCVTPD2PSZ128rr, {0, Unknown}}, + {X86::VCVTPD2PSZ128rrk, {0, Unknown}}, + {X86::VCVTPD2PSZ128rrkz, {0, Unknown}}, + {X86::VCVTPD2PSZ256rm, {0, Unknown}}, + {X86::VCVTPD2PSZ256rmb, {0, Unknown}}, + {X86::VCVTPD2PSZ256rmbk, {0, Unknown}}, + {X86::VCVTPD2PSZ256rmbkz, {0, Unknown}}, + {X86::VCVTPD2PSZ256rmk, {0, Unknown}}, + {X86::VCVTPD2PSZ256rmkz, {0, Unknown}}, + {X86::VCVTPD2PSZ256rr, {0, Unknown}}, + {X86::VCVTPD2PSZ256rrk, {0, Unknown}}, + {X86::VCVTPD2PSZ256rrkz, {0, Unknown}}, + {X86::VCVTPD2PSZrm, {0, Unknown}}, + {X86::VCVTPD2PSZrmb, {0, Unknown}}, + {X86::VCVTPD2PSZrmbk, {0, Unknown}}, + {X86::VCVTPD2PSZrmbkz, {0, Unknown}}, + {X86::VCVTPD2PSZrmk, {0, Unknown}}, + {X86::VCVTPD2PSZrmkz, {0, Unknown}}, + {X86::VCVTPD2PSZrr, {0, Unknown}}, + {X86::VCVTPD2PSZrrb, {0, Unknown}}, + {X86::VCVTPD2PSZrrbk, {0, Unknown}}, + {X86::VCVTPD2PSZrrbkz, {0, Unknown}}, + {X86::VCVTPD2PSZrrk, {0, Unknown}}, + {X86::VCVTPD2PSZrrkz, {0, Unknown}}, + {X86::VCVTPD2PSrm, {0, Unknown}}, + {X86::VCVTPD2PSrr, {0, Unknown}}, + {X86::VCVTPD2QQZ128rm, {1, Unknown}}, + {X86::VCVTPD2QQZ128rmb, {1, Unknown}}, + {X86::VCVTPD2QQZ128rmbk, {1, Unknown}}, + {X86::VCVTPD2QQZ128rmbkz, {1, Unknown}}, + {X86::VCVTPD2QQZ128rmk, {1, Unknown}}, + {X86::VCVTPD2QQZ128rmkz, {1, Unknown}}, + {X86::VCVTPD2QQZ128rr, {0, Unknown}}, + {X86::VCVTPD2QQZ128rrk, {0, Unknown}}, + {X86::VCVTPD2QQZ128rrkz, {0, Unknown}}, + {X86::VCVTPD2QQZ256rm, {0, Unknown}}, + {X86::VCVTPD2QQZ256rmb, {0, Unknown}}, + {X86::VCVTPD2QQZ256rmbk, {0, Unknown}}, + {X86::VCVTPD2QQZ256rmbkz, {0, Unknown}}, + {X86::VCVTPD2QQZ256rmk, {0, Unknown}}, + {X86::VCVTPD2QQZ256rmkz, {0, Unknown}}, + {X86::VCVTPD2QQZ256rr, {0, Unknown}}, + {X86::VCVTPD2QQZ256rrk, {0, Unknown}}, + {X86::VCVTPD2QQZ256rrkz, {0, Unknown}}, + {X86::VCVTPD2QQZrm, {0, Unknown}}, + {X86::VCVTPD2QQZrmb, {0, Unknown}}, + {X86::VCVTPD2QQZrmbk, {0, Unknown}}, + {X86::VCVTPD2QQZrmbkz, {0, Unknown}}, + {X86::VCVTPD2QQZrmk, {0, Unknown}}, + {X86::VCVTPD2QQZrmkz, {0, Unknown}}, + {X86::VCVTPD2QQZrr, {0, Unknown}}, + {X86::VCVTPD2QQZrrb, {0, Unknown}}, + {X86::VCVTPD2QQZrrbk, {0, Unknown}}, + {X86::VCVTPD2QQZrrbkz, {0, Unknown}}, + {X86::VCVTPD2QQZrrk, {0, Unknown}}, + {X86::VCVTPD2QQZrrkz, {0, Unknown}}, + {X86::VCVTPD2UDQZ128rm, {1, Unknown}}, + {X86::VCVTPD2UDQZ128rmb, {1, Unknown}}, + {X86::VCVTPD2UDQZ128rmbk, {1, Unknown}}, + {X86::VCVTPD2UDQZ128rmbkz, {1, Unknown}}, + {X86::VCVTPD2UDQZ128rmk, {1, Unknown}}, + {X86::VCVTPD2UDQZ128rmkz, {1, Unknown}}, + {X86::VCVTPD2UDQZ128rr, {0, Unknown}}, + {X86::VCVTPD2UDQZ128rrk, {0, Unknown}}, + {X86::VCVTPD2UDQZ128rrkz, {0, Unknown}}, + {X86::VCVTPD2UDQZ256rm, {0, Unknown}}, + {X86::VCVTPD2UDQZ256rmb, {0, Unknown}}, + {X86::VCVTPD2UDQZ256rmbk, {0, Unknown}}, + {X86::VCVTPD2UDQZ256rmbkz, {0, Unknown}}, + {X86::VCVTPD2UDQZ256rmk, {0, Unknown}}, + {X86::VCVTPD2UDQZ256rmkz, {0, Unknown}}, + {X86::VCVTPD2UDQZ256rr, {0, Unknown}}, + {X86::VCVTPD2UDQZ256rrk, {0, Unknown}}, + {X86::VCVTPD2UDQZ256rrkz, {0, Unknown}}, + {X86::VCVTPD2UDQZrm, {0, Unknown}}, + {X86::VCVTPD2UDQZrmb, {0, Unknown}}, + {X86::VCVTPD2UDQZrmbk, {0, Unknown}}, + {X86::VCVTPD2UDQZrmbkz, {0, Unknown}}, + {X86::VCVTPD2UDQZrmk, {0, Unknown}}, + {X86::VCVTPD2UDQZrmkz, {0, Unknown}}, + {X86::VCVTPD2UDQZrr, {0, Unknown}}, + {X86::VCVTPD2UDQZrrb, {0, Unknown}}, + {X86::VCVTPD2UDQZrrbk, {0, Unknown}}, + {X86::VCVTPD2UDQZrrbkz, {0, Unknown}}, + {X86::VCVTPD2UDQZrrk, {0, Unknown}}, + {X86::VCVTPD2UDQZrrkz, {0, Unknown}}, + {X86::VCVTPD2UQQZ128rm, {1, Unknown}}, + {X86::VCVTPD2UQQZ128rmb, {1, Unknown}}, + {X86::VCVTPD2UQQZ128rmbk, {1, Unknown}}, + {X86::VCVTPD2UQQZ128rmbkz, {1, Unknown}}, + {X86::VCVTPD2UQQZ128rmk, {1, Unknown}}, + {X86::VCVTPD2UQQZ128rmkz, {1, Unknown}}, + {X86::VCVTPD2UQQZ128rr, {0, Unknown}}, + {X86::VCVTPD2UQQZ128rrk, {0, Unknown}}, + {X86::VCVTPD2UQQZ128rrkz, {0, Unknown}}, + {X86::VCVTPD2UQQZ256rm, {0, Unknown}}, + {X86::VCVTPD2UQQZ256rmb, {0, Unknown}}, + {X86::VCVTPD2UQQZ256rmbk, {0, Unknown}}, + {X86::VCVTPD2UQQZ256rmbkz, {0, Unknown}}, + {X86::VCVTPD2UQQZ256rmk, {0, Unknown}}, + {X86::VCVTPD2UQQZ256rmkz, {0, Unknown}}, + {X86::VCVTPD2UQQZ256rr, {0, Unknown}}, + {X86::VCVTPD2UQQZ256rrk, {0, Unknown}}, + {X86::VCVTPD2UQQZ256rrkz, {0, Unknown}}, + {X86::VCVTPD2UQQZrm, {0, Unknown}}, + {X86::VCVTPD2UQQZrmb, {0, Unknown}}, + {X86::VCVTPD2UQQZrmbk, {0, Unknown}}, + {X86::VCVTPD2UQQZrmbkz, {0, Unknown}}, + {X86::VCVTPD2UQQZrmk, {0, Unknown}}, + {X86::VCVTPD2UQQZrmkz, {0, Unknown}}, + {X86::VCVTPD2UQQZrr, {0, Unknown}}, + {X86::VCVTPD2UQQZrrb, {0, Unknown}}, + {X86::VCVTPD2UQQZrrbk, {0, Unknown}}, + {X86::VCVTPD2UQQZrrbkz, {0, Unknown}}, + {X86::VCVTPD2UQQZrrk, {0, Unknown}}, + {X86::VCVTPD2UQQZrrkz, {0, Unknown}}, + {X86::VCVTPH2PSYrm, {0, Unknown}}, + {X86::VCVTPH2PSYrr, {0, Unknown}}, + {X86::VCVTPH2PSZ128rm, {1, Unknown}}, + {X86::VCVTPH2PSZ128rmk, {1, Unknown}}, + {X86::VCVTPH2PSZ128rmkz, {1, Unknown}}, + {X86::VCVTPH2PSZ128rr, {0, Unknown}}, + {X86::VCVTPH2PSZ128rrk, {0, Unknown}}, + {X86::VCVTPH2PSZ128rrkz, {0, Unknown}}, + {X86::VCVTPH2PSZ256rm, {0, Unknown}}, + {X86::VCVTPH2PSZ256rmk, {0, Unknown}}, + {X86::VCVTPH2PSZ256rmkz, {0, Unknown}}, + {X86::VCVTPH2PSZ256rr, {0, Unknown}}, + {X86::VCVTPH2PSZ256rrk, {0, Unknown}}, + {X86::VCVTPH2PSZ256rrkz, {0, Unknown}}, + {X86::VCVTPH2PSZrm, {0, Unknown}}, + {X86::VCVTPH2PSZrmk, {0, Unknown}}, + {X86::VCVTPH2PSZrmkz, {0, Unknown}}, + {X86::VCVTPH2PSZrr, {0, Unknown}}, + {X86::VCVTPH2PSZrrb, {0, Unknown}}, + {X86::VCVTPH2PSZrrbk, {0, Unknown}}, + {X86::VCVTPH2PSZrrbkz, {0, Unknown}}, + {X86::VCVTPH2PSZrrk, {0, Unknown}}, + {X86::VCVTPH2PSZrrkz, {0, Unknown}}, + {X86::VCVTPH2PSrm, {0, Unknown}}, + {X86::VCVTPH2PSrr, {0, Unknown}}, + {X86::VCVTPS2DQYrm, {0, Unknown}}, + {X86::VCVTPS2DQYrr, {0, Unknown}}, + {X86::VCVTPS2DQZ128rm, {1, Unknown}}, + {X86::VCVTPS2DQZ128rmb, {1, Unknown}}, + {X86::VCVTPS2DQZ128rmbk, {1, Unknown}}, + {X86::VCVTPS2DQZ128rmbkz, {1, Unknown}}, + {X86::VCVTPS2DQZ128rmk, {1, Unknown}}, + {X86::VCVTPS2DQZ128rmkz, {1, Unknown}}, + {X86::VCVTPS2DQZ128rr, {0, Unknown}}, + {X86::VCVTPS2DQZ128rrk, {0, Unknown}}, + {X86::VCVTPS2DQZ128rrkz, {0, Unknown}}, + {X86::VCVTPS2DQZ256rm, {0, Unknown}}, + {X86::VCVTPS2DQZ256rmb, {0, Unknown}}, + {X86::VCVTPS2DQZ256rmbk, {0, Unknown}}, + {X86::VCVTPS2DQZ256rmbkz, {0, Unknown}}, + {X86::VCVTPS2DQZ256rmk, {0, Unknown}}, + {X86::VCVTPS2DQZ256rmkz, {0, Unknown}}, + {X86::VCVTPS2DQZ256rr, {0, Unknown}}, + {X86::VCVTPS2DQZ256rrk, {0, Unknown}}, + {X86::VCVTPS2DQZ256rrkz, {0, Unknown}}, + {X86::VCVTPS2DQZrm, {0, Unknown}}, + {X86::VCVTPS2DQZrmb, {0, Unknown}}, + {X86::VCVTPS2DQZrmbk, {0, Unknown}}, + {X86::VCVTPS2DQZrmbkz, {0, Unknown}}, + {X86::VCVTPS2DQZrmk, {0, Unknown}}, + {X86::VCVTPS2DQZrmkz, {0, Unknown}}, + {X86::VCVTPS2DQZrr, {0, Unknown}}, + {X86::VCVTPS2DQZrrb, {0, Unknown}}, + {X86::VCVTPS2DQZrrbk, {0, Unknown}}, + {X86::VCVTPS2DQZrrbkz, {0, Unknown}}, + {X86::VCVTPS2DQZrrk, {0, Unknown}}, + {X86::VCVTPS2DQZrrkz, {0, Unknown}}, + {X86::VCVTPS2DQrm, {0, Unknown}}, + {X86::VCVTPS2DQrr, {0, Unknown}}, + {X86::VCVTPS2PDYrm, {0, Unknown}}, + {X86::VCVTPS2PDYrr, {0, Unknown}}, + {X86::VCVTPS2PDZ128rm, {1, Unknown}}, + {X86::VCVTPS2PDZ128rmb, {1, Unknown}}, + {X86::VCVTPS2PDZ128rmbk, {1, Unknown}}, + {X86::VCVTPS2PDZ128rmbkz, {1, Unknown}}, + {X86::VCVTPS2PDZ128rmk, {1, Unknown}}, + {X86::VCVTPS2PDZ128rmkz, {1, Unknown}}, + {X86::VCVTPS2PDZ128rr, {0, Unknown}}, + {X86::VCVTPS2PDZ128rrk, {0, Unknown}}, + {X86::VCVTPS2PDZ128rrkz, {0, Unknown}}, + {X86::VCVTPS2PDZ256rm, {0, Unknown}}, + {X86::VCVTPS2PDZ256rmb, {0, Unknown}}, + {X86::VCVTPS2PDZ256rmbk, {0, Unknown}}, + {X86::VCVTPS2PDZ256rmbkz, {0, Unknown}}, + {X86::VCVTPS2PDZ256rmk, {0, Unknown}}, + {X86::VCVTPS2PDZ256rmkz, {0, Unknown}}, + {X86::VCVTPS2PDZ256rr, {0, Unknown}}, + {X86::VCVTPS2PDZ256rrk, {0, Unknown}}, + {X86::VCVTPS2PDZ256rrkz, {0, Unknown}}, + {X86::VCVTPS2PDZrm, {0, Unknown}}, + {X86::VCVTPS2PDZrmb, {0, Unknown}}, + {X86::VCVTPS2PDZrmbk, {0, Unknown}}, + {X86::VCVTPS2PDZrmbkz, {0, Unknown}}, + {X86::VCVTPS2PDZrmk, {0, Unknown}}, + {X86::VCVTPS2PDZrmkz, {0, Unknown}}, + {X86::VCVTPS2PDZrr, {0, Unknown}}, + {X86::VCVTPS2PDZrrb, {0, Unknown}}, + {X86::VCVTPS2PDZrrbk, {0, Unknown}}, + {X86::VCVTPS2PDZrrbkz, {0, Unknown}}, + {X86::VCVTPS2PDZrrk, {0, Unknown}}, + {X86::VCVTPS2PDZrrkz, {0, Unknown}}, + {X86::VCVTPS2PDrm, {0, Unknown}}, + {X86::VCVTPS2PDrr, {0, Unknown}}, + {X86::VCVTPS2PHYmr, {0, Unknown}}, + {X86::VCVTPS2PHYrr, {0, Unknown}}, + {X86::VCVTPS2PHZ128mr, {1, Unknown}}, + {X86::VCVTPS2PHZ128mrk, {1, Unknown}}, + {X86::VCVTPS2PHZ128rr, {0, Unknown}}, + {X86::VCVTPS2PHZ128rrk, {0, Unknown}}, + {X86::VCVTPS2PHZ128rrkz, {0, Unknown}}, + {X86::VCVTPS2PHZ256mr, {0, Unknown}}, + {X86::VCVTPS2PHZ256mrk, {0, Unknown}}, + {X86::VCVTPS2PHZ256rr, {0, Unknown}}, + {X86::VCVTPS2PHZ256rrk, {0, Unknown}}, + {X86::VCVTPS2PHZ256rrkz, {0, Unknown}}, + {X86::VCVTPS2PHZmr, {0, Unknown}}, + {X86::VCVTPS2PHZmrk, {0, Unknown}}, + {X86::VCVTPS2PHZrr, {0, Unknown}}, + {X86::VCVTPS2PHZrrb, {0, Unknown}}, + {X86::VCVTPS2PHZrrbk, {0, Unknown}}, + {X86::VCVTPS2PHZrrbkz, {0, Unknown}}, + {X86::VCVTPS2PHZrrk, {0, Unknown}}, + {X86::VCVTPS2PHZrrkz, {0, Unknown}}, + {X86::VCVTPS2PHmr, {0, Unknown}}, + {X86::VCVTPS2PHrr, {0, Unknown}}, + {X86::VCVTPS2QQZ128rm, {1, Unknown}}, + {X86::VCVTPS2QQZ128rmb, {1, Unknown}}, + {X86::VCVTPS2QQZ128rmbk, {1, Unknown}}, + {X86::VCVTPS2QQZ128rmbkz, {1, Unknown}}, + {X86::VCVTPS2QQZ128rmk, {1, Unknown}}, + {X86::VCVTPS2QQZ128rmkz, {1, Unknown}}, + {X86::VCVTPS2QQZ128rr, {0, Unknown}}, + {X86::VCVTPS2QQZ128rrk, {0, Unknown}}, + {X86::VCVTPS2QQZ128rrkz, {0, Unknown}}, + {X86::VCVTPS2QQZ256rm, {0, Unknown}}, + {X86::VCVTPS2QQZ256rmb, {0, Unknown}}, + {X86::VCVTPS2QQZ256rmbk, {0, Unknown}}, + {X86::VCVTPS2QQZ256rmbkz, {0, Unknown}}, + {X86::VCVTPS2QQZ256rmk, {0, Unknown}}, + {X86::VCVTPS2QQZ256rmkz, {0, Unknown}}, + {X86::VCVTPS2QQZ256rr, {0, Unknown}}, + {X86::VCVTPS2QQZ256rrk, {0, Unknown}}, + {X86::VCVTPS2QQZ256rrkz, {0, Unknown}}, + {X86::VCVTPS2QQZrm, {0, Unknown}}, + {X86::VCVTPS2QQZrmb, {0, Unknown}}, + {X86::VCVTPS2QQZrmbk, {0, Unknown}}, + {X86::VCVTPS2QQZrmbkz, {0, Unknown}}, + {X86::VCVTPS2QQZrmk, {0, Unknown}}, + {X86::VCVTPS2QQZrmkz, {0, Unknown}}, + {X86::VCVTPS2QQZrr, {0, Unknown}}, + {X86::VCVTPS2QQZrrb, {0, Unknown}}, + {X86::VCVTPS2QQZrrbk, {0, Unknown}}, + {X86::VCVTPS2QQZrrbkz, {0, Unknown}}, + {X86::VCVTPS2QQZrrk, {0, Unknown}}, + {X86::VCVTPS2QQZrrkz, {0, Unknown}}, + {X86::VCVTPS2UDQZ128rm, {1, Unknown}}, + {X86::VCVTPS2UDQZ128rmb, {1, Unknown}}, + {X86::VCVTPS2UDQZ128rmbk, {1, Unknown}}, + {X86::VCVTPS2UDQZ128rmbkz, {1, Unknown}}, + {X86::VCVTPS2UDQZ128rmk, {1, Unknown}}, + {X86::VCVTPS2UDQZ128rmkz, {1, Unknown}}, + {X86::VCVTPS2UDQZ128rr, {0, Unknown}}, + {X86::VCVTPS2UDQZ128rrk, {0, Unknown}}, + {X86::VCVTPS2UDQZ128rrkz, {0, Unknown}}, + {X86::VCVTPS2UDQZ256rm, {0, Unknown}}, + {X86::VCVTPS2UDQZ256rmb, {0, Unknown}}, + {X86::VCVTPS2UDQZ256rmbk, {0, Unknown}}, + {X86::VCVTPS2UDQZ256rmbkz, {0, Unknown}}, + {X86::VCVTPS2UDQZ256rmk, {0, Unknown}}, + {X86::VCVTPS2UDQZ256rmkz, {0, Unknown}}, + {X86::VCVTPS2UDQZ256rr, {0, Unknown}}, + {X86::VCVTPS2UDQZ256rrk, {0, Unknown}}, + {X86::VCVTPS2UDQZ256rrkz, {0, Unknown}}, + {X86::VCVTPS2UDQZrm, {0, Unknown}}, + {X86::VCVTPS2UDQZrmb, {0, Unknown}}, + {X86::VCVTPS2UDQZrmbk, {0, Unknown}}, + {X86::VCVTPS2UDQZrmbkz, {0, Unknown}}, + {X86::VCVTPS2UDQZrmk, {0, Unknown}}, + {X86::VCVTPS2UDQZrmkz, {0, Unknown}}, + {X86::VCVTPS2UDQZrr, {0, Unknown}}, + {X86::VCVTPS2UDQZrrb, {0, Unknown}}, + {X86::VCVTPS2UDQZrrbk, {0, Unknown}}, + {X86::VCVTPS2UDQZrrbkz, {0, Unknown}}, + {X86::VCVTPS2UDQZrrk, {0, Unknown}}, + {X86::VCVTPS2UDQZrrkz, {0, Unknown}}, + {X86::VCVTPS2UQQZ128rm, {1, Unknown}}, + {X86::VCVTPS2UQQZ128rmb, {1, Unknown}}, + {X86::VCVTPS2UQQZ128rmbk, {1, Unknown}}, + {X86::VCVTPS2UQQZ128rmbkz, {1, Unknown}}, + {X86::VCVTPS2UQQZ128rmk, {1, Unknown}}, + {X86::VCVTPS2UQQZ128rmkz, {1, Unknown}}, + {X86::VCVTPS2UQQZ128rr, {0, Unknown}}, + {X86::VCVTPS2UQQZ128rrk, {0, Unknown}}, + {X86::VCVTPS2UQQZ128rrkz, {0, Unknown}}, + {X86::VCVTPS2UQQZ256rm, {0, Unknown}}, + {X86::VCVTPS2UQQZ256rmb, {0, Unknown}}, + {X86::VCVTPS2UQQZ256rmbk, {0, Unknown}}, + {X86::VCVTPS2UQQZ256rmbkz, {0, Unknown}}, + {X86::VCVTPS2UQQZ256rmk, {0, Unknown}}, + {X86::VCVTPS2UQQZ256rmkz, {0, Unknown}}, + {X86::VCVTPS2UQQZ256rr, {0, Unknown}}, + {X86::VCVTPS2UQQZ256rrk, {0, Unknown}}, + {X86::VCVTPS2UQQZ256rrkz, {0, Unknown}}, + {X86::VCVTPS2UQQZrm, {0, Unknown}}, + {X86::VCVTPS2UQQZrmb, {0, Unknown}}, + {X86::VCVTPS2UQQZrmbk, {0, Unknown}}, + {X86::VCVTPS2UQQZrmbkz, {0, Unknown}}, + {X86::VCVTPS2UQQZrmk, {0, Unknown}}, + {X86::VCVTPS2UQQZrmkz, {0, Unknown}}, + {X86::VCVTPS2UQQZrr, {0, Unknown}}, + {X86::VCVTPS2UQQZrrb, {0, Unknown}}, + {X86::VCVTPS2UQQZrrbk, {0, Unknown}}, + {X86::VCVTPS2UQQZrrbkz, {0, Unknown}}, + {X86::VCVTPS2UQQZrrk, {0, Unknown}}, + {X86::VCVTPS2UQQZrrkz, {0, Unknown}}, + {X86::VCVTQQ2PDZ128rm, {1, Unknown}}, + {X86::VCVTQQ2PDZ128rmb, {1, Unknown}}, + {X86::VCVTQQ2PDZ128rmbk, {1, Unknown}}, + {X86::VCVTQQ2PDZ128rmbkz, {1, Unknown}}, + {X86::VCVTQQ2PDZ128rmk, {1, Unknown}}, + {X86::VCVTQQ2PDZ128rmkz, {1, Unknown}}, + {X86::VCVTQQ2PDZ128rr, {0, Unknown}}, + {X86::VCVTQQ2PDZ128rrk, {0, Unknown}}, + {X86::VCVTQQ2PDZ128rrkz, {0, Unknown}}, + {X86::VCVTQQ2PDZ256rm, {0, Unknown}}, + {X86::VCVTQQ2PDZ256rmb, {0, Unknown}}, + {X86::VCVTQQ2PDZ256rmbk, {0, Unknown}}, + {X86::VCVTQQ2PDZ256rmbkz, {0, Unknown}}, + {X86::VCVTQQ2PDZ256rmk, {0, Unknown}}, + {X86::VCVTQQ2PDZ256rmkz, {0, Unknown}}, + {X86::VCVTQQ2PDZ256rr, {0, Unknown}}, + {X86::VCVTQQ2PDZ256rrk, {0, Unknown}}, + {X86::VCVTQQ2PDZ256rrkz, {0, Unknown}}, + {X86::VCVTQQ2PDZrm, {0, Unknown}}, + {X86::VCVTQQ2PDZrmb, {0, Unknown}}, + {X86::VCVTQQ2PDZrmbk, {0, Unknown}}, + {X86::VCVTQQ2PDZrmbkz, {0, Unknown}}, + {X86::VCVTQQ2PDZrmk, {0, Unknown}}, + {X86::VCVTQQ2PDZrmkz, {0, Unknown}}, + {X86::VCVTQQ2PDZrr, {0, Unknown}}, + {X86::VCVTQQ2PDZrrb, {0, Unknown}}, + {X86::VCVTQQ2PDZrrbk, {0, Unknown}}, + {X86::VCVTQQ2PDZrrbkz, {0, Unknown}}, + {X86::VCVTQQ2PDZrrk, {0, Unknown}}, + {X86::VCVTQQ2PDZrrkz, {0, Unknown}}, + {X86::VCVTQQ2PSZ128rm, {1, Unknown}}, + {X86::VCVTQQ2PSZ128rmb, {1, Unknown}}, + {X86::VCVTQQ2PSZ128rmbk, {1, Unknown}}, + {X86::VCVTQQ2PSZ128rmbkz, {1, Unknown}}, + {X86::VCVTQQ2PSZ128rmk, {1, Unknown}}, + {X86::VCVTQQ2PSZ128rmkz, {1, Unknown}}, + {X86::VCVTQQ2PSZ128rr, {0, Unknown}}, + {X86::VCVTQQ2PSZ128rrk, {0, Unknown}}, + {X86::VCVTQQ2PSZ128rrkz, {0, Unknown}}, + {X86::VCVTQQ2PSZ256rm, {0, Unknown}}, + {X86::VCVTQQ2PSZ256rmb, {0, Unknown}}, + {X86::VCVTQQ2PSZ256rmbk, {0, Unknown}}, + {X86::VCVTQQ2PSZ256rmbkz, {0, Unknown}}, + {X86::VCVTQQ2PSZ256rmk, {0, Unknown}}, + {X86::VCVTQQ2PSZ256rmkz, {0, Unknown}}, + {X86::VCVTQQ2PSZ256rr, {0, Unknown}}, + {X86::VCVTQQ2PSZ256rrk, {0, Unknown}}, + {X86::VCVTQQ2PSZ256rrkz, {0, Unknown}}, + {X86::VCVTQQ2PSZrm, {0, Unknown}}, + {X86::VCVTQQ2PSZrmb, {0, Unknown}}, + {X86::VCVTQQ2PSZrmbk, {0, Unknown}}, + {X86::VCVTQQ2PSZrmbkz, {0, Unknown}}, + {X86::VCVTQQ2PSZrmk, {0, Unknown}}, + {X86::VCVTQQ2PSZrmkz, {0, Unknown}}, + {X86::VCVTQQ2PSZrr, {0, Unknown}}, + {X86::VCVTQQ2PSZrrb, {0, Unknown}}, + {X86::VCVTQQ2PSZrrbk, {0, Unknown}}, + {X86::VCVTQQ2PSZrrbkz, {0, Unknown}}, + {X86::VCVTQQ2PSZrrk, {0, Unknown}}, + {X86::VCVTQQ2PSZrrkz, {0, Unknown}}, + {X86::VCVTSD2SI64Zrm_Int, {0, Unknown}}, + {X86::VCVTSD2SI64Zrr_Int, {0, Unknown}}, + {X86::VCVTSD2SI64Zrrb_Int, {0, Unknown}}, + {X86::VCVTSD2SI64rm_Int, {8, Unknown}}, + {X86::VCVTSD2SI64rr_Int, {0, Unknown}}, + {X86::VCVTSD2SIZrm_Int, {0, Unknown}}, + {X86::VCVTSD2SIZrr_Int, {0, Unknown}}, + {X86::VCVTSD2SIZrrb_Int, {0, Unknown}}, + {X86::VCVTSD2SIrm_Int, {0, Unknown}}, + {X86::VCVTSD2SIrr_Int, {0, Unknown}}, + {X86::VCVTSD2SSZrm, {0, Unknown}}, + {X86::VCVTSD2SSZrm_Int, {0, Unknown}}, + {X86::VCVTSD2SSZrm_Intk, {0, Unknown}}, + {X86::VCVTSD2SSZrm_Intkz, {0, Unknown}}, + {X86::VCVTSD2SSZrr, {0, Unknown}}, + {X86::VCVTSD2SSZrr_Int, {0, Unknown}}, + {X86::VCVTSD2SSZrr_Intk, {0, Unknown}}, + {X86::VCVTSD2SSZrr_Intkz, {0, Unknown}}, + {X86::VCVTSD2SSZrrb_Int, {0, Unknown}}, + {X86::VCVTSD2SSZrrb_Intk, {0, Unknown}}, + {X86::VCVTSD2SSZrrb_Intkz, {0, Unknown}}, + {X86::VCVTSD2SSrm, {0, Unknown}}, + {X86::VCVTSD2SSrm_Int, {0, Unknown}}, + {X86::VCVTSD2SSrr, {0, Unknown}}, + {X86::VCVTSD2SSrr_Int, {0, Unknown}}, + {X86::VCVTSD2USI64Zrm_Int, {0, Unknown}}, + {X86::VCVTSD2USI64Zrr_Int, {0, Unknown}}, + {X86::VCVTSD2USI64Zrrb_Int, {0, Unknown}}, + {X86::VCVTSD2USIZrm_Int, {0, Unknown}}, + {X86::VCVTSD2USIZrr_Int, {0, Unknown}}, + {X86::VCVTSD2USIZrrb_Int, {0, Unknown}}, + {X86::VCVTSI2SDZrm, {0, Unknown}}, + {X86::VCVTSI2SDZrm_Int, {0, Unknown}}, + {X86::VCVTSI2SDZrr, {0, Unknown}}, + {X86::VCVTSI2SDZrr_Int, {0, Unknown}}, + {X86::VCVTSI2SDZrrb_Int, {0, Unknown}}, + {X86::VCVTSI2SDrm, {0, Unknown}}, + {X86::VCVTSI2SDrm_Int, {0, Unknown}}, + {X86::VCVTSI2SDrr, {0, Unknown}}, + {X86::VCVTSI2SDrr_Int, {0, Unknown}}, + {X86::VCVTSI2SSZrm, {0, Unknown}}, + {X86::VCVTSI2SSZrm_Int, {0, Unknown}}, + {X86::VCVTSI2SSZrr, {0, Unknown}}, + {X86::VCVTSI2SSZrr_Int, {0, Unknown}}, + {X86::VCVTSI2SSZrrb_Int, {0, Unknown}}, + {X86::VCVTSI2SSrm, {0, Unknown}}, + {X86::VCVTSI2SSrm_Int, {0, Unknown}}, + {X86::VCVTSI2SSrr, {0, Unknown}}, + {X86::VCVTSI2SSrr_Int, {0, Unknown}}, + {X86::VCVTSI642SDZrm, {0, Unknown}}, + {X86::VCVTSI642SDZrm_Int, {0, Unknown}}, + {X86::VCVTSI642SDZrr, {0, Unknown}}, + {X86::VCVTSI642SDZrr_Int, {0, Unknown}}, + {X86::VCVTSI642SDZrrb_Int, {0, Unknown}}, + {X86::VCVTSI642SDrm, {0, Unknown}}, + {X86::VCVTSI642SDrm_Int, {0, Unknown}}, + {X86::VCVTSI642SDrr, {0, Unknown}}, + {X86::VCVTSI642SDrr_Int, {0, Unknown}}, + {X86::VCVTSI642SSZrm, {0, Unknown}}, + {X86::VCVTSI642SSZrm_Int, {0, Unknown}}, + {X86::VCVTSI642SSZrr, {0, Unknown}}, + {X86::VCVTSI642SSZrr_Int, {0, Unknown}}, + {X86::VCVTSI642SSZrrb_Int, {0, Unknown}}, + {X86::VCVTSI642SSrm, {0, Unknown}}, + {X86::VCVTSI642SSrm_Int, {0, Unknown}}, + {X86::VCVTSI642SSrr, {0, Unknown}}, + {X86::VCVTSI642SSrr_Int, {0, Unknown}}, + {X86::VCVTSS2SDZrm, {0, Unknown}}, + {X86::VCVTSS2SDZrm_Int, {0, Unknown}}, + {X86::VCVTSS2SDZrm_Intk, {0, Unknown}}, + {X86::VCVTSS2SDZrm_Intkz, {0, Unknown}}, + {X86::VCVTSS2SDZrr, {0, Unknown}}, + {X86::VCVTSS2SDZrr_Int, {0, Unknown}}, + {X86::VCVTSS2SDZrr_Intk, {0, Unknown}}, + {X86::VCVTSS2SDZrr_Intkz, {0, Unknown}}, + {X86::VCVTSS2SDZrrb_Int, {0, Unknown}}, + {X86::VCVTSS2SDZrrb_Intk, {0, Unknown}}, + {X86::VCVTSS2SDZrrb_Intkz, {0, Unknown}}, + {X86::VCVTSS2SDrm, {0, Unknown}}, + {X86::VCVTSS2SDrm_Int, {0, Unknown}}, + {X86::VCVTSS2SDrr, {0, Unknown}}, + {X86::VCVTSS2SDrr_Int, {0, Unknown}}, + {X86::VCVTSS2SI64Zrm_Int, {0, Unknown}}, + {X86::VCVTSS2SI64Zrr_Int, {0, Unknown}}, + {X86::VCVTSS2SI64Zrrb_Int, {0, Unknown}}, + {X86::VCVTSS2SI64rm_Int, {8, Unknown}}, + {X86::VCVTSS2SI64rr_Int, {0, Unknown}}, + {X86::VCVTSS2SIZrm_Int, {0, Unknown}}, + {X86::VCVTSS2SIZrr_Int, {0, Unknown}}, + {X86::VCVTSS2SIZrrb_Int, {0, Unknown}}, + {X86::VCVTSS2SIrm_Int, {0, Unknown}}, + {X86::VCVTSS2SIrr_Int, {0, Unknown}}, + {X86::VCVTSS2USI64Zrm_Int, {0, Unknown}}, + {X86::VCVTSS2USI64Zrr_Int, {0, Unknown}}, + {X86::VCVTSS2USI64Zrrb_Int, {0, Unknown}}, + {X86::VCVTSS2USIZrm_Int, {0, Unknown}}, + {X86::VCVTSS2USIZrr_Int, {0, Unknown}}, + {X86::VCVTSS2USIZrrb_Int, {0, Unknown}}, + {X86::VCVTTPD2DQYrm, {0, Unknown}}, + {X86::VCVTTPD2DQYrr, {0, Unknown}}, + {X86::VCVTTPD2DQZ128rm, {1, Unknown}}, + {X86::VCVTTPD2DQZ128rmb, {1, Unknown}}, + {X86::VCVTTPD2DQZ128rmbk, {1, Unknown}}, + {X86::VCVTTPD2DQZ128rmbkz, {1, Unknown}}, + {X86::VCVTTPD2DQZ128rmk, {1, Unknown}}, + {X86::VCVTTPD2DQZ128rmkz, {1, Unknown}}, + {X86::VCVTTPD2DQZ128rr, {0, Unknown}}, + {X86::VCVTTPD2DQZ128rrk, {0, Unknown}}, + {X86::VCVTTPD2DQZ128rrkz, {0, Unknown}}, + {X86::VCVTTPD2DQZ256rm, {0, Unknown}}, + {X86::VCVTTPD2DQZ256rmb, {0, Unknown}}, + {X86::VCVTTPD2DQZ256rmbk, {0, Unknown}}, + {X86::VCVTTPD2DQZ256rmbkz, {0, Unknown}}, + {X86::VCVTTPD2DQZ256rmk, {0, Unknown}}, + {X86::VCVTTPD2DQZ256rmkz, {0, Unknown}}, + {X86::VCVTTPD2DQZ256rr, {0, Unknown}}, + {X86::VCVTTPD2DQZ256rrk, {0, Unknown}}, + {X86::VCVTTPD2DQZ256rrkz, {0, Unknown}}, + {X86::VCVTTPD2DQZrm, {0, Unknown}}, + {X86::VCVTTPD2DQZrmb, {0, Unknown}}, + {X86::VCVTTPD2DQZrmbk, {0, Unknown}}, + {X86::VCVTTPD2DQZrmbkz, {0, Unknown}}, + {X86::VCVTTPD2DQZrmk, {0, Unknown}}, + {X86::VCVTTPD2DQZrmkz, {0, Unknown}}, + {X86::VCVTTPD2DQZrr, {0, Unknown}}, + {X86::VCVTTPD2DQZrrb, {0, Unknown}}, + {X86::VCVTTPD2DQZrrbk, {0, Unknown}}, + {X86::VCVTTPD2DQZrrbkz, {0, Unknown}}, + {X86::VCVTTPD2DQZrrk, {0, Unknown}}, + {X86::VCVTTPD2DQZrrkz, {0, Unknown}}, + {X86::VCVTTPD2DQrm, {0, Unknown}}, + {X86::VCVTTPD2DQrr, {0, Unknown}}, + {X86::VCVTTPD2QQZ128rm, {1, Unknown}}, + {X86::VCVTTPD2QQZ128rmb, {1, Unknown}}, + {X86::VCVTTPD2QQZ128rmbk, {1, Unknown}}, + {X86::VCVTTPD2QQZ128rmbkz, {1, Unknown}}, + {X86::VCVTTPD2QQZ128rmk, {1, Unknown}}, + {X86::VCVTTPD2QQZ128rmkz, {1, Unknown}}, + {X86::VCVTTPD2QQZ128rr, {0, Unknown}}, + {X86::VCVTTPD2QQZ128rrk, {0, Unknown}}, + {X86::VCVTTPD2QQZ128rrkz, {0, Unknown}}, + {X86::VCVTTPD2QQZ256rm, {0, Unknown}}, + {X86::VCVTTPD2QQZ256rmb, {0, Unknown}}, + {X86::VCVTTPD2QQZ256rmbk, {0, Unknown}}, + {X86::VCVTTPD2QQZ256rmbkz, {0, Unknown}}, + {X86::VCVTTPD2QQZ256rmk, {0, Unknown}}, + {X86::VCVTTPD2QQZ256rmkz, {0, Unknown}}, + {X86::VCVTTPD2QQZ256rr, {0, Unknown}}, + {X86::VCVTTPD2QQZ256rrk, {0, Unknown}}, + {X86::VCVTTPD2QQZ256rrkz, {0, Unknown}}, + {X86::VCVTTPD2QQZrm, {0, Unknown}}, + {X86::VCVTTPD2QQZrmb, {0, Unknown}}, + {X86::VCVTTPD2QQZrmbk, {0, Unknown}}, + {X86::VCVTTPD2QQZrmbkz, {0, Unknown}}, + {X86::VCVTTPD2QQZrmk, {0, Unknown}}, + {X86::VCVTTPD2QQZrmkz, {0, Unknown}}, + {X86::VCVTTPD2QQZrr, {0, Unknown}}, + {X86::VCVTTPD2QQZrrb, {0, Unknown}}, + {X86::VCVTTPD2QQZrrbk, {0, Unknown}}, + {X86::VCVTTPD2QQZrrbkz, {0, Unknown}}, + {X86::VCVTTPD2QQZrrk, {0, Unknown}}, + {X86::VCVTTPD2QQZrrkz, {0, Unknown}}, + {X86::VCVTTPD2UDQZ128rm, {1, Unknown}}, + {X86::VCVTTPD2UDQZ128rmb, {1, Unknown}}, + {X86::VCVTTPD2UDQZ128rmbk, {1, Unknown}}, + {X86::VCVTTPD2UDQZ128rmbkz, {1, Unknown}}, + {X86::VCVTTPD2UDQZ128rmk, {1, Unknown}}, + {X86::VCVTTPD2UDQZ128rmkz, {1, Unknown}}, + {X86::VCVTTPD2UDQZ128rr, {0, Unknown}}, + {X86::VCVTTPD2UDQZ128rrk, {0, Unknown}}, + {X86::VCVTTPD2UDQZ128rrkz, {0, Unknown}}, + {X86::VCVTTPD2UDQZ256rm, {0, Unknown}}, + {X86::VCVTTPD2UDQZ256rmb, {0, Unknown}}, + {X86::VCVTTPD2UDQZ256rmbk, {0, Unknown}}, + {X86::VCVTTPD2UDQZ256rmbkz, {0, Unknown}}, + {X86::VCVTTPD2UDQZ256rmk, {0, Unknown}}, + {X86::VCVTTPD2UDQZ256rmkz, {0, Unknown}}, + {X86::VCVTTPD2UDQZ256rr, {0, Unknown}}, + {X86::VCVTTPD2UDQZ256rrk, {0, Unknown}}, + {X86::VCVTTPD2UDQZ256rrkz, {0, Unknown}}, + {X86::VCVTTPD2UDQZrm, {0, Unknown}}, + {X86::VCVTTPD2UDQZrmb, {0, Unknown}}, + {X86::VCVTTPD2UDQZrmbk, {0, Unknown}}, + {X86::VCVTTPD2UDQZrmbkz, {0, Unknown}}, + {X86::VCVTTPD2UDQZrmk, {0, Unknown}}, + {X86::VCVTTPD2UDQZrmkz, {0, Unknown}}, + {X86::VCVTTPD2UDQZrr, {0, Unknown}}, + {X86::VCVTTPD2UDQZrrb, {0, Unknown}}, + {X86::VCVTTPD2UDQZrrbk, {0, Unknown}}, + {X86::VCVTTPD2UDQZrrbkz, {0, Unknown}}, + {X86::VCVTTPD2UDQZrrk, {0, Unknown}}, + {X86::VCVTTPD2UDQZrrkz, {0, Unknown}}, + {X86::VCVTTPD2UQQZ128rm, {1, Unknown}}, + {X86::VCVTTPD2UQQZ128rmb, {1, Unknown}}, + {X86::VCVTTPD2UQQZ128rmbk, {1, Unknown}}, + {X86::VCVTTPD2UQQZ128rmbkz, {1, Unknown}}, + {X86::VCVTTPD2UQQZ128rmk, {1, Unknown}}, + {X86::VCVTTPD2UQQZ128rmkz, {1, Unknown}}, + {X86::VCVTTPD2UQQZ128rr, {0, Unknown}}, + {X86::VCVTTPD2UQQZ128rrk, {0, Unknown}}, + {X86::VCVTTPD2UQQZ128rrkz, {0, Unknown}}, + {X86::VCVTTPD2UQQZ256rm, {0, Unknown}}, + {X86::VCVTTPD2UQQZ256rmb, {0, Unknown}}, + {X86::VCVTTPD2UQQZ256rmbk, {0, Unknown}}, + {X86::VCVTTPD2UQQZ256rmbkz, {0, Unknown}}, + {X86::VCVTTPD2UQQZ256rmk, {0, Unknown}}, + {X86::VCVTTPD2UQQZ256rmkz, {0, Unknown}}, + {X86::VCVTTPD2UQQZ256rr, {0, Unknown}}, + {X86::VCVTTPD2UQQZ256rrk, {0, Unknown}}, + {X86::VCVTTPD2UQQZ256rrkz, {0, Unknown}}, + {X86::VCVTTPD2UQQZrm, {0, Unknown}}, + {X86::VCVTTPD2UQQZrmb, {0, Unknown}}, + {X86::VCVTTPD2UQQZrmbk, {0, Unknown}}, + {X86::VCVTTPD2UQQZrmbkz, {0, Unknown}}, + {X86::VCVTTPD2UQQZrmk, {0, Unknown}}, + {X86::VCVTTPD2UQQZrmkz, {0, Unknown}}, + {X86::VCVTTPD2UQQZrr, {0, Unknown}}, + {X86::VCVTTPD2UQQZrrb, {0, Unknown}}, + {X86::VCVTTPD2UQQZrrbk, {0, Unknown}}, + {X86::VCVTTPD2UQQZrrbkz, {0, Unknown}}, + {X86::VCVTTPD2UQQZrrk, {0, Unknown}}, + {X86::VCVTTPD2UQQZrrkz, {0, Unknown}}, + {X86::VCVTTPS2DQYrm, {0, Unknown}}, + {X86::VCVTTPS2DQYrr, {0, Unknown}}, + {X86::VCVTTPS2DQZ128rm, {1, Unknown}}, + {X86::VCVTTPS2DQZ128rmb, {1, Unknown}}, + {X86::VCVTTPS2DQZ128rmbk, {1, Unknown}}, + {X86::VCVTTPS2DQZ128rmbkz, {1, Unknown}}, + {X86::VCVTTPS2DQZ128rmk, {1, Unknown}}, + {X86::VCVTTPS2DQZ128rmkz, {1, Unknown}}, + {X86::VCVTTPS2DQZ128rr, {0, Unknown}}, + {X86::VCVTTPS2DQZ128rrk, {0, Unknown}}, + {X86::VCVTTPS2DQZ128rrkz, {0, Unknown}}, + {X86::VCVTTPS2DQZ256rm, {0, Unknown}}, + {X86::VCVTTPS2DQZ256rmb, {0, Unknown}}, + {X86::VCVTTPS2DQZ256rmbk, {0, Unknown}}, + {X86::VCVTTPS2DQZ256rmbkz, {0, Unknown}}, + {X86::VCVTTPS2DQZ256rmk, {0, Unknown}}, + {X86::VCVTTPS2DQZ256rmkz, {0, Unknown}}, + {X86::VCVTTPS2DQZ256rr, {0, Unknown}}, + {X86::VCVTTPS2DQZ256rrk, {0, Unknown}}, + {X86::VCVTTPS2DQZ256rrkz, {0, Unknown}}, + {X86::VCVTTPS2DQZrm, {0, Unknown}}, + {X86::VCVTTPS2DQZrmb, {0, Unknown}}, + {X86::VCVTTPS2DQZrmbk, {0, Unknown}}, + {X86::VCVTTPS2DQZrmbkz, {0, Unknown}}, + {X86::VCVTTPS2DQZrmk, {0, Unknown}}, + {X86::VCVTTPS2DQZrmkz, {0, Unknown}}, + {X86::VCVTTPS2DQZrr, {0, Unknown}}, + {X86::VCVTTPS2DQZrrb, {0, Unknown}}, + {X86::VCVTTPS2DQZrrbk, {0, Unknown}}, + {X86::VCVTTPS2DQZrrbkz, {0, Unknown}}, + {X86::VCVTTPS2DQZrrk, {0, Unknown}}, + {X86::VCVTTPS2DQZrrkz, {0, Unknown}}, + {X86::VCVTTPS2DQrm, {0, Unknown}}, + {X86::VCVTTPS2DQrr, {0, Unknown}}, + {X86::VCVTTPS2QQZ128rm, {1, Unknown}}, + {X86::VCVTTPS2QQZ128rmb, {1, Unknown}}, + {X86::VCVTTPS2QQZ128rmbk, {1, Unknown}}, + {X86::VCVTTPS2QQZ128rmbkz, {1, Unknown}}, + {X86::VCVTTPS2QQZ128rmk, {1, Unknown}}, + {X86::VCVTTPS2QQZ128rmkz, {1, Unknown}}, + {X86::VCVTTPS2QQZ128rr, {0, Unknown}}, + {X86::VCVTTPS2QQZ128rrk, {0, Unknown}}, + {X86::VCVTTPS2QQZ128rrkz, {0, Unknown}}, + {X86::VCVTTPS2QQZ256rm, {0, Unknown}}, + {X86::VCVTTPS2QQZ256rmb, {0, Unknown}}, + {X86::VCVTTPS2QQZ256rmbk, {0, Unknown}}, + {X86::VCVTTPS2QQZ256rmbkz, {0, Unknown}}, + {X86::VCVTTPS2QQZ256rmk, {0, Unknown}}, + {X86::VCVTTPS2QQZ256rmkz, {0, Unknown}}, + {X86::VCVTTPS2QQZ256rr, {0, Unknown}}, + {X86::VCVTTPS2QQZ256rrk, {0, Unknown}}, + {X86::VCVTTPS2QQZ256rrkz, {0, Unknown}}, + {X86::VCVTTPS2QQZrm, {0, Unknown}}, + {X86::VCVTTPS2QQZrmb, {0, Unknown}}, + {X86::VCVTTPS2QQZrmbk, {0, Unknown}}, + {X86::VCVTTPS2QQZrmbkz, {0, Unknown}}, + {X86::VCVTTPS2QQZrmk, {0, Unknown}}, + {X86::VCVTTPS2QQZrmkz, {0, Unknown}}, + {X86::VCVTTPS2QQZrr, {0, Unknown}}, + {X86::VCVTTPS2QQZrrb, {0, Unknown}}, + {X86::VCVTTPS2QQZrrbk, {0, Unknown}}, + {X86::VCVTTPS2QQZrrbkz, {0, Unknown}}, + {X86::VCVTTPS2QQZrrk, {0, Unknown}}, + {X86::VCVTTPS2QQZrrkz, {0, Unknown}}, + {X86::VCVTTPS2UDQZ128rm, {1, Unknown}}, + {X86::VCVTTPS2UDQZ128rmb, {1, Unknown}}, + {X86::VCVTTPS2UDQZ128rmbk, {1, Unknown}}, + {X86::VCVTTPS2UDQZ128rmbkz, {1, Unknown}}, + {X86::VCVTTPS2UDQZ128rmk, {1, Unknown}}, + {X86::VCVTTPS2UDQZ128rmkz, {1, Unknown}}, + {X86::VCVTTPS2UDQZ128rr, {0, Unknown}}, + {X86::VCVTTPS2UDQZ128rrk, {0, Unknown}}, + {X86::VCVTTPS2UDQZ128rrkz, {0, Unknown}}, + {X86::VCVTTPS2UDQZ256rm, {0, Unknown}}, + {X86::VCVTTPS2UDQZ256rmb, {0, Unknown}}, + {X86::VCVTTPS2UDQZ256rmbk, {0, Unknown}}, + {X86::VCVTTPS2UDQZ256rmbkz, {0, Unknown}}, + {X86::VCVTTPS2UDQZ256rmk, {0, Unknown}}, + {X86::VCVTTPS2UDQZ256rmkz, {0, Unknown}}, + {X86::VCVTTPS2UDQZ256rr, {0, Unknown}}, + {X86::VCVTTPS2UDQZ256rrk, {0, Unknown}}, + {X86::VCVTTPS2UDQZ256rrkz, {0, Unknown}}, + {X86::VCVTTPS2UDQZrm, {0, Unknown}}, + {X86::VCVTTPS2UDQZrmb, {0, Unknown}}, + {X86::VCVTTPS2UDQZrmbk, {0, Unknown}}, + {X86::VCVTTPS2UDQZrmbkz, {0, Unknown}}, + {X86::VCVTTPS2UDQZrmk, {0, Unknown}}, + {X86::VCVTTPS2UDQZrmkz, {0, Unknown}}, + {X86::VCVTTPS2UDQZrr, {0, Unknown}}, + {X86::VCVTTPS2UDQZrrb, {0, Unknown}}, + {X86::VCVTTPS2UDQZrrbk, {0, Unknown}}, + {X86::VCVTTPS2UDQZrrbkz, {0, Unknown}}, + {X86::VCVTTPS2UDQZrrk, {0, Unknown}}, + {X86::VCVTTPS2UDQZrrkz, {0, Unknown}}, + {X86::VCVTTPS2UQQZ128rm, {1, Unknown}}, + {X86::VCVTTPS2UQQZ128rmb, {1, Unknown}}, + {X86::VCVTTPS2UQQZ128rmbk, {1, Unknown}}, + {X86::VCVTTPS2UQQZ128rmbkz, {1, Unknown}}, + {X86::VCVTTPS2UQQZ128rmk, {1, Unknown}}, + {X86::VCVTTPS2UQQZ128rmkz, {1, Unknown}}, + {X86::VCVTTPS2UQQZ128rr, {0, Unknown}}, + {X86::VCVTTPS2UQQZ128rrk, {0, Unknown}}, + {X86::VCVTTPS2UQQZ128rrkz, {0, Unknown}}, + {X86::VCVTTPS2UQQZ256rm, {0, Unknown}}, + {X86::VCVTTPS2UQQZ256rmb, {0, Unknown}}, + {X86::VCVTTPS2UQQZ256rmbk, {0, Unknown}}, + {X86::VCVTTPS2UQQZ256rmbkz, {0, Unknown}}, + {X86::VCVTTPS2UQQZ256rmk, {0, Unknown}}, + {X86::VCVTTPS2UQQZ256rmkz, {0, Unknown}}, + {X86::VCVTTPS2UQQZ256rr, {0, Unknown}}, + {X86::VCVTTPS2UQQZ256rrk, {0, Unknown}}, + {X86::VCVTTPS2UQQZ256rrkz, {0, Unknown}}, + {X86::VCVTTPS2UQQZrm, {0, Unknown}}, + {X86::VCVTTPS2UQQZrmb, {0, Unknown}}, + {X86::VCVTTPS2UQQZrmbk, {0, Unknown}}, + {X86::VCVTTPS2UQQZrmbkz, {0, Unknown}}, + {X86::VCVTTPS2UQQZrmk, {0, Unknown}}, + {X86::VCVTTPS2UQQZrmkz, {0, Unknown}}, + {X86::VCVTTPS2UQQZrr, {0, Unknown}}, + {X86::VCVTTPS2UQQZrrb, {0, Unknown}}, + {X86::VCVTTPS2UQQZrrbk, {0, Unknown}}, + {X86::VCVTTPS2UQQZrrbkz, {0, Unknown}}, + {X86::VCVTTPS2UQQZrrk, {0, Unknown}}, + {X86::VCVTTPS2UQQZrrkz, {0, Unknown}}, + {X86::VCVTTSD2SI64Zrm, {0, Unknown}}, + {X86::VCVTTSD2SI64Zrm_Int, {0, Unknown}}, + {X86::VCVTTSD2SI64Zrr, {0, Unknown}}, + {X86::VCVTTSD2SI64Zrr_Int, {0, Unknown}}, + {X86::VCVTTSD2SI64Zrrb_Int, {0, Unknown}}, + {X86::VCVTTSD2SI64rm, {8, Unknown}}, + {X86::VCVTTSD2SI64rm_Int, {8, Unknown}}, + {X86::VCVTTSD2SI64rr, {0, Unknown}}, + {X86::VCVTTSD2SI64rr_Int, {0, Unknown}}, + {X86::VCVTTSD2SIZrm, {0, Unknown}}, + {X86::VCVTTSD2SIZrm_Int, {0, Unknown}}, + {X86::VCVTTSD2SIZrr, {0, Unknown}}, + {X86::VCVTTSD2SIZrr_Int, {0, Unknown}}, + {X86::VCVTTSD2SIZrrb_Int, {0, Unknown}}, + {X86::VCVTTSD2SIrm, {0, Unknown}}, + {X86::VCVTTSD2SIrm_Int, {0, Unknown}}, + {X86::VCVTTSD2SIrr, {0, Unknown}}, + {X86::VCVTTSD2SIrr_Int, {0, Unknown}}, + {X86::VCVTTSD2USI64Zrm, {0, Unknown}}, + {X86::VCVTTSD2USI64Zrm_Int, {0, Unknown}}, + {X86::VCVTTSD2USI64Zrr, {0, Unknown}}, + {X86::VCVTTSD2USI64Zrr_Int, {0, Unknown}}, + {X86::VCVTTSD2USI64Zrrb_Int, {0, Unknown}}, + {X86::VCVTTSD2USIZrm, {0, Unknown}}, + {X86::VCVTTSD2USIZrm_Int, {0, Unknown}}, + {X86::VCVTTSD2USIZrr, {0, Unknown}}, + {X86::VCVTTSD2USIZrr_Int, {0, Unknown}}, + {X86::VCVTTSD2USIZrrb_Int, {0, Unknown}}, + {X86::VCVTTSS2SI64Zrm, {0, Unknown}}, + {X86::VCVTTSS2SI64Zrm_Int, {0, Unknown}}, + {X86::VCVTTSS2SI64Zrr, {0, Unknown}}, + {X86::VCVTTSS2SI64Zrr_Int, {0, Unknown}}, + {X86::VCVTTSS2SI64Zrrb_Int, {0, Unknown}}, + {X86::VCVTTSS2SI64rm, {8, Unknown}}, + {X86::VCVTTSS2SI64rm_Int, {8, Unknown}}, + {X86::VCVTTSS2SI64rr, {0, Unknown}}, + {X86::VCVTTSS2SI64rr_Int, {0, Unknown}}, + {X86::VCVTTSS2SIZrm, {0, Unknown}}, + {X86::VCVTTSS2SIZrm_Int, {0, Unknown}}, + {X86::VCVTTSS2SIZrr, {0, Unknown}}, + {X86::VCVTTSS2SIZrr_Int, {0, Unknown}}, + {X86::VCVTTSS2SIZrrb_Int, {0, Unknown}}, + {X86::VCVTTSS2SIrm, {0, Unknown}}, + {X86::VCVTTSS2SIrm_Int, {0, Unknown}}, + {X86::VCVTTSS2SIrr, {0, Unknown}}, + {X86::VCVTTSS2SIrr_Int, {0, Unknown}}, + {X86::VCVTTSS2USI64Zrm, {0, Unknown}}, + {X86::VCVTTSS2USI64Zrm_Int, {0, Unknown}}, + {X86::VCVTTSS2USI64Zrr, {0, Unknown}}, + {X86::VCVTTSS2USI64Zrr_Int, {0, Unknown}}, + {X86::VCVTTSS2USI64Zrrb_Int, {0, Unknown}}, + {X86::VCVTTSS2USIZrm, {0, Unknown}}, + {X86::VCVTTSS2USIZrm_Int, {0, Unknown}}, + {X86::VCVTTSS2USIZrr, {0, Unknown}}, + {X86::VCVTTSS2USIZrr_Int, {0, Unknown}}, + {X86::VCVTTSS2USIZrrb_Int, {0, Unknown}}, + {X86::VCVTUDQ2PDZ128rm, {1, Unknown}}, + {X86::VCVTUDQ2PDZ128rmb, {1, Unknown}}, + {X86::VCVTUDQ2PDZ128rmbk, {1, Unknown}}, + {X86::VCVTUDQ2PDZ128rmbkz, {1, Unknown}}, + {X86::VCVTUDQ2PDZ128rmk, {1, Unknown}}, + {X86::VCVTUDQ2PDZ128rmkz, {1, Unknown}}, + {X86::VCVTUDQ2PDZ128rr, {0, Unknown}}, + {X86::VCVTUDQ2PDZ128rrk, {0, Unknown}}, + {X86::VCVTUDQ2PDZ128rrkz, {0, Unknown}}, + {X86::VCVTUDQ2PDZ256rm, {0, Unknown}}, + {X86::VCVTUDQ2PDZ256rmb, {0, Unknown}}, + {X86::VCVTUDQ2PDZ256rmbk, {0, Unknown}}, + {X86::VCVTUDQ2PDZ256rmbkz, {0, Unknown}}, + {X86::VCVTUDQ2PDZ256rmk, {0, Unknown}}, + {X86::VCVTUDQ2PDZ256rmkz, {0, Unknown}}, + {X86::VCVTUDQ2PDZ256rr, {0, Unknown}}, + {X86::VCVTUDQ2PDZ256rrk, {0, Unknown}}, + {X86::VCVTUDQ2PDZ256rrkz, {0, Unknown}}, + {X86::VCVTUDQ2PDZrm, {0, Unknown}}, + {X86::VCVTUDQ2PDZrmb, {0, Unknown}}, + {X86::VCVTUDQ2PDZrmbk, {0, Unknown}}, + {X86::VCVTUDQ2PDZrmbkz, {0, Unknown}}, + {X86::VCVTUDQ2PDZrmk, {0, Unknown}}, + {X86::VCVTUDQ2PDZrmkz, {0, Unknown}}, + {X86::VCVTUDQ2PDZrr, {0, Unknown}}, + {X86::VCVTUDQ2PDZrrk, {0, Unknown}}, + {X86::VCVTUDQ2PDZrrkz, {0, Unknown}}, + {X86::VCVTUDQ2PSZ128rm, {1, Unknown}}, + {X86::VCVTUDQ2PSZ128rmb, {1, Unknown}}, + {X86::VCVTUDQ2PSZ128rmbk, {1, Unknown}}, + {X86::VCVTUDQ2PSZ128rmbkz, {1, Unknown}}, + {X86::VCVTUDQ2PSZ128rmk, {1, Unknown}}, + {X86::VCVTUDQ2PSZ128rmkz, {1, Unknown}}, + {X86::VCVTUDQ2PSZ128rr, {0, Unknown}}, + {X86::VCVTUDQ2PSZ128rrk, {0, Unknown}}, + {X86::VCVTUDQ2PSZ128rrkz, {0, Unknown}}, + {X86::VCVTUDQ2PSZ256rm, {0, Unknown}}, + {X86::VCVTUDQ2PSZ256rmb, {0, Unknown}}, + {X86::VCVTUDQ2PSZ256rmbk, {0, Unknown}}, + {X86::VCVTUDQ2PSZ256rmbkz, {0, Unknown}}, + {X86::VCVTUDQ2PSZ256rmk, {0, Unknown}}, + {X86::VCVTUDQ2PSZ256rmkz, {0, Unknown}}, + {X86::VCVTUDQ2PSZ256rr, {0, Unknown}}, + {X86::VCVTUDQ2PSZ256rrk, {0, Unknown}}, + {X86::VCVTUDQ2PSZ256rrkz, {0, Unknown}}, + {X86::VCVTUDQ2PSZrm, {0, Unknown}}, + {X86::VCVTUDQ2PSZrmb, {0, Unknown}}, + {X86::VCVTUDQ2PSZrmbk, {0, Unknown}}, + {X86::VCVTUDQ2PSZrmbkz, {0, Unknown}}, + {X86::VCVTUDQ2PSZrmk, {0, Unknown}}, + {X86::VCVTUDQ2PSZrmkz, {0, Unknown}}, + {X86::VCVTUDQ2PSZrr, {0, Unknown}}, + {X86::VCVTUDQ2PSZrrb, {0, Unknown}}, + {X86::VCVTUDQ2PSZrrbk, {0, Unknown}}, + {X86::VCVTUDQ2PSZrrbkz, {0, Unknown}}, + {X86::VCVTUDQ2PSZrrk, {0, Unknown}}, + {X86::VCVTUDQ2PSZrrkz, {0, Unknown}}, + {X86::VCVTUQQ2PDZ128rm, {1, Unknown}}, + {X86::VCVTUQQ2PDZ128rmb, {1, Unknown}}, + {X86::VCVTUQQ2PDZ128rmbk, {1, Unknown}}, + {X86::VCVTUQQ2PDZ128rmbkz, {1, Unknown}}, + {X86::VCVTUQQ2PDZ128rmk, {1, Unknown}}, + {X86::VCVTUQQ2PDZ128rmkz, {1, Unknown}}, + {X86::VCVTUQQ2PDZ128rr, {0, Unknown}}, + {X86::VCVTUQQ2PDZ128rrk, {0, Unknown}}, + {X86::VCVTUQQ2PDZ128rrkz, {0, Unknown}}, + {X86::VCVTUQQ2PDZ256rm, {0, Unknown}}, + {X86::VCVTUQQ2PDZ256rmb, {0, Unknown}}, + {X86::VCVTUQQ2PDZ256rmbk, {0, Unknown}}, + {X86::VCVTUQQ2PDZ256rmbkz, {0, Unknown}}, + {X86::VCVTUQQ2PDZ256rmk, {0, Unknown}}, + {X86::VCVTUQQ2PDZ256rmkz, {0, Unknown}}, + {X86::VCVTUQQ2PDZ256rr, {0, Unknown}}, + {X86::VCVTUQQ2PDZ256rrk, {0, Unknown}}, + {X86::VCVTUQQ2PDZ256rrkz, {0, Unknown}}, + {X86::VCVTUQQ2PDZrm, {0, Unknown}}, + {X86::VCVTUQQ2PDZrmb, {0, Unknown}}, + {X86::VCVTUQQ2PDZrmbk, {0, Unknown}}, + {X86::VCVTUQQ2PDZrmbkz, {0, Unknown}}, + {X86::VCVTUQQ2PDZrmk, {0, Unknown}}, + {X86::VCVTUQQ2PDZrmkz, {0, Unknown}}, + {X86::VCVTUQQ2PDZrr, {0, Unknown}}, + {X86::VCVTUQQ2PDZrrb, {0, Unknown}}, + {X86::VCVTUQQ2PDZrrbk, {0, Unknown}}, + {X86::VCVTUQQ2PDZrrbkz, {0, Unknown}}, + {X86::VCVTUQQ2PDZrrk, {0, Unknown}}, + {X86::VCVTUQQ2PDZrrkz, {0, Unknown}}, + {X86::VCVTUQQ2PSZ128rm, {1, Unknown}}, + {X86::VCVTUQQ2PSZ128rmb, {1, Unknown}}, + {X86::VCVTUQQ2PSZ128rmbk, {1, Unknown}}, + {X86::VCVTUQQ2PSZ128rmbkz, {1, Unknown}}, + {X86::VCVTUQQ2PSZ128rmk, {1, Unknown}}, + {X86::VCVTUQQ2PSZ128rmkz, {1, Unknown}}, + {X86::VCVTUQQ2PSZ128rr, {0, Unknown}}, + {X86::VCVTUQQ2PSZ128rrk, {0, Unknown}}, + {X86::VCVTUQQ2PSZ128rrkz, {0, Unknown}}, + {X86::VCVTUQQ2PSZ256rm, {0, Unknown}}, + {X86::VCVTUQQ2PSZ256rmb, {0, Unknown}}, + {X86::VCVTUQQ2PSZ256rmbk, {0, Unknown}}, + {X86::VCVTUQQ2PSZ256rmbkz, {0, Unknown}}, + {X86::VCVTUQQ2PSZ256rmk, {0, Unknown}}, + {X86::VCVTUQQ2PSZ256rmkz, {0, Unknown}}, + {X86::VCVTUQQ2PSZ256rr, {0, Unknown}}, + {X86::VCVTUQQ2PSZ256rrk, {0, Unknown}}, + {X86::VCVTUQQ2PSZ256rrkz, {0, Unknown}}, + {X86::VCVTUQQ2PSZrm, {0, Unknown}}, + {X86::VCVTUQQ2PSZrmb, {0, Unknown}}, + {X86::VCVTUQQ2PSZrmbk, {0, Unknown}}, + {X86::VCVTUQQ2PSZrmbkz, {0, Unknown}}, + {X86::VCVTUQQ2PSZrmk, {0, Unknown}}, + {X86::VCVTUQQ2PSZrmkz, {0, Unknown}}, + {X86::VCVTUQQ2PSZrr, {0, Unknown}}, + {X86::VCVTUQQ2PSZrrb, {0, Unknown}}, + {X86::VCVTUQQ2PSZrrbk, {0, Unknown}}, + {X86::VCVTUQQ2PSZrrbkz, {0, Unknown}}, + {X86::VCVTUQQ2PSZrrk, {0, Unknown}}, + {X86::VCVTUQQ2PSZrrkz, {0, Unknown}}, + {X86::VCVTUSI2SDZrm, {0, Unknown}}, + {X86::VCVTUSI2SDZrm_Int, {0, Unknown}}, + {X86::VCVTUSI2SDZrr, {0, Unknown}}, + {X86::VCVTUSI2SDZrr_Int, {0, Unknown}}, + {X86::VCVTUSI2SSZrm, {0, Unknown}}, + {X86::VCVTUSI2SSZrm_Int, {0, Unknown}}, + {X86::VCVTUSI2SSZrr, {0, Unknown}}, + {X86::VCVTUSI2SSZrr_Int, {0, Unknown}}, + {X86::VCVTUSI2SSZrrb_Int, {0, Unknown}}, + {X86::VCVTUSI642SDZrm, {0, Unknown}}, + {X86::VCVTUSI642SDZrm_Int, {0, Unknown}}, + {X86::VCVTUSI642SDZrr, {0, Unknown}}, + {X86::VCVTUSI642SDZrr_Int, {0, Unknown}}, + {X86::VCVTUSI642SDZrrb_Int, {0, Unknown}}, + {X86::VCVTUSI642SSZrm, {0, Unknown}}, + {X86::VCVTUSI642SSZrm_Int, {0, Unknown}}, + {X86::VCVTUSI642SSZrr, {0, Unknown}}, + {X86::VCVTUSI642SSZrr_Int, {0, Unknown}}, + {X86::VCVTUSI642SSZrrb_Int, {0, Unknown}}, + {X86::VDBPSADBWZ128rmi, {1, Unknown}}, + {X86::VDBPSADBWZ128rmik, {1, Unknown}}, + {X86::VDBPSADBWZ128rmikz, {1, Unknown}}, + {X86::VDBPSADBWZ128rri, {0, Unknown}}, + {X86::VDBPSADBWZ128rrik, {0, Unknown}}, + {X86::VDBPSADBWZ128rrikz, {0, Unknown}}, + {X86::VDBPSADBWZ256rmi, {0, Unknown}}, + {X86::VDBPSADBWZ256rmik, {0, Unknown}}, + {X86::VDBPSADBWZ256rmikz, {0, Unknown}}, + {X86::VDBPSADBWZ256rri, {0, Unknown}}, + {X86::VDBPSADBWZ256rrik, {0, Unknown}}, + {X86::VDBPSADBWZ256rrikz, {0, Unknown}}, + {X86::VDBPSADBWZrmi, {0, Unknown}}, + {X86::VDBPSADBWZrmik, {0, Unknown}}, + {X86::VDBPSADBWZrmikz, {0, Unknown}}, + {X86::VDBPSADBWZrri, {0, Unknown}}, + {X86::VDBPSADBWZrrik, {0, Unknown}}, + {X86::VDBPSADBWZrrikz, {0, Unknown}}, + {X86::VDIVPDYrm, {0, Unknown}}, + {X86::VDIVPDYrr, {0, Unknown}}, + {X86::VDIVPDZ128rm, {1, Unknown}}, + {X86::VDIVPDZ128rmb, {1, Unknown}}, + {X86::VDIVPDZ128rmbk, {1, Unknown}}, + {X86::VDIVPDZ128rmbkz, {1, Unknown}}, + {X86::VDIVPDZ128rmk, {1, Unknown}}, + {X86::VDIVPDZ128rmkz, {1, Unknown}}, + {X86::VDIVPDZ128rr, {0, Unknown}}, + {X86::VDIVPDZ128rrk, {0, Unknown}}, + {X86::VDIVPDZ128rrkz, {0, Unknown}}, + {X86::VDIVPDZ256rm, {0, Unknown}}, + {X86::VDIVPDZ256rmb, {0, Unknown}}, + {X86::VDIVPDZ256rmbk, {0, Unknown}}, + {X86::VDIVPDZ256rmbkz, {0, Unknown}}, + {X86::VDIVPDZ256rmk, {0, Unknown}}, + {X86::VDIVPDZ256rmkz, {0, Unknown}}, + {X86::VDIVPDZ256rr, {0, Unknown}}, + {X86::VDIVPDZ256rrk, {0, Unknown}}, + {X86::VDIVPDZ256rrkz, {0, Unknown}}, + {X86::VDIVPDZrm, {0, Unknown}}, + {X86::VDIVPDZrmb, {0, Unknown}}, + {X86::VDIVPDZrmbk, {0, Unknown}}, + {X86::VDIVPDZrmbkz, {0, Unknown}}, + {X86::VDIVPDZrmk, {0, Unknown}}, + {X86::VDIVPDZrmkz, {0, Unknown}}, + {X86::VDIVPDZrr, {0, Unknown}}, + {X86::VDIVPDZrrb, {0, Unknown}}, + {X86::VDIVPDZrrbk, {0, Unknown}}, + {X86::VDIVPDZrrbkz, {0, Unknown}}, + {X86::VDIVPDZrrk, {0, Unknown}}, + {X86::VDIVPDZrrkz, {0, Unknown}}, + {X86::VDIVPDrm, {0, Unknown}}, + {X86::VDIVPDrr, {0, Unknown}}, + {X86::VDIVPSYrm, {0, Unknown}}, + {X86::VDIVPSYrr, {0, Unknown}}, + {X86::VDIVPSZ128rm, {1, Unknown}}, + {X86::VDIVPSZ128rmb, {1, Unknown}}, + {X86::VDIVPSZ128rmbk, {1, Unknown}}, + {X86::VDIVPSZ128rmbkz, {1, Unknown}}, + {X86::VDIVPSZ128rmk, {1, Unknown}}, + {X86::VDIVPSZ128rmkz, {1, Unknown}}, + {X86::VDIVPSZ128rr, {0, Unknown}}, + {X86::VDIVPSZ128rrk, {0, Unknown}}, + {X86::VDIVPSZ128rrkz, {0, Unknown}}, + {X86::VDIVPSZ256rm, {0, Unknown}}, + {X86::VDIVPSZ256rmb, {0, Unknown}}, + {X86::VDIVPSZ256rmbk, {0, Unknown}}, + {X86::VDIVPSZ256rmbkz, {0, Unknown}}, + {X86::VDIVPSZ256rmk, {0, Unknown}}, + {X86::VDIVPSZ256rmkz, {0, Unknown}}, + {X86::VDIVPSZ256rr, {0, Unknown}}, + {X86::VDIVPSZ256rrk, {0, Unknown}}, + {X86::VDIVPSZ256rrkz, {0, Unknown}}, + {X86::VDIVPSZrm, {0, Unknown}}, + {X86::VDIVPSZrmb, {0, Unknown}}, + {X86::VDIVPSZrmbk, {0, Unknown}}, + {X86::VDIVPSZrmbkz, {0, Unknown}}, + {X86::VDIVPSZrmk, {0, Unknown}}, + {X86::VDIVPSZrmkz, {0, Unknown}}, + {X86::VDIVPSZrr, {0, Unknown}}, + {X86::VDIVPSZrrb, {0, Unknown}}, + {X86::VDIVPSZrrbk, {0, Unknown}}, + {X86::VDIVPSZrrbkz, {0, Unknown}}, + {X86::VDIVPSZrrk, {0, Unknown}}, + {X86::VDIVPSZrrkz, {0, Unknown}}, + {X86::VDIVPSrm, {0, Unknown}}, + {X86::VDIVPSrr, {0, Unknown}}, + {X86::VDIVSDZrm, {0, Unknown}}, + {X86::VDIVSDZrm_Int, {0, Unknown}}, + {X86::VDIVSDZrm_Intk, {0, Unknown}}, + {X86::VDIVSDZrm_Intkz, {0, Unknown}}, + {X86::VDIVSDZrr, {0, Unknown}}, + {X86::VDIVSDZrr_Int, {0, Unknown}}, + {X86::VDIVSDZrr_Intk, {0, Unknown}}, + {X86::VDIVSDZrr_Intkz, {0, Unknown}}, + {X86::VDIVSDZrrb_Int, {0, Unknown}}, + {X86::VDIVSDZrrb_Intk, {0, Unknown}}, + {X86::VDIVSDZrrb_Intkz, {0, Unknown}}, + {X86::VDIVSDrm, {0, Unknown}}, + {X86::VDIVSDrm_Int, {0, Unknown}}, + {X86::VDIVSDrr, {0, Unknown}}, + {X86::VDIVSDrr_Int, {0, Unknown}}, + {X86::VDIVSSZrm, {0, Unknown}}, + {X86::VDIVSSZrm_Int, {0, Unknown}}, + {X86::VDIVSSZrm_Intk, {0, Unknown}}, + {X86::VDIVSSZrm_Intkz, {0, Unknown}}, + {X86::VDIVSSZrr, {0, Unknown}}, + {X86::VDIVSSZrr_Int, {0, Unknown}}, + {X86::VDIVSSZrr_Intk, {0, Unknown}}, + {X86::VDIVSSZrr_Intkz, {0, Unknown}}, + {X86::VDIVSSZrrb_Int, {0, Unknown}}, + {X86::VDIVSSZrrb_Intk, {0, Unknown}}, + {X86::VDIVSSZrrb_Intkz, {0, Unknown}}, + {X86::VDIVSSrm, {0, Unknown}}, + {X86::VDIVSSrm_Int, {0, Unknown}}, + {X86::VDIVSSrr, {0, Unknown}}, + {X86::VDIVSSrr_Int, {0, Unknown}}, + {X86::VDPPDrmi, {0, Unknown}}, + {X86::VDPPDrri, {0, Unknown}}, + {X86::VDPPSYrmi, {0, Unknown}}, + {X86::VDPPSYrri, {0, Unknown}}, + {X86::VDPPSrmi, {0, Unknown}}, + {X86::VDPPSrri, {0, Unknown}}, + {X86::VERRm, {0, Unknown}}, + {X86::VERRr, {0, Unknown}}, + {X86::VERWm, {0, Unknown}}, + {X86::VERWr, {0, Unknown}}, + {X86::VEXPANDPDZ128rm, {1, Unknown}}, + {X86::VEXPANDPDZ128rmk, {1, Unknown}}, + {X86::VEXPANDPDZ128rmkz, {1, Unknown}}, + {X86::VEXPANDPDZ128rr, {0, Unknown}}, + {X86::VEXPANDPDZ128rrk, {0, Unknown}}, + {X86::VEXPANDPDZ128rrkz, {0, Unknown}}, + {X86::VEXPANDPDZ256rm, {0, Unknown}}, + {X86::VEXPANDPDZ256rmk, {0, Unknown}}, + {X86::VEXPANDPDZ256rmkz, {0, Unknown}}, + {X86::VEXPANDPDZ256rr, {0, Unknown}}, + {X86::VEXPANDPDZ256rrk, {0, Unknown}}, + {X86::VEXPANDPDZ256rrkz, {0, Unknown}}, + {X86::VEXPANDPDZrm, {0, Unknown}}, + {X86::VEXPANDPDZrmk, {0, Unknown}}, + {X86::VEXPANDPDZrmkz, {0, Unknown}}, + {X86::VEXPANDPDZrr, {0, Unknown}}, + {X86::VEXPANDPDZrrk, {0, Unknown}}, + {X86::VEXPANDPDZrrkz, {0, Unknown}}, + {X86::VEXPANDPSZ128rm, {1, Unknown}}, + {X86::VEXPANDPSZ128rmk, {1, Unknown}}, + {X86::VEXPANDPSZ128rmkz, {1, Unknown}}, + {X86::VEXPANDPSZ128rr, {0, Unknown}}, + {X86::VEXPANDPSZ128rrk, {0, Unknown}}, + {X86::VEXPANDPSZ128rrkz, {0, Unknown}}, + {X86::VEXPANDPSZ256rm, {0, Unknown}}, + {X86::VEXPANDPSZ256rmk, {0, Unknown}}, + {X86::VEXPANDPSZ256rmkz, {0, Unknown}}, + {X86::VEXPANDPSZ256rr, {0, Unknown}}, + {X86::VEXPANDPSZ256rrk, {0, Unknown}}, + {X86::VEXPANDPSZ256rrkz, {0, Unknown}}, + {X86::VEXPANDPSZrm, {0, Unknown}}, + {X86::VEXPANDPSZrmk, {0, Unknown}}, + {X86::VEXPANDPSZrmkz, {0, Unknown}}, + {X86::VEXPANDPSZrr, {0, Unknown}}, + {X86::VEXPANDPSZrrk, {0, Unknown}}, + {X86::VEXPANDPSZrrkz, {0, Unknown}}, + {X86::VEXTRACTF128mr, {1, Unknown}}, + {X86::VEXTRACTF128rr, {0, Unknown}}, + {X86::VEXTRACTF32x4Z256mr, {0, Unknown}}, + {X86::VEXTRACTF32x4Z256mrk, {0, Unknown}}, + {X86::VEXTRACTF32x4Z256rr, {0, Unknown}}, + {X86::VEXTRACTF32x4Z256rrk, {0, Unknown}}, + {X86::VEXTRACTF32x4Z256rrkz, {0, Unknown}}, + {X86::VEXTRACTF32x4Zmr, {0, Unknown}}, + {X86::VEXTRACTF32x4Zmrk, {0, Unknown}}, + {X86::VEXTRACTF32x4Zrr, {0, Unknown}}, + {X86::VEXTRACTF32x4Zrrk, {0, Unknown}}, + {X86::VEXTRACTF32x4Zrrkz, {0, Unknown}}, + {X86::VEXTRACTF32x8Zmr, {0, Unknown}}, + {X86::VEXTRACTF32x8Zmrk, {0, Unknown}}, + {X86::VEXTRACTF32x8Zrr, {0, Unknown}}, + {X86::VEXTRACTF32x8Zrrk, {0, Unknown}}, + {X86::VEXTRACTF32x8Zrrkz, {0, Unknown}}, + {X86::VEXTRACTF64x2Z256mr, {0, Unknown}}, + {X86::VEXTRACTF64x2Z256mrk, {0, Unknown}}, + {X86::VEXTRACTF64x2Z256rr, {0, Unknown}}, + {X86::VEXTRACTF64x2Z256rrk, {0, Unknown}}, + {X86::VEXTRACTF64x2Z256rrkz, {0, Unknown}}, + {X86::VEXTRACTF64x2Zmr, {0, Unknown}}, + {X86::VEXTRACTF64x2Zmrk, {0, Unknown}}, + {X86::VEXTRACTF64x2Zrr, {0, Unknown}}, + {X86::VEXTRACTF64x2Zrrk, {0, Unknown}}, + {X86::VEXTRACTF64x2Zrrkz, {0, Unknown}}, + {X86::VEXTRACTF64x4Zmr, {0, Unknown}}, + {X86::VEXTRACTF64x4Zmrk, {0, Unknown}}, + {X86::VEXTRACTF64x4Zrr, {0, Unknown}}, + {X86::VEXTRACTF64x4Zrrk, {0, Unknown}}, + {X86::VEXTRACTF64x4Zrrkz, {0, Unknown}}, + {X86::VEXTRACTI128mr, {1, Unknown}}, + {X86::VEXTRACTI128rr, {0, Unknown}}, + {X86::VEXTRACTI32x4Z256mr, {0, Unknown}}, + {X86::VEXTRACTI32x4Z256mrk, {0, Unknown}}, + {X86::VEXTRACTI32x4Z256rr, {0, Unknown}}, + {X86::VEXTRACTI32x4Z256rrk, {0, Unknown}}, + {X86::VEXTRACTI32x4Z256rrkz, {0, Unknown}}, + {X86::VEXTRACTI32x4Zmr, {0, Unknown}}, + {X86::VEXTRACTI32x4Zmrk, {0, Unknown}}, + {X86::VEXTRACTI32x4Zrr, {0, Unknown}}, + {X86::VEXTRACTI32x4Zrrk, {0, Unknown}}, + {X86::VEXTRACTI32x4Zrrkz, {0, Unknown}}, + {X86::VEXTRACTI32x8Zmr, {0, Unknown}}, + {X86::VEXTRACTI32x8Zmrk, {0, Unknown}}, + {X86::VEXTRACTI32x8Zrr, {0, Unknown}}, + {X86::VEXTRACTI32x8Zrrk, {0, Unknown}}, + {X86::VEXTRACTI32x8Zrrkz, {0, Unknown}}, + {X86::VEXTRACTI64x2Z256mr, {0, Unknown}}, + {X86::VEXTRACTI64x2Z256mrk, {0, Unknown}}, + {X86::VEXTRACTI64x2Z256rr, {0, Unknown}}, + {X86::VEXTRACTI64x2Z256rrk, {0, Unknown}}, + {X86::VEXTRACTI64x2Z256rrkz, {0, Unknown}}, + {X86::VEXTRACTI64x2Zmr, {0, Unknown}}, + {X86::VEXTRACTI64x2Zmrk, {0, Unknown}}, + {X86::VEXTRACTI64x2Zrr, {0, Unknown}}, + {X86::VEXTRACTI64x2Zrrk, {0, Unknown}}, + {X86::VEXTRACTI64x2Zrrkz, {0, Unknown}}, + {X86::VEXTRACTI64x4Zmr, {0, Unknown}}, + {X86::VEXTRACTI64x4Zmrk, {0, Unknown}}, + {X86::VEXTRACTI64x4Zrr, {0, Unknown}}, + {X86::VEXTRACTI64x4Zrrk, {0, Unknown}}, + {X86::VEXTRACTI64x4Zrrkz, {0, Unknown}}, + {X86::VEXTRACTPSZmr, {0, Unknown}}, + {X86::VEXTRACTPSZrr, {0, Unknown}}, + {X86::VEXTRACTPSmr, {0, Unknown}}, + {X86::VEXTRACTPSrr, {0, Unknown}}, + {X86::VFMADD132PDYm, {0, Unknown}}, + {X86::VFMADD132PDYr, {0, Unknown}}, + {X86::VFMADD132PDZ128m, {0, Unknown}}, + {X86::VFMADD132PDZ128mb, {0, Unknown}}, + {X86::VFMADD132PDZ128mbk, {0, Unknown}}, + {X86::VFMADD132PDZ128mbkz, {0, Unknown}}, + {X86::VFMADD132PDZ128mk, {0, Unknown}}, + {X86::VFMADD132PDZ128mkz, {0, Unknown}}, + {X86::VFMADD132PDZ128r, {0, Unknown}}, + {X86::VFMADD132PDZ128rk, {0, Unknown}}, + {X86::VFMADD132PDZ128rkz, {0, Unknown}}, + {X86::VFMADD132PDZ256m, {0, Unknown}}, + {X86::VFMADD132PDZ256mb, {0, Unknown}}, + {X86::VFMADD132PDZ256mbk, {0, Unknown}}, + {X86::VFMADD132PDZ256mbkz, {0, Unknown}}, + {X86::VFMADD132PDZ256mk, {0, Unknown}}, + {X86::VFMADD132PDZ256mkz, {0, Unknown}}, + {X86::VFMADD132PDZ256r, {0, Unknown}}, + {X86::VFMADD132PDZ256rk, {0, Unknown}}, + {X86::VFMADD132PDZ256rkz, {0, Unknown}}, + {X86::VFMADD132PDZm, {0, Unknown}}, + {X86::VFMADD132PDZmb, {0, Unknown}}, + {X86::VFMADD132PDZmbk, {0, Unknown}}, + {X86::VFMADD132PDZmbkz, {0, Unknown}}, + {X86::VFMADD132PDZmk, {0, Unknown}}, + {X86::VFMADD132PDZmkz, {0, Unknown}}, + {X86::VFMADD132PDZr, {0, Unknown}}, + {X86::VFMADD132PDZrb, {0, Unknown}}, + {X86::VFMADD132PDZrbk, {0, Unknown}}, + {X86::VFMADD132PDZrbkz, {0, Unknown}}, + {X86::VFMADD132PDZrk, {0, Unknown}}, + {X86::VFMADD132PDZrkz, {0, Unknown}}, + {X86::VFMADD132PDm, {0, Unknown}}, + {X86::VFMADD132PDr, {0, Unknown}}, + {X86::VFMADD132PSYm, {0, Unknown}}, + {X86::VFMADD132PSYr, {0, Unknown}}, + {X86::VFMADD132PSZ128m, {0, Unknown}}, + {X86::VFMADD132PSZ128mb, {0, Unknown}}, + {X86::VFMADD132PSZ128mbk, {0, Unknown}}, + {X86::VFMADD132PSZ128mbkz, {0, Unknown}}, + {X86::VFMADD132PSZ128mk, {0, Unknown}}, + {X86::VFMADD132PSZ128mkz, {0, Unknown}}, + {X86::VFMADD132PSZ128r, {0, Unknown}}, + {X86::VFMADD132PSZ128rk, {0, Unknown}}, + {X86::VFMADD132PSZ128rkz, {0, Unknown}}, + {X86::VFMADD132PSZ256m, {0, Unknown}}, + {X86::VFMADD132PSZ256mb, {0, Unknown}}, + {X86::VFMADD132PSZ256mbk, {0, Unknown}}, + {X86::VFMADD132PSZ256mbkz, {0, Unknown}}, + {X86::VFMADD132PSZ256mk, {0, Unknown}}, + {X86::VFMADD132PSZ256mkz, {0, Unknown}}, + {X86::VFMADD132PSZ256r, {0, Unknown}}, + {X86::VFMADD132PSZ256rk, {0, Unknown}}, + {X86::VFMADD132PSZ256rkz, {0, Unknown}}, + {X86::VFMADD132PSZm, {0, Unknown}}, + {X86::VFMADD132PSZmb, {0, Unknown}}, + {X86::VFMADD132PSZmbk, {0, Unknown}}, + {X86::VFMADD132PSZmbkz, {0, Unknown}}, + {X86::VFMADD132PSZmk, {0, Unknown}}, + {X86::VFMADD132PSZmkz, {0, Unknown}}, + {X86::VFMADD132PSZr, {0, Unknown}}, + {X86::VFMADD132PSZrb, {0, Unknown}}, + {X86::VFMADD132PSZrbk, {0, Unknown}}, + {X86::VFMADD132PSZrbkz, {0, Unknown}}, + {X86::VFMADD132PSZrk, {0, Unknown}}, + {X86::VFMADD132PSZrkz, {0, Unknown}}, + {X86::VFMADD132PSm, {0, Unknown}}, + {X86::VFMADD132PSr, {0, Unknown}}, + {X86::VFMADD132SDZm, {0, Unknown}}, + {X86::VFMADD132SDZm_Int, {0, Unknown}}, + {X86::VFMADD132SDZm_Intk, {0, Unknown}}, + {X86::VFMADD132SDZm_Intkz, {0, Unknown}}, + {X86::VFMADD132SDZr, {0, Unknown}}, + {X86::VFMADD132SDZr_Int, {0, Unknown}}, + {X86::VFMADD132SDZr_Intk, {0, Unknown}}, + {X86::VFMADD132SDZr_Intkz, {0, Unknown}}, + {X86::VFMADD132SDZrb_Int, {0, Unknown}}, + {X86::VFMADD132SDZrb_Intk, {0, Unknown}}, + {X86::VFMADD132SDZrb_Intkz, {0, Unknown}}, + {X86::VFMADD132SDm, {0, Unknown}}, + {X86::VFMADD132SDm_Int, {0, Unknown}}, + {X86::VFMADD132SDr, {0, Unknown}}, + {X86::VFMADD132SDr_Int, {0, Unknown}}, + {X86::VFMADD132SSZm, {0, Unknown}}, + {X86::VFMADD132SSZm_Int, {0, Unknown}}, + {X86::VFMADD132SSZm_Intk, {0, Unknown}}, + {X86::VFMADD132SSZm_Intkz, {0, Unknown}}, + {X86::VFMADD132SSZr, {0, Unknown}}, + {X86::VFMADD132SSZr_Int, {0, Unknown}}, + {X86::VFMADD132SSZr_Intk, {0, Unknown}}, + {X86::VFMADD132SSZr_Intkz, {0, Unknown}}, + {X86::VFMADD132SSZrb_Int, {0, Unknown}}, + {X86::VFMADD132SSZrb_Intk, {0, Unknown}}, + {X86::VFMADD132SSZrb_Intkz, {0, Unknown}}, + {X86::VFMADD132SSm, {0, Unknown}}, + {X86::VFMADD132SSm_Int, {0, Unknown}}, + {X86::VFMADD132SSr, {0, Unknown}}, + {X86::VFMADD132SSr_Int, {0, Unknown}}, + {X86::VFMADD213PDYm, {0, Unknown}}, + {X86::VFMADD213PDYr, {0, Unknown}}, + {X86::VFMADD213PDZ128m, {0, Unknown}}, + {X86::VFMADD213PDZ128mb, {0, Unknown}}, + {X86::VFMADD213PDZ128mbk, {0, Unknown}}, + {X86::VFMADD213PDZ128mbkz, {0, Unknown}}, + {X86::VFMADD213PDZ128mk, {0, Unknown}}, + {X86::VFMADD213PDZ128mkz, {0, Unknown}}, + {X86::VFMADD213PDZ128r, {0, Unknown}}, + {X86::VFMADD213PDZ128rk, {0, Unknown}}, + {X86::VFMADD213PDZ128rkz, {0, Unknown}}, + {X86::VFMADD213PDZ256m, {0, Unknown}}, + {X86::VFMADD213PDZ256mb, {0, Unknown}}, + {X86::VFMADD213PDZ256mbk, {0, Unknown}}, + {X86::VFMADD213PDZ256mbkz, {0, Unknown}}, + {X86::VFMADD213PDZ256mk, {0, Unknown}}, + {X86::VFMADD213PDZ256mkz, {0, Unknown}}, + {X86::VFMADD213PDZ256r, {0, Unknown}}, + {X86::VFMADD213PDZ256rk, {0, Unknown}}, + {X86::VFMADD213PDZ256rkz, {0, Unknown}}, + {X86::VFMADD213PDZm, {0, Unknown}}, + {X86::VFMADD213PDZmb, {0, Unknown}}, + {X86::VFMADD213PDZmbk, {0, Unknown}}, + {X86::VFMADD213PDZmbkz, {0, Unknown}}, + {X86::VFMADD213PDZmk, {0, Unknown}}, + {X86::VFMADD213PDZmkz, {0, Unknown}}, + {X86::VFMADD213PDZr, {0, Unknown}}, + {X86::VFMADD213PDZrb, {0, Unknown}}, + {X86::VFMADD213PDZrbk, {0, Unknown}}, + {X86::VFMADD213PDZrbkz, {0, Unknown}}, + {X86::VFMADD213PDZrk, {0, Unknown}}, + {X86::VFMADD213PDZrkz, {0, Unknown}}, + {X86::VFMADD213PDm, {0, Unknown}}, + {X86::VFMADD213PDr, {0, Unknown}}, + {X86::VFMADD213PSYm, {0, Unknown}}, + {X86::VFMADD213PSYr, {0, Unknown}}, + {X86::VFMADD213PSZ128m, {0, Unknown}}, + {X86::VFMADD213PSZ128mb, {0, Unknown}}, + {X86::VFMADD213PSZ128mbk, {0, Unknown}}, + {X86::VFMADD213PSZ128mbkz, {0, Unknown}}, + {X86::VFMADD213PSZ128mk, {0, Unknown}}, + {X86::VFMADD213PSZ128mkz, {0, Unknown}}, + {X86::VFMADD213PSZ128r, {0, Unknown}}, + {X86::VFMADD213PSZ128rk, {0, Unknown}}, + {X86::VFMADD213PSZ128rkz, {0, Unknown}}, + {X86::VFMADD213PSZ256m, {0, Unknown}}, + {X86::VFMADD213PSZ256mb, {0, Unknown}}, + {X86::VFMADD213PSZ256mbk, {0, Unknown}}, + {X86::VFMADD213PSZ256mbkz, {0, Unknown}}, + {X86::VFMADD213PSZ256mk, {0, Unknown}}, + {X86::VFMADD213PSZ256mkz, {0, Unknown}}, + {X86::VFMADD213PSZ256r, {0, Unknown}}, + {X86::VFMADD213PSZ256rk, {0, Unknown}}, + {X86::VFMADD213PSZ256rkz, {0, Unknown}}, + {X86::VFMADD213PSZm, {0, Unknown}}, + {X86::VFMADD213PSZmb, {0, Unknown}}, + {X86::VFMADD213PSZmbk, {0, Unknown}}, + {X86::VFMADD213PSZmbkz, {0, Unknown}}, + {X86::VFMADD213PSZmk, {0, Unknown}}, + {X86::VFMADD213PSZmkz, {0, Unknown}}, + {X86::VFMADD213PSZr, {0, Unknown}}, + {X86::VFMADD213PSZrb, {0, Unknown}}, + {X86::VFMADD213PSZrbk, {0, Unknown}}, + {X86::VFMADD213PSZrbkz, {0, Unknown}}, + {X86::VFMADD213PSZrk, {0, Unknown}}, + {X86::VFMADD213PSZrkz, {0, Unknown}}, + {X86::VFMADD213PSm, {0, Unknown}}, + {X86::VFMADD213PSr, {0, Unknown}}, + {X86::VFMADD213SDZm, {0, Unknown}}, + {X86::VFMADD213SDZm_Int, {0, Unknown}}, + {X86::VFMADD213SDZm_Intk, {0, Unknown}}, + {X86::VFMADD213SDZm_Intkz, {0, Unknown}}, + {X86::VFMADD213SDZr, {0, Unknown}}, + {X86::VFMADD213SDZr_Int, {0, Unknown}}, + {X86::VFMADD213SDZr_Intk, {0, Unknown}}, + {X86::VFMADD213SDZr_Intkz, {0, Unknown}}, + {X86::VFMADD213SDZrb_Int, {0, Unknown}}, + {X86::VFMADD213SDZrb_Intk, {0, Unknown}}, + {X86::VFMADD213SDZrb_Intkz, {0, Unknown}}, + {X86::VFMADD213SDm, {0, Unknown}}, + {X86::VFMADD213SDm_Int, {0, Unknown}}, + {X86::VFMADD213SDr, {0, Unknown}}, + {X86::VFMADD213SDr_Int, {0, Unknown}}, + {X86::VFMADD213SSZm, {0, Unknown}}, + {X86::VFMADD213SSZm_Int, {0, Unknown}}, + {X86::VFMADD213SSZm_Intk, {0, Unknown}}, + {X86::VFMADD213SSZm_Intkz, {0, Unknown}}, + {X86::VFMADD213SSZr, {0, Unknown}}, + {X86::VFMADD213SSZr_Int, {0, Unknown}}, + {X86::VFMADD213SSZr_Intk, {0, Unknown}}, + {X86::VFMADD213SSZr_Intkz, {0, Unknown}}, + {X86::VFMADD213SSZrb_Int, {0, Unknown}}, + {X86::VFMADD213SSZrb_Intk, {0, Unknown}}, + {X86::VFMADD213SSZrb_Intkz, {0, Unknown}}, + {X86::VFMADD213SSm, {0, Unknown}}, + {X86::VFMADD213SSm_Int, {0, Unknown}}, + {X86::VFMADD213SSr, {0, Unknown}}, + {X86::VFMADD213SSr_Int, {0, Unknown}}, + {X86::VFMADD231PDYm, {0, Unknown}}, + {X86::VFMADD231PDYr, {0, Unknown}}, + {X86::VFMADD231PDZ128m, {0, Unknown}}, + {X86::VFMADD231PDZ128mb, {0, Unknown}}, + {X86::VFMADD231PDZ128mbk, {0, Unknown}}, + {X86::VFMADD231PDZ128mbkz, {0, Unknown}}, + {X86::VFMADD231PDZ128mk, {0, Unknown}}, + {X86::VFMADD231PDZ128mkz, {0, Unknown}}, + {X86::VFMADD231PDZ128r, {0, Unknown}}, + {X86::VFMADD231PDZ128rk, {0, Unknown}}, + {X86::VFMADD231PDZ128rkz, {0, Unknown}}, + {X86::VFMADD231PDZ256m, {0, Unknown}}, + {X86::VFMADD231PDZ256mb, {0, Unknown}}, + {X86::VFMADD231PDZ256mbk, {0, Unknown}}, + {X86::VFMADD231PDZ256mbkz, {0, Unknown}}, + {X86::VFMADD231PDZ256mk, {0, Unknown}}, + {X86::VFMADD231PDZ256mkz, {0, Unknown}}, + {X86::VFMADD231PDZ256r, {0, Unknown}}, + {X86::VFMADD231PDZ256rk, {0, Unknown}}, + {X86::VFMADD231PDZ256rkz, {0, Unknown}}, + {X86::VFMADD231PDZm, {0, Unknown}}, + {X86::VFMADD231PDZmb, {0, Unknown}}, + {X86::VFMADD231PDZmbk, {0, Unknown}}, + {X86::VFMADD231PDZmbkz, {0, Unknown}}, + {X86::VFMADD231PDZmk, {0, Unknown}}, + {X86::VFMADD231PDZmkz, {0, Unknown}}, + {X86::VFMADD231PDZr, {0, Unknown}}, + {X86::VFMADD231PDZrb, {0, Unknown}}, + {X86::VFMADD231PDZrbk, {0, Unknown}}, + {X86::VFMADD231PDZrbkz, {0, Unknown}}, + {X86::VFMADD231PDZrk, {0, Unknown}}, + {X86::VFMADD231PDZrkz, {0, Unknown}}, + {X86::VFMADD231PDm, {0, Unknown}}, + {X86::VFMADD231PDr, {0, Unknown}}, + {X86::VFMADD231PSYm, {0, Unknown}}, + {X86::VFMADD231PSYr, {0, Unknown}}, + {X86::VFMADD231PSZ128m, {0, Unknown}}, + {X86::VFMADD231PSZ128mb, {0, Unknown}}, + {X86::VFMADD231PSZ128mbk, {0, Unknown}}, + {X86::VFMADD231PSZ128mbkz, {0, Unknown}}, + {X86::VFMADD231PSZ128mk, {0, Unknown}}, + {X86::VFMADD231PSZ128mkz, {0, Unknown}}, + {X86::VFMADD231PSZ128r, {0, Unknown}}, + {X86::VFMADD231PSZ128rk, {0, Unknown}}, + {X86::VFMADD231PSZ128rkz, {0, Unknown}}, + {X86::VFMADD231PSZ256m, {0, Unknown}}, + {X86::VFMADD231PSZ256mb, {0, Unknown}}, + {X86::VFMADD231PSZ256mbk, {0, Unknown}}, + {X86::VFMADD231PSZ256mbkz, {0, Unknown}}, + {X86::VFMADD231PSZ256mk, {0, Unknown}}, + {X86::VFMADD231PSZ256mkz, {0, Unknown}}, + {X86::VFMADD231PSZ256r, {0, Unknown}}, + {X86::VFMADD231PSZ256rk, {0, Unknown}}, + {X86::VFMADD231PSZ256rkz, {0, Unknown}}, + {X86::VFMADD231PSZm, {0, Unknown}}, + {X86::VFMADD231PSZmb, {0, Unknown}}, + {X86::VFMADD231PSZmbk, {0, Unknown}}, + {X86::VFMADD231PSZmbkz, {0, Unknown}}, + {X86::VFMADD231PSZmk, {0, Unknown}}, + {X86::VFMADD231PSZmkz, {0, Unknown}}, + {X86::VFMADD231PSZr, {0, Unknown}}, + {X86::VFMADD231PSZrb, {0, Unknown}}, + {X86::VFMADD231PSZrbk, {0, Unknown}}, + {X86::VFMADD231PSZrbkz, {0, Unknown}}, + {X86::VFMADD231PSZrk, {0, Unknown}}, + {X86::VFMADD231PSZrkz, {0, Unknown}}, + {X86::VFMADD231PSm, {0, Unknown}}, + {X86::VFMADD231PSr, {0, Unknown}}, + {X86::VFMADD231SDZm, {0, Unknown}}, + {X86::VFMADD231SDZm_Int, {0, Unknown}}, + {X86::VFMADD231SDZm_Intk, {0, Unknown}}, + {X86::VFMADD231SDZm_Intkz, {0, Unknown}}, + {X86::VFMADD231SDZr, {0, Unknown}}, + {X86::VFMADD231SDZr_Int, {0, Unknown}}, + {X86::VFMADD231SDZr_Intk, {0, Unknown}}, + {X86::VFMADD231SDZr_Intkz, {0, Unknown}}, + {X86::VFMADD231SDZrb_Int, {0, Unknown}}, + {X86::VFMADD231SDZrb_Intk, {0, Unknown}}, + {X86::VFMADD231SDZrb_Intkz, {0, Unknown}}, + {X86::VFMADD231SDm, {0, Unknown}}, + {X86::VFMADD231SDm_Int, {0, Unknown}}, + {X86::VFMADD231SDr, {0, Unknown}}, + {X86::VFMADD231SDr_Int, {0, Unknown}}, + {X86::VFMADD231SSZm, {0, Unknown}}, + {X86::VFMADD231SSZm_Int, {0, Unknown}}, + {X86::VFMADD231SSZm_Intk, {0, Unknown}}, + {X86::VFMADD231SSZm_Intkz, {0, Unknown}}, + {X86::VFMADD231SSZr, {0, Unknown}}, + {X86::VFMADD231SSZr_Int, {0, Unknown}}, + {X86::VFMADD231SSZr_Intk, {0, Unknown}}, + {X86::VFMADD231SSZr_Intkz, {0, Unknown}}, + {X86::VFMADD231SSZrb_Int, {0, Unknown}}, + {X86::VFMADD231SSZrb_Intk, {0, Unknown}}, + {X86::VFMADD231SSZrb_Intkz, {0, Unknown}}, + {X86::VFMADD231SSm, {0, Unknown}}, + {X86::VFMADD231SSm_Int, {0, Unknown}}, + {X86::VFMADD231SSr, {0, Unknown}}, + {X86::VFMADD231SSr_Int, {0, Unknown}}, + {X86::VFMADDPD4Ymr, {0, Unknown}}, + {X86::VFMADDPD4Yrm, {0, Unknown}}, + {X86::VFMADDPD4Yrr, {0, Unknown}}, + {X86::VFMADDPD4Yrr_REV, {0, Unknown}}, + {X86::VFMADDPD4mr, {0, Unknown}}, + {X86::VFMADDPD4rm, {0, Unknown}}, + {X86::VFMADDPD4rr, {0, Unknown}}, + {X86::VFMADDPD4rr_REV, {0, Unknown}}, + {X86::VFMADDPS4Ymr, {0, Unknown}}, + {X86::VFMADDPS4Yrm, {0, Unknown}}, + {X86::VFMADDPS4Yrr, {0, Unknown}}, + {X86::VFMADDPS4Yrr_REV, {0, Unknown}}, + {X86::VFMADDPS4mr, {0, Unknown}}, + {X86::VFMADDPS4rm, {0, Unknown}}, + {X86::VFMADDPS4rr, {0, Unknown}}, + {X86::VFMADDPS4rr_REV, {0, Unknown}}, + {X86::VFMADDSD4mr, {0, Unknown}}, + {X86::VFMADDSD4mr_Int, {0, Unknown}}, + {X86::VFMADDSD4rm, {0, Unknown}}, + {X86::VFMADDSD4rm_Int, {0, Unknown}}, + {X86::VFMADDSD4rr, {0, Unknown}}, + {X86::VFMADDSD4rr_Int, {0, Unknown}}, + {X86::VFMADDSD4rr_Int_REV, {0, Unknown}}, + {X86::VFMADDSD4rr_REV, {0, Unknown}}, + {X86::VFMADDSS4mr, {0, Unknown}}, + {X86::VFMADDSS4mr_Int, {0, Unknown}}, + {X86::VFMADDSS4rm, {0, Unknown}}, + {X86::VFMADDSS4rm_Int, {0, Unknown}}, + {X86::VFMADDSS4rr, {0, Unknown}}, + {X86::VFMADDSS4rr_Int, {0, Unknown}}, + {X86::VFMADDSS4rr_Int_REV, {0, Unknown}}, + {X86::VFMADDSS4rr_REV, {0, Unknown}}, + {X86::VFMADDSUB132PDYm, {0, Unknown}}, + {X86::VFMADDSUB132PDYr, {0, Unknown}}, + {X86::VFMADDSUB132PDZ128m, {0, Unknown}}, + {X86::VFMADDSUB132PDZ128mb, {0, Unknown}}, + {X86::VFMADDSUB132PDZ128mbk, {0, Unknown}}, + {X86::VFMADDSUB132PDZ128mbkz, {0, Unknown}}, + {X86::VFMADDSUB132PDZ128mk, {0, Unknown}}, + {X86::VFMADDSUB132PDZ128mkz, {0, Unknown}}, + {X86::VFMADDSUB132PDZ128r, {0, Unknown}}, + {X86::VFMADDSUB132PDZ128rk, {0, Unknown}}, + {X86::VFMADDSUB132PDZ128rkz, {0, Unknown}}, + {X86::VFMADDSUB132PDZ256m, {0, Unknown}}, + {X86::VFMADDSUB132PDZ256mb, {0, Unknown}}, + {X86::VFMADDSUB132PDZ256mbk, {0, Unknown}}, + {X86::VFMADDSUB132PDZ256mbkz, {0, Unknown}}, + {X86::VFMADDSUB132PDZ256mk, {0, Unknown}}, + {X86::VFMADDSUB132PDZ256mkz, {0, Unknown}}, + {X86::VFMADDSUB132PDZ256r, {0, Unknown}}, + {X86::VFMADDSUB132PDZ256rk, {0, Unknown}}, + {X86::VFMADDSUB132PDZ256rkz, {0, Unknown}}, + {X86::VFMADDSUB132PDZm, {0, Unknown}}, + {X86::VFMADDSUB132PDZmb, {0, Unknown}}, + {X86::VFMADDSUB132PDZmbk, {0, Unknown}}, + {X86::VFMADDSUB132PDZmbkz, {0, Unknown}}, + {X86::VFMADDSUB132PDZmk, {0, Unknown}}, + {X86::VFMADDSUB132PDZmkz, {0, Unknown}}, + {X86::VFMADDSUB132PDZr, {0, Unknown}}, + {X86::VFMADDSUB132PDZrb, {0, Unknown}}, + {X86::VFMADDSUB132PDZrbk, {0, Unknown}}, + {X86::VFMADDSUB132PDZrbkz, {0, Unknown}}, + {X86::VFMADDSUB132PDZrk, {0, Unknown}}, + {X86::VFMADDSUB132PDZrkz, {0, Unknown}}, + {X86::VFMADDSUB132PDm, {0, Unknown}}, + {X86::VFMADDSUB132PDr, {0, Unknown}}, + {X86::VFMADDSUB132PSYm, {0, Unknown}}, + {X86::VFMADDSUB132PSYr, {0, Unknown}}, + {X86::VFMADDSUB132PSZ128m, {0, Unknown}}, + {X86::VFMADDSUB132PSZ128mb, {0, Unknown}}, + {X86::VFMADDSUB132PSZ128mbk, {0, Unknown}}, + {X86::VFMADDSUB132PSZ128mbkz, {0, Unknown}}, + {X86::VFMADDSUB132PSZ128mk, {0, Unknown}}, + {X86::VFMADDSUB132PSZ128mkz, {0, Unknown}}, + {X86::VFMADDSUB132PSZ128r, {0, Unknown}}, + {X86::VFMADDSUB132PSZ128rk, {0, Unknown}}, + {X86::VFMADDSUB132PSZ128rkz, {0, Unknown}}, + {X86::VFMADDSUB132PSZ256m, {0, Unknown}}, + {X86::VFMADDSUB132PSZ256mb, {0, Unknown}}, + {X86::VFMADDSUB132PSZ256mbk, {0, Unknown}}, + {X86::VFMADDSUB132PSZ256mbkz, {0, Unknown}}, + {X86::VFMADDSUB132PSZ256mk, {0, Unknown}}, + {X86::VFMADDSUB132PSZ256mkz, {0, Unknown}}, + {X86::VFMADDSUB132PSZ256r, {0, Unknown}}, + {X86::VFMADDSUB132PSZ256rk, {0, Unknown}}, + {X86::VFMADDSUB132PSZ256rkz, {0, Unknown}}, + {X86::VFMADDSUB132PSZm, {0, Unknown}}, + {X86::VFMADDSUB132PSZmb, {0, Unknown}}, + {X86::VFMADDSUB132PSZmbk, {0, Unknown}}, + {X86::VFMADDSUB132PSZmbkz, {0, Unknown}}, + {X86::VFMADDSUB132PSZmk, {0, Unknown}}, + {X86::VFMADDSUB132PSZmkz, {0, Unknown}}, + {X86::VFMADDSUB132PSZr, {0, Unknown}}, + {X86::VFMADDSUB132PSZrb, {0, Unknown}}, + {X86::VFMADDSUB132PSZrbk, {0, Unknown}}, + {X86::VFMADDSUB132PSZrbkz, {0, Unknown}}, + {X86::VFMADDSUB132PSZrk, {0, Unknown}}, + {X86::VFMADDSUB132PSZrkz, {0, Unknown}}, + {X86::VFMADDSUB132PSm, {0, Unknown}}, + {X86::VFMADDSUB132PSr, {0, Unknown}}, + {X86::VFMADDSUB213PDYm, {0, Unknown}}, + {X86::VFMADDSUB213PDYr, {0, Unknown}}, + {X86::VFMADDSUB213PDZ128m, {0, Unknown}}, + {X86::VFMADDSUB213PDZ128mb, {0, Unknown}}, + {X86::VFMADDSUB213PDZ128mbk, {0, Unknown}}, + {X86::VFMADDSUB213PDZ128mbkz, {0, Unknown}}, + {X86::VFMADDSUB213PDZ128mk, {0, Unknown}}, + {X86::VFMADDSUB213PDZ128mkz, {0, Unknown}}, + {X86::VFMADDSUB213PDZ128r, {0, Unknown}}, + {X86::VFMADDSUB213PDZ128rk, {0, Unknown}}, + {X86::VFMADDSUB213PDZ128rkz, {0, Unknown}}, + {X86::VFMADDSUB213PDZ256m, {0, Unknown}}, + {X86::VFMADDSUB213PDZ256mb, {0, Unknown}}, + {X86::VFMADDSUB213PDZ256mbk, {0, Unknown}}, + {X86::VFMADDSUB213PDZ256mbkz, {0, Unknown}}, + {X86::VFMADDSUB213PDZ256mk, {0, Unknown}}, + {X86::VFMADDSUB213PDZ256mkz, {0, Unknown}}, + {X86::VFMADDSUB213PDZ256r, {0, Unknown}}, + {X86::VFMADDSUB213PDZ256rk, {0, Unknown}}, + {X86::VFMADDSUB213PDZ256rkz, {0, Unknown}}, + {X86::VFMADDSUB213PDZm, {0, Unknown}}, + {X86::VFMADDSUB213PDZmb, {0, Unknown}}, + {X86::VFMADDSUB213PDZmbk, {0, Unknown}}, + {X86::VFMADDSUB213PDZmbkz, {0, Unknown}}, + {X86::VFMADDSUB213PDZmk, {0, Unknown}}, + {X86::VFMADDSUB213PDZmkz, {0, Unknown}}, + {X86::VFMADDSUB213PDZr, {0, Unknown}}, + {X86::VFMADDSUB213PDZrb, {0, Unknown}}, + {X86::VFMADDSUB213PDZrbk, {0, Unknown}}, + {X86::VFMADDSUB213PDZrbkz, {0, Unknown}}, + {X86::VFMADDSUB213PDZrk, {0, Unknown}}, + {X86::VFMADDSUB213PDZrkz, {0, Unknown}}, + {X86::VFMADDSUB213PDm, {0, Unknown}}, + {X86::VFMADDSUB213PDr, {0, Unknown}}, + {X86::VFMADDSUB213PSYm, {0, Unknown}}, + {X86::VFMADDSUB213PSYr, {0, Unknown}}, + {X86::VFMADDSUB213PSZ128m, {0, Unknown}}, + {X86::VFMADDSUB213PSZ128mb, {0, Unknown}}, + {X86::VFMADDSUB213PSZ128mbk, {0, Unknown}}, + {X86::VFMADDSUB213PSZ128mbkz, {0, Unknown}}, + {X86::VFMADDSUB213PSZ128mk, {0, Unknown}}, + {X86::VFMADDSUB213PSZ128mkz, {0, Unknown}}, + {X86::VFMADDSUB213PSZ128r, {0, Unknown}}, + {X86::VFMADDSUB213PSZ128rk, {0, Unknown}}, + {X86::VFMADDSUB213PSZ128rkz, {0, Unknown}}, + {X86::VFMADDSUB213PSZ256m, {0, Unknown}}, + {X86::VFMADDSUB213PSZ256mb, {0, Unknown}}, + {X86::VFMADDSUB213PSZ256mbk, {0, Unknown}}, + {X86::VFMADDSUB213PSZ256mbkz, {0, Unknown}}, + {X86::VFMADDSUB213PSZ256mk, {0, Unknown}}, + {X86::VFMADDSUB213PSZ256mkz, {0, Unknown}}, + {X86::VFMADDSUB213PSZ256r, {0, Unknown}}, + {X86::VFMADDSUB213PSZ256rk, {0, Unknown}}, + {X86::VFMADDSUB213PSZ256rkz, {0, Unknown}}, + {X86::VFMADDSUB213PSZm, {0, Unknown}}, + {X86::VFMADDSUB213PSZmb, {0, Unknown}}, + {X86::VFMADDSUB213PSZmbk, {0, Unknown}}, + {X86::VFMADDSUB213PSZmbkz, {0, Unknown}}, + {X86::VFMADDSUB213PSZmk, {0, Unknown}}, + {X86::VFMADDSUB213PSZmkz, {0, Unknown}}, + {X86::VFMADDSUB213PSZr, {0, Unknown}}, + {X86::VFMADDSUB213PSZrb, {0, Unknown}}, + {X86::VFMADDSUB213PSZrbk, {0, Unknown}}, + {X86::VFMADDSUB213PSZrbkz, {0, Unknown}}, + {X86::VFMADDSUB213PSZrk, {0, Unknown}}, + {X86::VFMADDSUB213PSZrkz, {0, Unknown}}, + {X86::VFMADDSUB213PSm, {0, Unknown}}, + {X86::VFMADDSUB213PSr, {0, Unknown}}, + {X86::VFMADDSUB231PDYm, {0, Unknown}}, + {X86::VFMADDSUB231PDYr, {0, Unknown}}, + {X86::VFMADDSUB231PDZ128m, {0, Unknown}}, + {X86::VFMADDSUB231PDZ128mb, {0, Unknown}}, + {X86::VFMADDSUB231PDZ128mbk, {0, Unknown}}, + {X86::VFMADDSUB231PDZ128mbkz, {0, Unknown}}, + {X86::VFMADDSUB231PDZ128mk, {0, Unknown}}, + {X86::VFMADDSUB231PDZ128mkz, {0, Unknown}}, + {X86::VFMADDSUB231PDZ128r, {0, Unknown}}, + {X86::VFMADDSUB231PDZ128rk, {0, Unknown}}, + {X86::VFMADDSUB231PDZ128rkz, {0, Unknown}}, + {X86::VFMADDSUB231PDZ256m, {0, Unknown}}, + {X86::VFMADDSUB231PDZ256mb, {0, Unknown}}, + {X86::VFMADDSUB231PDZ256mbk, {0, Unknown}}, + {X86::VFMADDSUB231PDZ256mbkz, {0, Unknown}}, + {X86::VFMADDSUB231PDZ256mk, {0, Unknown}}, + {X86::VFMADDSUB231PDZ256mkz, {0, Unknown}}, + {X86::VFMADDSUB231PDZ256r, {0, Unknown}}, + {X86::VFMADDSUB231PDZ256rk, {0, Unknown}}, + {X86::VFMADDSUB231PDZ256rkz, {0, Unknown}}, + {X86::VFMADDSUB231PDZm, {0, Unknown}}, + {X86::VFMADDSUB231PDZmb, {0, Unknown}}, + {X86::VFMADDSUB231PDZmbk, {0, Unknown}}, + {X86::VFMADDSUB231PDZmbkz, {0, Unknown}}, + {X86::VFMADDSUB231PDZmk, {0, Unknown}}, + {X86::VFMADDSUB231PDZmkz, {0, Unknown}}, + {X86::VFMADDSUB231PDZr, {0, Unknown}}, + {X86::VFMADDSUB231PDZrb, {0, Unknown}}, + {X86::VFMADDSUB231PDZrbk, {0, Unknown}}, + {X86::VFMADDSUB231PDZrbkz, {0, Unknown}}, + {X86::VFMADDSUB231PDZrk, {0, Unknown}}, + {X86::VFMADDSUB231PDZrkz, {0, Unknown}}, + {X86::VFMADDSUB231PDm, {0, Unknown}}, + {X86::VFMADDSUB231PDr, {0, Unknown}}, + {X86::VFMADDSUB231PSYm, {0, Unknown}}, + {X86::VFMADDSUB231PSYr, {0, Unknown}}, + {X86::VFMADDSUB231PSZ128m, {0, Unknown}}, + {X86::VFMADDSUB231PSZ128mb, {0, Unknown}}, + {X86::VFMADDSUB231PSZ128mbk, {0, Unknown}}, + {X86::VFMADDSUB231PSZ128mbkz, {0, Unknown}}, + {X86::VFMADDSUB231PSZ128mk, {0, Unknown}}, + {X86::VFMADDSUB231PSZ128mkz, {0, Unknown}}, + {X86::VFMADDSUB231PSZ128r, {0, Unknown}}, + {X86::VFMADDSUB231PSZ128rk, {0, Unknown}}, + {X86::VFMADDSUB231PSZ128rkz, {0, Unknown}}, + {X86::VFMADDSUB231PSZ256m, {0, Unknown}}, + {X86::VFMADDSUB231PSZ256mb, {0, Unknown}}, + {X86::VFMADDSUB231PSZ256mbk, {0, Unknown}}, + {X86::VFMADDSUB231PSZ256mbkz, {0, Unknown}}, + {X86::VFMADDSUB231PSZ256mk, {0, Unknown}}, + {X86::VFMADDSUB231PSZ256mkz, {0, Unknown}}, + {X86::VFMADDSUB231PSZ256r, {0, Unknown}}, + {X86::VFMADDSUB231PSZ256rk, {0, Unknown}}, + {X86::VFMADDSUB231PSZ256rkz, {0, Unknown}}, + {X86::VFMADDSUB231PSZm, {0, Unknown}}, + {X86::VFMADDSUB231PSZmb, {0, Unknown}}, + {X86::VFMADDSUB231PSZmbk, {0, Unknown}}, + {X86::VFMADDSUB231PSZmbkz, {0, Unknown}}, + {X86::VFMADDSUB231PSZmk, {0, Unknown}}, + {X86::VFMADDSUB231PSZmkz, {0, Unknown}}, + {X86::VFMADDSUB231PSZr, {0, Unknown}}, + {X86::VFMADDSUB231PSZrb, {0, Unknown}}, + {X86::VFMADDSUB231PSZrbk, {0, Unknown}}, + {X86::VFMADDSUB231PSZrbkz, {0, Unknown}}, + {X86::VFMADDSUB231PSZrk, {0, Unknown}}, + {X86::VFMADDSUB231PSZrkz, {0, Unknown}}, + {X86::VFMADDSUB231PSm, {0, Unknown}}, + {X86::VFMADDSUB231PSr, {0, Unknown}}, + {X86::VFMADDSUBPD4Ymr, {0, Unknown}}, + {X86::VFMADDSUBPD4Yrm, {0, Unknown}}, + {X86::VFMADDSUBPD4Yrr, {0, Unknown}}, + {X86::VFMADDSUBPD4Yrr_REV, {0, Unknown}}, + {X86::VFMADDSUBPD4mr, {0, Unknown}}, + {X86::VFMADDSUBPD4rm, {0, Unknown}}, + {X86::VFMADDSUBPD4rr, {0, Unknown}}, + {X86::VFMADDSUBPD4rr_REV, {0, Unknown}}, + {X86::VFMADDSUBPS4Ymr, {0, Unknown}}, + {X86::VFMADDSUBPS4Yrm, {0, Unknown}}, + {X86::VFMADDSUBPS4Yrr, {0, Unknown}}, + {X86::VFMADDSUBPS4Yrr_REV, {0, Unknown}}, + {X86::VFMADDSUBPS4mr, {0, Unknown}}, + {X86::VFMADDSUBPS4rm, {0, Unknown}}, + {X86::VFMADDSUBPS4rr, {0, Unknown}}, + {X86::VFMADDSUBPS4rr_REV, {0, Unknown}}, + {X86::VFMSUB132PDYm, {0, Unknown}}, + {X86::VFMSUB132PDYr, {0, Unknown}}, + {X86::VFMSUB132PDZ128m, {0, Unknown}}, + {X86::VFMSUB132PDZ128mb, {0, Unknown}}, + {X86::VFMSUB132PDZ128mbk, {0, Unknown}}, + {X86::VFMSUB132PDZ128mbkz, {0, Unknown}}, + {X86::VFMSUB132PDZ128mk, {0, Unknown}}, + {X86::VFMSUB132PDZ128mkz, {0, Unknown}}, + {X86::VFMSUB132PDZ128r, {0, Unknown}}, + {X86::VFMSUB132PDZ128rk, {0, Unknown}}, + {X86::VFMSUB132PDZ128rkz, {0, Unknown}}, + {X86::VFMSUB132PDZ256m, {0, Unknown}}, + {X86::VFMSUB132PDZ256mb, {0, Unknown}}, + {X86::VFMSUB132PDZ256mbk, {0, Unknown}}, + {X86::VFMSUB132PDZ256mbkz, {0, Unknown}}, + {X86::VFMSUB132PDZ256mk, {0, Unknown}}, + {X86::VFMSUB132PDZ256mkz, {0, Unknown}}, + {X86::VFMSUB132PDZ256r, {0, Unknown}}, + {X86::VFMSUB132PDZ256rk, {0, Unknown}}, + {X86::VFMSUB132PDZ256rkz, {0, Unknown}}, + {X86::VFMSUB132PDZm, {0, Unknown}}, + {X86::VFMSUB132PDZmb, {0, Unknown}}, + {X86::VFMSUB132PDZmbk, {0, Unknown}}, + {X86::VFMSUB132PDZmbkz, {0, Unknown}}, + {X86::VFMSUB132PDZmk, {0, Unknown}}, + {X86::VFMSUB132PDZmkz, {0, Unknown}}, + {X86::VFMSUB132PDZr, {0, Unknown}}, + {X86::VFMSUB132PDZrb, {0, Unknown}}, + {X86::VFMSUB132PDZrbk, {0, Unknown}}, + {X86::VFMSUB132PDZrbkz, {0, Unknown}}, + {X86::VFMSUB132PDZrk, {0, Unknown}}, + {X86::VFMSUB132PDZrkz, {0, Unknown}}, + {X86::VFMSUB132PDm, {0, Unknown}}, + {X86::VFMSUB132PDr, {0, Unknown}}, + {X86::VFMSUB132PSYm, {0, Unknown}}, + {X86::VFMSUB132PSYr, {0, Unknown}}, + {X86::VFMSUB132PSZ128m, {0, Unknown}}, + {X86::VFMSUB132PSZ128mb, {0, Unknown}}, + {X86::VFMSUB132PSZ128mbk, {0, Unknown}}, + {X86::VFMSUB132PSZ128mbkz, {0, Unknown}}, + {X86::VFMSUB132PSZ128mk, {0, Unknown}}, + {X86::VFMSUB132PSZ128mkz, {0, Unknown}}, + {X86::VFMSUB132PSZ128r, {0, Unknown}}, + {X86::VFMSUB132PSZ128rk, {0, Unknown}}, + {X86::VFMSUB132PSZ128rkz, {0, Unknown}}, + {X86::VFMSUB132PSZ256m, {0, Unknown}}, + {X86::VFMSUB132PSZ256mb, {0, Unknown}}, + {X86::VFMSUB132PSZ256mbk, {0, Unknown}}, + {X86::VFMSUB132PSZ256mbkz, {0, Unknown}}, + {X86::VFMSUB132PSZ256mk, {0, Unknown}}, + {X86::VFMSUB132PSZ256mkz, {0, Unknown}}, + {X86::VFMSUB132PSZ256r, {0, Unknown}}, + {X86::VFMSUB132PSZ256rk, {0, Unknown}}, + {X86::VFMSUB132PSZ256rkz, {0, Unknown}}, + {X86::VFMSUB132PSZm, {0, Unknown}}, + {X86::VFMSUB132PSZmb, {0, Unknown}}, + {X86::VFMSUB132PSZmbk, {0, Unknown}}, + {X86::VFMSUB132PSZmbkz, {0, Unknown}}, + {X86::VFMSUB132PSZmk, {0, Unknown}}, + {X86::VFMSUB132PSZmkz, {0, Unknown}}, + {X86::VFMSUB132PSZr, {0, Unknown}}, + {X86::VFMSUB132PSZrb, {0, Unknown}}, + {X86::VFMSUB132PSZrbk, {0, Unknown}}, + {X86::VFMSUB132PSZrbkz, {0, Unknown}}, + {X86::VFMSUB132PSZrk, {0, Unknown}}, + {X86::VFMSUB132PSZrkz, {0, Unknown}}, + {X86::VFMSUB132PSm, {0, Unknown}}, + {X86::VFMSUB132PSr, {0, Unknown}}, + {X86::VFMSUB132SDZm, {0, Unknown}}, + {X86::VFMSUB132SDZm_Int, {0, Unknown}}, + {X86::VFMSUB132SDZm_Intk, {0, Unknown}}, + {X86::VFMSUB132SDZm_Intkz, {0, Unknown}}, + {X86::VFMSUB132SDZr, {0, Unknown}}, + {X86::VFMSUB132SDZr_Int, {0, Unknown}}, + {X86::VFMSUB132SDZr_Intk, {0, Unknown}}, + {X86::VFMSUB132SDZr_Intkz, {0, Unknown}}, + {X86::VFMSUB132SDZrb_Int, {0, Unknown}}, + {X86::VFMSUB132SDZrb_Intk, {0, Unknown}}, + {X86::VFMSUB132SDZrb_Intkz, {0, Unknown}}, + {X86::VFMSUB132SDm, {0, Unknown}}, + {X86::VFMSUB132SDm_Int, {0, Unknown}}, + {X86::VFMSUB132SDr, {0, Unknown}}, + {X86::VFMSUB132SDr_Int, {0, Unknown}}, + {X86::VFMSUB132SSZm, {0, Unknown}}, + {X86::VFMSUB132SSZm_Int, {0, Unknown}}, + {X86::VFMSUB132SSZm_Intk, {0, Unknown}}, + {X86::VFMSUB132SSZm_Intkz, {0, Unknown}}, + {X86::VFMSUB132SSZr, {0, Unknown}}, + {X86::VFMSUB132SSZr_Int, {0, Unknown}}, + {X86::VFMSUB132SSZr_Intk, {0, Unknown}}, + {X86::VFMSUB132SSZr_Intkz, {0, Unknown}}, + {X86::VFMSUB132SSZrb_Int, {0, Unknown}}, + {X86::VFMSUB132SSZrb_Intk, {0, Unknown}}, + {X86::VFMSUB132SSZrb_Intkz, {0, Unknown}}, + {X86::VFMSUB132SSm, {0, Unknown}}, + {X86::VFMSUB132SSm_Int, {0, Unknown}}, + {X86::VFMSUB132SSr, {0, Unknown}}, + {X86::VFMSUB132SSr_Int, {0, Unknown}}, + {X86::VFMSUB213PDYm, {0, Unknown}}, + {X86::VFMSUB213PDYr, {0, Unknown}}, + {X86::VFMSUB213PDZ128m, {0, Unknown}}, + {X86::VFMSUB213PDZ128mb, {0, Unknown}}, + {X86::VFMSUB213PDZ128mbk, {0, Unknown}}, + {X86::VFMSUB213PDZ128mbkz, {0, Unknown}}, + {X86::VFMSUB213PDZ128mk, {0, Unknown}}, + {X86::VFMSUB213PDZ128mkz, {0, Unknown}}, + {X86::VFMSUB213PDZ128r, {0, Unknown}}, + {X86::VFMSUB213PDZ128rk, {0, Unknown}}, + {X86::VFMSUB213PDZ128rkz, {0, Unknown}}, + {X86::VFMSUB213PDZ256m, {0, Unknown}}, + {X86::VFMSUB213PDZ256mb, {0, Unknown}}, + {X86::VFMSUB213PDZ256mbk, {0, Unknown}}, + {X86::VFMSUB213PDZ256mbkz, {0, Unknown}}, + {X86::VFMSUB213PDZ256mk, {0, Unknown}}, + {X86::VFMSUB213PDZ256mkz, {0, Unknown}}, + {X86::VFMSUB213PDZ256r, {0, Unknown}}, + {X86::VFMSUB213PDZ256rk, {0, Unknown}}, + {X86::VFMSUB213PDZ256rkz, {0, Unknown}}, + {X86::VFMSUB213PDZm, {0, Unknown}}, + {X86::VFMSUB213PDZmb, {0, Unknown}}, + {X86::VFMSUB213PDZmbk, {0, Unknown}}, + {X86::VFMSUB213PDZmbkz, {0, Unknown}}, + {X86::VFMSUB213PDZmk, {0, Unknown}}, + {X86::VFMSUB213PDZmkz, {0, Unknown}}, + {X86::VFMSUB213PDZr, {0, Unknown}}, + {X86::VFMSUB213PDZrb, {0, Unknown}}, + {X86::VFMSUB213PDZrbk, {0, Unknown}}, + {X86::VFMSUB213PDZrbkz, {0, Unknown}}, + {X86::VFMSUB213PDZrk, {0, Unknown}}, + {X86::VFMSUB213PDZrkz, {0, Unknown}}, + {X86::VFMSUB213PDm, {0, Unknown}}, + {X86::VFMSUB213PDr, {0, Unknown}}, + {X86::VFMSUB213PSYm, {0, Unknown}}, + {X86::VFMSUB213PSYr, {0, Unknown}}, + {X86::VFMSUB213PSZ128m, {0, Unknown}}, + {X86::VFMSUB213PSZ128mb, {0, Unknown}}, + {X86::VFMSUB213PSZ128mbk, {0, Unknown}}, + {X86::VFMSUB213PSZ128mbkz, {0, Unknown}}, + {X86::VFMSUB213PSZ128mk, {0, Unknown}}, + {X86::VFMSUB213PSZ128mkz, {0, Unknown}}, + {X86::VFMSUB213PSZ128r, {0, Unknown}}, + {X86::VFMSUB213PSZ128rk, {0, Unknown}}, + {X86::VFMSUB213PSZ128rkz, {0, Unknown}}, + {X86::VFMSUB213PSZ256m, {0, Unknown}}, + {X86::VFMSUB213PSZ256mb, {0, Unknown}}, + {X86::VFMSUB213PSZ256mbk, {0, Unknown}}, + {X86::VFMSUB213PSZ256mbkz, {0, Unknown}}, + {X86::VFMSUB213PSZ256mk, {0, Unknown}}, + {X86::VFMSUB213PSZ256mkz, {0, Unknown}}, + {X86::VFMSUB213PSZ256r, {0, Unknown}}, + {X86::VFMSUB213PSZ256rk, {0, Unknown}}, + {X86::VFMSUB213PSZ256rkz, {0, Unknown}}, + {X86::VFMSUB213PSZm, {0, Unknown}}, + {X86::VFMSUB213PSZmb, {0, Unknown}}, + {X86::VFMSUB213PSZmbk, {0, Unknown}}, + {X86::VFMSUB213PSZmbkz, {0, Unknown}}, + {X86::VFMSUB213PSZmk, {0, Unknown}}, + {X86::VFMSUB213PSZmkz, {0, Unknown}}, + {X86::VFMSUB213PSZr, {0, Unknown}}, + {X86::VFMSUB213PSZrb, {0, Unknown}}, + {X86::VFMSUB213PSZrbk, {0, Unknown}}, + {X86::VFMSUB213PSZrbkz, {0, Unknown}}, + {X86::VFMSUB213PSZrk, {0, Unknown}}, + {X86::VFMSUB213PSZrkz, {0, Unknown}}, + {X86::VFMSUB213PSm, {0, Unknown}}, + {X86::VFMSUB213PSr, {0, Unknown}}, + {X86::VFMSUB213SDZm, {0, Unknown}}, + {X86::VFMSUB213SDZm_Int, {0, Unknown}}, + {X86::VFMSUB213SDZm_Intk, {0, Unknown}}, + {X86::VFMSUB213SDZm_Intkz, {0, Unknown}}, + {X86::VFMSUB213SDZr, {0, Unknown}}, + {X86::VFMSUB213SDZr_Int, {0, Unknown}}, + {X86::VFMSUB213SDZr_Intk, {0, Unknown}}, + {X86::VFMSUB213SDZr_Intkz, {0, Unknown}}, + {X86::VFMSUB213SDZrb_Int, {0, Unknown}}, + {X86::VFMSUB213SDZrb_Intk, {0, Unknown}}, + {X86::VFMSUB213SDZrb_Intkz, {0, Unknown}}, + {X86::VFMSUB213SDm, {0, Unknown}}, + {X86::VFMSUB213SDm_Int, {0, Unknown}}, + {X86::VFMSUB213SDr, {0, Unknown}}, + {X86::VFMSUB213SDr_Int, {0, Unknown}}, + {X86::VFMSUB213SSZm, {0, Unknown}}, + {X86::VFMSUB213SSZm_Int, {0, Unknown}}, + {X86::VFMSUB213SSZm_Intk, {0, Unknown}}, + {X86::VFMSUB213SSZm_Intkz, {0, Unknown}}, + {X86::VFMSUB213SSZr, {0, Unknown}}, + {X86::VFMSUB213SSZr_Int, {0, Unknown}}, + {X86::VFMSUB213SSZr_Intk, {0, Unknown}}, + {X86::VFMSUB213SSZr_Intkz, {0, Unknown}}, + {X86::VFMSUB213SSZrb_Int, {0, Unknown}}, + {X86::VFMSUB213SSZrb_Intk, {0, Unknown}}, + {X86::VFMSUB213SSZrb_Intkz, {0, Unknown}}, + {X86::VFMSUB213SSm, {0, Unknown}}, + {X86::VFMSUB213SSm_Int, {0, Unknown}}, + {X86::VFMSUB213SSr, {0, Unknown}}, + {X86::VFMSUB213SSr_Int, {0, Unknown}}, + {X86::VFMSUB231PDYm, {0, Unknown}}, + {X86::VFMSUB231PDYr, {0, Unknown}}, + {X86::VFMSUB231PDZ128m, {0, Unknown}}, + {X86::VFMSUB231PDZ128mb, {0, Unknown}}, + {X86::VFMSUB231PDZ128mbk, {0, Unknown}}, + {X86::VFMSUB231PDZ128mbkz, {0, Unknown}}, + {X86::VFMSUB231PDZ128mk, {0, Unknown}}, + {X86::VFMSUB231PDZ128mkz, {0, Unknown}}, + {X86::VFMSUB231PDZ128r, {0, Unknown}}, + {X86::VFMSUB231PDZ128rk, {0, Unknown}}, + {X86::VFMSUB231PDZ128rkz, {0, Unknown}}, + {X86::VFMSUB231PDZ256m, {0, Unknown}}, + {X86::VFMSUB231PDZ256mb, {0, Unknown}}, + {X86::VFMSUB231PDZ256mbk, {0, Unknown}}, + {X86::VFMSUB231PDZ256mbkz, {0, Unknown}}, + {X86::VFMSUB231PDZ256mk, {0, Unknown}}, + {X86::VFMSUB231PDZ256mkz, {0, Unknown}}, + {X86::VFMSUB231PDZ256r, {0, Unknown}}, + {X86::VFMSUB231PDZ256rk, {0, Unknown}}, + {X86::VFMSUB231PDZ256rkz, {0, Unknown}}, + {X86::VFMSUB231PDZm, {0, Unknown}}, + {X86::VFMSUB231PDZmb, {0, Unknown}}, + {X86::VFMSUB231PDZmbk, {0, Unknown}}, + {X86::VFMSUB231PDZmbkz, {0, Unknown}}, + {X86::VFMSUB231PDZmk, {0, Unknown}}, + {X86::VFMSUB231PDZmkz, {0, Unknown}}, + {X86::VFMSUB231PDZr, {0, Unknown}}, + {X86::VFMSUB231PDZrb, {0, Unknown}}, + {X86::VFMSUB231PDZrbk, {0, Unknown}}, + {X86::VFMSUB231PDZrbkz, {0, Unknown}}, + {X86::VFMSUB231PDZrk, {0, Unknown}}, + {X86::VFMSUB231PDZrkz, {0, Unknown}}, + {X86::VFMSUB231PDm, {0, Unknown}}, + {X86::VFMSUB231PDr, {0, Unknown}}, + {X86::VFMSUB231PSYm, {0, Unknown}}, + {X86::VFMSUB231PSYr, {0, Unknown}}, + {X86::VFMSUB231PSZ128m, {0, Unknown}}, + {X86::VFMSUB231PSZ128mb, {0, Unknown}}, + {X86::VFMSUB231PSZ128mbk, {0, Unknown}}, + {X86::VFMSUB231PSZ128mbkz, {0, Unknown}}, + {X86::VFMSUB231PSZ128mk, {0, Unknown}}, + {X86::VFMSUB231PSZ128mkz, {0, Unknown}}, + {X86::VFMSUB231PSZ128r, {0, Unknown}}, + {X86::VFMSUB231PSZ128rk, {0, Unknown}}, + {X86::VFMSUB231PSZ128rkz, {0, Unknown}}, + {X86::VFMSUB231PSZ256m, {0, Unknown}}, + {X86::VFMSUB231PSZ256mb, {0, Unknown}}, + {X86::VFMSUB231PSZ256mbk, {0, Unknown}}, + {X86::VFMSUB231PSZ256mbkz, {0, Unknown}}, + {X86::VFMSUB231PSZ256mk, {0, Unknown}}, + {X86::VFMSUB231PSZ256mkz, {0, Unknown}}, + {X86::VFMSUB231PSZ256r, {0, Unknown}}, + {X86::VFMSUB231PSZ256rk, {0, Unknown}}, + {X86::VFMSUB231PSZ256rkz, {0, Unknown}}, + {X86::VFMSUB231PSZm, {0, Unknown}}, + {X86::VFMSUB231PSZmb, {0, Unknown}}, + {X86::VFMSUB231PSZmbk, {0, Unknown}}, + {X86::VFMSUB231PSZmbkz, {0, Unknown}}, + {X86::VFMSUB231PSZmk, {0, Unknown}}, + {X86::VFMSUB231PSZmkz, {0, Unknown}}, + {X86::VFMSUB231PSZr, {0, Unknown}}, + {X86::VFMSUB231PSZrb, {0, Unknown}}, + {X86::VFMSUB231PSZrbk, {0, Unknown}}, + {X86::VFMSUB231PSZrbkz, {0, Unknown}}, + {X86::VFMSUB231PSZrk, {0, Unknown}}, + {X86::VFMSUB231PSZrkz, {0, Unknown}}, + {X86::VFMSUB231PSm, {0, Unknown}}, + {X86::VFMSUB231PSr, {0, Unknown}}, + {X86::VFMSUB231SDZm, {0, Unknown}}, + {X86::VFMSUB231SDZm_Int, {0, Unknown}}, + {X86::VFMSUB231SDZm_Intk, {0, Unknown}}, + {X86::VFMSUB231SDZm_Intkz, {0, Unknown}}, + {X86::VFMSUB231SDZr, {0, Unknown}}, + {X86::VFMSUB231SDZr_Int, {0, Unknown}}, + {X86::VFMSUB231SDZr_Intk, {0, Unknown}}, + {X86::VFMSUB231SDZr_Intkz, {0, Unknown}}, + {X86::VFMSUB231SDZrb_Int, {0, Unknown}}, + {X86::VFMSUB231SDZrb_Intk, {0, Unknown}}, + {X86::VFMSUB231SDZrb_Intkz, {0, Unknown}}, + {X86::VFMSUB231SDm, {0, Unknown}}, + {X86::VFMSUB231SDm_Int, {0, Unknown}}, + {X86::VFMSUB231SDr, {0, Unknown}}, + {X86::VFMSUB231SDr_Int, {0, Unknown}}, + {X86::VFMSUB231SSZm, {0, Unknown}}, + {X86::VFMSUB231SSZm_Int, {0, Unknown}}, + {X86::VFMSUB231SSZm_Intk, {0, Unknown}}, + {X86::VFMSUB231SSZm_Intkz, {0, Unknown}}, + {X86::VFMSUB231SSZr, {0, Unknown}}, + {X86::VFMSUB231SSZr_Int, {0, Unknown}}, + {X86::VFMSUB231SSZr_Intk, {0, Unknown}}, + {X86::VFMSUB231SSZr_Intkz, {0, Unknown}}, + {X86::VFMSUB231SSZrb_Int, {0, Unknown}}, + {X86::VFMSUB231SSZrb_Intk, {0, Unknown}}, + {X86::VFMSUB231SSZrb_Intkz, {0, Unknown}}, + {X86::VFMSUB231SSm, {0, Unknown}}, + {X86::VFMSUB231SSm_Int, {0, Unknown}}, + {X86::VFMSUB231SSr, {0, Unknown}}, + {X86::VFMSUB231SSr_Int, {0, Unknown}}, + {X86::VFMSUBADD132PDYm, {0, Unknown}}, + {X86::VFMSUBADD132PDYr, {0, Unknown}}, + {X86::VFMSUBADD132PDZ128m, {0, Unknown}}, + {X86::VFMSUBADD132PDZ128mb, {0, Unknown}}, + {X86::VFMSUBADD132PDZ128mbk, {0, Unknown}}, + {X86::VFMSUBADD132PDZ128mbkz, {0, Unknown}}, + {X86::VFMSUBADD132PDZ128mk, {0, Unknown}}, + {X86::VFMSUBADD132PDZ128mkz, {0, Unknown}}, + {X86::VFMSUBADD132PDZ128r, {0, Unknown}}, + {X86::VFMSUBADD132PDZ128rk, {0, Unknown}}, + {X86::VFMSUBADD132PDZ128rkz, {0, Unknown}}, + {X86::VFMSUBADD132PDZ256m, {0, Unknown}}, + {X86::VFMSUBADD132PDZ256mb, {0, Unknown}}, + {X86::VFMSUBADD132PDZ256mbk, {0, Unknown}}, + {X86::VFMSUBADD132PDZ256mbkz, {0, Unknown}}, + {X86::VFMSUBADD132PDZ256mk, {0, Unknown}}, + {X86::VFMSUBADD132PDZ256mkz, {0, Unknown}}, + {X86::VFMSUBADD132PDZ256r, {0, Unknown}}, + {X86::VFMSUBADD132PDZ256rk, {0, Unknown}}, + {X86::VFMSUBADD132PDZ256rkz, {0, Unknown}}, + {X86::VFMSUBADD132PDZm, {0, Unknown}}, + {X86::VFMSUBADD132PDZmb, {0, Unknown}}, + {X86::VFMSUBADD132PDZmbk, {0, Unknown}}, + {X86::VFMSUBADD132PDZmbkz, {0, Unknown}}, + {X86::VFMSUBADD132PDZmk, {0, Unknown}}, + {X86::VFMSUBADD132PDZmkz, {0, Unknown}}, + {X86::VFMSUBADD132PDZr, {0, Unknown}}, + {X86::VFMSUBADD132PDZrb, {0, Unknown}}, + {X86::VFMSUBADD132PDZrbk, {0, Unknown}}, + {X86::VFMSUBADD132PDZrbkz, {0, Unknown}}, + {X86::VFMSUBADD132PDZrk, {0, Unknown}}, + {X86::VFMSUBADD132PDZrkz, {0, Unknown}}, + {X86::VFMSUBADD132PDm, {0, Unknown}}, + {X86::VFMSUBADD132PDr, {0, Unknown}}, + {X86::VFMSUBADD132PSYm, {0, Unknown}}, + {X86::VFMSUBADD132PSYr, {0, Unknown}}, + {X86::VFMSUBADD132PSZ128m, {0, Unknown}}, + {X86::VFMSUBADD132PSZ128mb, {0, Unknown}}, + {X86::VFMSUBADD132PSZ128mbk, {0, Unknown}}, + {X86::VFMSUBADD132PSZ128mbkz, {0, Unknown}}, + {X86::VFMSUBADD132PSZ128mk, {0, Unknown}}, + {X86::VFMSUBADD132PSZ128mkz, {0, Unknown}}, + {X86::VFMSUBADD132PSZ128r, {0, Unknown}}, + {X86::VFMSUBADD132PSZ128rk, {0, Unknown}}, + {X86::VFMSUBADD132PSZ128rkz, {0, Unknown}}, + {X86::VFMSUBADD132PSZ256m, {0, Unknown}}, + {X86::VFMSUBADD132PSZ256mb, {0, Unknown}}, + {X86::VFMSUBADD132PSZ256mbk, {0, Unknown}}, + {X86::VFMSUBADD132PSZ256mbkz, {0, Unknown}}, + {X86::VFMSUBADD132PSZ256mk, {0, Unknown}}, + {X86::VFMSUBADD132PSZ256mkz, {0, Unknown}}, + {X86::VFMSUBADD132PSZ256r, {0, Unknown}}, + {X86::VFMSUBADD132PSZ256rk, {0, Unknown}}, + {X86::VFMSUBADD132PSZ256rkz, {0, Unknown}}, + {X86::VFMSUBADD132PSZm, {0, Unknown}}, + {X86::VFMSUBADD132PSZmb, {0, Unknown}}, + {X86::VFMSUBADD132PSZmbk, {0, Unknown}}, + {X86::VFMSUBADD132PSZmbkz, {0, Unknown}}, + {X86::VFMSUBADD132PSZmk, {0, Unknown}}, + {X86::VFMSUBADD132PSZmkz, {0, Unknown}}, + {X86::VFMSUBADD132PSZr, {0, Unknown}}, + {X86::VFMSUBADD132PSZrb, {0, Unknown}}, + {X86::VFMSUBADD132PSZrbk, {0, Unknown}}, + {X86::VFMSUBADD132PSZrbkz, {0, Unknown}}, + {X86::VFMSUBADD132PSZrk, {0, Unknown}}, + {X86::VFMSUBADD132PSZrkz, {0, Unknown}}, + {X86::VFMSUBADD132PSm, {0, Unknown}}, + {X86::VFMSUBADD132PSr, {0, Unknown}}, + {X86::VFMSUBADD213PDYm, {0, Unknown}}, + {X86::VFMSUBADD213PDYr, {0, Unknown}}, + {X86::VFMSUBADD213PDZ128m, {0, Unknown}}, + {X86::VFMSUBADD213PDZ128mb, {0, Unknown}}, + {X86::VFMSUBADD213PDZ128mbk, {0, Unknown}}, + {X86::VFMSUBADD213PDZ128mbkz, {0, Unknown}}, + {X86::VFMSUBADD213PDZ128mk, {0, Unknown}}, + {X86::VFMSUBADD213PDZ128mkz, {0, Unknown}}, + {X86::VFMSUBADD213PDZ128r, {0, Unknown}}, + {X86::VFMSUBADD213PDZ128rk, {0, Unknown}}, + {X86::VFMSUBADD213PDZ128rkz, {0, Unknown}}, + {X86::VFMSUBADD213PDZ256m, {0, Unknown}}, + {X86::VFMSUBADD213PDZ256mb, {0, Unknown}}, + {X86::VFMSUBADD213PDZ256mbk, {0, Unknown}}, + {X86::VFMSUBADD213PDZ256mbkz, {0, Unknown}}, + {X86::VFMSUBADD213PDZ256mk, {0, Unknown}}, + {X86::VFMSUBADD213PDZ256mkz, {0, Unknown}}, + {X86::VFMSUBADD213PDZ256r, {0, Unknown}}, + {X86::VFMSUBADD213PDZ256rk, {0, Unknown}}, + {X86::VFMSUBADD213PDZ256rkz, {0, Unknown}}, + {X86::VFMSUBADD213PDZm, {0, Unknown}}, + {X86::VFMSUBADD213PDZmb, {0, Unknown}}, + {X86::VFMSUBADD213PDZmbk, {0, Unknown}}, + {X86::VFMSUBADD213PDZmbkz, {0, Unknown}}, + {X86::VFMSUBADD213PDZmk, {0, Unknown}}, + {X86::VFMSUBADD213PDZmkz, {0, Unknown}}, + {X86::VFMSUBADD213PDZr, {0, Unknown}}, + {X86::VFMSUBADD213PDZrb, {0, Unknown}}, + {X86::VFMSUBADD213PDZrbk, {0, Unknown}}, + {X86::VFMSUBADD213PDZrbkz, {0, Unknown}}, + {X86::VFMSUBADD213PDZrk, {0, Unknown}}, + {X86::VFMSUBADD213PDZrkz, {0, Unknown}}, + {X86::VFMSUBADD213PDm, {0, Unknown}}, + {X86::VFMSUBADD213PDr, {0, Unknown}}, + {X86::VFMSUBADD213PSYm, {0, Unknown}}, + {X86::VFMSUBADD213PSYr, {0, Unknown}}, + {X86::VFMSUBADD213PSZ128m, {0, Unknown}}, + {X86::VFMSUBADD213PSZ128mb, {0, Unknown}}, + {X86::VFMSUBADD213PSZ128mbk, {0, Unknown}}, + {X86::VFMSUBADD213PSZ128mbkz, {0, Unknown}}, + {X86::VFMSUBADD213PSZ128mk, {0, Unknown}}, + {X86::VFMSUBADD213PSZ128mkz, {0, Unknown}}, + {X86::VFMSUBADD213PSZ128r, {0, Unknown}}, + {X86::VFMSUBADD213PSZ128rk, {0, Unknown}}, + {X86::VFMSUBADD213PSZ128rkz, {0, Unknown}}, + {X86::VFMSUBADD213PSZ256m, {0, Unknown}}, + {X86::VFMSUBADD213PSZ256mb, {0, Unknown}}, + {X86::VFMSUBADD213PSZ256mbk, {0, Unknown}}, + {X86::VFMSUBADD213PSZ256mbkz, {0, Unknown}}, + {X86::VFMSUBADD213PSZ256mk, {0, Unknown}}, + {X86::VFMSUBADD213PSZ256mkz, {0, Unknown}}, + {X86::VFMSUBADD213PSZ256r, {0, Unknown}}, + {X86::VFMSUBADD213PSZ256rk, {0, Unknown}}, + {X86::VFMSUBADD213PSZ256rkz, {0, Unknown}}, + {X86::VFMSUBADD213PSZm, {0, Unknown}}, + {X86::VFMSUBADD213PSZmb, {0, Unknown}}, + {X86::VFMSUBADD213PSZmbk, {0, Unknown}}, + {X86::VFMSUBADD213PSZmbkz, {0, Unknown}}, + {X86::VFMSUBADD213PSZmk, {0, Unknown}}, + {X86::VFMSUBADD213PSZmkz, {0, Unknown}}, + {X86::VFMSUBADD213PSZr, {0, Unknown}}, + {X86::VFMSUBADD213PSZrb, {0, Unknown}}, + {X86::VFMSUBADD213PSZrbk, {0, Unknown}}, + {X86::VFMSUBADD213PSZrbkz, {0, Unknown}}, + {X86::VFMSUBADD213PSZrk, {0, Unknown}}, + {X86::VFMSUBADD213PSZrkz, {0, Unknown}}, + {X86::VFMSUBADD213PSm, {0, Unknown}}, + {X86::VFMSUBADD213PSr, {0, Unknown}}, + {X86::VFMSUBADD231PDYm, {0, Unknown}}, + {X86::VFMSUBADD231PDYr, {0, Unknown}}, + {X86::VFMSUBADD231PDZ128m, {0, Unknown}}, + {X86::VFMSUBADD231PDZ128mb, {0, Unknown}}, + {X86::VFMSUBADD231PDZ128mbk, {0, Unknown}}, + {X86::VFMSUBADD231PDZ128mbkz, {0, Unknown}}, + {X86::VFMSUBADD231PDZ128mk, {0, Unknown}}, + {X86::VFMSUBADD231PDZ128mkz, {0, Unknown}}, + {X86::VFMSUBADD231PDZ128r, {0, Unknown}}, + {X86::VFMSUBADD231PDZ128rk, {0, Unknown}}, + {X86::VFMSUBADD231PDZ128rkz, {0, Unknown}}, + {X86::VFMSUBADD231PDZ256m, {0, Unknown}}, + {X86::VFMSUBADD231PDZ256mb, {0, Unknown}}, + {X86::VFMSUBADD231PDZ256mbk, {0, Unknown}}, + {X86::VFMSUBADD231PDZ256mbkz, {0, Unknown}}, + {X86::VFMSUBADD231PDZ256mk, {0, Unknown}}, + {X86::VFMSUBADD231PDZ256mkz, {0, Unknown}}, + {X86::VFMSUBADD231PDZ256r, {0, Unknown}}, + {X86::VFMSUBADD231PDZ256rk, {0, Unknown}}, + {X86::VFMSUBADD231PDZ256rkz, {0, Unknown}}, + {X86::VFMSUBADD231PDZm, {0, Unknown}}, + {X86::VFMSUBADD231PDZmb, {0, Unknown}}, + {X86::VFMSUBADD231PDZmbk, {0, Unknown}}, + {X86::VFMSUBADD231PDZmbkz, {0, Unknown}}, + {X86::VFMSUBADD231PDZmk, {0, Unknown}}, + {X86::VFMSUBADD231PDZmkz, {0, Unknown}}, + {X86::VFMSUBADD231PDZr, {0, Unknown}}, + {X86::VFMSUBADD231PDZrb, {0, Unknown}}, + {X86::VFMSUBADD231PDZrbk, {0, Unknown}}, + {X86::VFMSUBADD231PDZrbkz, {0, Unknown}}, + {X86::VFMSUBADD231PDZrk, {0, Unknown}}, + {X86::VFMSUBADD231PDZrkz, {0, Unknown}}, + {X86::VFMSUBADD231PDm, {0, Unknown}}, + {X86::VFMSUBADD231PDr, {0, Unknown}}, + {X86::VFMSUBADD231PSYm, {0, Unknown}}, + {X86::VFMSUBADD231PSYr, {0, Unknown}}, + {X86::VFMSUBADD231PSZ128m, {0, Unknown}}, + {X86::VFMSUBADD231PSZ128mb, {0, Unknown}}, + {X86::VFMSUBADD231PSZ128mbk, {0, Unknown}}, + {X86::VFMSUBADD231PSZ128mbkz, {0, Unknown}}, + {X86::VFMSUBADD231PSZ128mk, {0, Unknown}}, + {X86::VFMSUBADD231PSZ128mkz, {0, Unknown}}, + {X86::VFMSUBADD231PSZ128r, {0, Unknown}}, + {X86::VFMSUBADD231PSZ128rk, {0, Unknown}}, + {X86::VFMSUBADD231PSZ128rkz, {0, Unknown}}, + {X86::VFMSUBADD231PSZ256m, {0, Unknown}}, + {X86::VFMSUBADD231PSZ256mb, {0, Unknown}}, + {X86::VFMSUBADD231PSZ256mbk, {0, Unknown}}, + {X86::VFMSUBADD231PSZ256mbkz, {0, Unknown}}, + {X86::VFMSUBADD231PSZ256mk, {0, Unknown}}, + {X86::VFMSUBADD231PSZ256mkz, {0, Unknown}}, + {X86::VFMSUBADD231PSZ256r, {0, Unknown}}, + {X86::VFMSUBADD231PSZ256rk, {0, Unknown}}, + {X86::VFMSUBADD231PSZ256rkz, {0, Unknown}}, + {X86::VFMSUBADD231PSZm, {0, Unknown}}, + {X86::VFMSUBADD231PSZmb, {0, Unknown}}, + {X86::VFMSUBADD231PSZmbk, {0, Unknown}}, + {X86::VFMSUBADD231PSZmbkz, {0, Unknown}}, + {X86::VFMSUBADD231PSZmk, {0, Unknown}}, + {X86::VFMSUBADD231PSZmkz, {0, Unknown}}, + {X86::VFMSUBADD231PSZr, {0, Unknown}}, + {X86::VFMSUBADD231PSZrb, {0, Unknown}}, + {X86::VFMSUBADD231PSZrbk, {0, Unknown}}, + {X86::VFMSUBADD231PSZrbkz, {0, Unknown}}, + {X86::VFMSUBADD231PSZrk, {0, Unknown}}, + {X86::VFMSUBADD231PSZrkz, {0, Unknown}}, + {X86::VFMSUBADD231PSm, {0, Unknown}}, + {X86::VFMSUBADD231PSr, {0, Unknown}}, + {X86::VFMSUBADDPD4Ymr, {0, Unknown}}, + {X86::VFMSUBADDPD4Yrm, {0, Unknown}}, + {X86::VFMSUBADDPD4Yrr, {0, Unknown}}, + {X86::VFMSUBADDPD4Yrr_REV, {0, Unknown}}, + {X86::VFMSUBADDPD4mr, {0, Unknown}}, + {X86::VFMSUBADDPD4rm, {0, Unknown}}, + {X86::VFMSUBADDPD4rr, {0, Unknown}}, + {X86::VFMSUBADDPD4rr_REV, {0, Unknown}}, + {X86::VFMSUBADDPS4Ymr, {0, Unknown}}, + {X86::VFMSUBADDPS4Yrm, {0, Unknown}}, + {X86::VFMSUBADDPS4Yrr, {0, Unknown}}, + {X86::VFMSUBADDPS4Yrr_REV, {0, Unknown}}, + {X86::VFMSUBADDPS4mr, {0, Unknown}}, + {X86::VFMSUBADDPS4rm, {0, Unknown}}, + {X86::VFMSUBADDPS4rr, {0, Unknown}}, + {X86::VFMSUBADDPS4rr_REV, {0, Unknown}}, + {X86::VFMSUBPD4Ymr, {0, Unknown}}, + {X86::VFMSUBPD4Yrm, {0, Unknown}}, + {X86::VFMSUBPD4Yrr, {0, Unknown}}, + {X86::VFMSUBPD4Yrr_REV, {0, Unknown}}, + {X86::VFMSUBPD4mr, {0, Unknown}}, + {X86::VFMSUBPD4rm, {0, Unknown}}, + {X86::VFMSUBPD4rr, {0, Unknown}}, + {X86::VFMSUBPD4rr_REV, {0, Unknown}}, + {X86::VFMSUBPS4Ymr, {0, Unknown}}, + {X86::VFMSUBPS4Yrm, {0, Unknown}}, + {X86::VFMSUBPS4Yrr, {0, Unknown}}, + {X86::VFMSUBPS4Yrr_REV, {0, Unknown}}, + {X86::VFMSUBPS4mr, {0, Unknown}}, + {X86::VFMSUBPS4rm, {0, Unknown}}, + {X86::VFMSUBPS4rr, {0, Unknown}}, + {X86::VFMSUBPS4rr_REV, {0, Unknown}}, + {X86::VFMSUBSD4mr, {0, Unknown}}, + {X86::VFMSUBSD4mr_Int, {0, Unknown}}, + {X86::VFMSUBSD4rm, {0, Unknown}}, + {X86::VFMSUBSD4rm_Int, {0, Unknown}}, + {X86::VFMSUBSD4rr, {0, Unknown}}, + {X86::VFMSUBSD4rr_Int, {0, Unknown}}, + {X86::VFMSUBSD4rr_Int_REV, {0, Unknown}}, + {X86::VFMSUBSD4rr_REV, {0, Unknown}}, + {X86::VFMSUBSS4mr, {0, Unknown}}, + {X86::VFMSUBSS4mr_Int, {0, Unknown}}, + {X86::VFMSUBSS4rm, {0, Unknown}}, + {X86::VFMSUBSS4rm_Int, {0, Unknown}}, + {X86::VFMSUBSS4rr, {0, Unknown}}, + {X86::VFMSUBSS4rr_Int, {0, Unknown}}, + {X86::VFMSUBSS4rr_Int_REV, {0, Unknown}}, + {X86::VFMSUBSS4rr_REV, {0, Unknown}}, + {X86::VFNMADD132PDYm, {0, Unknown}}, + {X86::VFNMADD132PDYr, {0, Unknown}}, + {X86::VFNMADD132PDZ128m, {0, Unknown}}, + {X86::VFNMADD132PDZ128mb, {0, Unknown}}, + {X86::VFNMADD132PDZ128mbk, {0, Unknown}}, + {X86::VFNMADD132PDZ128mbkz, {0, Unknown}}, + {X86::VFNMADD132PDZ128mk, {0, Unknown}}, + {X86::VFNMADD132PDZ128mkz, {0, Unknown}}, + {X86::VFNMADD132PDZ128r, {0, Unknown}}, + {X86::VFNMADD132PDZ128rk, {0, Unknown}}, + {X86::VFNMADD132PDZ128rkz, {0, Unknown}}, + {X86::VFNMADD132PDZ256m, {0, Unknown}}, + {X86::VFNMADD132PDZ256mb, {0, Unknown}}, + {X86::VFNMADD132PDZ256mbk, {0, Unknown}}, + {X86::VFNMADD132PDZ256mbkz, {0, Unknown}}, + {X86::VFNMADD132PDZ256mk, {0, Unknown}}, + {X86::VFNMADD132PDZ256mkz, {0, Unknown}}, + {X86::VFNMADD132PDZ256r, {0, Unknown}}, + {X86::VFNMADD132PDZ256rk, {0, Unknown}}, + {X86::VFNMADD132PDZ256rkz, {0, Unknown}}, + {X86::VFNMADD132PDZm, {0, Unknown}}, + {X86::VFNMADD132PDZmb, {0, Unknown}}, + {X86::VFNMADD132PDZmbk, {0, Unknown}}, + {X86::VFNMADD132PDZmbkz, {0, Unknown}}, + {X86::VFNMADD132PDZmk, {0, Unknown}}, + {X86::VFNMADD132PDZmkz, {0, Unknown}}, + {X86::VFNMADD132PDZr, {0, Unknown}}, + {X86::VFNMADD132PDZrb, {0, Unknown}}, + {X86::VFNMADD132PDZrbk, {0, Unknown}}, + {X86::VFNMADD132PDZrbkz, {0, Unknown}}, + {X86::VFNMADD132PDZrk, {0, Unknown}}, + {X86::VFNMADD132PDZrkz, {0, Unknown}}, + {X86::VFNMADD132PDm, {0, Unknown}}, + {X86::VFNMADD132PDr, {0, Unknown}}, + {X86::VFNMADD132PSYm, {0, Unknown}}, + {X86::VFNMADD132PSYr, {0, Unknown}}, + {X86::VFNMADD132PSZ128m, {0, Unknown}}, + {X86::VFNMADD132PSZ128mb, {0, Unknown}}, + {X86::VFNMADD132PSZ128mbk, {0, Unknown}}, + {X86::VFNMADD132PSZ128mbkz, {0, Unknown}}, + {X86::VFNMADD132PSZ128mk, {0, Unknown}}, + {X86::VFNMADD132PSZ128mkz, {0, Unknown}}, + {X86::VFNMADD132PSZ128r, {0, Unknown}}, + {X86::VFNMADD132PSZ128rk, {0, Unknown}}, + {X86::VFNMADD132PSZ128rkz, {0, Unknown}}, + {X86::VFNMADD132PSZ256m, {0, Unknown}}, + {X86::VFNMADD132PSZ256mb, {0, Unknown}}, + {X86::VFNMADD132PSZ256mbk, {0, Unknown}}, + {X86::VFNMADD132PSZ256mbkz, {0, Unknown}}, + {X86::VFNMADD132PSZ256mk, {0, Unknown}}, + {X86::VFNMADD132PSZ256mkz, {0, Unknown}}, + {X86::VFNMADD132PSZ256r, {0, Unknown}}, + {X86::VFNMADD132PSZ256rk, {0, Unknown}}, + {X86::VFNMADD132PSZ256rkz, {0, Unknown}}, + {X86::VFNMADD132PSZm, {0, Unknown}}, + {X86::VFNMADD132PSZmb, {0, Unknown}}, + {X86::VFNMADD132PSZmbk, {0, Unknown}}, + {X86::VFNMADD132PSZmbkz, {0, Unknown}}, + {X86::VFNMADD132PSZmk, {0, Unknown}}, + {X86::VFNMADD132PSZmkz, {0, Unknown}}, + {X86::VFNMADD132PSZr, {0, Unknown}}, + {X86::VFNMADD132PSZrb, {0, Unknown}}, + {X86::VFNMADD132PSZrbk, {0, Unknown}}, + {X86::VFNMADD132PSZrbkz, {0, Unknown}}, + {X86::VFNMADD132PSZrk, {0, Unknown}}, + {X86::VFNMADD132PSZrkz, {0, Unknown}}, + {X86::VFNMADD132PSm, {0, Unknown}}, + {X86::VFNMADD132PSr, {0, Unknown}}, + {X86::VFNMADD132SDZm, {0, Unknown}}, + {X86::VFNMADD132SDZm_Int, {0, Unknown}}, + {X86::VFNMADD132SDZm_Intk, {0, Unknown}}, + {X86::VFNMADD132SDZm_Intkz, {0, Unknown}}, + {X86::VFNMADD132SDZr, {0, Unknown}}, + {X86::VFNMADD132SDZr_Int, {0, Unknown}}, + {X86::VFNMADD132SDZr_Intk, {0, Unknown}}, + {X86::VFNMADD132SDZr_Intkz, {0, Unknown}}, + {X86::VFNMADD132SDZrb_Int, {0, Unknown}}, + {X86::VFNMADD132SDZrb_Intk, {0, Unknown}}, + {X86::VFNMADD132SDZrb_Intkz, {0, Unknown}}, + {X86::VFNMADD132SDm, {0, Unknown}}, + {X86::VFNMADD132SDm_Int, {0, Unknown}}, + {X86::VFNMADD132SDr, {0, Unknown}}, + {X86::VFNMADD132SDr_Int, {0, Unknown}}, + {X86::VFNMADD132SSZm, {0, Unknown}}, + {X86::VFNMADD132SSZm_Int, {0, Unknown}}, + {X86::VFNMADD132SSZm_Intk, {0, Unknown}}, + {X86::VFNMADD132SSZm_Intkz, {0, Unknown}}, + {X86::VFNMADD132SSZr, {0, Unknown}}, + {X86::VFNMADD132SSZr_Int, {0, Unknown}}, + {X86::VFNMADD132SSZr_Intk, {0, Unknown}}, + {X86::VFNMADD132SSZr_Intkz, {0, Unknown}}, + {X86::VFNMADD132SSZrb_Int, {0, Unknown}}, + {X86::VFNMADD132SSZrb_Intk, {0, Unknown}}, + {X86::VFNMADD132SSZrb_Intkz, {0, Unknown}}, + {X86::VFNMADD132SSm, {0, Unknown}}, + {X86::VFNMADD132SSm_Int, {0, Unknown}}, + {X86::VFNMADD132SSr, {0, Unknown}}, + {X86::VFNMADD132SSr_Int, {0, Unknown}}, + {X86::VFNMADD213PDYm, {0, Unknown}}, + {X86::VFNMADD213PDYr, {0, Unknown}}, + {X86::VFNMADD213PDZ128m, {0, Unknown}}, + {X86::VFNMADD213PDZ128mb, {0, Unknown}}, + {X86::VFNMADD213PDZ128mbk, {0, Unknown}}, + {X86::VFNMADD213PDZ128mbkz, {0, Unknown}}, + {X86::VFNMADD213PDZ128mk, {0, Unknown}}, + {X86::VFNMADD213PDZ128mkz, {0, Unknown}}, + {X86::VFNMADD213PDZ128r, {0, Unknown}}, + {X86::VFNMADD213PDZ128rk, {0, Unknown}}, + {X86::VFNMADD213PDZ128rkz, {0, Unknown}}, + {X86::VFNMADD213PDZ256m, {0, Unknown}}, + {X86::VFNMADD213PDZ256mb, {0, Unknown}}, + {X86::VFNMADD213PDZ256mbk, {0, Unknown}}, + {X86::VFNMADD213PDZ256mbkz, {0, Unknown}}, + {X86::VFNMADD213PDZ256mk, {0, Unknown}}, + {X86::VFNMADD213PDZ256mkz, {0, Unknown}}, + {X86::VFNMADD213PDZ256r, {0, Unknown}}, + {X86::VFNMADD213PDZ256rk, {0, Unknown}}, + {X86::VFNMADD213PDZ256rkz, {0, Unknown}}, + {X86::VFNMADD213PDZm, {0, Unknown}}, + {X86::VFNMADD213PDZmb, {0, Unknown}}, + {X86::VFNMADD213PDZmbk, {0, Unknown}}, + {X86::VFNMADD213PDZmbkz, {0, Unknown}}, + {X86::VFNMADD213PDZmk, {0, Unknown}}, + {X86::VFNMADD213PDZmkz, {0, Unknown}}, + {X86::VFNMADD213PDZr, {0, Unknown}}, + {X86::VFNMADD213PDZrb, {0, Unknown}}, + {X86::VFNMADD213PDZrbk, {0, Unknown}}, + {X86::VFNMADD213PDZrbkz, {0, Unknown}}, + {X86::VFNMADD213PDZrk, {0, Unknown}}, + {X86::VFNMADD213PDZrkz, {0, Unknown}}, + {X86::VFNMADD213PDm, {0, Unknown}}, + {X86::VFNMADD213PDr, {0, Unknown}}, + {X86::VFNMADD213PSYm, {0, Unknown}}, + {X86::VFNMADD213PSYr, {0, Unknown}}, + {X86::VFNMADD213PSZ128m, {0, Unknown}}, + {X86::VFNMADD213PSZ128mb, {0, Unknown}}, + {X86::VFNMADD213PSZ128mbk, {0, Unknown}}, + {X86::VFNMADD213PSZ128mbkz, {0, Unknown}}, + {X86::VFNMADD213PSZ128mk, {0, Unknown}}, + {X86::VFNMADD213PSZ128mkz, {0, Unknown}}, + {X86::VFNMADD213PSZ128r, {0, Unknown}}, + {X86::VFNMADD213PSZ128rk, {0, Unknown}}, + {X86::VFNMADD213PSZ128rkz, {0, Unknown}}, + {X86::VFNMADD213PSZ256m, {0, Unknown}}, + {X86::VFNMADD213PSZ256mb, {0, Unknown}}, + {X86::VFNMADD213PSZ256mbk, {0, Unknown}}, + {X86::VFNMADD213PSZ256mbkz, {0, Unknown}}, + {X86::VFNMADD213PSZ256mk, {0, Unknown}}, + {X86::VFNMADD213PSZ256mkz, {0, Unknown}}, + {X86::VFNMADD213PSZ256r, {0, Unknown}}, + {X86::VFNMADD213PSZ256rk, {0, Unknown}}, + {X86::VFNMADD213PSZ256rkz, {0, Unknown}}, + {X86::VFNMADD213PSZm, {0, Unknown}}, + {X86::VFNMADD213PSZmb, {0, Unknown}}, + {X86::VFNMADD213PSZmbk, {0, Unknown}}, + {X86::VFNMADD213PSZmbkz, {0, Unknown}}, + {X86::VFNMADD213PSZmk, {0, Unknown}}, + {X86::VFNMADD213PSZmkz, {0, Unknown}}, + {X86::VFNMADD213PSZr, {0, Unknown}}, + {X86::VFNMADD213PSZrb, {0, Unknown}}, + {X86::VFNMADD213PSZrbk, {0, Unknown}}, + {X86::VFNMADD213PSZrbkz, {0, Unknown}}, + {X86::VFNMADD213PSZrk, {0, Unknown}}, + {X86::VFNMADD213PSZrkz, {0, Unknown}}, + {X86::VFNMADD213PSm, {0, Unknown}}, + {X86::VFNMADD213PSr, {0, Unknown}}, + {X86::VFNMADD213SDZm, {0, Unknown}}, + {X86::VFNMADD213SDZm_Int, {0, Unknown}}, + {X86::VFNMADD213SDZm_Intk, {0, Unknown}}, + {X86::VFNMADD213SDZm_Intkz, {0, Unknown}}, + {X86::VFNMADD213SDZr, {0, Unknown}}, + {X86::VFNMADD213SDZr_Int, {0, Unknown}}, + {X86::VFNMADD213SDZr_Intk, {0, Unknown}}, + {X86::VFNMADD213SDZr_Intkz, {0, Unknown}}, + {X86::VFNMADD213SDZrb_Int, {0, Unknown}}, + {X86::VFNMADD213SDZrb_Intk, {0, Unknown}}, + {X86::VFNMADD213SDZrb_Intkz, {0, Unknown}}, + {X86::VFNMADD213SDm, {0, Unknown}}, + {X86::VFNMADD213SDm_Int, {0, Unknown}}, + {X86::VFNMADD213SDr, {0, Unknown}}, + {X86::VFNMADD213SDr_Int, {0, Unknown}}, + {X86::VFNMADD213SSZm, {0, Unknown}}, + {X86::VFNMADD213SSZm_Int, {0, Unknown}}, + {X86::VFNMADD213SSZm_Intk, {0, Unknown}}, + {X86::VFNMADD213SSZm_Intkz, {0, Unknown}}, + {X86::VFNMADD213SSZr, {0, Unknown}}, + {X86::VFNMADD213SSZr_Int, {0, Unknown}}, + {X86::VFNMADD213SSZr_Intk, {0, Unknown}}, + {X86::VFNMADD213SSZr_Intkz, {0, Unknown}}, + {X86::VFNMADD213SSZrb_Int, {0, Unknown}}, + {X86::VFNMADD213SSZrb_Intk, {0, Unknown}}, + {X86::VFNMADD213SSZrb_Intkz, {0, Unknown}}, + {X86::VFNMADD213SSm, {0, Unknown}}, + {X86::VFNMADD213SSm_Int, {0, Unknown}}, + {X86::VFNMADD213SSr, {0, Unknown}}, + {X86::VFNMADD213SSr_Int, {0, Unknown}}, + {X86::VFNMADD231PDYm, {0, Unknown}}, + {X86::VFNMADD231PDYr, {0, Unknown}}, + {X86::VFNMADD231PDZ128m, {0, Unknown}}, + {X86::VFNMADD231PDZ128mb, {0, Unknown}}, + {X86::VFNMADD231PDZ128mbk, {0, Unknown}}, + {X86::VFNMADD231PDZ128mbkz, {0, Unknown}}, + {X86::VFNMADD231PDZ128mk, {0, Unknown}}, + {X86::VFNMADD231PDZ128mkz, {0, Unknown}}, + {X86::VFNMADD231PDZ128r, {0, Unknown}}, + {X86::VFNMADD231PDZ128rk, {0, Unknown}}, + {X86::VFNMADD231PDZ128rkz, {0, Unknown}}, + {X86::VFNMADD231PDZ256m, {0, Unknown}}, + {X86::VFNMADD231PDZ256mb, {0, Unknown}}, + {X86::VFNMADD231PDZ256mbk, {0, Unknown}}, + {X86::VFNMADD231PDZ256mbkz, {0, Unknown}}, + {X86::VFNMADD231PDZ256mk, {0, Unknown}}, + {X86::VFNMADD231PDZ256mkz, {0, Unknown}}, + {X86::VFNMADD231PDZ256r, {0, Unknown}}, + {X86::VFNMADD231PDZ256rk, {0, Unknown}}, + {X86::VFNMADD231PDZ256rkz, {0, Unknown}}, + {X86::VFNMADD231PDZm, {0, Unknown}}, + {X86::VFNMADD231PDZmb, {0, Unknown}}, + {X86::VFNMADD231PDZmbk, {0, Unknown}}, + {X86::VFNMADD231PDZmbkz, {0, Unknown}}, + {X86::VFNMADD231PDZmk, {0, Unknown}}, + {X86::VFNMADD231PDZmkz, {0, Unknown}}, + {X86::VFNMADD231PDZr, {0, Unknown}}, + {X86::VFNMADD231PDZrb, {0, Unknown}}, + {X86::VFNMADD231PDZrbk, {0, Unknown}}, + {X86::VFNMADD231PDZrbkz, {0, Unknown}}, + {X86::VFNMADD231PDZrk, {0, Unknown}}, + {X86::VFNMADD231PDZrkz, {0, Unknown}}, + {X86::VFNMADD231PDm, {0, Unknown}}, + {X86::VFNMADD231PDr, {0, Unknown}}, + {X86::VFNMADD231PSYm, {0, Unknown}}, + {X86::VFNMADD231PSYr, {0, Unknown}}, + {X86::VFNMADD231PSZ128m, {0, Unknown}}, + {X86::VFNMADD231PSZ128mb, {0, Unknown}}, + {X86::VFNMADD231PSZ128mbk, {0, Unknown}}, + {X86::VFNMADD231PSZ128mbkz, {0, Unknown}}, + {X86::VFNMADD231PSZ128mk, {0, Unknown}}, + {X86::VFNMADD231PSZ128mkz, {0, Unknown}}, + {X86::VFNMADD231PSZ128r, {0, Unknown}}, + {X86::VFNMADD231PSZ128rk, {0, Unknown}}, + {X86::VFNMADD231PSZ128rkz, {0, Unknown}}, + {X86::VFNMADD231PSZ256m, {0, Unknown}}, + {X86::VFNMADD231PSZ256mb, {0, Unknown}}, + {X86::VFNMADD231PSZ256mbk, {0, Unknown}}, + {X86::VFNMADD231PSZ256mbkz, {0, Unknown}}, + {X86::VFNMADD231PSZ256mk, {0, Unknown}}, + {X86::VFNMADD231PSZ256mkz, {0, Unknown}}, + {X86::VFNMADD231PSZ256r, {0, Unknown}}, + {X86::VFNMADD231PSZ256rk, {0, Unknown}}, + {X86::VFNMADD231PSZ256rkz, {0, Unknown}}, + {X86::VFNMADD231PSZm, {0, Unknown}}, + {X86::VFNMADD231PSZmb, {0, Unknown}}, + {X86::VFNMADD231PSZmbk, {0, Unknown}}, + {X86::VFNMADD231PSZmbkz, {0, Unknown}}, + {X86::VFNMADD231PSZmk, {0, Unknown}}, + {X86::VFNMADD231PSZmkz, {0, Unknown}}, + {X86::VFNMADD231PSZr, {0, Unknown}}, + {X86::VFNMADD231PSZrb, {0, Unknown}}, + {X86::VFNMADD231PSZrbk, {0, Unknown}}, + {X86::VFNMADD231PSZrbkz, {0, Unknown}}, + {X86::VFNMADD231PSZrk, {0, Unknown}}, + {X86::VFNMADD231PSZrkz, {0, Unknown}}, + {X86::VFNMADD231PSm, {0, Unknown}}, + {X86::VFNMADD231PSr, {0, Unknown}}, + {X86::VFNMADD231SDZm, {0, Unknown}}, + {X86::VFNMADD231SDZm_Int, {0, Unknown}}, + {X86::VFNMADD231SDZm_Intk, {0, Unknown}}, + {X86::VFNMADD231SDZm_Intkz, {0, Unknown}}, + {X86::VFNMADD231SDZr, {0, Unknown}}, + {X86::VFNMADD231SDZr_Int, {0, Unknown}}, + {X86::VFNMADD231SDZr_Intk, {0, Unknown}}, + {X86::VFNMADD231SDZr_Intkz, {0, Unknown}}, + {X86::VFNMADD231SDZrb_Int, {0, Unknown}}, + {X86::VFNMADD231SDZrb_Intk, {0, Unknown}}, + {X86::VFNMADD231SDZrb_Intkz, {0, Unknown}}, + {X86::VFNMADD231SDm, {0, Unknown}}, + {X86::VFNMADD231SDm_Int, {0, Unknown}}, + {X86::VFNMADD231SDr, {0, Unknown}}, + {X86::VFNMADD231SDr_Int, {0, Unknown}}, + {X86::VFNMADD231SSZm, {0, Unknown}}, + {X86::VFNMADD231SSZm_Int, {0, Unknown}}, + {X86::VFNMADD231SSZm_Intk, {0, Unknown}}, + {X86::VFNMADD231SSZm_Intkz, {0, Unknown}}, + {X86::VFNMADD231SSZr, {0, Unknown}}, + {X86::VFNMADD231SSZr_Int, {0, Unknown}}, + {X86::VFNMADD231SSZr_Intk, {0, Unknown}}, + {X86::VFNMADD231SSZr_Intkz, {0, Unknown}}, + {X86::VFNMADD231SSZrb_Int, {0, Unknown}}, + {X86::VFNMADD231SSZrb_Intk, {0, Unknown}}, + {X86::VFNMADD231SSZrb_Intkz, {0, Unknown}}, + {X86::VFNMADD231SSm, {0, Unknown}}, + {X86::VFNMADD231SSm_Int, {0, Unknown}}, + {X86::VFNMADD231SSr, {0, Unknown}}, + {X86::VFNMADD231SSr_Int, {0, Unknown}}, + {X86::VFNMADDPD4Ymr, {0, Unknown}}, + {X86::VFNMADDPD4Yrm, {0, Unknown}}, + {X86::VFNMADDPD4Yrr, {0, Unknown}}, + {X86::VFNMADDPD4Yrr_REV, {0, Unknown}}, + {X86::VFNMADDPD4mr, {0, Unknown}}, + {X86::VFNMADDPD4rm, {0, Unknown}}, + {X86::VFNMADDPD4rr, {0, Unknown}}, + {X86::VFNMADDPD4rr_REV, {0, Unknown}}, + {X86::VFNMADDPS4Ymr, {0, Unknown}}, + {X86::VFNMADDPS4Yrm, {0, Unknown}}, + {X86::VFNMADDPS4Yrr, {0, Unknown}}, + {X86::VFNMADDPS4Yrr_REV, {0, Unknown}}, + {X86::VFNMADDPS4mr, {0, Unknown}}, + {X86::VFNMADDPS4rm, {0, Unknown}}, + {X86::VFNMADDPS4rr, {0, Unknown}}, + {X86::VFNMADDPS4rr_REV, {0, Unknown}}, + {X86::VFNMADDSD4mr, {0, Unknown}}, + {X86::VFNMADDSD4mr_Int, {0, Unknown}}, + {X86::VFNMADDSD4rm, {0, Unknown}}, + {X86::VFNMADDSD4rm_Int, {0, Unknown}}, + {X86::VFNMADDSD4rr, {0, Unknown}}, + {X86::VFNMADDSD4rr_Int, {0, Unknown}}, + {X86::VFNMADDSD4rr_Int_REV, {0, Unknown}}, + {X86::VFNMADDSD4rr_REV, {0, Unknown}}, + {X86::VFNMADDSS4mr, {0, Unknown}}, + {X86::VFNMADDSS4mr_Int, {0, Unknown}}, + {X86::VFNMADDSS4rm, {0, Unknown}}, + {X86::VFNMADDSS4rm_Int, {0, Unknown}}, + {X86::VFNMADDSS4rr, {0, Unknown}}, + {X86::VFNMADDSS4rr_Int, {0, Unknown}}, + {X86::VFNMADDSS4rr_Int_REV, {0, Unknown}}, + {X86::VFNMADDSS4rr_REV, {0, Unknown}}, + {X86::VFNMSUB132PDYm, {0, Unknown}}, + {X86::VFNMSUB132PDYr, {0, Unknown}}, + {X86::VFNMSUB132PDZ128m, {0, Unknown}}, + {X86::VFNMSUB132PDZ128mb, {0, Unknown}}, + {X86::VFNMSUB132PDZ128mbk, {0, Unknown}}, + {X86::VFNMSUB132PDZ128mbkz, {0, Unknown}}, + {X86::VFNMSUB132PDZ128mk, {0, Unknown}}, + {X86::VFNMSUB132PDZ128mkz, {0, Unknown}}, + {X86::VFNMSUB132PDZ128r, {0, Unknown}}, + {X86::VFNMSUB132PDZ128rk, {0, Unknown}}, + {X86::VFNMSUB132PDZ128rkz, {0, Unknown}}, + {X86::VFNMSUB132PDZ256m, {0, Unknown}}, + {X86::VFNMSUB132PDZ256mb, {0, Unknown}}, + {X86::VFNMSUB132PDZ256mbk, {0, Unknown}}, + {X86::VFNMSUB132PDZ256mbkz, {0, Unknown}}, + {X86::VFNMSUB132PDZ256mk, {0, Unknown}}, + {X86::VFNMSUB132PDZ256mkz, {0, Unknown}}, + {X86::VFNMSUB132PDZ256r, {0, Unknown}}, + {X86::VFNMSUB132PDZ256rk, {0, Unknown}}, + {X86::VFNMSUB132PDZ256rkz, {0, Unknown}}, + {X86::VFNMSUB132PDZm, {0, Unknown}}, + {X86::VFNMSUB132PDZmb, {0, Unknown}}, + {X86::VFNMSUB132PDZmbk, {0, Unknown}}, + {X86::VFNMSUB132PDZmbkz, {0, Unknown}}, + {X86::VFNMSUB132PDZmk, {0, Unknown}}, + {X86::VFNMSUB132PDZmkz, {0, Unknown}}, + {X86::VFNMSUB132PDZr, {0, Unknown}}, + {X86::VFNMSUB132PDZrb, {0, Unknown}}, + {X86::VFNMSUB132PDZrbk, {0, Unknown}}, + {X86::VFNMSUB132PDZrbkz, {0, Unknown}}, + {X86::VFNMSUB132PDZrk, {0, Unknown}}, + {X86::VFNMSUB132PDZrkz, {0, Unknown}}, + {X86::VFNMSUB132PDm, {0, Unknown}}, + {X86::VFNMSUB132PDr, {0, Unknown}}, + {X86::VFNMSUB132PSYm, {0, Unknown}}, + {X86::VFNMSUB132PSYr, {0, Unknown}}, + {X86::VFNMSUB132PSZ128m, {0, Unknown}}, + {X86::VFNMSUB132PSZ128mb, {0, Unknown}}, + {X86::VFNMSUB132PSZ128mbk, {0, Unknown}}, + {X86::VFNMSUB132PSZ128mbkz, {0, Unknown}}, + {X86::VFNMSUB132PSZ128mk, {0, Unknown}}, + {X86::VFNMSUB132PSZ128mkz, {0, Unknown}}, + {X86::VFNMSUB132PSZ128r, {0, Unknown}}, + {X86::VFNMSUB132PSZ128rk, {0, Unknown}}, + {X86::VFNMSUB132PSZ128rkz, {0, Unknown}}, + {X86::VFNMSUB132PSZ256m, {0, Unknown}}, + {X86::VFNMSUB132PSZ256mb, {0, Unknown}}, + {X86::VFNMSUB132PSZ256mbk, {0, Unknown}}, + {X86::VFNMSUB132PSZ256mbkz, {0, Unknown}}, + {X86::VFNMSUB132PSZ256mk, {0, Unknown}}, + {X86::VFNMSUB132PSZ256mkz, {0, Unknown}}, + {X86::VFNMSUB132PSZ256r, {0, Unknown}}, + {X86::VFNMSUB132PSZ256rk, {0, Unknown}}, + {X86::VFNMSUB132PSZ256rkz, {0, Unknown}}, + {X86::VFNMSUB132PSZm, {0, Unknown}}, + {X86::VFNMSUB132PSZmb, {0, Unknown}}, + {X86::VFNMSUB132PSZmbk, {0, Unknown}}, + {X86::VFNMSUB132PSZmbkz, {0, Unknown}}, + {X86::VFNMSUB132PSZmk, {0, Unknown}}, + {X86::VFNMSUB132PSZmkz, {0, Unknown}}, + {X86::VFNMSUB132PSZr, {0, Unknown}}, + {X86::VFNMSUB132PSZrb, {0, Unknown}}, + {X86::VFNMSUB132PSZrbk, {0, Unknown}}, + {X86::VFNMSUB132PSZrbkz, {0, Unknown}}, + {X86::VFNMSUB132PSZrk, {0, Unknown}}, + {X86::VFNMSUB132PSZrkz, {0, Unknown}}, + {X86::VFNMSUB132PSm, {0, Unknown}}, + {X86::VFNMSUB132PSr, {0, Unknown}}, + {X86::VFNMSUB132SDZm, {0, Unknown}}, + {X86::VFNMSUB132SDZm_Int, {0, Unknown}}, + {X86::VFNMSUB132SDZm_Intk, {0, Unknown}}, + {X86::VFNMSUB132SDZm_Intkz, {0, Unknown}}, + {X86::VFNMSUB132SDZr, {0, Unknown}}, + {X86::VFNMSUB132SDZr_Int, {0, Unknown}}, + {X86::VFNMSUB132SDZr_Intk, {0, Unknown}}, + {X86::VFNMSUB132SDZr_Intkz, {0, Unknown}}, + {X86::VFNMSUB132SDZrb_Int, {0, Unknown}}, + {X86::VFNMSUB132SDZrb_Intk, {0, Unknown}}, + {X86::VFNMSUB132SDZrb_Intkz, {0, Unknown}}, + {X86::VFNMSUB132SDm, {0, Unknown}}, + {X86::VFNMSUB132SDm_Int, {0, Unknown}}, + {X86::VFNMSUB132SDr, {0, Unknown}}, + {X86::VFNMSUB132SDr_Int, {0, Unknown}}, + {X86::VFNMSUB132SSZm, {0, Unknown}}, + {X86::VFNMSUB132SSZm_Int, {0, Unknown}}, + {X86::VFNMSUB132SSZm_Intk, {0, Unknown}}, + {X86::VFNMSUB132SSZm_Intkz, {0, Unknown}}, + {X86::VFNMSUB132SSZr, {0, Unknown}}, + {X86::VFNMSUB132SSZr_Int, {0, Unknown}}, + {X86::VFNMSUB132SSZr_Intk, {0, Unknown}}, + {X86::VFNMSUB132SSZr_Intkz, {0, Unknown}}, + {X86::VFNMSUB132SSZrb_Int, {0, Unknown}}, + {X86::VFNMSUB132SSZrb_Intk, {0, Unknown}}, + {X86::VFNMSUB132SSZrb_Intkz, {0, Unknown}}, + {X86::VFNMSUB132SSm, {0, Unknown}}, + {X86::VFNMSUB132SSm_Int, {0, Unknown}}, + {X86::VFNMSUB132SSr, {0, Unknown}}, + {X86::VFNMSUB132SSr_Int, {0, Unknown}}, + {X86::VFNMSUB213PDYm, {0, Unknown}}, + {X86::VFNMSUB213PDYr, {0, Unknown}}, + {X86::VFNMSUB213PDZ128m, {0, Unknown}}, + {X86::VFNMSUB213PDZ128mb, {0, Unknown}}, + {X86::VFNMSUB213PDZ128mbk, {0, Unknown}}, + {X86::VFNMSUB213PDZ128mbkz, {0, Unknown}}, + {X86::VFNMSUB213PDZ128mk, {0, Unknown}}, + {X86::VFNMSUB213PDZ128mkz, {0, Unknown}}, + {X86::VFNMSUB213PDZ128r, {0, Unknown}}, + {X86::VFNMSUB213PDZ128rk, {0, Unknown}}, + {X86::VFNMSUB213PDZ128rkz, {0, Unknown}}, + {X86::VFNMSUB213PDZ256m, {0, Unknown}}, + {X86::VFNMSUB213PDZ256mb, {0, Unknown}}, + {X86::VFNMSUB213PDZ256mbk, {0, Unknown}}, + {X86::VFNMSUB213PDZ256mbkz, {0, Unknown}}, + {X86::VFNMSUB213PDZ256mk, {0, Unknown}}, + {X86::VFNMSUB213PDZ256mkz, {0, Unknown}}, + {X86::VFNMSUB213PDZ256r, {0, Unknown}}, + {X86::VFNMSUB213PDZ256rk, {0, Unknown}}, + {X86::VFNMSUB213PDZ256rkz, {0, Unknown}}, + {X86::VFNMSUB213PDZm, {0, Unknown}}, + {X86::VFNMSUB213PDZmb, {0, Unknown}}, + {X86::VFNMSUB213PDZmbk, {0, Unknown}}, + {X86::VFNMSUB213PDZmbkz, {0, Unknown}}, + {X86::VFNMSUB213PDZmk, {0, Unknown}}, + {X86::VFNMSUB213PDZmkz, {0, Unknown}}, + {X86::VFNMSUB213PDZr, {0, Unknown}}, + {X86::VFNMSUB213PDZrb, {0, Unknown}}, + {X86::VFNMSUB213PDZrbk, {0, Unknown}}, + {X86::VFNMSUB213PDZrbkz, {0, Unknown}}, + {X86::VFNMSUB213PDZrk, {0, Unknown}}, + {X86::VFNMSUB213PDZrkz, {0, Unknown}}, + {X86::VFNMSUB213PDm, {0, Unknown}}, + {X86::VFNMSUB213PDr, {0, Unknown}}, + {X86::VFNMSUB213PSYm, {0, Unknown}}, + {X86::VFNMSUB213PSYr, {0, Unknown}}, + {X86::VFNMSUB213PSZ128m, {0, Unknown}}, + {X86::VFNMSUB213PSZ128mb, {0, Unknown}}, + {X86::VFNMSUB213PSZ128mbk, {0, Unknown}}, + {X86::VFNMSUB213PSZ128mbkz, {0, Unknown}}, + {X86::VFNMSUB213PSZ128mk, {0, Unknown}}, + {X86::VFNMSUB213PSZ128mkz, {0, Unknown}}, + {X86::VFNMSUB213PSZ128r, {0, Unknown}}, + {X86::VFNMSUB213PSZ128rk, {0, Unknown}}, + {X86::VFNMSUB213PSZ128rkz, {0, Unknown}}, + {X86::VFNMSUB213PSZ256m, {0, Unknown}}, + {X86::VFNMSUB213PSZ256mb, {0, Unknown}}, + {X86::VFNMSUB213PSZ256mbk, {0, Unknown}}, + {X86::VFNMSUB213PSZ256mbkz, {0, Unknown}}, + {X86::VFNMSUB213PSZ256mk, {0, Unknown}}, + {X86::VFNMSUB213PSZ256mkz, {0, Unknown}}, + {X86::VFNMSUB213PSZ256r, {0, Unknown}}, + {X86::VFNMSUB213PSZ256rk, {0, Unknown}}, + {X86::VFNMSUB213PSZ256rkz, {0, Unknown}}, + {X86::VFNMSUB213PSZm, {0, Unknown}}, + {X86::VFNMSUB213PSZmb, {0, Unknown}}, + {X86::VFNMSUB213PSZmbk, {0, Unknown}}, + {X86::VFNMSUB213PSZmbkz, {0, Unknown}}, + {X86::VFNMSUB213PSZmk, {0, Unknown}}, + {X86::VFNMSUB213PSZmkz, {0, Unknown}}, + {X86::VFNMSUB213PSZr, {0, Unknown}}, + {X86::VFNMSUB213PSZrb, {0, Unknown}}, + {X86::VFNMSUB213PSZrbk, {0, Unknown}}, + {X86::VFNMSUB213PSZrbkz, {0, Unknown}}, + {X86::VFNMSUB213PSZrk, {0, Unknown}}, + {X86::VFNMSUB213PSZrkz, {0, Unknown}}, + {X86::VFNMSUB213PSm, {0, Unknown}}, + {X86::VFNMSUB213PSr, {0, Unknown}}, + {X86::VFNMSUB213SDZm, {0, Unknown}}, + {X86::VFNMSUB213SDZm_Int, {0, Unknown}}, + {X86::VFNMSUB213SDZm_Intk, {0, Unknown}}, + {X86::VFNMSUB213SDZm_Intkz, {0, Unknown}}, + {X86::VFNMSUB213SDZr, {0, Unknown}}, + {X86::VFNMSUB213SDZr_Int, {0, Unknown}}, + {X86::VFNMSUB213SDZr_Intk, {0, Unknown}}, + {X86::VFNMSUB213SDZr_Intkz, {0, Unknown}}, + {X86::VFNMSUB213SDZrb_Int, {0, Unknown}}, + {X86::VFNMSUB213SDZrb_Intk, {0, Unknown}}, + {X86::VFNMSUB213SDZrb_Intkz, {0, Unknown}}, + {X86::VFNMSUB213SDm, {0, Unknown}}, + {X86::VFNMSUB213SDm_Int, {0, Unknown}}, + {X86::VFNMSUB213SDr, {0, Unknown}}, + {X86::VFNMSUB213SDr_Int, {0, Unknown}}, + {X86::VFNMSUB213SSZm, {0, Unknown}}, + {X86::VFNMSUB213SSZm_Int, {0, Unknown}}, + {X86::VFNMSUB213SSZm_Intk, {0, Unknown}}, + {X86::VFNMSUB213SSZm_Intkz, {0, Unknown}}, + {X86::VFNMSUB213SSZr, {0, Unknown}}, + {X86::VFNMSUB213SSZr_Int, {0, Unknown}}, + {X86::VFNMSUB213SSZr_Intk, {0, Unknown}}, + {X86::VFNMSUB213SSZr_Intkz, {0, Unknown}}, + {X86::VFNMSUB213SSZrb_Int, {0, Unknown}}, + {X86::VFNMSUB213SSZrb_Intk, {0, Unknown}}, + {X86::VFNMSUB213SSZrb_Intkz, {0, Unknown}}, + {X86::VFNMSUB213SSm, {0, Unknown}}, + {X86::VFNMSUB213SSm_Int, {0, Unknown}}, + {X86::VFNMSUB213SSr, {0, Unknown}}, + {X86::VFNMSUB213SSr_Int, {0, Unknown}}, + {X86::VFNMSUB231PDYm, {0, Unknown}}, + {X86::VFNMSUB231PDYr, {0, Unknown}}, + {X86::VFNMSUB231PDZ128m, {0, Unknown}}, + {X86::VFNMSUB231PDZ128mb, {0, Unknown}}, + {X86::VFNMSUB231PDZ128mbk, {0, Unknown}}, + {X86::VFNMSUB231PDZ128mbkz, {0, Unknown}}, + {X86::VFNMSUB231PDZ128mk, {0, Unknown}}, + {X86::VFNMSUB231PDZ128mkz, {0, Unknown}}, + {X86::VFNMSUB231PDZ128r, {0, Unknown}}, + {X86::VFNMSUB231PDZ128rk, {0, Unknown}}, + {X86::VFNMSUB231PDZ128rkz, {0, Unknown}}, + {X86::VFNMSUB231PDZ256m, {0, Unknown}}, + {X86::VFNMSUB231PDZ256mb, {0, Unknown}}, + {X86::VFNMSUB231PDZ256mbk, {0, Unknown}}, + {X86::VFNMSUB231PDZ256mbkz, {0, Unknown}}, + {X86::VFNMSUB231PDZ256mk, {0, Unknown}}, + {X86::VFNMSUB231PDZ256mkz, {0, Unknown}}, + {X86::VFNMSUB231PDZ256r, {0, Unknown}}, + {X86::VFNMSUB231PDZ256rk, {0, Unknown}}, + {X86::VFNMSUB231PDZ256rkz, {0, Unknown}}, + {X86::VFNMSUB231PDZm, {0, Unknown}}, + {X86::VFNMSUB231PDZmb, {0, Unknown}}, + {X86::VFNMSUB231PDZmbk, {0, Unknown}}, + {X86::VFNMSUB231PDZmbkz, {0, Unknown}}, + {X86::VFNMSUB231PDZmk, {0, Unknown}}, + {X86::VFNMSUB231PDZmkz, {0, Unknown}}, + {X86::VFNMSUB231PDZr, {0, Unknown}}, + {X86::VFNMSUB231PDZrb, {0, Unknown}}, + {X86::VFNMSUB231PDZrbk, {0, Unknown}}, + {X86::VFNMSUB231PDZrbkz, {0, Unknown}}, + {X86::VFNMSUB231PDZrk, {0, Unknown}}, + {X86::VFNMSUB231PDZrkz, {0, Unknown}}, + {X86::VFNMSUB231PDm, {0, Unknown}}, + {X86::VFNMSUB231PDr, {0, Unknown}}, + {X86::VFNMSUB231PSYm, {0, Unknown}}, + {X86::VFNMSUB231PSYr, {0, Unknown}}, + {X86::VFNMSUB231PSZ128m, {0, Unknown}}, + {X86::VFNMSUB231PSZ128mb, {0, Unknown}}, + {X86::VFNMSUB231PSZ128mbk, {0, Unknown}}, + {X86::VFNMSUB231PSZ128mbkz, {0, Unknown}}, + {X86::VFNMSUB231PSZ128mk, {0, Unknown}}, + {X86::VFNMSUB231PSZ128mkz, {0, Unknown}}, + {X86::VFNMSUB231PSZ128r, {0, Unknown}}, + {X86::VFNMSUB231PSZ128rk, {0, Unknown}}, + {X86::VFNMSUB231PSZ128rkz, {0, Unknown}}, + {X86::VFNMSUB231PSZ256m, {0, Unknown}}, + {X86::VFNMSUB231PSZ256mb, {0, Unknown}}, + {X86::VFNMSUB231PSZ256mbk, {0, Unknown}}, + {X86::VFNMSUB231PSZ256mbkz, {0, Unknown}}, + {X86::VFNMSUB231PSZ256mk, {0, Unknown}}, + {X86::VFNMSUB231PSZ256mkz, {0, Unknown}}, + {X86::VFNMSUB231PSZ256r, {0, Unknown}}, + {X86::VFNMSUB231PSZ256rk, {0, Unknown}}, + {X86::VFNMSUB231PSZ256rkz, {0, Unknown}}, + {X86::VFNMSUB231PSZm, {0, Unknown}}, + {X86::VFNMSUB231PSZmb, {0, Unknown}}, + {X86::VFNMSUB231PSZmbk, {0, Unknown}}, + {X86::VFNMSUB231PSZmbkz, {0, Unknown}}, + {X86::VFNMSUB231PSZmk, {0, Unknown}}, + {X86::VFNMSUB231PSZmkz, {0, Unknown}}, + {X86::VFNMSUB231PSZr, {0, Unknown}}, + {X86::VFNMSUB231PSZrb, {0, Unknown}}, + {X86::VFNMSUB231PSZrbk, {0, Unknown}}, + {X86::VFNMSUB231PSZrbkz, {0, Unknown}}, + {X86::VFNMSUB231PSZrk, {0, Unknown}}, + {X86::VFNMSUB231PSZrkz, {0, Unknown}}, + {X86::VFNMSUB231PSm, {0, Unknown}}, + {X86::VFNMSUB231PSr, {0, Unknown}}, + {X86::VFNMSUB231SDZm, {0, Unknown}}, + {X86::VFNMSUB231SDZm_Int, {0, Unknown}}, + {X86::VFNMSUB231SDZm_Intk, {0, Unknown}}, + {X86::VFNMSUB231SDZm_Intkz, {0, Unknown}}, + {X86::VFNMSUB231SDZr, {0, Unknown}}, + {X86::VFNMSUB231SDZr_Int, {0, Unknown}}, + {X86::VFNMSUB231SDZr_Intk, {0, Unknown}}, + {X86::VFNMSUB231SDZr_Intkz, {0, Unknown}}, + {X86::VFNMSUB231SDZrb_Int, {0, Unknown}}, + {X86::VFNMSUB231SDZrb_Intk, {0, Unknown}}, + {X86::VFNMSUB231SDZrb_Intkz, {0, Unknown}}, + {X86::VFNMSUB231SDm, {0, Unknown}}, + {X86::VFNMSUB231SDm_Int, {0, Unknown}}, + {X86::VFNMSUB231SDr, {0, Unknown}}, + {X86::VFNMSUB231SDr_Int, {0, Unknown}}, + {X86::VFNMSUB231SSZm, {0, Unknown}}, + {X86::VFNMSUB231SSZm_Int, {0, Unknown}}, + {X86::VFNMSUB231SSZm_Intk, {0, Unknown}}, + {X86::VFNMSUB231SSZm_Intkz, {0, Unknown}}, + {X86::VFNMSUB231SSZr, {0, Unknown}}, + {X86::VFNMSUB231SSZr_Int, {0, Unknown}}, + {X86::VFNMSUB231SSZr_Intk, {0, Unknown}}, + {X86::VFNMSUB231SSZr_Intkz, {0, Unknown}}, + {X86::VFNMSUB231SSZrb_Int, {0, Unknown}}, + {X86::VFNMSUB231SSZrb_Intk, {0, Unknown}}, + {X86::VFNMSUB231SSZrb_Intkz, {0, Unknown}}, + {X86::VFNMSUB231SSm, {0, Unknown}}, + {X86::VFNMSUB231SSm_Int, {0, Unknown}}, + {X86::VFNMSUB231SSr, {0, Unknown}}, + {X86::VFNMSUB231SSr_Int, {0, Unknown}}, + {X86::VFNMSUBPD4Ymr, {0, Unknown}}, + {X86::VFNMSUBPD4Yrm, {0, Unknown}}, + {X86::VFNMSUBPD4Yrr, {0, Unknown}}, + {X86::VFNMSUBPD4Yrr_REV, {0, Unknown}}, + {X86::VFNMSUBPD4mr, {0, Unknown}}, + {X86::VFNMSUBPD4rm, {0, Unknown}}, + {X86::VFNMSUBPD4rr, {0, Unknown}}, + {X86::VFNMSUBPD4rr_REV, {0, Unknown}}, + {X86::VFNMSUBPS4Ymr, {0, Unknown}}, + {X86::VFNMSUBPS4Yrm, {0, Unknown}}, + {X86::VFNMSUBPS4Yrr, {0, Unknown}}, + {X86::VFNMSUBPS4Yrr_REV, {0, Unknown}}, + {X86::VFNMSUBPS4mr, {0, Unknown}}, + {X86::VFNMSUBPS4rm, {0, Unknown}}, + {X86::VFNMSUBPS4rr, {0, Unknown}}, + {X86::VFNMSUBPS4rr_REV, {0, Unknown}}, + {X86::VFNMSUBSD4mr, {0, Unknown}}, + {X86::VFNMSUBSD4mr_Int, {0, Unknown}}, + {X86::VFNMSUBSD4rm, {0, Unknown}}, + {X86::VFNMSUBSD4rm_Int, {0, Unknown}}, + {X86::VFNMSUBSD4rr, {0, Unknown}}, + {X86::VFNMSUBSD4rr_Int, {0, Unknown}}, + {X86::VFNMSUBSD4rr_Int_REV, {0, Unknown}}, + {X86::VFNMSUBSD4rr_REV, {0, Unknown}}, + {X86::VFNMSUBSS4mr, {0, Unknown}}, + {X86::VFNMSUBSS4mr_Int, {0, Unknown}}, + {X86::VFNMSUBSS4rm, {0, Unknown}}, + {X86::VFNMSUBSS4rm_Int, {0, Unknown}}, + {X86::VFNMSUBSS4rr, {0, Unknown}}, + {X86::VFNMSUBSS4rr_Int, {0, Unknown}}, + {X86::VFNMSUBSS4rr_Int_REV, {0, Unknown}}, + {X86::VFNMSUBSS4rr_REV, {0, Unknown}}, + {X86::VFPCLASSPDZ128rm, {1, Unknown}}, + {X86::VFPCLASSPDZ128rmb, {1, Unknown}}, + {X86::VFPCLASSPDZ128rmbk, {1, Unknown}}, + {X86::VFPCLASSPDZ128rmk, {1, Unknown}}, + {X86::VFPCLASSPDZ128rr, {0, Unknown}}, + {X86::VFPCLASSPDZ128rrk, {0, Unknown}}, + {X86::VFPCLASSPDZ256rm, {0, Unknown}}, + {X86::VFPCLASSPDZ256rmb, {0, Unknown}}, + {X86::VFPCLASSPDZ256rmbk, {0, Unknown}}, + {X86::VFPCLASSPDZ256rmk, {0, Unknown}}, + {X86::VFPCLASSPDZ256rr, {0, Unknown}}, + {X86::VFPCLASSPDZ256rrk, {0, Unknown}}, + {X86::VFPCLASSPDZrm, {0, Unknown}}, + {X86::VFPCLASSPDZrmb, {0, Unknown}}, + {X86::VFPCLASSPDZrmbk, {0, Unknown}}, + {X86::VFPCLASSPDZrmk, {0, Unknown}}, + {X86::VFPCLASSPDZrr, {0, Unknown}}, + {X86::VFPCLASSPDZrrk, {0, Unknown}}, + {X86::VFPCLASSPSZ128rm, {1, Unknown}}, + {X86::VFPCLASSPSZ128rmb, {1, Unknown}}, + {X86::VFPCLASSPSZ128rmbk, {1, Unknown}}, + {X86::VFPCLASSPSZ128rmk, {1, Unknown}}, + {X86::VFPCLASSPSZ128rr, {0, Unknown}}, + {X86::VFPCLASSPSZ128rrk, {0, Unknown}}, + {X86::VFPCLASSPSZ256rm, {0, Unknown}}, + {X86::VFPCLASSPSZ256rmb, {0, Unknown}}, + {X86::VFPCLASSPSZ256rmbk, {0, Unknown}}, + {X86::VFPCLASSPSZ256rmk, {0, Unknown}}, + {X86::VFPCLASSPSZ256rr, {0, Unknown}}, + {X86::VFPCLASSPSZ256rrk, {0, Unknown}}, + {X86::VFPCLASSPSZrm, {0, Unknown}}, + {X86::VFPCLASSPSZrmb, {0, Unknown}}, + {X86::VFPCLASSPSZrmbk, {0, Unknown}}, + {X86::VFPCLASSPSZrmk, {0, Unknown}}, + {X86::VFPCLASSPSZrr, {0, Unknown}}, + {X86::VFPCLASSPSZrrk, {0, Unknown}}, + {X86::VFRCZPDYrm, {0, Unknown}}, + {X86::VFRCZPDYrr, {0, Unknown}}, + {X86::VFRCZPDrm, {0, Unknown}}, + {X86::VFRCZPDrr, {0, Unknown}}, + {X86::VFRCZPSYrm, {0, Unknown}}, + {X86::VFRCZPSYrr, {0, Unknown}}, + {X86::VFRCZPSrm, {0, Unknown}}, + {X86::VFRCZPSrr, {0, Unknown}}, + {X86::VFRCZSDrm, {0, Unknown}}, + {X86::VFRCZSDrr, {0, Unknown}}, + {X86::VFRCZSSrm, {0, Unknown}}, + {X86::VFRCZSSrr, {0, Unknown}}, + {X86::VGATHERDPDYrm, {0, Unknown}}, + {X86::VGATHERDPDZ128rm, {1, Unknown}}, + {X86::VGATHERDPDZ256rm, {0, Unknown}}, + {X86::VGATHERDPDZrm, {0, Unknown}}, + {X86::VGATHERDPDrm, {0, Unknown}}, + {X86::VGATHERDPSYrm, {0, Unknown}}, + {X86::VGATHERDPSZ128rm, {1, Unknown}}, + {X86::VGATHERDPSZ256rm, {0, Unknown}}, + {X86::VGATHERDPSZrm, {0, Unknown}}, + {X86::VGATHERDPSrm, {0, Unknown}}, + {X86::VGATHERPF0DPDm, {0, Unknown}}, + {X86::VGATHERPF0DPSm, {0, Unknown}}, + {X86::VGATHERPF0QPDm, {0, Unknown}}, + {X86::VGATHERPF0QPSm, {0, Unknown}}, + {X86::VGATHERPF1DPDm, {0, Unknown}}, + {X86::VGATHERPF1DPSm, {0, Unknown}}, + {X86::VGATHERPF1QPDm, {0, Unknown}}, + {X86::VGATHERPF1QPSm, {0, Unknown}}, + {X86::VGATHERQPDYrm, {0, Unknown}}, + {X86::VGATHERQPDZ128rm, {1, Unknown}}, + {X86::VGATHERQPDZ256rm, {0, Unknown}}, + {X86::VGATHERQPDZrm, {0, Unknown}}, + {X86::VGATHERQPDrm, {0, Unknown}}, + {X86::VGATHERQPSYrm, {0, Unknown}}, + {X86::VGATHERQPSZ128rm, {1, Unknown}}, + {X86::VGATHERQPSZ256rm, {0, Unknown}}, + {X86::VGATHERQPSZrm, {0, Unknown}}, + {X86::VGATHERQPSrm, {0, Unknown}}, + {X86::VGF2P8AFFINEINVQBYrmi, {0, Unknown}}, + {X86::VGF2P8AFFINEINVQBYrri, {0, Unknown}}, + {X86::VGF2P8AFFINEINVQBZ128rmbi, {1, Unknown}}, + {X86::VGF2P8AFFINEINVQBZ128rmbik, {1, Unknown}}, + {X86::VGF2P8AFFINEINVQBZ128rmbikz, {1, Unknown}}, + {X86::VGF2P8AFFINEINVQBZ128rmi, {1, Unknown}}, + {X86::VGF2P8AFFINEINVQBZ128rmik, {1, Unknown}}, + {X86::VGF2P8AFFINEINVQBZ128rmikz, {1, Unknown}}, + {X86::VGF2P8AFFINEINVQBZ128rri, {0, Unknown}}, + {X86::VGF2P8AFFINEINVQBZ128rrik, {0, Unknown}}, + {X86::VGF2P8AFFINEINVQBZ128rrikz, {0, Unknown}}, + {X86::VGF2P8AFFINEINVQBZ256rmbi, {0, Unknown}}, + {X86::VGF2P8AFFINEINVQBZ256rmbik, {0, Unknown}}, + {X86::VGF2P8AFFINEINVQBZ256rmbikz, {0, Unknown}}, + {X86::VGF2P8AFFINEINVQBZ256rmi, {0, Unknown}}, + {X86::VGF2P8AFFINEINVQBZ256rmik, {0, Unknown}}, + {X86::VGF2P8AFFINEINVQBZ256rmikz, {0, Unknown}}, + {X86::VGF2P8AFFINEINVQBZ256rri, {0, Unknown}}, + {X86::VGF2P8AFFINEINVQBZ256rrik, {0, Unknown}}, + {X86::VGF2P8AFFINEINVQBZ256rrikz, {0, Unknown}}, + {X86::VGF2P8AFFINEINVQBZrmbi, {0, Unknown}}, + {X86::VGF2P8AFFINEINVQBZrmbik, {0, Unknown}}, + {X86::VGF2P8AFFINEINVQBZrmbikz, {0, Unknown}}, + {X86::VGF2P8AFFINEINVQBZrmi, {0, Unknown}}, + {X86::VGF2P8AFFINEINVQBZrmik, {0, Unknown}}, + {X86::VGF2P8AFFINEINVQBZrmikz, {0, Unknown}}, + {X86::VGF2P8AFFINEINVQBZrri, {0, Unknown}}, + {X86::VGF2P8AFFINEINVQBZrrik, {0, Unknown}}, + {X86::VGF2P8AFFINEINVQBZrrikz, {0, Unknown}}, + {X86::VGF2P8AFFINEINVQBrmi, {0, Unknown}}, + {X86::VGF2P8AFFINEINVQBrri, {0, Unknown}}, + {X86::VGF2P8AFFINEQBYrmi, {0, Unknown}}, + {X86::VGF2P8AFFINEQBYrri, {0, Unknown}}, + {X86::VGF2P8AFFINEQBZ128rmbi, {1, Unknown}}, + {X86::VGF2P8AFFINEQBZ128rmbik, {1, Unknown}}, + {X86::VGF2P8AFFINEQBZ128rmbikz, {1, Unknown}}, + {X86::VGF2P8AFFINEQBZ128rmi, {1, Unknown}}, + {X86::VGF2P8AFFINEQBZ128rmik, {1, Unknown}}, + {X86::VGF2P8AFFINEQBZ128rmikz, {1, Unknown}}, + {X86::VGF2P8AFFINEQBZ128rri, {0, Unknown}}, + {X86::VGF2P8AFFINEQBZ128rrik, {0, Unknown}}, + {X86::VGF2P8AFFINEQBZ128rrikz, {0, Unknown}}, + {X86::VGF2P8AFFINEQBZ256rmbi, {0, Unknown}}, + {X86::VGF2P8AFFINEQBZ256rmbik, {0, Unknown}}, + {X86::VGF2P8AFFINEQBZ256rmbikz, {0, Unknown}}, + {X86::VGF2P8AFFINEQBZ256rmi, {0, Unknown}}, + {X86::VGF2P8AFFINEQBZ256rmik, {0, Unknown}}, + {X86::VGF2P8AFFINEQBZ256rmikz, {0, Unknown}}, + {X86::VGF2P8AFFINEQBZ256rri, {0, Unknown}}, + {X86::VGF2P8AFFINEQBZ256rrik, {0, Unknown}}, + {X86::VGF2P8AFFINEQBZ256rrikz, {0, Unknown}}, + {X86::VGF2P8AFFINEQBZrmbi, {0, Unknown}}, + {X86::VGF2P8AFFINEQBZrmbik, {0, Unknown}}, + {X86::VGF2P8AFFINEQBZrmbikz, {0, Unknown}}, + {X86::VGF2P8AFFINEQBZrmi, {0, Unknown}}, + {X86::VGF2P8AFFINEQBZrmik, {0, Unknown}}, + {X86::VGF2P8AFFINEQBZrmikz, {0, Unknown}}, + {X86::VGF2P8AFFINEQBZrri, {0, Unknown}}, + {X86::VGF2P8AFFINEQBZrrik, {0, Unknown}}, + {X86::VGF2P8AFFINEQBZrrikz, {0, Unknown}}, + {X86::VGF2P8AFFINEQBrmi, {0, Unknown}}, + {X86::VGF2P8AFFINEQBrri, {0, Unknown}}, + {X86::VGF2P8MULBYrm, {0, Unknown}}, + {X86::VGF2P8MULBYrr, {0, Unknown}}, + {X86::VGF2P8MULBZ128rm, {1, Unknown}}, + {X86::VGF2P8MULBZ128rmk, {1, Unknown}}, + {X86::VGF2P8MULBZ128rmkz, {1, Unknown}}, + {X86::VGF2P8MULBZ128rr, {0, Unknown}}, + {X86::VGF2P8MULBZ128rrk, {0, Unknown}}, + {X86::VGF2P8MULBZ128rrkz, {0, Unknown}}, + {X86::VGF2P8MULBZ256rm, {0, Unknown}}, + {X86::VGF2P8MULBZ256rmk, {0, Unknown}}, + {X86::VGF2P8MULBZ256rmkz, {0, Unknown}}, + {X86::VGF2P8MULBZ256rr, {0, Unknown}}, + {X86::VGF2P8MULBZ256rrk, {0, Unknown}}, + {X86::VGF2P8MULBZ256rrkz, {0, Unknown}}, + {X86::VGF2P8MULBZrm, {0, Unknown}}, + {X86::VGF2P8MULBZrmk, {0, Unknown}}, + {X86::VGF2P8MULBZrmkz, {0, Unknown}}, + {X86::VGF2P8MULBZrr, {0, Unknown}}, + {X86::VGF2P8MULBZrrk, {0, Unknown}}, + {X86::VGF2P8MULBZrrkz, {0, Unknown}}, + {X86::VGF2P8MULBrm, {0, Unknown}}, + {X86::VGF2P8MULBrr, {0, Unknown}}, + {X86::VHADDPDYrm, {0, Unknown}}, + {X86::VHADDPDYrr, {0, Unknown}}, + {X86::VHADDPDrm, {0, Unknown}}, + {X86::VHADDPDrr, {0, Unknown}}, + {X86::VHADDPSYrm, {0, Unknown}}, + {X86::VHADDPSYrr, {0, Unknown}}, + {X86::VHADDPSrm, {0, Unknown}}, + {X86::VHADDPSrr, {0, Unknown}}, + {X86::VHSUBPDYrm, {0, Unknown}}, + {X86::VHSUBPDYrr, {0, Unknown}}, + {X86::VHSUBPDrm, {0, Unknown}}, + {X86::VHSUBPDrr, {0, Unknown}}, + {X86::VHSUBPSYrm, {0, Unknown}}, + {X86::VHSUBPSYrr, {0, Unknown}}, + {X86::VHSUBPSrm, {0, Unknown}}, + {X86::VHSUBPSrr, {0, Unknown}}, + {X86::VINSERTF128rm, {1, Unknown}}, + {X86::VINSERTF128rr, {0, Unknown}}, + {X86::VINSERTF32x4Z256rm, {0, Unknown}}, + {X86::VINSERTF32x4Z256rmk, {0, Unknown}}, + {X86::VINSERTF32x4Z256rmkz, {0, Unknown}}, + {X86::VINSERTF32x4Z256rr, {0, Unknown}}, + {X86::VINSERTF32x4Z256rrk, {0, Unknown}}, + {X86::VINSERTF32x4Z256rrkz, {0, Unknown}}, + {X86::VINSERTF32x4Zrm, {0, Unknown}}, + {X86::VINSERTF32x4Zrmk, {0, Unknown}}, + {X86::VINSERTF32x4Zrmkz, {0, Unknown}}, + {X86::VINSERTF32x4Zrr, {0, Unknown}}, + {X86::VINSERTF32x4Zrrk, {0, Unknown}}, + {X86::VINSERTF32x4Zrrkz, {0, Unknown}}, + {X86::VINSERTF32x8Zrm, {0, Unknown}}, + {X86::VINSERTF32x8Zrmk, {0, Unknown}}, + {X86::VINSERTF32x8Zrmkz, {0, Unknown}}, + {X86::VINSERTF32x8Zrr, {0, Unknown}}, + {X86::VINSERTF32x8Zrrk, {0, Unknown}}, + {X86::VINSERTF32x8Zrrkz, {0, Unknown}}, + {X86::VINSERTF64x2Z256rm, {0, Unknown}}, + {X86::VINSERTF64x2Z256rmk, {0, Unknown}}, + {X86::VINSERTF64x2Z256rmkz, {0, Unknown}}, + {X86::VINSERTF64x2Z256rr, {0, Unknown}}, + {X86::VINSERTF64x2Z256rrk, {0, Unknown}}, + {X86::VINSERTF64x2Z256rrkz, {0, Unknown}}, + {X86::VINSERTF64x2Zrm, {0, Unknown}}, + {X86::VINSERTF64x2Zrmk, {0, Unknown}}, + {X86::VINSERTF64x2Zrmkz, {0, Unknown}}, + {X86::VINSERTF64x2Zrr, {0, Unknown}}, + {X86::VINSERTF64x2Zrrk, {0, Unknown}}, + {X86::VINSERTF64x2Zrrkz, {0, Unknown}}, + {X86::VINSERTF64x4Zrm, {0, Unknown}}, + {X86::VINSERTF64x4Zrmk, {0, Unknown}}, + {X86::VINSERTF64x4Zrmkz, {0, Unknown}}, + {X86::VINSERTF64x4Zrr, {0, Unknown}}, + {X86::VINSERTF64x4Zrrk, {0, Unknown}}, + {X86::VINSERTF64x4Zrrkz, {0, Unknown}}, + {X86::VINSERTI128rm, {1, Unknown}}, + {X86::VINSERTI128rr, {0, Unknown}}, + {X86::VINSERTI32x4Z256rm, {0, Unknown}}, + {X86::VINSERTI32x4Z256rmk, {0, Unknown}}, + {X86::VINSERTI32x4Z256rmkz, {0, Unknown}}, + {X86::VINSERTI32x4Z256rr, {0, Unknown}}, + {X86::VINSERTI32x4Z256rrk, {0, Unknown}}, + {X86::VINSERTI32x4Z256rrkz, {0, Unknown}}, + {X86::VINSERTI32x4Zrm, {0, Unknown}}, + {X86::VINSERTI32x4Zrmk, {0, Unknown}}, + {X86::VINSERTI32x4Zrmkz, {0, Unknown}}, + {X86::VINSERTI32x4Zrr, {0, Unknown}}, + {X86::VINSERTI32x4Zrrk, {0, Unknown}}, + {X86::VINSERTI32x4Zrrkz, {0, Unknown}}, + {X86::VINSERTI32x8Zrm, {0, Unknown}}, + {X86::VINSERTI32x8Zrmk, {0, Unknown}}, + {X86::VINSERTI32x8Zrmkz, {0, Unknown}}, + {X86::VINSERTI32x8Zrr, {0, Unknown}}, + {X86::VINSERTI32x8Zrrk, {0, Unknown}}, + {X86::VINSERTI32x8Zrrkz, {0, Unknown}}, + {X86::VINSERTI64x2Z256rm, {0, Unknown}}, + {X86::VINSERTI64x2Z256rmk, {0, Unknown}}, + {X86::VINSERTI64x2Z256rmkz, {0, Unknown}}, + {X86::VINSERTI64x2Z256rr, {0, Unknown}}, + {X86::VINSERTI64x2Z256rrk, {0, Unknown}}, + {X86::VINSERTI64x2Z256rrkz, {0, Unknown}}, + {X86::VINSERTI64x2Zrm, {0, Unknown}}, + {X86::VINSERTI64x2Zrmk, {0, Unknown}}, + {X86::VINSERTI64x2Zrmkz, {0, Unknown}}, + {X86::VINSERTI64x2Zrr, {0, Unknown}}, + {X86::VINSERTI64x2Zrrk, {0, Unknown}}, + {X86::VINSERTI64x2Zrrkz, {0, Unknown}}, + {X86::VINSERTI64x4Zrm, {0, Unknown}}, + {X86::VINSERTI64x4Zrmk, {0, Unknown}}, + {X86::VINSERTI64x4Zrmkz, {0, Unknown}}, + {X86::VINSERTI64x4Zrr, {0, Unknown}}, + {X86::VINSERTI64x4Zrrk, {0, Unknown}}, + {X86::VINSERTI64x4Zrrkz, {0, Unknown}}, + {X86::VINSERTPSZrm, {0, Unknown}}, + {X86::VINSERTPSZrr, {0, Unknown}}, + {X86::VINSERTPSrm, {0, Unknown}}, + {X86::VINSERTPSrr, {0, Unknown}}, + {X86::VLDDQUYrm, {0, Unknown}}, + {X86::VLDDQUrm, {0, Unknown}}, + {X86::VLDMXCSR, {0, Unknown}}, + {X86::VMASKMOVDQU, {0, Unknown}}, + {X86::VMASKMOVDQU64, {0, Unknown}}, + {X86::VMASKMOVPDYmr, {0, Unknown}}, + {X86::VMASKMOVPDYrm, {0, Unknown}}, + {X86::VMASKMOVPDmr, {0, Unknown}}, + {X86::VMASKMOVPDrm, {0, Unknown}}, + {X86::VMASKMOVPSYmr, {0, Unknown}}, + {X86::VMASKMOVPSYrm, {0, Unknown}}, + {X86::VMASKMOVPSmr, {0, Unknown}}, + {X86::VMASKMOVPSrm, {0, Unknown}}, + {X86::VMAXCPDYrm, {0, Unknown}}, + {X86::VMAXCPDYrr, {0, Unknown}}, + {X86::VMAXCPDZ128rm, {1, Unknown}}, + {X86::VMAXCPDZ128rmb, {1, Unknown}}, + {X86::VMAXCPDZ128rmbk, {1, Unknown}}, + {X86::VMAXCPDZ128rmbkz, {1, Unknown}}, + {X86::VMAXCPDZ128rmk, {1, Unknown}}, + {X86::VMAXCPDZ128rmkz, {1, Unknown}}, + {X86::VMAXCPDZ128rr, {0, Unknown}}, + {X86::VMAXCPDZ128rrk, {0, Unknown}}, + {X86::VMAXCPDZ128rrkz, {0, Unknown}}, + {X86::VMAXCPDZ256rm, {0, Unknown}}, + {X86::VMAXCPDZ256rmb, {0, Unknown}}, + {X86::VMAXCPDZ256rmbk, {0, Unknown}}, + {X86::VMAXCPDZ256rmbkz, {0, Unknown}}, + {X86::VMAXCPDZ256rmk, {0, Unknown}}, + {X86::VMAXCPDZ256rmkz, {0, Unknown}}, + {X86::VMAXCPDZ256rr, {0, Unknown}}, + {X86::VMAXCPDZ256rrk, {0, Unknown}}, + {X86::VMAXCPDZ256rrkz, {0, Unknown}}, + {X86::VMAXCPDZrm, {0, Unknown}}, + {X86::VMAXCPDZrmb, {0, Unknown}}, + {X86::VMAXCPDZrmbk, {0, Unknown}}, + {X86::VMAXCPDZrmbkz, {0, Unknown}}, + {X86::VMAXCPDZrmk, {0, Unknown}}, + {X86::VMAXCPDZrmkz, {0, Unknown}}, + {X86::VMAXCPDZrr, {0, Unknown}}, + {X86::VMAXCPDZrrk, {0, Unknown}}, + {X86::VMAXCPDZrrkz, {0, Unknown}}, + {X86::VMAXCPDrm, {0, Unknown}}, + {X86::VMAXCPDrr, {0, Unknown}}, + {X86::VMAXCPSYrm, {0, Unknown}}, + {X86::VMAXCPSYrr, {0, Unknown}}, + {X86::VMAXCPSZ128rm, {1, Unknown}}, + {X86::VMAXCPSZ128rmb, {1, Unknown}}, + {X86::VMAXCPSZ128rmbk, {1, Unknown}}, + {X86::VMAXCPSZ128rmbkz, {1, Unknown}}, + {X86::VMAXCPSZ128rmk, {1, Unknown}}, + {X86::VMAXCPSZ128rmkz, {1, Unknown}}, + {X86::VMAXCPSZ128rr, {0, Unknown}}, + {X86::VMAXCPSZ128rrk, {0, Unknown}}, + {X86::VMAXCPSZ128rrkz, {0, Unknown}}, + {X86::VMAXCPSZ256rm, {0, Unknown}}, + {X86::VMAXCPSZ256rmb, {0, Unknown}}, + {X86::VMAXCPSZ256rmbk, {0, Unknown}}, + {X86::VMAXCPSZ256rmbkz, {0, Unknown}}, + {X86::VMAXCPSZ256rmk, {0, Unknown}}, + {X86::VMAXCPSZ256rmkz, {0, Unknown}}, + {X86::VMAXCPSZ256rr, {0, Unknown}}, + {X86::VMAXCPSZ256rrk, {0, Unknown}}, + {X86::VMAXCPSZ256rrkz, {0, Unknown}}, + {X86::VMAXCPSZrm, {0, Unknown}}, + {X86::VMAXCPSZrmb, {0, Unknown}}, + {X86::VMAXCPSZrmbk, {0, Unknown}}, + {X86::VMAXCPSZrmbkz, {0, Unknown}}, + {X86::VMAXCPSZrmk, {0, Unknown}}, + {X86::VMAXCPSZrmkz, {0, Unknown}}, + {X86::VMAXCPSZrr, {0, Unknown}}, + {X86::VMAXCPSZrrk, {0, Unknown}}, + {X86::VMAXCPSZrrkz, {0, Unknown}}, + {X86::VMAXCPSrm, {0, Unknown}}, + {X86::VMAXCPSrr, {0, Unknown}}, + {X86::VMAXCSDZrm, {0, Unknown}}, + {X86::VMAXCSDZrr, {0, Unknown}}, + {X86::VMAXCSDrm, {0, Unknown}}, + {X86::VMAXCSDrr, {0, Unknown}}, + {X86::VMAXCSSZrm, {0, Unknown}}, + {X86::VMAXCSSZrr, {0, Unknown}}, + {X86::VMAXCSSrm, {0, Unknown}}, + {X86::VMAXCSSrr, {0, Unknown}}, + {X86::VMAXPDYrm, {0, Unknown}}, + {X86::VMAXPDYrr, {0, Unknown}}, + {X86::VMAXPDZ128rm, {1, Unknown}}, + {X86::VMAXPDZ128rmb, {1, Unknown}}, + {X86::VMAXPDZ128rmbk, {1, Unknown}}, + {X86::VMAXPDZ128rmbkz, {1, Unknown}}, + {X86::VMAXPDZ128rmk, {1, Unknown}}, + {X86::VMAXPDZ128rmkz, {1, Unknown}}, + {X86::VMAXPDZ128rr, {0, Unknown}}, + {X86::VMAXPDZ128rrk, {0, Unknown}}, + {X86::VMAXPDZ128rrkz, {0, Unknown}}, + {X86::VMAXPDZ256rm, {0, Unknown}}, + {X86::VMAXPDZ256rmb, {0, Unknown}}, + {X86::VMAXPDZ256rmbk, {0, Unknown}}, + {X86::VMAXPDZ256rmbkz, {0, Unknown}}, + {X86::VMAXPDZ256rmk, {0, Unknown}}, + {X86::VMAXPDZ256rmkz, {0, Unknown}}, + {X86::VMAXPDZ256rr, {0, Unknown}}, + {X86::VMAXPDZ256rrk, {0, Unknown}}, + {X86::VMAXPDZ256rrkz, {0, Unknown}}, + {X86::VMAXPDZrm, {0, Unknown}}, + {X86::VMAXPDZrmb, {0, Unknown}}, + {X86::VMAXPDZrmbk, {0, Unknown}}, + {X86::VMAXPDZrmbkz, {0, Unknown}}, + {X86::VMAXPDZrmk, {0, Unknown}}, + {X86::VMAXPDZrmkz, {0, Unknown}}, + {X86::VMAXPDZrr, {0, Unknown}}, + {X86::VMAXPDZrrb, {0, Unknown}}, + {X86::VMAXPDZrrbk, {0, Unknown}}, + {X86::VMAXPDZrrbkz, {0, Unknown}}, + {X86::VMAXPDZrrk, {0, Unknown}}, + {X86::VMAXPDZrrkz, {0, Unknown}}, + {X86::VMAXPDrm, {0, Unknown}}, + {X86::VMAXPDrr, {0, Unknown}}, + {X86::VMAXPSYrm, {0, Unknown}}, + {X86::VMAXPSYrr, {0, Unknown}}, + {X86::VMAXPSZ128rm, {1, Unknown}}, + {X86::VMAXPSZ128rmb, {1, Unknown}}, + {X86::VMAXPSZ128rmbk, {1, Unknown}}, + {X86::VMAXPSZ128rmbkz, {1, Unknown}}, + {X86::VMAXPSZ128rmk, {1, Unknown}}, + {X86::VMAXPSZ128rmkz, {1, Unknown}}, + {X86::VMAXPSZ128rr, {0, Unknown}}, + {X86::VMAXPSZ128rrk, {0, Unknown}}, + {X86::VMAXPSZ128rrkz, {0, Unknown}}, + {X86::VMAXPSZ256rm, {0, Unknown}}, + {X86::VMAXPSZ256rmb, {0, Unknown}}, + {X86::VMAXPSZ256rmbk, {0, Unknown}}, + {X86::VMAXPSZ256rmbkz, {0, Unknown}}, + {X86::VMAXPSZ256rmk, {0, Unknown}}, + {X86::VMAXPSZ256rmkz, {0, Unknown}}, + {X86::VMAXPSZ256rr, {0, Unknown}}, + {X86::VMAXPSZ256rrk, {0, Unknown}}, + {X86::VMAXPSZ256rrkz, {0, Unknown}}, + {X86::VMAXPSZrm, {0, Unknown}}, + {X86::VMAXPSZrmb, {0, Unknown}}, + {X86::VMAXPSZrmbk, {0, Unknown}}, + {X86::VMAXPSZrmbkz, {0, Unknown}}, + {X86::VMAXPSZrmk, {0, Unknown}}, + {X86::VMAXPSZrmkz, {0, Unknown}}, + {X86::VMAXPSZrr, {0, Unknown}}, + {X86::VMAXPSZrrb, {0, Unknown}}, + {X86::VMAXPSZrrbk, {0, Unknown}}, + {X86::VMAXPSZrrbkz, {0, Unknown}}, + {X86::VMAXPSZrrk, {0, Unknown}}, + {X86::VMAXPSZrrkz, {0, Unknown}}, + {X86::VMAXPSrm, {0, Unknown}}, + {X86::VMAXPSrr, {0, Unknown}}, + {X86::VMAXSDZrm, {0, Unknown}}, + {X86::VMAXSDZrm_Int, {0, Unknown}}, + {X86::VMAXSDZrm_Intk, {0, Unknown}}, + {X86::VMAXSDZrm_Intkz, {0, Unknown}}, + {X86::VMAXSDZrr, {0, Unknown}}, + {X86::VMAXSDZrr_Int, {0, Unknown}}, + {X86::VMAXSDZrr_Intk, {0, Unknown}}, + {X86::VMAXSDZrr_Intkz, {0, Unknown}}, + {X86::VMAXSDZrrb_Int, {0, Unknown}}, + {X86::VMAXSDZrrb_Intk, {0, Unknown}}, + {X86::VMAXSDZrrb_Intkz, {0, Unknown}}, + {X86::VMAXSDrm, {0, Unknown}}, + {X86::VMAXSDrm_Int, {0, Unknown}}, + {X86::VMAXSDrr, {0, Unknown}}, + {X86::VMAXSDrr_Int, {0, Unknown}}, + {X86::VMAXSSZrm, {0, Unknown}}, + {X86::VMAXSSZrm_Int, {0, Unknown}}, + {X86::VMAXSSZrm_Intk, {0, Unknown}}, + {X86::VMAXSSZrm_Intkz, {0, Unknown}}, + {X86::VMAXSSZrr, {0, Unknown}}, + {X86::VMAXSSZrr_Int, {0, Unknown}}, + {X86::VMAXSSZrr_Intk, {0, Unknown}}, + {X86::VMAXSSZrr_Intkz, {0, Unknown}}, + {X86::VMAXSSZrrb_Int, {0, Unknown}}, + {X86::VMAXSSZrrb_Intk, {0, Unknown}}, + {X86::VMAXSSZrrb_Intkz, {0, Unknown}}, + {X86::VMAXSSrm, {0, Unknown}}, + {X86::VMAXSSrm_Int, {0, Unknown}}, + {X86::VMAXSSrr, {0, Unknown}}, + {X86::VMAXSSrr_Int, {0, Unknown}}, + {X86::VMCALL, {0, Unknown}}, + {X86::VMCLEARm, {0, Unknown}}, + {X86::VMFUNC, {0, Unknown}}, + {X86::VMINCPDYrm, {0, Unknown}}, + {X86::VMINCPDYrr, {0, Unknown}}, + {X86::VMINCPDZ128rm, {1, Unknown}}, + {X86::VMINCPDZ128rmb, {1, Unknown}}, + {X86::VMINCPDZ128rmbk, {1, Unknown}}, + {X86::VMINCPDZ128rmbkz, {1, Unknown}}, + {X86::VMINCPDZ128rmk, {1, Unknown}}, + {X86::VMINCPDZ128rmkz, {1, Unknown}}, + {X86::VMINCPDZ128rr, {0, Unknown}}, + {X86::VMINCPDZ128rrk, {0, Unknown}}, + {X86::VMINCPDZ128rrkz, {0, Unknown}}, + {X86::VMINCPDZ256rm, {0, Unknown}}, + {X86::VMINCPDZ256rmb, {0, Unknown}}, + {X86::VMINCPDZ256rmbk, {0, Unknown}}, + {X86::VMINCPDZ256rmbkz, {0, Unknown}}, + {X86::VMINCPDZ256rmk, {0, Unknown}}, + {X86::VMINCPDZ256rmkz, {0, Unknown}}, + {X86::VMINCPDZ256rr, {0, Unknown}}, + {X86::VMINCPDZ256rrk, {0, Unknown}}, + {X86::VMINCPDZ256rrkz, {0, Unknown}}, + {X86::VMINCPDZrm, {0, Unknown}}, + {X86::VMINCPDZrmb, {0, Unknown}}, + {X86::VMINCPDZrmbk, {0, Unknown}}, + {X86::VMINCPDZrmbkz, {0, Unknown}}, + {X86::VMINCPDZrmk, {0, Unknown}}, + {X86::VMINCPDZrmkz, {0, Unknown}}, + {X86::VMINCPDZrr, {0, Unknown}}, + {X86::VMINCPDZrrk, {0, Unknown}}, + {X86::VMINCPDZrrkz, {0, Unknown}}, + {X86::VMINCPDrm, {0, Unknown}}, + {X86::VMINCPDrr, {0, Unknown}}, + {X86::VMINCPSYrm, {0, Unknown}}, + {X86::VMINCPSYrr, {0, Unknown}}, + {X86::VMINCPSZ128rm, {1, Unknown}}, + {X86::VMINCPSZ128rmb, {1, Unknown}}, + {X86::VMINCPSZ128rmbk, {1, Unknown}}, + {X86::VMINCPSZ128rmbkz, {1, Unknown}}, + {X86::VMINCPSZ128rmk, {1, Unknown}}, + {X86::VMINCPSZ128rmkz, {1, Unknown}}, + {X86::VMINCPSZ128rr, {0, Unknown}}, + {X86::VMINCPSZ128rrk, {0, Unknown}}, + {X86::VMINCPSZ128rrkz, {0, Unknown}}, + {X86::VMINCPSZ256rm, {0, Unknown}}, + {X86::VMINCPSZ256rmb, {0, Unknown}}, + {X86::VMINCPSZ256rmbk, {0, Unknown}}, + {X86::VMINCPSZ256rmbkz, {0, Unknown}}, + {X86::VMINCPSZ256rmk, {0, Unknown}}, + {X86::VMINCPSZ256rmkz, {0, Unknown}}, + {X86::VMINCPSZ256rr, {0, Unknown}}, + {X86::VMINCPSZ256rrk, {0, Unknown}}, + {X86::VMINCPSZ256rrkz, {0, Unknown}}, + {X86::VMINCPSZrm, {0, Unknown}}, + {X86::VMINCPSZrmb, {0, Unknown}}, + {X86::VMINCPSZrmbk, {0, Unknown}}, + {X86::VMINCPSZrmbkz, {0, Unknown}}, + {X86::VMINCPSZrmk, {0, Unknown}}, + {X86::VMINCPSZrmkz, {0, Unknown}}, + {X86::VMINCPSZrr, {0, Unknown}}, + {X86::VMINCPSZrrk, {0, Unknown}}, + {X86::VMINCPSZrrkz, {0, Unknown}}, + {X86::VMINCPSrm, {0, Unknown}}, + {X86::VMINCPSrr, {0, Unknown}}, + {X86::VMINCSDZrm, {0, Unknown}}, + {X86::VMINCSDZrr, {0, Unknown}}, + {X86::VMINCSDrm, {0, Unknown}}, + {X86::VMINCSDrr, {0, Unknown}}, + {X86::VMINCSSZrm, {0, Unknown}}, + {X86::VMINCSSZrr, {0, Unknown}}, + {X86::VMINCSSrm, {0, Unknown}}, + {X86::VMINCSSrr, {0, Unknown}}, + {X86::VMINPDYrm, {0, Unknown}}, + {X86::VMINPDYrr, {0, Unknown}}, + {X86::VMINPDZ128rm, {1, Unknown}}, + {X86::VMINPDZ128rmb, {1, Unknown}}, + {X86::VMINPDZ128rmbk, {1, Unknown}}, + {X86::VMINPDZ128rmbkz, {1, Unknown}}, + {X86::VMINPDZ128rmk, {1, Unknown}}, + {X86::VMINPDZ128rmkz, {1, Unknown}}, + {X86::VMINPDZ128rr, {0, Unknown}}, + {X86::VMINPDZ128rrk, {0, Unknown}}, + {X86::VMINPDZ128rrkz, {0, Unknown}}, + {X86::VMINPDZ256rm, {0, Unknown}}, + {X86::VMINPDZ256rmb, {0, Unknown}}, + {X86::VMINPDZ256rmbk, {0, Unknown}}, + {X86::VMINPDZ256rmbkz, {0, Unknown}}, + {X86::VMINPDZ256rmk, {0, Unknown}}, + {X86::VMINPDZ256rmkz, {0, Unknown}}, + {X86::VMINPDZ256rr, {0, Unknown}}, + {X86::VMINPDZ256rrk, {0, Unknown}}, + {X86::VMINPDZ256rrkz, {0, Unknown}}, + {X86::VMINPDZrm, {0, Unknown}}, + {X86::VMINPDZrmb, {0, Unknown}}, + {X86::VMINPDZrmbk, {0, Unknown}}, + {X86::VMINPDZrmbkz, {0, Unknown}}, + {X86::VMINPDZrmk, {0, Unknown}}, + {X86::VMINPDZrmkz, {0, Unknown}}, + {X86::VMINPDZrr, {0, Unknown}}, + {X86::VMINPDZrrb, {0, Unknown}}, + {X86::VMINPDZrrbk, {0, Unknown}}, + {X86::VMINPDZrrbkz, {0, Unknown}}, + {X86::VMINPDZrrk, {0, Unknown}}, + {X86::VMINPDZrrkz, {0, Unknown}}, + {X86::VMINPDrm, {0, Unknown}}, + {X86::VMINPDrr, {0, Unknown}}, + {X86::VMINPSYrm, {0, Unknown}}, + {X86::VMINPSYrr, {0, Unknown}}, + {X86::VMINPSZ128rm, {1, Unknown}}, + {X86::VMINPSZ128rmb, {1, Unknown}}, + {X86::VMINPSZ128rmbk, {1, Unknown}}, + {X86::VMINPSZ128rmbkz, {1, Unknown}}, + {X86::VMINPSZ128rmk, {1, Unknown}}, + {X86::VMINPSZ128rmkz, {1, Unknown}}, + {X86::VMINPSZ128rr, {0, Unknown}}, + {X86::VMINPSZ128rrk, {0, Unknown}}, + {X86::VMINPSZ128rrkz, {0, Unknown}}, + {X86::VMINPSZ256rm, {0, Unknown}}, + {X86::VMINPSZ256rmb, {0, Unknown}}, + {X86::VMINPSZ256rmbk, {0, Unknown}}, + {X86::VMINPSZ256rmbkz, {0, Unknown}}, + {X86::VMINPSZ256rmk, {0, Unknown}}, + {X86::VMINPSZ256rmkz, {0, Unknown}}, + {X86::VMINPSZ256rr, {0, Unknown}}, + {X86::VMINPSZ256rrk, {0, Unknown}}, + {X86::VMINPSZ256rrkz, {0, Unknown}}, + {X86::VMINPSZrm, {0, Unknown}}, + {X86::VMINPSZrmb, {0, Unknown}}, + {X86::VMINPSZrmbk, {0, Unknown}}, + {X86::VMINPSZrmbkz, {0, Unknown}}, + {X86::VMINPSZrmk, {0, Unknown}}, + {X86::VMINPSZrmkz, {0, Unknown}}, + {X86::VMINPSZrr, {0, Unknown}}, + {X86::VMINPSZrrb, {0, Unknown}}, + {X86::VMINPSZrrbk, {0, Unknown}}, + {X86::VMINPSZrrbkz, {0, Unknown}}, + {X86::VMINPSZrrk, {0, Unknown}}, + {X86::VMINPSZrrkz, {0, Unknown}}, + {X86::VMINPSrm, {0, Unknown}}, + {X86::VMINPSrr, {0, Unknown}}, + {X86::VMINSDZrm, {0, Unknown}}, + {X86::VMINSDZrm_Int, {0, Unknown}}, + {X86::VMINSDZrm_Intk, {0, Unknown}}, + {X86::VMINSDZrm_Intkz, {0, Unknown}}, + {X86::VMINSDZrr, {0, Unknown}}, + {X86::VMINSDZrr_Int, {0, Unknown}}, + {X86::VMINSDZrr_Intk, {0, Unknown}}, + {X86::VMINSDZrr_Intkz, {0, Unknown}}, + {X86::VMINSDZrrb_Int, {0, Unknown}}, + {X86::VMINSDZrrb_Intk, {0, Unknown}}, + {X86::VMINSDZrrb_Intkz, {0, Unknown}}, + {X86::VMINSDrm, {0, Unknown}}, + {X86::VMINSDrm_Int, {0, Unknown}}, + {X86::VMINSDrr, {0, Unknown}}, + {X86::VMINSDrr_Int, {0, Unknown}}, + {X86::VMINSSZrm, {0, Unknown}}, + {X86::VMINSSZrm_Int, {0, Unknown}}, + {X86::VMINSSZrm_Intk, {0, Unknown}}, + {X86::VMINSSZrm_Intkz, {0, Unknown}}, + {X86::VMINSSZrr, {0, Unknown}}, + {X86::VMINSSZrr_Int, {0, Unknown}}, + {X86::VMINSSZrr_Intk, {0, Unknown}}, + {X86::VMINSSZrr_Intkz, {0, Unknown}}, + {X86::VMINSSZrrb_Int, {0, Unknown}}, + {X86::VMINSSZrrb_Intk, {0, Unknown}}, + {X86::VMINSSZrrb_Intkz, {0, Unknown}}, + {X86::VMINSSrm, {0, Unknown}}, + {X86::VMINSSrm_Int, {0, Unknown}}, + {X86::VMINSSrr, {0, Unknown}}, + {X86::VMINSSrr_Int, {0, Unknown}}, + {X86::VMLAUNCH, {0, Unknown}}, + {X86::VMLOAD32, {0, Unknown}}, + {X86::VMLOAD64, {0, Unknown}}, + {X86::VMMCALL, {0, Unknown}}, + {X86::VMOV64toPQIZrm, {0, Unknown}}, + {X86::VMOV64toPQIZrr, {0, Unknown}}, + {X86::VMOV64toPQIrm, {0, Unknown}}, + {X86::VMOV64toPQIrr, {0, Unknown}}, + {X86::VMOV64toSDZrm, {0, Unknown}}, + {X86::VMOV64toSDZrr, {0, Unknown}}, + {X86::VMOV64toSDrm, {0, Unknown}}, + {X86::VMOV64toSDrr, {0, Unknown}}, + {X86::VMOVAPDYmr, {0, Unknown}}, + {X86::VMOVAPDYrm, {0, Unknown}}, + {X86::VMOVAPDYrr, {0, Unknown}}, + {X86::VMOVAPDYrr_REV, {0, Unknown}}, + {X86::VMOVAPDZ128mr, {1, Unknown}}, + {X86::VMOVAPDZ128mrk, {1, Unknown}}, + {X86::VMOVAPDZ128rm, {1, Unknown}}, + {X86::VMOVAPDZ128rmk, {1, Unknown}}, + {X86::VMOVAPDZ128rmkz, {1, Unknown}}, + {X86::VMOVAPDZ128rr, {0, Unknown}}, + {X86::VMOVAPDZ128rr_REV, {0, Unknown}}, + {X86::VMOVAPDZ128rrk, {0, Unknown}}, + {X86::VMOVAPDZ128rrk_REV, {0, Unknown}}, + {X86::VMOVAPDZ128rrkz, {0, Unknown}}, + {X86::VMOVAPDZ128rrkz_REV, {0, Unknown}}, + {X86::VMOVAPDZ256mr, {0, Unknown}}, + {X86::VMOVAPDZ256mrk, {0, Unknown}}, + {X86::VMOVAPDZ256rm, {0, Unknown}}, + {X86::VMOVAPDZ256rmk, {0, Unknown}}, + {X86::VMOVAPDZ256rmkz, {0, Unknown}}, + {X86::VMOVAPDZ256rr, {0, Unknown}}, + {X86::VMOVAPDZ256rr_REV, {0, Unknown}}, + {X86::VMOVAPDZ256rrk, {0, Unknown}}, + {X86::VMOVAPDZ256rrk_REV, {0, Unknown}}, + {X86::VMOVAPDZ256rrkz, {0, Unknown}}, + {X86::VMOVAPDZ256rrkz_REV, {0, Unknown}}, + {X86::VMOVAPDZmr, {0, Unknown}}, + {X86::VMOVAPDZmrk, {0, Unknown}}, + {X86::VMOVAPDZrm, {0, Unknown}}, + {X86::VMOVAPDZrmk, {0, Unknown}}, + {X86::VMOVAPDZrmkz, {0, Unknown}}, + {X86::VMOVAPDZrr, {0, Unknown}}, + {X86::VMOVAPDZrr_REV, {0, Unknown}}, + {X86::VMOVAPDZrrk, {0, Unknown}}, + {X86::VMOVAPDZrrk_REV, {0, Unknown}}, + {X86::VMOVAPDZrrkz, {0, Unknown}}, + {X86::VMOVAPDZrrkz_REV, {0, Unknown}}, + {X86::VMOVAPDmr, {0, Unknown}}, + {X86::VMOVAPDrm, {0, Unknown}}, + {X86::VMOVAPDrr, {0, Unknown}}, + {X86::VMOVAPDrr_REV, {0, Unknown}}, + {X86::VMOVAPSYmr, {0, Unknown}}, + {X86::VMOVAPSYrm, {0, Unknown}}, + {X86::VMOVAPSYrr, {0, Unknown}}, + {X86::VMOVAPSYrr_REV, {0, Unknown}}, + {X86::VMOVAPSZ128mr, {1, Unknown}}, + {X86::VMOVAPSZ128mr_NOVLX, {1, Unknown}}, + {X86::VMOVAPSZ128mrk, {1, Unknown}}, + {X86::VMOVAPSZ128rm, {1, Unknown}}, + {X86::VMOVAPSZ128rm_NOVLX, {1, Unknown}}, + {X86::VMOVAPSZ128rmk, {1, Unknown}}, + {X86::VMOVAPSZ128rmkz, {1, Unknown}}, + {X86::VMOVAPSZ128rr, {0, Unknown}}, + {X86::VMOVAPSZ128rr_REV, {0, Unknown}}, + {X86::VMOVAPSZ128rrk, {0, Unknown}}, + {X86::VMOVAPSZ128rrk_REV, {0, Unknown}}, + {X86::VMOVAPSZ128rrkz, {0, Unknown}}, + {X86::VMOVAPSZ128rrkz_REV, {0, Unknown}}, + {X86::VMOVAPSZ256mr, {0, Unknown}}, + {X86::VMOVAPSZ256mr_NOVLX, {0, Unknown}}, + {X86::VMOVAPSZ256mrk, {0, Unknown}}, + {X86::VMOVAPSZ256rm, {0, Unknown}}, + {X86::VMOVAPSZ256rm_NOVLX, {0, Unknown}}, + {X86::VMOVAPSZ256rmk, {0, Unknown}}, + {X86::VMOVAPSZ256rmkz, {0, Unknown}}, + {X86::VMOVAPSZ256rr, {0, Unknown}}, + {X86::VMOVAPSZ256rr_REV, {0, Unknown}}, + {X86::VMOVAPSZ256rrk, {0, Unknown}}, + {X86::VMOVAPSZ256rrk_REV, {0, Unknown}}, + {X86::VMOVAPSZ256rrkz, {0, Unknown}}, + {X86::VMOVAPSZ256rrkz_REV, {0, Unknown}}, + {X86::VMOVAPSZmr, {0, Unknown}}, + {X86::VMOVAPSZmrk, {0, Unknown}}, + {X86::VMOVAPSZrm, {0, Unknown}}, + {X86::VMOVAPSZrmk, {0, Unknown}}, + {X86::VMOVAPSZrmkz, {0, Unknown}}, + {X86::VMOVAPSZrr, {0, Unknown}}, + {X86::VMOVAPSZrr_REV, {0, Unknown}}, + {X86::VMOVAPSZrrk, {0, Unknown}}, + {X86::VMOVAPSZrrk_REV, {0, Unknown}}, + {X86::VMOVAPSZrrkz, {0, Unknown}}, + {X86::VMOVAPSZrrkz_REV, {0, Unknown}}, + {X86::VMOVAPSmr, {0, Unknown}}, + {X86::VMOVAPSrm, {0, Unknown}}, + {X86::VMOVAPSrr, {0, Unknown}}, + {X86::VMOVAPSrr_REV, {0, Unknown}}, + {X86::VMOVDDUPYrm, {0, Unknown}}, + {X86::VMOVDDUPYrr, {0, Unknown}}, + {X86::VMOVDDUPZ128rm, {1, Unknown}}, + {X86::VMOVDDUPZ128rmk, {1, Unknown}}, + {X86::VMOVDDUPZ128rmkz, {1, Unknown}}, + {X86::VMOVDDUPZ128rr, {0, Unknown}}, + {X86::VMOVDDUPZ128rrk, {0, Unknown}}, + {X86::VMOVDDUPZ128rrkz, {0, Unknown}}, + {X86::VMOVDDUPZ256rm, {0, Unknown}}, + {X86::VMOVDDUPZ256rmk, {0, Unknown}}, + {X86::VMOVDDUPZ256rmkz, {0, Unknown}}, + {X86::VMOVDDUPZ256rr, {0, Unknown}}, + {X86::VMOVDDUPZ256rrk, {0, Unknown}}, + {X86::VMOVDDUPZ256rrkz, {0, Unknown}}, + {X86::VMOVDDUPZrm, {0, Unknown}}, + {X86::VMOVDDUPZrmk, {0, Unknown}}, + {X86::VMOVDDUPZrmkz, {0, Unknown}}, + {X86::VMOVDDUPZrr, {0, Unknown}}, + {X86::VMOVDDUPZrrk, {0, Unknown}}, + {X86::VMOVDDUPZrrkz, {0, Unknown}}, + {X86::VMOVDDUPrm, {0, Unknown}}, + {X86::VMOVDDUPrr, {0, Unknown}}, + {X86::VMOVDI2PDIZrm, {0, Unknown}}, + {X86::VMOVDI2PDIZrr, {0, Unknown}}, + {X86::VMOVDI2PDIrm, {0, Unknown}}, + {X86::VMOVDI2PDIrr, {0, Unknown}}, + {X86::VMOVDI2SSZrm, {0, Unknown}}, + {X86::VMOVDI2SSZrr, {0, Unknown}}, + {X86::VMOVDI2SSrm, {0, Unknown}}, + {X86::VMOVDI2SSrr, {0, Unknown}}, + {X86::VMOVDQA32Z128mr, {1, Unknown}}, + {X86::VMOVDQA32Z128mrk, {1, Unknown}}, + {X86::VMOVDQA32Z128rm, {1, Unknown}}, + {X86::VMOVDQA32Z128rmk, {1, Unknown}}, + {X86::VMOVDQA32Z128rmkz, {1, Unknown}}, + {X86::VMOVDQA32Z128rr, {0, Unknown}}, + {X86::VMOVDQA32Z128rr_REV, {0, Unknown}}, + {X86::VMOVDQA32Z128rrk, {0, Unknown}}, + {X86::VMOVDQA32Z128rrk_REV, {0, Unknown}}, + {X86::VMOVDQA32Z128rrkz, {0, Unknown}}, + {X86::VMOVDQA32Z128rrkz_REV, {0, Unknown}}, + {X86::VMOVDQA32Z256mr, {0, Unknown}}, + {X86::VMOVDQA32Z256mrk, {0, Unknown}}, + {X86::VMOVDQA32Z256rm, {0, Unknown}}, + {X86::VMOVDQA32Z256rmk, {0, Unknown}}, + {X86::VMOVDQA32Z256rmkz, {0, Unknown}}, + {X86::VMOVDQA32Z256rr, {0, Unknown}}, + {X86::VMOVDQA32Z256rr_REV, {0, Unknown}}, + {X86::VMOVDQA32Z256rrk, {0, Unknown}}, + {X86::VMOVDQA32Z256rrk_REV, {0, Unknown}}, + {X86::VMOVDQA32Z256rrkz, {0, Unknown}}, + {X86::VMOVDQA32Z256rrkz_REV, {0, Unknown}}, + {X86::VMOVDQA32Zmr, {0, Unknown}}, + {X86::VMOVDQA32Zmrk, {0, Unknown}}, + {X86::VMOVDQA32Zrm, {0, Unknown}}, + {X86::VMOVDQA32Zrmk, {0, Unknown}}, + {X86::VMOVDQA32Zrmkz, {0, Unknown}}, + {X86::VMOVDQA32Zrr, {0, Unknown}}, + {X86::VMOVDQA32Zrr_REV, {0, Unknown}}, + {X86::VMOVDQA32Zrrk, {0, Unknown}}, + {X86::VMOVDQA32Zrrk_REV, {0, Unknown}}, + {X86::VMOVDQA32Zrrkz, {0, Unknown}}, + {X86::VMOVDQA32Zrrkz_REV, {0, Unknown}}, + {X86::VMOVDQA64Z128mr, {1, Unknown}}, + {X86::VMOVDQA64Z128mrk, {1, Unknown}}, + {X86::VMOVDQA64Z128rm, {1, Unknown}}, + {X86::VMOVDQA64Z128rmk, {1, Unknown}}, + {X86::VMOVDQA64Z128rmkz, {1, Unknown}}, + {X86::VMOVDQA64Z128rr, {0, Unknown}}, + {X86::VMOVDQA64Z128rr_REV, {0, Unknown}}, + {X86::VMOVDQA64Z128rrk, {0, Unknown}}, + {X86::VMOVDQA64Z128rrk_REV, {0, Unknown}}, + {X86::VMOVDQA64Z128rrkz, {0, Unknown}}, + {X86::VMOVDQA64Z128rrkz_REV, {0, Unknown}}, + {X86::VMOVDQA64Z256mr, {0, Unknown}}, + {X86::VMOVDQA64Z256mrk, {0, Unknown}}, + {X86::VMOVDQA64Z256rm, {0, Unknown}}, + {X86::VMOVDQA64Z256rmk, {0, Unknown}}, + {X86::VMOVDQA64Z256rmkz, {0, Unknown}}, + {X86::VMOVDQA64Z256rr, {0, Unknown}}, + {X86::VMOVDQA64Z256rr_REV, {0, Unknown}}, + {X86::VMOVDQA64Z256rrk, {0, Unknown}}, + {X86::VMOVDQA64Z256rrk_REV, {0, Unknown}}, + {X86::VMOVDQA64Z256rrkz, {0, Unknown}}, + {X86::VMOVDQA64Z256rrkz_REV, {0, Unknown}}, + {X86::VMOVDQA64Zmr, {0, Unknown}}, + {X86::VMOVDQA64Zmrk, {0, Unknown}}, + {X86::VMOVDQA64Zrm, {0, Unknown}}, + {X86::VMOVDQA64Zrmk, {0, Unknown}}, + {X86::VMOVDQA64Zrmkz, {0, Unknown}}, + {X86::VMOVDQA64Zrr, {0, Unknown}}, + {X86::VMOVDQA64Zrr_REV, {0, Unknown}}, + {X86::VMOVDQA64Zrrk, {0, Unknown}}, + {X86::VMOVDQA64Zrrk_REV, {0, Unknown}}, + {X86::VMOVDQA64Zrrkz, {0, Unknown}}, + {X86::VMOVDQA64Zrrkz_REV, {0, Unknown}}, + {X86::VMOVDQAYmr, {0, Unknown}}, + {X86::VMOVDQAYrm, {0, Unknown}}, + {X86::VMOVDQAYrr, {0, Unknown}}, + {X86::VMOVDQAYrr_REV, {0, Unknown}}, + {X86::VMOVDQAmr, {0, Unknown}}, + {X86::VMOVDQArm, {0, Unknown}}, + {X86::VMOVDQArr, {0, Unknown}}, + {X86::VMOVDQArr_REV, {0, Unknown}}, + {X86::VMOVDQU16Z128mr, {1, Unknown}}, + {X86::VMOVDQU16Z128mrk, {1, Unknown}}, + {X86::VMOVDQU16Z128rm, {1, Unknown}}, + {X86::VMOVDQU16Z128rmk, {1, Unknown}}, + {X86::VMOVDQU16Z128rmkz, {1, Unknown}}, + {X86::VMOVDQU16Z128rr, {0, Unknown}}, + {X86::VMOVDQU16Z128rr_REV, {0, Unknown}}, + {X86::VMOVDQU16Z128rrk, {0, Unknown}}, + {X86::VMOVDQU16Z128rrk_REV, {0, Unknown}}, + {X86::VMOVDQU16Z128rrkz, {0, Unknown}}, + {X86::VMOVDQU16Z128rrkz_REV, {0, Unknown}}, + {X86::VMOVDQU16Z256mr, {0, Unknown}}, + {X86::VMOVDQU16Z256mrk, {0, Unknown}}, + {X86::VMOVDQU16Z256rm, {0, Unknown}}, + {X86::VMOVDQU16Z256rmk, {0, Unknown}}, + {X86::VMOVDQU16Z256rmkz, {0, Unknown}}, + {X86::VMOVDQU16Z256rr, {0, Unknown}}, + {X86::VMOVDQU16Z256rr_REV, {0, Unknown}}, + {X86::VMOVDQU16Z256rrk, {0, Unknown}}, + {X86::VMOVDQU16Z256rrk_REV, {0, Unknown}}, + {X86::VMOVDQU16Z256rrkz, {0, Unknown}}, + {X86::VMOVDQU16Z256rrkz_REV, {0, Unknown}}, + {X86::VMOVDQU16Zmr, {0, Unknown}}, + {X86::VMOVDQU16Zmrk, {0, Unknown}}, + {X86::VMOVDQU16Zrm, {0, Unknown}}, + {X86::VMOVDQU16Zrmk, {0, Unknown}}, + {X86::VMOVDQU16Zrmkz, {0, Unknown}}, + {X86::VMOVDQU16Zrr, {0, Unknown}}, + {X86::VMOVDQU16Zrr_REV, {0, Unknown}}, + {X86::VMOVDQU16Zrrk, {0, Unknown}}, + {X86::VMOVDQU16Zrrk_REV, {0, Unknown}}, + {X86::VMOVDQU16Zrrkz, {0, Unknown}}, + {X86::VMOVDQU16Zrrkz_REV, {0, Unknown}}, + {X86::VMOVDQU32Z128mr, {1, Unknown}}, + {X86::VMOVDQU32Z128mrk, {1, Unknown}}, + {X86::VMOVDQU32Z128rm, {1, Unknown}}, + {X86::VMOVDQU32Z128rmk, {1, Unknown}}, + {X86::VMOVDQU32Z128rmkz, {1, Unknown}}, + {X86::VMOVDQU32Z128rr, {0, Unknown}}, + {X86::VMOVDQU32Z128rr_REV, {0, Unknown}}, + {X86::VMOVDQU32Z128rrk, {0, Unknown}}, + {X86::VMOVDQU32Z128rrk_REV, {0, Unknown}}, + {X86::VMOVDQU32Z128rrkz, {0, Unknown}}, + {X86::VMOVDQU32Z128rrkz_REV, {0, Unknown}}, + {X86::VMOVDQU32Z256mr, {0, Unknown}}, + {X86::VMOVDQU32Z256mrk, {0, Unknown}}, + {X86::VMOVDQU32Z256rm, {0, Unknown}}, + {X86::VMOVDQU32Z256rmk, {0, Unknown}}, + {X86::VMOVDQU32Z256rmkz, {0, Unknown}}, + {X86::VMOVDQU32Z256rr, {0, Unknown}}, + {X86::VMOVDQU32Z256rr_REV, {0, Unknown}}, + {X86::VMOVDQU32Z256rrk, {0, Unknown}}, + {X86::VMOVDQU32Z256rrk_REV, {0, Unknown}}, + {X86::VMOVDQU32Z256rrkz, {0, Unknown}}, + {X86::VMOVDQU32Z256rrkz_REV, {0, Unknown}}, + {X86::VMOVDQU32Zmr, {0, Unknown}}, + {X86::VMOVDQU32Zmrk, {0, Unknown}}, + {X86::VMOVDQU32Zrm, {0, Unknown}}, + {X86::VMOVDQU32Zrmk, {0, Unknown}}, + {X86::VMOVDQU32Zrmkz, {0, Unknown}}, + {X86::VMOVDQU32Zrr, {0, Unknown}}, + {X86::VMOVDQU32Zrr_REV, {0, Unknown}}, + {X86::VMOVDQU32Zrrk, {0, Unknown}}, + {X86::VMOVDQU32Zrrk_REV, {0, Unknown}}, + {X86::VMOVDQU32Zrrkz, {0, Unknown}}, + {X86::VMOVDQU32Zrrkz_REV, {0, Unknown}}, + {X86::VMOVDQU64Z128mr, {1, Unknown}}, + {X86::VMOVDQU64Z128mrk, {1, Unknown}}, + {X86::VMOVDQU64Z128rm, {1, Unknown}}, + {X86::VMOVDQU64Z128rmk, {1, Unknown}}, + {X86::VMOVDQU64Z128rmkz, {1, Unknown}}, + {X86::VMOVDQU64Z128rr, {0, Unknown}}, + {X86::VMOVDQU64Z128rr_REV, {0, Unknown}}, + {X86::VMOVDQU64Z128rrk, {0, Unknown}}, + {X86::VMOVDQU64Z128rrk_REV, {0, Unknown}}, + {X86::VMOVDQU64Z128rrkz, {0, Unknown}}, + {X86::VMOVDQU64Z128rrkz_REV, {0, Unknown}}, + {X86::VMOVDQU64Z256mr, {0, Unknown}}, + {X86::VMOVDQU64Z256mrk, {0, Unknown}}, + {X86::VMOVDQU64Z256rm, {0, Unknown}}, + {X86::VMOVDQU64Z256rmk, {0, Unknown}}, + {X86::VMOVDQU64Z256rmkz, {0, Unknown}}, + {X86::VMOVDQU64Z256rr, {0, Unknown}}, + {X86::VMOVDQU64Z256rr_REV, {0, Unknown}}, + {X86::VMOVDQU64Z256rrk, {0, Unknown}}, + {X86::VMOVDQU64Z256rrk_REV, {0, Unknown}}, + {X86::VMOVDQU64Z256rrkz, {0, Unknown}}, + {X86::VMOVDQU64Z256rrkz_REV, {0, Unknown}}, + {X86::VMOVDQU64Zmr, {0, Unknown}}, + {X86::VMOVDQU64Zmrk, {0, Unknown}}, + {X86::VMOVDQU64Zrm, {0, Unknown}}, + {X86::VMOVDQU64Zrmk, {0, Unknown}}, + {X86::VMOVDQU64Zrmkz, {0, Unknown}}, + {X86::VMOVDQU64Zrr, {0, Unknown}}, + {X86::VMOVDQU64Zrr_REV, {0, Unknown}}, + {X86::VMOVDQU64Zrrk, {0, Unknown}}, + {X86::VMOVDQU64Zrrk_REV, {0, Unknown}}, + {X86::VMOVDQU64Zrrkz, {0, Unknown}}, + {X86::VMOVDQU64Zrrkz_REV, {0, Unknown}}, + {X86::VMOVDQU8Z128mr, {1, Unknown}}, + {X86::VMOVDQU8Z128mrk, {1, Unknown}}, + {X86::VMOVDQU8Z128rm, {1, Unknown}}, + {X86::VMOVDQU8Z128rmk, {1, Unknown}}, + {X86::VMOVDQU8Z128rmkz, {1, Unknown}}, + {X86::VMOVDQU8Z128rr, {0, Unknown}}, + {X86::VMOVDQU8Z128rr_REV, {0, Unknown}}, + {X86::VMOVDQU8Z128rrk, {0, Unknown}}, + {X86::VMOVDQU8Z128rrk_REV, {0, Unknown}}, + {X86::VMOVDQU8Z128rrkz, {0, Unknown}}, + {X86::VMOVDQU8Z128rrkz_REV, {0, Unknown}}, + {X86::VMOVDQU8Z256mr, {0, Unknown}}, + {X86::VMOVDQU8Z256mrk, {0, Unknown}}, + {X86::VMOVDQU8Z256rm, {0, Unknown}}, + {X86::VMOVDQU8Z256rmk, {0, Unknown}}, + {X86::VMOVDQU8Z256rmkz, {0, Unknown}}, + {X86::VMOVDQU8Z256rr, {0, Unknown}}, + {X86::VMOVDQU8Z256rr_REV, {0, Unknown}}, + {X86::VMOVDQU8Z256rrk, {0, Unknown}}, + {X86::VMOVDQU8Z256rrk_REV, {0, Unknown}}, + {X86::VMOVDQU8Z256rrkz, {0, Unknown}}, + {X86::VMOVDQU8Z256rrkz_REV, {0, Unknown}}, + {X86::VMOVDQU8Zmr, {0, Unknown}}, + {X86::VMOVDQU8Zmrk, {0, Unknown}}, + {X86::VMOVDQU8Zrm, {0, Unknown}}, + {X86::VMOVDQU8Zrmk, {0, Unknown}}, + {X86::VMOVDQU8Zrmkz, {0, Unknown}}, + {X86::VMOVDQU8Zrr, {0, Unknown}}, + {X86::VMOVDQU8Zrr_REV, {0, Unknown}}, + {X86::VMOVDQU8Zrrk, {0, Unknown}}, + {X86::VMOVDQU8Zrrk_REV, {0, Unknown}}, + {X86::VMOVDQU8Zrrkz, {0, Unknown}}, + {X86::VMOVDQU8Zrrkz_REV, {0, Unknown}}, + {X86::VMOVDQUYmr, {0, Unknown}}, + {X86::VMOVDQUYrm, {0, Unknown}}, + {X86::VMOVDQUYrr, {0, Unknown}}, + {X86::VMOVDQUYrr_REV, {0, Unknown}}, + {X86::VMOVDQUmr, {0, Unknown}}, + {X86::VMOVDQUrm, {0, Unknown}}, + {X86::VMOVDQUrr, {0, Unknown}}, + {X86::VMOVDQUrr_REV, {0, Unknown}}, + {X86::VMOVHLPSZrr, {0, Unknown}}, + {X86::VMOVHLPSrr, {0, Unknown}}, + {X86::VMOVHPDZ128mr, {1, Unknown}}, + {X86::VMOVHPDZ128rm, {1, Unknown}}, + {X86::VMOVHPDmr, {0, Unknown}}, + {X86::VMOVHPDrm, {0, Unknown}}, + {X86::VMOVHPSZ128mr, {1, Unknown}}, + {X86::VMOVHPSZ128rm, {1, Unknown}}, + {X86::VMOVHPSmr, {0, Unknown}}, + {X86::VMOVHPSrm, {0, Unknown}}, + {X86::VMOVLHPSZrr, {0, Unknown}}, + {X86::VMOVLHPSrr, {0, Unknown}}, + {X86::VMOVLPDZ128mr, {1, Unknown}}, + {X86::VMOVLPDZ128rm, {1, Unknown}}, + {X86::VMOVLPDmr, {0, Unknown}}, + {X86::VMOVLPDrm, {0, Unknown}}, + {X86::VMOVLPSZ128mr, {1, Unknown}}, + {X86::VMOVLPSZ128rm, {1, Unknown}}, + {X86::VMOVLPSmr, {0, Unknown}}, + {X86::VMOVLPSrm, {0, Unknown}}, + {X86::VMOVMSKPDYrr, {0, Unknown}}, + {X86::VMOVMSKPDrr, {0, Unknown}}, + {X86::VMOVMSKPSYrr, {0, Unknown}}, + {X86::VMOVMSKPSrr, {0, Unknown}}, + {X86::VMOVNTDQAYrm, {0, Unknown}}, + {X86::VMOVNTDQAZ128rm, {1, Unknown}}, + {X86::VMOVNTDQAZ256rm, {0, Unknown}}, + {X86::VMOVNTDQAZrm, {0, Unknown}}, + {X86::VMOVNTDQArm, {0, Unknown}}, + {X86::VMOVNTDQYmr, {0, Unknown}}, + {X86::VMOVNTDQZ128mr, {1, Unknown}}, + {X86::VMOVNTDQZ256mr, {0, Unknown}}, + {X86::VMOVNTDQZmr, {0, Unknown}}, + {X86::VMOVNTDQmr, {0, Unknown}}, + {X86::VMOVNTPDYmr, {0, Unknown}}, + {X86::VMOVNTPDZ128mr, {1, Unknown}}, + {X86::VMOVNTPDZ256mr, {0, Unknown}}, + {X86::VMOVNTPDZmr, {0, Unknown}}, + {X86::VMOVNTPDmr, {0, Unknown}}, + {X86::VMOVNTPSYmr, {0, Unknown}}, + {X86::VMOVNTPSZ128mr, {1, Unknown}}, + {X86::VMOVNTPSZ256mr, {0, Unknown}}, + {X86::VMOVNTPSZmr, {0, Unknown}}, + {X86::VMOVNTPSmr, {0, Unknown}}, + {X86::VMOVPDI2DIZmr, {0, Unknown}}, + {X86::VMOVPDI2DIZrr, {0, Unknown}}, + {X86::VMOVPDI2DImr, {0, Unknown}}, + {X86::VMOVPDI2DIrr, {0, Unknown}}, + {X86::VMOVPQI2QIZmr, {0, Unknown}}, + {X86::VMOVPQI2QIZrr, {0, Unknown}}, + {X86::VMOVPQI2QImr, {0, Unknown}}, + {X86::VMOVPQI2QIrr, {0, Unknown}}, + {X86::VMOVPQIto64Zmr, {0, Unknown}}, + {X86::VMOVPQIto64Zrr, {0, Unknown}}, + {X86::VMOVPQIto64mr, {8, Unknown}}, + {X86::VMOVPQIto64rr, {0, Unknown}}, + {X86::VMOVQI2PQIZrm, {0, Unknown}}, + {X86::VMOVQI2PQIrm, {0, Unknown}}, + {X86::VMOVSDZmr, {0, Unknown}}, + {X86::VMOVSDZmrk, {0, Unknown}}, + {X86::VMOVSDZrm, {0, Unknown}}, + {X86::VMOVSDZrmk, {0, Unknown}}, + {X86::VMOVSDZrmkz, {0, Unknown}}, + {X86::VMOVSDZrr, {0, Unknown}}, + {X86::VMOVSDZrr_REV, {0, Unknown}}, + {X86::VMOVSDZrrk, {0, Unknown}}, + {X86::VMOVSDZrrk_REV, {0, Unknown}}, + {X86::VMOVSDZrrkz, {0, Unknown}}, + {X86::VMOVSDZrrkz_REV, {0, Unknown}}, + {X86::VMOVSDmr, {0, Unknown}}, + {X86::VMOVSDrm, {0, Unknown}}, + {X86::VMOVSDrr, {0, Unknown}}, + {X86::VMOVSDrr_REV, {0, Unknown}}, + {X86::VMOVSDto64Zmr, {0, Unknown}}, + {X86::VMOVSDto64Zrr, {0, Unknown}}, + {X86::VMOVSDto64mr, {8, Unknown}}, + {X86::VMOVSDto64rr, {0, Unknown}}, + {X86::VMOVSHDUPYrm, {0, Unknown}}, + {X86::VMOVSHDUPYrr, {0, Unknown}}, + {X86::VMOVSHDUPZ128rm, {1, Unknown}}, + {X86::VMOVSHDUPZ128rmk, {1, Unknown}}, + {X86::VMOVSHDUPZ128rmkz, {1, Unknown}}, + {X86::VMOVSHDUPZ128rr, {0, Unknown}}, + {X86::VMOVSHDUPZ128rrk, {0, Unknown}}, + {X86::VMOVSHDUPZ128rrkz, {0, Unknown}}, + {X86::VMOVSHDUPZ256rm, {0, Unknown}}, + {X86::VMOVSHDUPZ256rmk, {0, Unknown}}, + {X86::VMOVSHDUPZ256rmkz, {0, Unknown}}, + {X86::VMOVSHDUPZ256rr, {0, Unknown}}, + {X86::VMOVSHDUPZ256rrk, {0, Unknown}}, + {X86::VMOVSHDUPZ256rrkz, {0, Unknown}}, + {X86::VMOVSHDUPZrm, {0, Unknown}}, + {X86::VMOVSHDUPZrmk, {0, Unknown}}, + {X86::VMOVSHDUPZrmkz, {0, Unknown}}, + {X86::VMOVSHDUPZrr, {0, Unknown}}, + {X86::VMOVSHDUPZrrk, {0, Unknown}}, + {X86::VMOVSHDUPZrrkz, {0, Unknown}}, + {X86::VMOVSHDUPrm, {0, Unknown}}, + {X86::VMOVSHDUPrr, {0, Unknown}}, + {X86::VMOVSLDUPYrm, {0, Unknown}}, + {X86::VMOVSLDUPYrr, {0, Unknown}}, + {X86::VMOVSLDUPZ128rm, {1, Unknown}}, + {X86::VMOVSLDUPZ128rmk, {1, Unknown}}, + {X86::VMOVSLDUPZ128rmkz, {1, Unknown}}, + {X86::VMOVSLDUPZ128rr, {0, Unknown}}, + {X86::VMOVSLDUPZ128rrk, {0, Unknown}}, + {X86::VMOVSLDUPZ128rrkz, {0, Unknown}}, + {X86::VMOVSLDUPZ256rm, {0, Unknown}}, + {X86::VMOVSLDUPZ256rmk, {0, Unknown}}, + {X86::VMOVSLDUPZ256rmkz, {0, Unknown}}, + {X86::VMOVSLDUPZ256rr, {0, Unknown}}, + {X86::VMOVSLDUPZ256rrk, {0, Unknown}}, + {X86::VMOVSLDUPZ256rrkz, {0, Unknown}}, + {X86::VMOVSLDUPZrm, {0, Unknown}}, + {X86::VMOVSLDUPZrmk, {0, Unknown}}, + {X86::VMOVSLDUPZrmkz, {0, Unknown}}, + {X86::VMOVSLDUPZrr, {0, Unknown}}, + {X86::VMOVSLDUPZrrk, {0, Unknown}}, + {X86::VMOVSLDUPZrrkz, {0, Unknown}}, + {X86::VMOVSLDUPrm, {0, Unknown}}, + {X86::VMOVSLDUPrr, {0, Unknown}}, + {X86::VMOVSS2DIZmr, {0, Unknown}}, + {X86::VMOVSS2DIZrr, {0, Unknown}}, + {X86::VMOVSS2DImr, {0, Unknown}}, + {X86::VMOVSS2DIrr, {0, Unknown}}, + {X86::VMOVSSZmr, {0, Unknown}}, + {X86::VMOVSSZmrk, {0, Unknown}}, + {X86::VMOVSSZrm, {0, Unknown}}, + {X86::VMOVSSZrmk, {0, Unknown}}, + {X86::VMOVSSZrmkz, {0, Unknown}}, + {X86::VMOVSSZrr, {0, Unknown}}, + {X86::VMOVSSZrr_REV, {0, Unknown}}, + {X86::VMOVSSZrrk, {0, Unknown}}, + {X86::VMOVSSZrrk_REV, {0, Unknown}}, + {X86::VMOVSSZrrkz, {0, Unknown}}, + {X86::VMOVSSZrrkz_REV, {0, Unknown}}, + {X86::VMOVSSmr, {0, Unknown}}, + {X86::VMOVSSrm, {0, Unknown}}, + {X86::VMOVSSrr, {0, Unknown}}, + {X86::VMOVSSrr_REV, {0, Unknown}}, + {X86::VMOVUPDYmr, {0, Unknown}}, + {X86::VMOVUPDYrm, {0, Unknown}}, + {X86::VMOVUPDYrr, {0, Unknown}}, + {X86::VMOVUPDYrr_REV, {0, Unknown}}, + {X86::VMOVUPDZ128mr, {1, Unknown}}, + {X86::VMOVUPDZ128mrk, {1, Unknown}}, + {X86::VMOVUPDZ128rm, {1, Unknown}}, + {X86::VMOVUPDZ128rmk, {1, Unknown}}, + {X86::VMOVUPDZ128rmkz, {1, Unknown}}, + {X86::VMOVUPDZ128rr, {0, Unknown}}, + {X86::VMOVUPDZ128rr_REV, {0, Unknown}}, + {X86::VMOVUPDZ128rrk, {0, Unknown}}, + {X86::VMOVUPDZ128rrk_REV, {0, Unknown}}, + {X86::VMOVUPDZ128rrkz, {0, Unknown}}, + {X86::VMOVUPDZ128rrkz_REV, {0, Unknown}}, + {X86::VMOVUPDZ256mr, {0, Unknown}}, + {X86::VMOVUPDZ256mrk, {0, Unknown}}, + {X86::VMOVUPDZ256rm, {0, Unknown}}, + {X86::VMOVUPDZ256rmk, {0, Unknown}}, + {X86::VMOVUPDZ256rmkz, {0, Unknown}}, + {X86::VMOVUPDZ256rr, {0, Unknown}}, + {X86::VMOVUPDZ256rr_REV, {0, Unknown}}, + {X86::VMOVUPDZ256rrk, {0, Unknown}}, + {X86::VMOVUPDZ256rrk_REV, {0, Unknown}}, + {X86::VMOVUPDZ256rrkz, {0, Unknown}}, + {X86::VMOVUPDZ256rrkz_REV, {0, Unknown}}, + {X86::VMOVUPDZmr, {0, Unknown}}, + {X86::VMOVUPDZmrk, {0, Unknown}}, + {X86::VMOVUPDZrm, {0, Unknown}}, + {X86::VMOVUPDZrmk, {0, Unknown}}, + {X86::VMOVUPDZrmkz, {0, Unknown}}, + {X86::VMOVUPDZrr, {0, Unknown}}, + {X86::VMOVUPDZrr_REV, {0, Unknown}}, + {X86::VMOVUPDZrrk, {0, Unknown}}, + {X86::VMOVUPDZrrk_REV, {0, Unknown}}, + {X86::VMOVUPDZrrkz, {0, Unknown}}, + {X86::VMOVUPDZrrkz_REV, {0, Unknown}}, + {X86::VMOVUPDmr, {0, Unknown}}, + {X86::VMOVUPDrm, {0, Unknown}}, + {X86::VMOVUPDrr, {0, Unknown}}, + {X86::VMOVUPDrr_REV, {0, Unknown}}, + {X86::VMOVUPSYmr, {0, Unknown}}, + {X86::VMOVUPSYrm, {0, Unknown}}, + {X86::VMOVUPSYrr, {0, Unknown}}, + {X86::VMOVUPSYrr_REV, {0, Unknown}}, + {X86::VMOVUPSZ128mr, {1, Unknown}}, + {X86::VMOVUPSZ128mr_NOVLX, {1, Unknown}}, + {X86::VMOVUPSZ128mrk, {1, Unknown}}, + {X86::VMOVUPSZ128rm, {1, Unknown}}, + {X86::VMOVUPSZ128rm_NOVLX, {1, Unknown}}, + {X86::VMOVUPSZ128rmk, {1, Unknown}}, + {X86::VMOVUPSZ128rmkz, {1, Unknown}}, + {X86::VMOVUPSZ128rr, {0, Unknown}}, + {X86::VMOVUPSZ128rr_REV, {0, Unknown}}, + {X86::VMOVUPSZ128rrk, {0, Unknown}}, + {X86::VMOVUPSZ128rrk_REV, {0, Unknown}}, + {X86::VMOVUPSZ128rrkz, {0, Unknown}}, + {X86::VMOVUPSZ128rrkz_REV, {0, Unknown}}, + {X86::VMOVUPSZ256mr, {0, Unknown}}, + {X86::VMOVUPSZ256mr_NOVLX, {0, Unknown}}, + {X86::VMOVUPSZ256mrk, {0, Unknown}}, + {X86::VMOVUPSZ256rm, {0, Unknown}}, + {X86::VMOVUPSZ256rm_NOVLX, {0, Unknown}}, + {X86::VMOVUPSZ256rmk, {0, Unknown}}, + {X86::VMOVUPSZ256rmkz, {0, Unknown}}, + {X86::VMOVUPSZ256rr, {0, Unknown}}, + {X86::VMOVUPSZ256rr_REV, {0, Unknown}}, + {X86::VMOVUPSZ256rrk, {0, Unknown}}, + {X86::VMOVUPSZ256rrk_REV, {0, Unknown}}, + {X86::VMOVUPSZ256rrkz, {0, Unknown}}, + {X86::VMOVUPSZ256rrkz_REV, {0, Unknown}}, + {X86::VMOVUPSZmr, {0, Unknown}}, + {X86::VMOVUPSZmrk, {0, Unknown}}, + {X86::VMOVUPSZrm, {0, Unknown}}, + {X86::VMOVUPSZrmk, {0, Unknown}}, + {X86::VMOVUPSZrmkz, {0, Unknown}}, + {X86::VMOVUPSZrr, {0, Unknown}}, + {X86::VMOVUPSZrr_REV, {0, Unknown}}, + {X86::VMOVUPSZrrk, {0, Unknown}}, + {X86::VMOVUPSZrrk_REV, {0, Unknown}}, + {X86::VMOVUPSZrrkz, {0, Unknown}}, + {X86::VMOVUPSZrrkz_REV, {0, Unknown}}, + {X86::VMOVUPSmr, {0, Unknown}}, + {X86::VMOVUPSrm, {0, Unknown}}, + {X86::VMOVUPSrr, {0, Unknown}}, + {X86::VMOVUPSrr_REV, {0, Unknown}}, + {X86::VMOVZPQILo2PQIZrr, {0, Unknown}}, + {X86::VMOVZPQILo2PQIrr, {0, Unknown}}, + {X86::VMPSADBWYrmi, {0, Unknown}}, + {X86::VMPSADBWYrri, {0, Unknown}}, + {X86::VMPSADBWrmi, {0, Unknown}}, + {X86::VMPSADBWrri, {0, Unknown}}, + {X86::VMPTRLDm, {0, Unknown}}, + {X86::VMPTRSTm, {0, Unknown}}, + {X86::VMREAD32mr, {4, Unknown}}, + {X86::VMREAD32rr, {0, Unknown}}, + {X86::VMREAD64mr, {8, Unknown}}, + {X86::VMREAD64rr, {0, Unknown}}, + {X86::VMRESUME, {0, Unknown}}, + {X86::VMRUN32, {0, Unknown}}, + {X86::VMRUN64, {0, Unknown}}, + {X86::VMSAVE32, {0, Unknown}}, + {X86::VMSAVE64, {0, Unknown}}, + {X86::VMULPDYrm, {0, Unknown}}, + {X86::VMULPDYrr, {0, Unknown}}, + {X86::VMULPDZ128rm, {1, Unknown}}, + {X86::VMULPDZ128rmb, {1, Unknown}}, + {X86::VMULPDZ128rmbk, {1, Unknown}}, + {X86::VMULPDZ128rmbkz, {1, Unknown}}, + {X86::VMULPDZ128rmk, {1, Unknown}}, + {X86::VMULPDZ128rmkz, {1, Unknown}}, + {X86::VMULPDZ128rr, {0, Unknown}}, + {X86::VMULPDZ128rrk, {0, Unknown}}, + {X86::VMULPDZ128rrkz, {0, Unknown}}, + {X86::VMULPDZ256rm, {0, Unknown}}, + {X86::VMULPDZ256rmb, {0, Unknown}}, + {X86::VMULPDZ256rmbk, {0, Unknown}}, + {X86::VMULPDZ256rmbkz, {0, Unknown}}, + {X86::VMULPDZ256rmk, {0, Unknown}}, + {X86::VMULPDZ256rmkz, {0, Unknown}}, + {X86::VMULPDZ256rr, {0, Unknown}}, + {X86::VMULPDZ256rrk, {0, Unknown}}, + {X86::VMULPDZ256rrkz, {0, Unknown}}, + {X86::VMULPDZrm, {0, Unknown}}, + {X86::VMULPDZrmb, {0, Unknown}}, + {X86::VMULPDZrmbk, {0, Unknown}}, + {X86::VMULPDZrmbkz, {0, Unknown}}, + {X86::VMULPDZrmk, {0, Unknown}}, + {X86::VMULPDZrmkz, {0, Unknown}}, + {X86::VMULPDZrr, {0, Unknown}}, + {X86::VMULPDZrrb, {0, Unknown}}, + {X86::VMULPDZrrbk, {0, Unknown}}, + {X86::VMULPDZrrbkz, {0, Unknown}}, + {X86::VMULPDZrrk, {0, Unknown}}, + {X86::VMULPDZrrkz, {0, Unknown}}, + {X86::VMULPDrm, {0, Unknown}}, + {X86::VMULPDrr, {0, Unknown}}, + {X86::VMULPSYrm, {0, Unknown}}, + {X86::VMULPSYrr, {0, Unknown}}, + {X86::VMULPSZ128rm, {1, Unknown}}, + {X86::VMULPSZ128rmb, {1, Unknown}}, + {X86::VMULPSZ128rmbk, {1, Unknown}}, + {X86::VMULPSZ128rmbkz, {1, Unknown}}, + {X86::VMULPSZ128rmk, {1, Unknown}}, + {X86::VMULPSZ128rmkz, {1, Unknown}}, + {X86::VMULPSZ128rr, {0, Unknown}}, + {X86::VMULPSZ128rrk, {0, Unknown}}, + {X86::VMULPSZ128rrkz, {0, Unknown}}, + {X86::VMULPSZ256rm, {0, Unknown}}, + {X86::VMULPSZ256rmb, {0, Unknown}}, + {X86::VMULPSZ256rmbk, {0, Unknown}}, + {X86::VMULPSZ256rmbkz, {0, Unknown}}, + {X86::VMULPSZ256rmk, {0, Unknown}}, + {X86::VMULPSZ256rmkz, {0, Unknown}}, + {X86::VMULPSZ256rr, {0, Unknown}}, + {X86::VMULPSZ256rrk, {0, Unknown}}, + {X86::VMULPSZ256rrkz, {0, Unknown}}, + {X86::VMULPSZrm, {0, Unknown}}, + {X86::VMULPSZrmb, {0, Unknown}}, + {X86::VMULPSZrmbk, {0, Unknown}}, + {X86::VMULPSZrmbkz, {0, Unknown}}, + {X86::VMULPSZrmk, {0, Unknown}}, + {X86::VMULPSZrmkz, {0, Unknown}}, + {X86::VMULPSZrr, {0, Unknown}}, + {X86::VMULPSZrrb, {0, Unknown}}, + {X86::VMULPSZrrbk, {0, Unknown}}, + {X86::VMULPSZrrbkz, {0, Unknown}}, + {X86::VMULPSZrrk, {0, Unknown}}, + {X86::VMULPSZrrkz, {0, Unknown}}, + {X86::VMULPSrm, {0, Unknown}}, + {X86::VMULPSrr, {0, Unknown}}, + {X86::VMULSDZrm, {0, Unknown}}, + {X86::VMULSDZrm_Int, {0, Unknown}}, + {X86::VMULSDZrm_Intk, {0, Unknown}}, + {X86::VMULSDZrm_Intkz, {0, Unknown}}, + {X86::VMULSDZrr, {0, Unknown}}, + {X86::VMULSDZrr_Int, {0, Unknown}}, + {X86::VMULSDZrr_Intk, {0, Unknown}}, + {X86::VMULSDZrr_Intkz, {0, Unknown}}, + {X86::VMULSDZrrb_Int, {0, Unknown}}, + {X86::VMULSDZrrb_Intk, {0, Unknown}}, + {X86::VMULSDZrrb_Intkz, {0, Unknown}}, + {X86::VMULSDrm, {0, Unknown}}, + {X86::VMULSDrm_Int, {0, Unknown}}, + {X86::VMULSDrr, {0, Unknown}}, + {X86::VMULSDrr_Int, {0, Unknown}}, + {X86::VMULSSZrm, {0, Unknown}}, + {X86::VMULSSZrm_Int, {0, Unknown}}, + {X86::VMULSSZrm_Intk, {0, Unknown}}, + {X86::VMULSSZrm_Intkz, {0, Unknown}}, + {X86::VMULSSZrr, {0, Unknown}}, + {X86::VMULSSZrr_Int, {0, Unknown}}, + {X86::VMULSSZrr_Intk, {0, Unknown}}, + {X86::VMULSSZrr_Intkz, {0, Unknown}}, + {X86::VMULSSZrrb_Int, {0, Unknown}}, + {X86::VMULSSZrrb_Intk, {0, Unknown}}, + {X86::VMULSSZrrb_Intkz, {0, Unknown}}, + {X86::VMULSSrm, {0, Unknown}}, + {X86::VMULSSrm_Int, {0, Unknown}}, + {X86::VMULSSrr, {0, Unknown}}, + {X86::VMULSSrr_Int, {0, Unknown}}, + {X86::VMWRITE32rm, {4, Unknown}}, + {X86::VMWRITE32rr, {0, Unknown}}, + {X86::VMWRITE64rm, {8, Unknown}}, + {X86::VMWRITE64rr, {0, Unknown}}, + {X86::VMXOFF, {0, Unknown}}, + {X86::VMXON, {0, Unknown}}, + {X86::VORPDYrm, {0, Unknown}}, + {X86::VORPDYrr, {0, Unknown}}, + {X86::VORPDZ128rm, {1, Unknown}}, + {X86::VORPDZ128rmb, {1, Unknown}}, + {X86::VORPDZ128rmbk, {1, Unknown}}, + {X86::VORPDZ128rmbkz, {1, Unknown}}, + {X86::VORPDZ128rmk, {1, Unknown}}, + {X86::VORPDZ128rmkz, {1, Unknown}}, + {X86::VORPDZ128rr, {0, Unknown}}, + {X86::VORPDZ128rrk, {0, Unknown}}, + {X86::VORPDZ128rrkz, {0, Unknown}}, + {X86::VORPDZ256rm, {0, Unknown}}, + {X86::VORPDZ256rmb, {0, Unknown}}, + {X86::VORPDZ256rmbk, {0, Unknown}}, + {X86::VORPDZ256rmbkz, {0, Unknown}}, + {X86::VORPDZ256rmk, {0, Unknown}}, + {X86::VORPDZ256rmkz, {0, Unknown}}, + {X86::VORPDZ256rr, {0, Unknown}}, + {X86::VORPDZ256rrk, {0, Unknown}}, + {X86::VORPDZ256rrkz, {0, Unknown}}, + {X86::VORPDZrm, {0, Unknown}}, + {X86::VORPDZrmb, {0, Unknown}}, + {X86::VORPDZrmbk, {0, Unknown}}, + {X86::VORPDZrmbkz, {0, Unknown}}, + {X86::VORPDZrmk, {0, Unknown}}, + {X86::VORPDZrmkz, {0, Unknown}}, + {X86::VORPDZrr, {0, Unknown}}, + {X86::VORPDZrrk, {0, Unknown}}, + {X86::VORPDZrrkz, {0, Unknown}}, + {X86::VORPDrm, {0, Unknown}}, + {X86::VORPDrr, {0, Unknown}}, + {X86::VORPSYrm, {0, Unknown}}, + {X86::VORPSYrr, {0, Unknown}}, + {X86::VORPSZ128rm, {1, Unknown}}, + {X86::VORPSZ128rmb, {1, Unknown}}, + {X86::VORPSZ128rmbk, {1, Unknown}}, + {X86::VORPSZ128rmbkz, {1, Unknown}}, + {X86::VORPSZ128rmk, {1, Unknown}}, + {X86::VORPSZ128rmkz, {1, Unknown}}, + {X86::VORPSZ128rr, {0, Unknown}}, + {X86::VORPSZ128rrk, {0, Unknown}}, + {X86::VORPSZ128rrkz, {0, Unknown}}, + {X86::VORPSZ256rm, {0, Unknown}}, + {X86::VORPSZ256rmb, {0, Unknown}}, + {X86::VORPSZ256rmbk, {0, Unknown}}, + {X86::VORPSZ256rmbkz, {0, Unknown}}, + {X86::VORPSZ256rmk, {0, Unknown}}, + {X86::VORPSZ256rmkz, {0, Unknown}}, + {X86::VORPSZ256rr, {0, Unknown}}, + {X86::VORPSZ256rrk, {0, Unknown}}, + {X86::VORPSZ256rrkz, {0, Unknown}}, + {X86::VORPSZrm, {0, Unknown}}, + {X86::VORPSZrmb, {0, Unknown}}, + {X86::VORPSZrmbk, {0, Unknown}}, + {X86::VORPSZrmbkz, {0, Unknown}}, + {X86::VORPSZrmk, {0, Unknown}}, + {X86::VORPSZrmkz, {0, Unknown}}, + {X86::VORPSZrr, {0, Unknown}}, + {X86::VORPSZrrk, {0, Unknown}}, + {X86::VORPSZrrkz, {0, Unknown}}, + {X86::VORPSrm, {0, Unknown}}, + {X86::VORPSrr, {0, Unknown}}, + {X86::VPABSBYrm, {0, Unknown}}, + {X86::VPABSBYrr, {0, Unknown}}, + {X86::VPABSBZ128rm, {1, Unknown}}, + {X86::VPABSBZ128rmk, {1, Unknown}}, + {X86::VPABSBZ128rmkz, {1, Unknown}}, + {X86::VPABSBZ128rr, {0, Unknown}}, + {X86::VPABSBZ128rrk, {0, Unknown}}, + {X86::VPABSBZ128rrkz, {0, Unknown}}, + {X86::VPABSBZ256rm, {0, Unknown}}, + {X86::VPABSBZ256rmk, {0, Unknown}}, + {X86::VPABSBZ256rmkz, {0, Unknown}}, + {X86::VPABSBZ256rr, {0, Unknown}}, + {X86::VPABSBZ256rrk, {0, Unknown}}, + {X86::VPABSBZ256rrkz, {0, Unknown}}, + {X86::VPABSBZrm, {0, Unknown}}, + {X86::VPABSBZrmk, {0, Unknown}}, + {X86::VPABSBZrmkz, {0, Unknown}}, + {X86::VPABSBZrr, {0, Unknown}}, + {X86::VPABSBZrrk, {0, Unknown}}, + {X86::VPABSBZrrkz, {0, Unknown}}, + {X86::VPABSBrm, {0, Unknown}}, + {X86::VPABSBrr, {0, Unknown}}, + {X86::VPABSDYrm, {0, Unknown}}, + {X86::VPABSDYrr, {0, Unknown}}, + {X86::VPABSDZ128rm, {1, Unknown}}, + {X86::VPABSDZ128rmb, {1, Unknown}}, + {X86::VPABSDZ128rmbk, {1, Unknown}}, + {X86::VPABSDZ128rmbkz, {1, Unknown}}, + {X86::VPABSDZ128rmk, {1, Unknown}}, + {X86::VPABSDZ128rmkz, {1, Unknown}}, + {X86::VPABSDZ128rr, {0, Unknown}}, + {X86::VPABSDZ128rrk, {0, Unknown}}, + {X86::VPABSDZ128rrkz, {0, Unknown}}, + {X86::VPABSDZ256rm, {0, Unknown}}, + {X86::VPABSDZ256rmb, {0, Unknown}}, + {X86::VPABSDZ256rmbk, {0, Unknown}}, + {X86::VPABSDZ256rmbkz, {0, Unknown}}, + {X86::VPABSDZ256rmk, {0, Unknown}}, + {X86::VPABSDZ256rmkz, {0, Unknown}}, + {X86::VPABSDZ256rr, {0, Unknown}}, + {X86::VPABSDZ256rrk, {0, Unknown}}, + {X86::VPABSDZ256rrkz, {0, Unknown}}, + {X86::VPABSDZrm, {0, Unknown}}, + {X86::VPABSDZrmb, {0, Unknown}}, + {X86::VPABSDZrmbk, {0, Unknown}}, + {X86::VPABSDZrmbkz, {0, Unknown}}, + {X86::VPABSDZrmk, {0, Unknown}}, + {X86::VPABSDZrmkz, {0, Unknown}}, + {X86::VPABSDZrr, {0, Unknown}}, + {X86::VPABSDZrrk, {0, Unknown}}, + {X86::VPABSDZrrkz, {0, Unknown}}, + {X86::VPABSDrm, {0, Unknown}}, + {X86::VPABSDrr, {0, Unknown}}, + {X86::VPABSQZ128rm, {1, Unknown}}, + {X86::VPABSQZ128rmb, {1, Unknown}}, + {X86::VPABSQZ128rmbk, {1, Unknown}}, + {X86::VPABSQZ128rmbkz, {1, Unknown}}, + {X86::VPABSQZ128rmk, {1, Unknown}}, + {X86::VPABSQZ128rmkz, {1, Unknown}}, + {X86::VPABSQZ128rr, {0, Unknown}}, + {X86::VPABSQZ128rrk, {0, Unknown}}, + {X86::VPABSQZ128rrkz, {0, Unknown}}, + {X86::VPABSQZ256rm, {0, Unknown}}, + {X86::VPABSQZ256rmb, {0, Unknown}}, + {X86::VPABSQZ256rmbk, {0, Unknown}}, + {X86::VPABSQZ256rmbkz, {0, Unknown}}, + {X86::VPABSQZ256rmk, {0, Unknown}}, + {X86::VPABSQZ256rmkz, {0, Unknown}}, + {X86::VPABSQZ256rr, {0, Unknown}}, + {X86::VPABSQZ256rrk, {0, Unknown}}, + {X86::VPABSQZ256rrkz, {0, Unknown}}, + {X86::VPABSQZrm, {0, Unknown}}, + {X86::VPABSQZrmb, {0, Unknown}}, + {X86::VPABSQZrmbk, {0, Unknown}}, + {X86::VPABSQZrmbkz, {0, Unknown}}, + {X86::VPABSQZrmk, {0, Unknown}}, + {X86::VPABSQZrmkz, {0, Unknown}}, + {X86::VPABSQZrr, {0, Unknown}}, + {X86::VPABSQZrrk, {0, Unknown}}, + {X86::VPABSQZrrkz, {0, Unknown}}, + {X86::VPABSWYrm, {0, Unknown}}, + {X86::VPABSWYrr, {0, Unknown}}, + {X86::VPABSWZ128rm, {1, Unknown}}, + {X86::VPABSWZ128rmk, {1, Unknown}}, + {X86::VPABSWZ128rmkz, {1, Unknown}}, + {X86::VPABSWZ128rr, {0, Unknown}}, + {X86::VPABSWZ128rrk, {0, Unknown}}, + {X86::VPABSWZ128rrkz, {0, Unknown}}, + {X86::VPABSWZ256rm, {0, Unknown}}, + {X86::VPABSWZ256rmk, {0, Unknown}}, + {X86::VPABSWZ256rmkz, {0, Unknown}}, + {X86::VPABSWZ256rr, {0, Unknown}}, + {X86::VPABSWZ256rrk, {0, Unknown}}, + {X86::VPABSWZ256rrkz, {0, Unknown}}, + {X86::VPABSWZrm, {0, Unknown}}, + {X86::VPABSWZrmk, {0, Unknown}}, + {X86::VPABSWZrmkz, {0, Unknown}}, + {X86::VPABSWZrr, {0, Unknown}}, + {X86::VPABSWZrrk, {0, Unknown}}, + {X86::VPABSWZrrkz, {0, Unknown}}, + {X86::VPABSWrm, {0, Unknown}}, + {X86::VPABSWrr, {0, Unknown}}, + {X86::VPACKSSDWYrm, {0, Unknown}}, + {X86::VPACKSSDWYrr, {0, Unknown}}, + {X86::VPACKSSDWZ128rm, {1, Unknown}}, + {X86::VPACKSSDWZ128rmb, {1, Unknown}}, + {X86::VPACKSSDWZ128rmbk, {1, Unknown}}, + {X86::VPACKSSDWZ128rmbkz, {1, Unknown}}, + {X86::VPACKSSDWZ128rmk, {1, Unknown}}, + {X86::VPACKSSDWZ128rmkz, {1, Unknown}}, + {X86::VPACKSSDWZ128rr, {0, Unknown}}, + {X86::VPACKSSDWZ128rrk, {0, Unknown}}, + {X86::VPACKSSDWZ128rrkz, {0, Unknown}}, + {X86::VPACKSSDWZ256rm, {0, Unknown}}, + {X86::VPACKSSDWZ256rmb, {0, Unknown}}, + {X86::VPACKSSDWZ256rmbk, {0, Unknown}}, + {X86::VPACKSSDWZ256rmbkz, {0, Unknown}}, + {X86::VPACKSSDWZ256rmk, {0, Unknown}}, + {X86::VPACKSSDWZ256rmkz, {0, Unknown}}, + {X86::VPACKSSDWZ256rr, {0, Unknown}}, + {X86::VPACKSSDWZ256rrk, {0, Unknown}}, + {X86::VPACKSSDWZ256rrkz, {0, Unknown}}, + {X86::VPACKSSDWZrm, {0, Unknown}}, + {X86::VPACKSSDWZrmb, {0, Unknown}}, + {X86::VPACKSSDWZrmbk, {0, Unknown}}, + {X86::VPACKSSDWZrmbkz, {0, Unknown}}, + {X86::VPACKSSDWZrmk, {0, Unknown}}, + {X86::VPACKSSDWZrmkz, {0, Unknown}}, + {X86::VPACKSSDWZrr, {0, Unknown}}, + {X86::VPACKSSDWZrrk, {0, Unknown}}, + {X86::VPACKSSDWZrrkz, {0, Unknown}}, + {X86::VPACKSSDWrm, {0, Unknown}}, + {X86::VPACKSSDWrr, {0, Unknown}}, + {X86::VPACKSSWBYrm, {0, Unknown}}, + {X86::VPACKSSWBYrr, {0, Unknown}}, + {X86::VPACKSSWBZ128rm, {1, Unknown}}, + {X86::VPACKSSWBZ128rmk, {1, Unknown}}, + {X86::VPACKSSWBZ128rmkz, {1, Unknown}}, + {X86::VPACKSSWBZ128rr, {0, Unknown}}, + {X86::VPACKSSWBZ128rrk, {0, Unknown}}, + {X86::VPACKSSWBZ128rrkz, {0, Unknown}}, + {X86::VPACKSSWBZ256rm, {0, Unknown}}, + {X86::VPACKSSWBZ256rmk, {0, Unknown}}, + {X86::VPACKSSWBZ256rmkz, {0, Unknown}}, + {X86::VPACKSSWBZ256rr, {0, Unknown}}, + {X86::VPACKSSWBZ256rrk, {0, Unknown}}, + {X86::VPACKSSWBZ256rrkz, {0, Unknown}}, + {X86::VPACKSSWBZrm, {0, Unknown}}, + {X86::VPACKSSWBZrmk, {0, Unknown}}, + {X86::VPACKSSWBZrmkz, {0, Unknown}}, + {X86::VPACKSSWBZrr, {0, Unknown}}, + {X86::VPACKSSWBZrrk, {0, Unknown}}, + {X86::VPACKSSWBZrrkz, {0, Unknown}}, + {X86::VPACKSSWBrm, {0, Unknown}}, + {X86::VPACKSSWBrr, {0, Unknown}}, + {X86::VPACKUSDWYrm, {0, Unknown}}, + {X86::VPACKUSDWYrr, {0, Unknown}}, + {X86::VPACKUSDWZ128rm, {1, Unknown}}, + {X86::VPACKUSDWZ128rmb, {1, Unknown}}, + {X86::VPACKUSDWZ128rmbk, {1, Unknown}}, + {X86::VPACKUSDWZ128rmbkz, {1, Unknown}}, + {X86::VPACKUSDWZ128rmk, {1, Unknown}}, + {X86::VPACKUSDWZ128rmkz, {1, Unknown}}, + {X86::VPACKUSDWZ128rr, {0, Unknown}}, + {X86::VPACKUSDWZ128rrk, {0, Unknown}}, + {X86::VPACKUSDWZ128rrkz, {0, Unknown}}, + {X86::VPACKUSDWZ256rm, {0, Unknown}}, + {X86::VPACKUSDWZ256rmb, {0, Unknown}}, + {X86::VPACKUSDWZ256rmbk, {0, Unknown}}, + {X86::VPACKUSDWZ256rmbkz, {0, Unknown}}, + {X86::VPACKUSDWZ256rmk, {0, Unknown}}, + {X86::VPACKUSDWZ256rmkz, {0, Unknown}}, + {X86::VPACKUSDWZ256rr, {0, Unknown}}, + {X86::VPACKUSDWZ256rrk, {0, Unknown}}, + {X86::VPACKUSDWZ256rrkz, {0, Unknown}}, + {X86::VPACKUSDWZrm, {0, Unknown}}, + {X86::VPACKUSDWZrmb, {0, Unknown}}, + {X86::VPACKUSDWZrmbk, {0, Unknown}}, + {X86::VPACKUSDWZrmbkz, {0, Unknown}}, + {X86::VPACKUSDWZrmk, {0, Unknown}}, + {X86::VPACKUSDWZrmkz, {0, Unknown}}, + {X86::VPACKUSDWZrr, {0, Unknown}}, + {X86::VPACKUSDWZrrk, {0, Unknown}}, + {X86::VPACKUSDWZrrkz, {0, Unknown}}, + {X86::VPACKUSDWrm, {0, Unknown}}, + {X86::VPACKUSDWrr, {0, Unknown}}, + {X86::VPACKUSWBYrm, {0, Unknown}}, + {X86::VPACKUSWBYrr, {0, Unknown}}, + {X86::VPACKUSWBZ128rm, {1, Unknown}}, + {X86::VPACKUSWBZ128rmk, {1, Unknown}}, + {X86::VPACKUSWBZ128rmkz, {1, Unknown}}, + {X86::VPACKUSWBZ128rr, {0, Unknown}}, + {X86::VPACKUSWBZ128rrk, {0, Unknown}}, + {X86::VPACKUSWBZ128rrkz, {0, Unknown}}, + {X86::VPACKUSWBZ256rm, {0, Unknown}}, + {X86::VPACKUSWBZ256rmk, {0, Unknown}}, + {X86::VPACKUSWBZ256rmkz, {0, Unknown}}, + {X86::VPACKUSWBZ256rr, {0, Unknown}}, + {X86::VPACKUSWBZ256rrk, {0, Unknown}}, + {X86::VPACKUSWBZ256rrkz, {0, Unknown}}, + {X86::VPACKUSWBZrm, {0, Unknown}}, + {X86::VPACKUSWBZrmk, {0, Unknown}}, + {X86::VPACKUSWBZrmkz, {0, Unknown}}, + {X86::VPACKUSWBZrr, {0, Unknown}}, + {X86::VPACKUSWBZrrk, {0, Unknown}}, + {X86::VPACKUSWBZrrkz, {0, Unknown}}, + {X86::VPACKUSWBrm, {0, Unknown}}, + {X86::VPACKUSWBrr, {0, Unknown}}, + {X86::VPADDBYrm, {0, Unknown}}, + {X86::VPADDBYrr, {0, Unknown}}, + {X86::VPADDBZ128rm, {1, Unknown}}, + {X86::VPADDBZ128rmk, {1, Unknown}}, + {X86::VPADDBZ128rmkz, {1, Unknown}}, + {X86::VPADDBZ128rr, {0, Unknown}}, + {X86::VPADDBZ128rrk, {0, Unknown}}, + {X86::VPADDBZ128rrkz, {0, Unknown}}, + {X86::VPADDBZ256rm, {0, Unknown}}, + {X86::VPADDBZ256rmk, {0, Unknown}}, + {X86::VPADDBZ256rmkz, {0, Unknown}}, + {X86::VPADDBZ256rr, {0, Unknown}}, + {X86::VPADDBZ256rrk, {0, Unknown}}, + {X86::VPADDBZ256rrkz, {0, Unknown}}, + {X86::VPADDBZrm, {0, Unknown}}, + {X86::VPADDBZrmk, {0, Unknown}}, + {X86::VPADDBZrmkz, {0, Unknown}}, + {X86::VPADDBZrr, {0, Unknown}}, + {X86::VPADDBZrrk, {0, Unknown}}, + {X86::VPADDBZrrkz, {0, Unknown}}, + {X86::VPADDBrm, {0, Unknown}}, + {X86::VPADDBrr, {0, Unknown}}, + {X86::VPADDDYrm, {0, Unknown}}, + {X86::VPADDDYrr, {0, Unknown}}, + {X86::VPADDDZ128rm, {1, Unknown}}, + {X86::VPADDDZ128rmb, {1, Unknown}}, + {X86::VPADDDZ128rmbk, {1, Unknown}}, + {X86::VPADDDZ128rmbkz, {1, Unknown}}, + {X86::VPADDDZ128rmk, {1, Unknown}}, + {X86::VPADDDZ128rmkz, {1, Unknown}}, + {X86::VPADDDZ128rr, {0, Unknown}}, + {X86::VPADDDZ128rrk, {0, Unknown}}, + {X86::VPADDDZ128rrkz, {0, Unknown}}, + {X86::VPADDDZ256rm, {0, Unknown}}, + {X86::VPADDDZ256rmb, {0, Unknown}}, + {X86::VPADDDZ256rmbk, {0, Unknown}}, + {X86::VPADDDZ256rmbkz, {0, Unknown}}, + {X86::VPADDDZ256rmk, {0, Unknown}}, + {X86::VPADDDZ256rmkz, {0, Unknown}}, + {X86::VPADDDZ256rr, {0, Unknown}}, + {X86::VPADDDZ256rrk, {0, Unknown}}, + {X86::VPADDDZ256rrkz, {0, Unknown}}, + {X86::VPADDDZrm, {0, Unknown}}, + {X86::VPADDDZrmb, {0, Unknown}}, + {X86::VPADDDZrmbk, {0, Unknown}}, + {X86::VPADDDZrmbkz, {0, Unknown}}, + {X86::VPADDDZrmk, {0, Unknown}}, + {X86::VPADDDZrmkz, {0, Unknown}}, + {X86::VPADDDZrr, {0, Unknown}}, + {X86::VPADDDZrrk, {0, Unknown}}, + {X86::VPADDDZrrkz, {0, Unknown}}, + {X86::VPADDDrm, {0, Unknown}}, + {X86::VPADDDrr, {0, Unknown}}, + {X86::VPADDQYrm, {0, Unknown}}, + {X86::VPADDQYrr, {0, Unknown}}, + {X86::VPADDQZ128rm, {1, Unknown}}, + {X86::VPADDQZ128rmb, {1, Unknown}}, + {X86::VPADDQZ128rmbk, {1, Unknown}}, + {X86::VPADDQZ128rmbkz, {1, Unknown}}, + {X86::VPADDQZ128rmk, {1, Unknown}}, + {X86::VPADDQZ128rmkz, {1, Unknown}}, + {X86::VPADDQZ128rr, {0, Unknown}}, + {X86::VPADDQZ128rrk, {0, Unknown}}, + {X86::VPADDQZ128rrkz, {0, Unknown}}, + {X86::VPADDQZ256rm, {0, Unknown}}, + {X86::VPADDQZ256rmb, {0, Unknown}}, + {X86::VPADDQZ256rmbk, {0, Unknown}}, + {X86::VPADDQZ256rmbkz, {0, Unknown}}, + {X86::VPADDQZ256rmk, {0, Unknown}}, + {X86::VPADDQZ256rmkz, {0, Unknown}}, + {X86::VPADDQZ256rr, {0, Unknown}}, + {X86::VPADDQZ256rrk, {0, Unknown}}, + {X86::VPADDQZ256rrkz, {0, Unknown}}, + {X86::VPADDQZrm, {0, Unknown}}, + {X86::VPADDQZrmb, {0, Unknown}}, + {X86::VPADDQZrmbk, {0, Unknown}}, + {X86::VPADDQZrmbkz, {0, Unknown}}, + {X86::VPADDQZrmk, {0, Unknown}}, + {X86::VPADDQZrmkz, {0, Unknown}}, + {X86::VPADDQZrr, {0, Unknown}}, + {X86::VPADDQZrrk, {0, Unknown}}, + {X86::VPADDQZrrkz, {0, Unknown}}, + {X86::VPADDQrm, {0, Unknown}}, + {X86::VPADDQrr, {0, Unknown}}, + {X86::VPADDSBYrm, {0, Unknown}}, + {X86::VPADDSBYrr, {0, Unknown}}, + {X86::VPADDSBZ128rm, {1, Unknown}}, + {X86::VPADDSBZ128rmk, {1, Unknown}}, + {X86::VPADDSBZ128rmkz, {1, Unknown}}, + {X86::VPADDSBZ128rr, {0, Unknown}}, + {X86::VPADDSBZ128rrk, {0, Unknown}}, + {X86::VPADDSBZ128rrkz, {0, Unknown}}, + {X86::VPADDSBZ256rm, {0, Unknown}}, + {X86::VPADDSBZ256rmk, {0, Unknown}}, + {X86::VPADDSBZ256rmkz, {0, Unknown}}, + {X86::VPADDSBZ256rr, {0, Unknown}}, + {X86::VPADDSBZ256rrk, {0, Unknown}}, + {X86::VPADDSBZ256rrkz, {0, Unknown}}, + {X86::VPADDSBZrm, {0, Unknown}}, + {X86::VPADDSBZrmk, {0, Unknown}}, + {X86::VPADDSBZrmkz, {0, Unknown}}, + {X86::VPADDSBZrr, {0, Unknown}}, + {X86::VPADDSBZrrk, {0, Unknown}}, + {X86::VPADDSBZrrkz, {0, Unknown}}, + {X86::VPADDSBrm, {0, Unknown}}, + {X86::VPADDSBrr, {0, Unknown}}, + {X86::VPADDSWYrm, {0, Unknown}}, + {X86::VPADDSWYrr, {0, Unknown}}, + {X86::VPADDSWZ128rm, {1, Unknown}}, + {X86::VPADDSWZ128rmk, {1, Unknown}}, + {X86::VPADDSWZ128rmkz, {1, Unknown}}, + {X86::VPADDSWZ128rr, {0, Unknown}}, + {X86::VPADDSWZ128rrk, {0, Unknown}}, + {X86::VPADDSWZ128rrkz, {0, Unknown}}, + {X86::VPADDSWZ256rm, {0, Unknown}}, + {X86::VPADDSWZ256rmk, {0, Unknown}}, + {X86::VPADDSWZ256rmkz, {0, Unknown}}, + {X86::VPADDSWZ256rr, {0, Unknown}}, + {X86::VPADDSWZ256rrk, {0, Unknown}}, + {X86::VPADDSWZ256rrkz, {0, Unknown}}, + {X86::VPADDSWZrm, {0, Unknown}}, + {X86::VPADDSWZrmk, {0, Unknown}}, + {X86::VPADDSWZrmkz, {0, Unknown}}, + {X86::VPADDSWZrr, {0, Unknown}}, + {X86::VPADDSWZrrk, {0, Unknown}}, + {X86::VPADDSWZrrkz, {0, Unknown}}, + {X86::VPADDSWrm, {0, Unknown}}, + {X86::VPADDSWrr, {0, Unknown}}, + {X86::VPADDUSBYrm, {0, Unknown}}, + {X86::VPADDUSBYrr, {0, Unknown}}, + {X86::VPADDUSBZ128rm, {1, Unknown}}, + {X86::VPADDUSBZ128rmk, {1, Unknown}}, + {X86::VPADDUSBZ128rmkz, {1, Unknown}}, + {X86::VPADDUSBZ128rr, {0, Unknown}}, + {X86::VPADDUSBZ128rrk, {0, Unknown}}, + {X86::VPADDUSBZ128rrkz, {0, Unknown}}, + {X86::VPADDUSBZ256rm, {0, Unknown}}, + {X86::VPADDUSBZ256rmk, {0, Unknown}}, + {X86::VPADDUSBZ256rmkz, {0, Unknown}}, + {X86::VPADDUSBZ256rr, {0, Unknown}}, + {X86::VPADDUSBZ256rrk, {0, Unknown}}, + {X86::VPADDUSBZ256rrkz, {0, Unknown}}, + {X86::VPADDUSBZrm, {0, Unknown}}, + {X86::VPADDUSBZrmk, {0, Unknown}}, + {X86::VPADDUSBZrmkz, {0, Unknown}}, + {X86::VPADDUSBZrr, {0, Unknown}}, + {X86::VPADDUSBZrrk, {0, Unknown}}, + {X86::VPADDUSBZrrkz, {0, Unknown}}, + {X86::VPADDUSBrm, {0, Unknown}}, + {X86::VPADDUSBrr, {0, Unknown}}, + {X86::VPADDUSWYrm, {0, Unknown}}, + {X86::VPADDUSWYrr, {0, Unknown}}, + {X86::VPADDUSWZ128rm, {1, Unknown}}, + {X86::VPADDUSWZ128rmk, {1, Unknown}}, + {X86::VPADDUSWZ128rmkz, {1, Unknown}}, + {X86::VPADDUSWZ128rr, {0, Unknown}}, + {X86::VPADDUSWZ128rrk, {0, Unknown}}, + {X86::VPADDUSWZ128rrkz, {0, Unknown}}, + {X86::VPADDUSWZ256rm, {0, Unknown}}, + {X86::VPADDUSWZ256rmk, {0, Unknown}}, + {X86::VPADDUSWZ256rmkz, {0, Unknown}}, + {X86::VPADDUSWZ256rr, {0, Unknown}}, + {X86::VPADDUSWZ256rrk, {0, Unknown}}, + {X86::VPADDUSWZ256rrkz, {0, Unknown}}, + {X86::VPADDUSWZrm, {0, Unknown}}, + {X86::VPADDUSWZrmk, {0, Unknown}}, + {X86::VPADDUSWZrmkz, {0, Unknown}}, + {X86::VPADDUSWZrr, {0, Unknown}}, + {X86::VPADDUSWZrrk, {0, Unknown}}, + {X86::VPADDUSWZrrkz, {0, Unknown}}, + {X86::VPADDUSWrm, {0, Unknown}}, + {X86::VPADDUSWrr, {0, Unknown}}, + {X86::VPADDWYrm, {0, Unknown}}, + {X86::VPADDWYrr, {0, Unknown}}, + {X86::VPADDWZ128rm, {1, Unknown}}, + {X86::VPADDWZ128rmk, {1, Unknown}}, + {X86::VPADDWZ128rmkz, {1, Unknown}}, + {X86::VPADDWZ128rr, {0, Unknown}}, + {X86::VPADDWZ128rrk, {0, Unknown}}, + {X86::VPADDWZ128rrkz, {0, Unknown}}, + {X86::VPADDWZ256rm, {0, Unknown}}, + {X86::VPADDWZ256rmk, {0, Unknown}}, + {X86::VPADDWZ256rmkz, {0, Unknown}}, + {X86::VPADDWZ256rr, {0, Unknown}}, + {X86::VPADDWZ256rrk, {0, Unknown}}, + {X86::VPADDWZ256rrkz, {0, Unknown}}, + {X86::VPADDWZrm, {0, Unknown}}, + {X86::VPADDWZrmk, {0, Unknown}}, + {X86::VPADDWZrmkz, {0, Unknown}}, + {X86::VPADDWZrr, {0, Unknown}}, + {X86::VPADDWZrrk, {0, Unknown}}, + {X86::VPADDWZrrkz, {0, Unknown}}, + {X86::VPADDWrm, {0, Unknown}}, + {X86::VPADDWrr, {0, Unknown}}, + {X86::VPALIGNRYrmi, {0, Unknown}}, + {X86::VPALIGNRYrri, {0, Unknown}}, + {X86::VPALIGNRZ128rmi, {1, Unknown}}, + {X86::VPALIGNRZ128rmik, {1, Unknown}}, + {X86::VPALIGNRZ128rmikz, {1, Unknown}}, + {X86::VPALIGNRZ128rri, {0, Unknown}}, + {X86::VPALIGNRZ128rrik, {0, Unknown}}, + {X86::VPALIGNRZ128rrikz, {0, Unknown}}, + {X86::VPALIGNRZ256rmi, {0, Unknown}}, + {X86::VPALIGNRZ256rmik, {0, Unknown}}, + {X86::VPALIGNRZ256rmikz, {0, Unknown}}, + {X86::VPALIGNRZ256rri, {0, Unknown}}, + {X86::VPALIGNRZ256rrik, {0, Unknown}}, + {X86::VPALIGNRZ256rrikz, {0, Unknown}}, + {X86::VPALIGNRZrmi, {0, Unknown}}, + {X86::VPALIGNRZrmik, {0, Unknown}}, + {X86::VPALIGNRZrmikz, {0, Unknown}}, + {X86::VPALIGNRZrri, {0, Unknown}}, + {X86::VPALIGNRZrrik, {0, Unknown}}, + {X86::VPALIGNRZrrikz, {0, Unknown}}, + {X86::VPALIGNRrmi, {0, Unknown}}, + {X86::VPALIGNRrri, {0, Unknown}}, + {X86::VPANDDZ128rm, {1, Unknown}}, + {X86::VPANDDZ128rmb, {1, Unknown}}, + {X86::VPANDDZ128rmbk, {1, Unknown}}, + {X86::VPANDDZ128rmbkz, {1, Unknown}}, + {X86::VPANDDZ128rmk, {1, Unknown}}, + {X86::VPANDDZ128rmkz, {1, Unknown}}, + {X86::VPANDDZ128rr, {0, Unknown}}, + {X86::VPANDDZ128rrk, {0, Unknown}}, + {X86::VPANDDZ128rrkz, {0, Unknown}}, + {X86::VPANDDZ256rm, {0, Unknown}}, + {X86::VPANDDZ256rmb, {0, Unknown}}, + {X86::VPANDDZ256rmbk, {0, Unknown}}, + {X86::VPANDDZ256rmbkz, {0, Unknown}}, + {X86::VPANDDZ256rmk, {0, Unknown}}, + {X86::VPANDDZ256rmkz, {0, Unknown}}, + {X86::VPANDDZ256rr, {0, Unknown}}, + {X86::VPANDDZ256rrk, {0, Unknown}}, + {X86::VPANDDZ256rrkz, {0, Unknown}}, + {X86::VPANDDZrm, {0, Unknown}}, + {X86::VPANDDZrmb, {0, Unknown}}, + {X86::VPANDDZrmbk, {0, Unknown}}, + {X86::VPANDDZrmbkz, {0, Unknown}}, + {X86::VPANDDZrmk, {0, Unknown}}, + {X86::VPANDDZrmkz, {0, Unknown}}, + {X86::VPANDDZrr, {0, Unknown}}, + {X86::VPANDDZrrk, {0, Unknown}}, + {X86::VPANDDZrrkz, {0, Unknown}}, + {X86::VPANDNDZ128rm, {1, Unknown}}, + {X86::VPANDNDZ128rmb, {1, Unknown}}, + {X86::VPANDNDZ128rmbk, {1, Unknown}}, + {X86::VPANDNDZ128rmbkz, {1, Unknown}}, + {X86::VPANDNDZ128rmk, {1, Unknown}}, + {X86::VPANDNDZ128rmkz, {1, Unknown}}, + {X86::VPANDNDZ128rr, {0, Unknown}}, + {X86::VPANDNDZ128rrk, {0, Unknown}}, + {X86::VPANDNDZ128rrkz, {0, Unknown}}, + {X86::VPANDNDZ256rm, {0, Unknown}}, + {X86::VPANDNDZ256rmb, {0, Unknown}}, + {X86::VPANDNDZ256rmbk, {0, Unknown}}, + {X86::VPANDNDZ256rmbkz, {0, Unknown}}, + {X86::VPANDNDZ256rmk, {0, Unknown}}, + {X86::VPANDNDZ256rmkz, {0, Unknown}}, + {X86::VPANDNDZ256rr, {0, Unknown}}, + {X86::VPANDNDZ256rrk, {0, Unknown}}, + {X86::VPANDNDZ256rrkz, {0, Unknown}}, + {X86::VPANDNDZrm, {0, Unknown}}, + {X86::VPANDNDZrmb, {0, Unknown}}, + {X86::VPANDNDZrmbk, {0, Unknown}}, + {X86::VPANDNDZrmbkz, {0, Unknown}}, + {X86::VPANDNDZrmk, {0, Unknown}}, + {X86::VPANDNDZrmkz, {0, Unknown}}, + {X86::VPANDNDZrr, {0, Unknown}}, + {X86::VPANDNDZrrk, {0, Unknown}}, + {X86::VPANDNDZrrkz, {0, Unknown}}, + {X86::VPANDNQZ128rm, {1, Unknown}}, + {X86::VPANDNQZ128rmb, {1, Unknown}}, + {X86::VPANDNQZ128rmbk, {1, Unknown}}, + {X86::VPANDNQZ128rmbkz, {1, Unknown}}, + {X86::VPANDNQZ128rmk, {1, Unknown}}, + {X86::VPANDNQZ128rmkz, {1, Unknown}}, + {X86::VPANDNQZ128rr, {0, Unknown}}, + {X86::VPANDNQZ128rrk, {0, Unknown}}, + {X86::VPANDNQZ128rrkz, {0, Unknown}}, + {X86::VPANDNQZ256rm, {0, Unknown}}, + {X86::VPANDNQZ256rmb, {0, Unknown}}, + {X86::VPANDNQZ256rmbk, {0, Unknown}}, + {X86::VPANDNQZ256rmbkz, {0, Unknown}}, + {X86::VPANDNQZ256rmk, {0, Unknown}}, + {X86::VPANDNQZ256rmkz, {0, Unknown}}, + {X86::VPANDNQZ256rr, {0, Unknown}}, + {X86::VPANDNQZ256rrk, {0, Unknown}}, + {X86::VPANDNQZ256rrkz, {0, Unknown}}, + {X86::VPANDNQZrm, {0, Unknown}}, + {X86::VPANDNQZrmb, {0, Unknown}}, + {X86::VPANDNQZrmbk, {0, Unknown}}, + {X86::VPANDNQZrmbkz, {0, Unknown}}, + {X86::VPANDNQZrmk, {0, Unknown}}, + {X86::VPANDNQZrmkz, {0, Unknown}}, + {X86::VPANDNQZrr, {0, Unknown}}, + {X86::VPANDNQZrrk, {0, Unknown}}, + {X86::VPANDNQZrrkz, {0, Unknown}}, + {X86::VPANDNYrm, {0, Unknown}}, + {X86::VPANDNYrr, {0, Unknown}}, + {X86::VPANDNrm, {0, Unknown}}, + {X86::VPANDNrr, {0, Unknown}}, + {X86::VPANDQZ128rm, {1, Unknown}}, + {X86::VPANDQZ128rmb, {1, Unknown}}, + {X86::VPANDQZ128rmbk, {1, Unknown}}, + {X86::VPANDQZ128rmbkz, {1, Unknown}}, + {X86::VPANDQZ128rmk, {1, Unknown}}, + {X86::VPANDQZ128rmkz, {1, Unknown}}, + {X86::VPANDQZ128rr, {0, Unknown}}, + {X86::VPANDQZ128rrk, {0, Unknown}}, + {X86::VPANDQZ128rrkz, {0, Unknown}}, + {X86::VPANDQZ256rm, {0, Unknown}}, + {X86::VPANDQZ256rmb, {0, Unknown}}, + {X86::VPANDQZ256rmbk, {0, Unknown}}, + {X86::VPANDQZ256rmbkz, {0, Unknown}}, + {X86::VPANDQZ256rmk, {0, Unknown}}, + {X86::VPANDQZ256rmkz, {0, Unknown}}, + {X86::VPANDQZ256rr, {0, Unknown}}, + {X86::VPANDQZ256rrk, {0, Unknown}}, + {X86::VPANDQZ256rrkz, {0, Unknown}}, + {X86::VPANDQZrm, {0, Unknown}}, + {X86::VPANDQZrmb, {0, Unknown}}, + {X86::VPANDQZrmbk, {0, Unknown}}, + {X86::VPANDQZrmbkz, {0, Unknown}}, + {X86::VPANDQZrmk, {0, Unknown}}, + {X86::VPANDQZrmkz, {0, Unknown}}, + {X86::VPANDQZrr, {0, Unknown}}, + {X86::VPANDQZrrk, {0, Unknown}}, + {X86::VPANDQZrrkz, {0, Unknown}}, + {X86::VPANDYrm, {0, Unknown}}, + {X86::VPANDYrr, {0, Unknown}}, + {X86::VPANDrm, {0, Unknown}}, + {X86::VPANDrr, {0, Unknown}}, + {X86::VPAVGBYrm, {0, Unknown}}, + {X86::VPAVGBYrr, {0, Unknown}}, + {X86::VPAVGBZ128rm, {1, Unknown}}, + {X86::VPAVGBZ128rmk, {1, Unknown}}, + {X86::VPAVGBZ128rmkz, {1, Unknown}}, + {X86::VPAVGBZ128rr, {0, Unknown}}, + {X86::VPAVGBZ128rrk, {0, Unknown}}, + {X86::VPAVGBZ128rrkz, {0, Unknown}}, + {X86::VPAVGBZ256rm, {0, Unknown}}, + {X86::VPAVGBZ256rmk, {0, Unknown}}, + {X86::VPAVGBZ256rmkz, {0, Unknown}}, + {X86::VPAVGBZ256rr, {0, Unknown}}, + {X86::VPAVGBZ256rrk, {0, Unknown}}, + {X86::VPAVGBZ256rrkz, {0, Unknown}}, + {X86::VPAVGBZrm, {0, Unknown}}, + {X86::VPAVGBZrmk, {0, Unknown}}, + {X86::VPAVGBZrmkz, {0, Unknown}}, + {X86::VPAVGBZrr, {0, Unknown}}, + {X86::VPAVGBZrrk, {0, Unknown}}, + {X86::VPAVGBZrrkz, {0, Unknown}}, + {X86::VPAVGBrm, {0, Unknown}}, + {X86::VPAVGBrr, {0, Unknown}}, + {X86::VPAVGWYrm, {0, Unknown}}, + {X86::VPAVGWYrr, {0, Unknown}}, + {X86::VPAVGWZ128rm, {1, Unknown}}, + {X86::VPAVGWZ128rmk, {1, Unknown}}, + {X86::VPAVGWZ128rmkz, {1, Unknown}}, + {X86::VPAVGWZ128rr, {0, Unknown}}, + {X86::VPAVGWZ128rrk, {0, Unknown}}, + {X86::VPAVGWZ128rrkz, {0, Unknown}}, + {X86::VPAVGWZ256rm, {0, Unknown}}, + {X86::VPAVGWZ256rmk, {0, Unknown}}, + {X86::VPAVGWZ256rmkz, {0, Unknown}}, + {X86::VPAVGWZ256rr, {0, Unknown}}, + {X86::VPAVGWZ256rrk, {0, Unknown}}, + {X86::VPAVGWZ256rrkz, {0, Unknown}}, + {X86::VPAVGWZrm, {0, Unknown}}, + {X86::VPAVGWZrmk, {0, Unknown}}, + {X86::VPAVGWZrmkz, {0, Unknown}}, + {X86::VPAVGWZrr, {0, Unknown}}, + {X86::VPAVGWZrrk, {0, Unknown}}, + {X86::VPAVGWZrrkz, {0, Unknown}}, + {X86::VPAVGWrm, {0, Unknown}}, + {X86::VPAVGWrr, {0, Unknown}}, + {X86::VPBLENDDYrmi, {0, Unknown}}, + {X86::VPBLENDDYrri, {0, Unknown}}, + {X86::VPBLENDDrmi, {0, Unknown}}, + {X86::VPBLENDDrri, {0, Unknown}}, + {X86::VPBLENDMBZ128rm, {1, Unknown}}, + {X86::VPBLENDMBZ128rmk, {1, Unknown}}, + {X86::VPBLENDMBZ128rmkz, {1, Unknown}}, + {X86::VPBLENDMBZ128rr, {0, Unknown}}, + {X86::VPBLENDMBZ128rrk, {0, Unknown}}, + {X86::VPBLENDMBZ128rrkz, {0, Unknown}}, + {X86::VPBLENDMBZ256rm, {0, Unknown}}, + {X86::VPBLENDMBZ256rmk, {0, Unknown}}, + {X86::VPBLENDMBZ256rmkz, {0, Unknown}}, + {X86::VPBLENDMBZ256rr, {0, Unknown}}, + {X86::VPBLENDMBZ256rrk, {0, Unknown}}, + {X86::VPBLENDMBZ256rrkz, {0, Unknown}}, + {X86::VPBLENDMBZrm, {0, Unknown}}, + {X86::VPBLENDMBZrmk, {0, Unknown}}, + {X86::VPBLENDMBZrmkz, {0, Unknown}}, + {X86::VPBLENDMBZrr, {0, Unknown}}, + {X86::VPBLENDMBZrrk, {0, Unknown}}, + {X86::VPBLENDMBZrrkz, {0, Unknown}}, + {X86::VPBLENDMDZ128rm, {1, Unknown}}, + {X86::VPBLENDMDZ128rmb, {1, Unknown}}, + {X86::VPBLENDMDZ128rmbk, {1, Unknown}}, + {X86::VPBLENDMDZ128rmbkz, {1, Unknown}}, + {X86::VPBLENDMDZ128rmk, {1, Unknown}}, + {X86::VPBLENDMDZ128rmkz, {1, Unknown}}, + {X86::VPBLENDMDZ128rr, {0, Unknown}}, + {X86::VPBLENDMDZ128rrk, {0, Unknown}}, + {X86::VPBLENDMDZ128rrkz, {0, Unknown}}, + {X86::VPBLENDMDZ256rm, {0, Unknown}}, + {X86::VPBLENDMDZ256rmb, {0, Unknown}}, + {X86::VPBLENDMDZ256rmbk, {0, Unknown}}, + {X86::VPBLENDMDZ256rmbkz, {0, Unknown}}, + {X86::VPBLENDMDZ256rmk, {0, Unknown}}, + {X86::VPBLENDMDZ256rmkz, {0, Unknown}}, + {X86::VPBLENDMDZ256rr, {0, Unknown}}, + {X86::VPBLENDMDZ256rrk, {0, Unknown}}, + {X86::VPBLENDMDZ256rrkz, {0, Unknown}}, + {X86::VPBLENDMDZrm, {0, Unknown}}, + {X86::VPBLENDMDZrmb, {0, Unknown}}, + {X86::VPBLENDMDZrmbk, {0, Unknown}}, + {X86::VPBLENDMDZrmbkz, {0, Unknown}}, + {X86::VPBLENDMDZrmk, {0, Unknown}}, + {X86::VPBLENDMDZrmkz, {0, Unknown}}, + {X86::VPBLENDMDZrr, {0, Unknown}}, + {X86::VPBLENDMDZrrk, {0, Unknown}}, + {X86::VPBLENDMDZrrkz, {0, Unknown}}, + {X86::VPBLENDMQZ128rm, {1, Unknown}}, + {X86::VPBLENDMQZ128rmb, {1, Unknown}}, + {X86::VPBLENDMQZ128rmbk, {1, Unknown}}, + {X86::VPBLENDMQZ128rmbkz, {1, Unknown}}, + {X86::VPBLENDMQZ128rmk, {1, Unknown}}, + {X86::VPBLENDMQZ128rmkz, {1, Unknown}}, + {X86::VPBLENDMQZ128rr, {0, Unknown}}, + {X86::VPBLENDMQZ128rrk, {0, Unknown}}, + {X86::VPBLENDMQZ128rrkz, {0, Unknown}}, + {X86::VPBLENDMQZ256rm, {0, Unknown}}, + {X86::VPBLENDMQZ256rmb, {0, Unknown}}, + {X86::VPBLENDMQZ256rmbk, {0, Unknown}}, + {X86::VPBLENDMQZ256rmbkz, {0, Unknown}}, + {X86::VPBLENDMQZ256rmk, {0, Unknown}}, + {X86::VPBLENDMQZ256rmkz, {0, Unknown}}, + {X86::VPBLENDMQZ256rr, {0, Unknown}}, + {X86::VPBLENDMQZ256rrk, {0, Unknown}}, + {X86::VPBLENDMQZ256rrkz, {0, Unknown}}, + {X86::VPBLENDMQZrm, {0, Unknown}}, + {X86::VPBLENDMQZrmb, {0, Unknown}}, + {X86::VPBLENDMQZrmbk, {0, Unknown}}, + {X86::VPBLENDMQZrmbkz, {0, Unknown}}, + {X86::VPBLENDMQZrmk, {0, Unknown}}, + {X86::VPBLENDMQZrmkz, {0, Unknown}}, + {X86::VPBLENDMQZrr, {0, Unknown}}, + {X86::VPBLENDMQZrrk, {0, Unknown}}, + {X86::VPBLENDMQZrrkz, {0, Unknown}}, + {X86::VPBLENDMWZ128rm, {1, Unknown}}, + {X86::VPBLENDMWZ128rmk, {1, Unknown}}, + {X86::VPBLENDMWZ128rmkz, {1, Unknown}}, + {X86::VPBLENDMWZ128rr, {0, Unknown}}, + {X86::VPBLENDMWZ128rrk, {0, Unknown}}, + {X86::VPBLENDMWZ128rrkz, {0, Unknown}}, + {X86::VPBLENDMWZ256rm, {0, Unknown}}, + {X86::VPBLENDMWZ256rmk, {0, Unknown}}, + {X86::VPBLENDMWZ256rmkz, {0, Unknown}}, + {X86::VPBLENDMWZ256rr, {0, Unknown}}, + {X86::VPBLENDMWZ256rrk, {0, Unknown}}, + {X86::VPBLENDMWZ256rrkz, {0, Unknown}}, + {X86::VPBLENDMWZrm, {0, Unknown}}, + {X86::VPBLENDMWZrmk, {0, Unknown}}, + {X86::VPBLENDMWZrmkz, {0, Unknown}}, + {X86::VPBLENDMWZrr, {0, Unknown}}, + {X86::VPBLENDMWZrrk, {0, Unknown}}, + {X86::VPBLENDMWZrrkz, {0, Unknown}}, + {X86::VPBLENDVBYrm, {0, Unknown}}, + {X86::VPBLENDVBYrr, {0, Unknown}}, + {X86::VPBLENDVBrm, {0, Unknown}}, + {X86::VPBLENDVBrr, {0, Unknown}}, + {X86::VPBLENDWYrmi, {0, Unknown}}, + {X86::VPBLENDWYrri, {0, Unknown}}, + {X86::VPBLENDWrmi, {0, Unknown}}, + {X86::VPBLENDWrri, {0, Unknown}}, + {X86::VPBROADCASTBYrm, {0, Unknown}}, + {X86::VPBROADCASTBYrr, {0, Unknown}}, + {X86::VPBROADCASTBZ128m, {0, Unknown}}, + {X86::VPBROADCASTBZ128mk, {0, Unknown}}, + {X86::VPBROADCASTBZ128mkz, {0, Unknown}}, + {X86::VPBROADCASTBZ128r, {0, Unknown}}, + {X86::VPBROADCASTBZ128rk, {0, Unknown}}, + {X86::VPBROADCASTBZ128rkz, {0, Unknown}}, + {X86::VPBROADCASTBZ256m, {0, Unknown}}, + {X86::VPBROADCASTBZ256mk, {0, Unknown}}, + {X86::VPBROADCASTBZ256mkz, {0, Unknown}}, + {X86::VPBROADCASTBZ256r, {0, Unknown}}, + {X86::VPBROADCASTBZ256rk, {0, Unknown}}, + {X86::VPBROADCASTBZ256rkz, {0, Unknown}}, + {X86::VPBROADCASTBZm, {0, Unknown}}, + {X86::VPBROADCASTBZmk, {0, Unknown}}, + {X86::VPBROADCASTBZmkz, {0, Unknown}}, + {X86::VPBROADCASTBZr, {0, Unknown}}, + {X86::VPBROADCASTBZrk, {0, Unknown}}, + {X86::VPBROADCASTBZrkz, {0, Unknown}}, + {X86::VPBROADCASTBrZ128r, {0, Unknown}}, + {X86::VPBROADCASTBrZ128rk, {0, Unknown}}, + {X86::VPBROADCASTBrZ128rkz, {0, Unknown}}, + {X86::VPBROADCASTBrZ256r, {0, Unknown}}, + {X86::VPBROADCASTBrZ256rk, {0, Unknown}}, + {X86::VPBROADCASTBrZ256rkz, {0, Unknown}}, + {X86::VPBROADCASTBrZr, {0, Unknown}}, + {X86::VPBROADCASTBrZrk, {0, Unknown}}, + {X86::VPBROADCASTBrZrkz, {0, Unknown}}, + {X86::VPBROADCASTBrm, {0, Unknown}}, + {X86::VPBROADCASTBrr, {0, Unknown}}, + {X86::VPBROADCASTDYrm, {0, Unknown}}, + {X86::VPBROADCASTDYrr, {0, Unknown}}, + {X86::VPBROADCASTDZ128m, {0, Unknown}}, + {X86::VPBROADCASTDZ128mk, {0, Unknown}}, + {X86::VPBROADCASTDZ128mkz, {0, Unknown}}, + {X86::VPBROADCASTDZ128r, {0, Unknown}}, + {X86::VPBROADCASTDZ128rk, {0, Unknown}}, + {X86::VPBROADCASTDZ128rkz, {0, Unknown}}, + {X86::VPBROADCASTDZ256m, {0, Unknown}}, + {X86::VPBROADCASTDZ256mk, {0, Unknown}}, + {X86::VPBROADCASTDZ256mkz, {0, Unknown}}, + {X86::VPBROADCASTDZ256r, {0, Unknown}}, + {X86::VPBROADCASTDZ256rk, {0, Unknown}}, + {X86::VPBROADCASTDZ256rkz, {0, Unknown}}, + {X86::VPBROADCASTDZm, {0, Unknown}}, + {X86::VPBROADCASTDZmk, {0, Unknown}}, + {X86::VPBROADCASTDZmkz, {0, Unknown}}, + {X86::VPBROADCASTDZr, {0, Unknown}}, + {X86::VPBROADCASTDZrk, {0, Unknown}}, + {X86::VPBROADCASTDZrkz, {0, Unknown}}, + {X86::VPBROADCASTDrZ128r, {0, Unknown}}, + {X86::VPBROADCASTDrZ128rk, {0, Unknown}}, + {X86::VPBROADCASTDrZ128rkz, {0, Unknown}}, + {X86::VPBROADCASTDrZ256r, {0, Unknown}}, + {X86::VPBROADCASTDrZ256rk, {0, Unknown}}, + {X86::VPBROADCASTDrZ256rkz, {0, Unknown}}, + {X86::VPBROADCASTDrZr, {0, Unknown}}, + {X86::VPBROADCASTDrZrk, {0, Unknown}}, + {X86::VPBROADCASTDrZrkz, {0, Unknown}}, + {X86::VPBROADCASTDrm, {0, Unknown}}, + {X86::VPBROADCASTDrr, {0, Unknown}}, + {X86::VPBROADCASTMB2QZ128rr, {0, Unknown}}, + {X86::VPBROADCASTMB2QZ256rr, {0, Unknown}}, + {X86::VPBROADCASTMB2QZrr, {0, Unknown}}, + {X86::VPBROADCASTMW2DZ128rr, {0, Unknown}}, + {X86::VPBROADCASTMW2DZ256rr, {0, Unknown}}, + {X86::VPBROADCASTMW2DZrr, {0, Unknown}}, + {X86::VPBROADCASTQYrm, {0, Unknown}}, + {X86::VPBROADCASTQYrr, {0, Unknown}}, + {X86::VPBROADCASTQZ128m, {0, Unknown}}, + {X86::VPBROADCASTQZ128mk, {0, Unknown}}, + {X86::VPBROADCASTQZ128mkz, {0, Unknown}}, + {X86::VPBROADCASTQZ128r, {0, Unknown}}, + {X86::VPBROADCASTQZ128rk, {0, Unknown}}, + {X86::VPBROADCASTQZ128rkz, {0, Unknown}}, + {X86::VPBROADCASTQZ256m, {0, Unknown}}, + {X86::VPBROADCASTQZ256mk, {0, Unknown}}, + {X86::VPBROADCASTQZ256mkz, {0, Unknown}}, + {X86::VPBROADCASTQZ256r, {0, Unknown}}, + {X86::VPBROADCASTQZ256rk, {0, Unknown}}, + {X86::VPBROADCASTQZ256rkz, {0, Unknown}}, + {X86::VPBROADCASTQZm, {0, Unknown}}, + {X86::VPBROADCASTQZmk, {0, Unknown}}, + {X86::VPBROADCASTQZmkz, {0, Unknown}}, + {X86::VPBROADCASTQZr, {0, Unknown}}, + {X86::VPBROADCASTQZrk, {0, Unknown}}, + {X86::VPBROADCASTQZrkz, {0, Unknown}}, + {X86::VPBROADCASTQrZ128r, {0, Unknown}}, + {X86::VPBROADCASTQrZ128rk, {0, Unknown}}, + {X86::VPBROADCASTQrZ128rkz, {0, Unknown}}, + {X86::VPBROADCASTQrZ256r, {0, Unknown}}, + {X86::VPBROADCASTQrZ256rk, {0, Unknown}}, + {X86::VPBROADCASTQrZ256rkz, {0, Unknown}}, + {X86::VPBROADCASTQrZr, {0, Unknown}}, + {X86::VPBROADCASTQrZrk, {0, Unknown}}, + {X86::VPBROADCASTQrZrkz, {0, Unknown}}, + {X86::VPBROADCASTQrm, {0, Unknown}}, + {X86::VPBROADCASTQrr, {0, Unknown}}, + {X86::VPBROADCASTWYrm, {0, Unknown}}, + {X86::VPBROADCASTWYrr, {0, Unknown}}, + {X86::VPBROADCASTWZ128m, {0, Unknown}}, + {X86::VPBROADCASTWZ128mk, {0, Unknown}}, + {X86::VPBROADCASTWZ128mkz, {0, Unknown}}, + {X86::VPBROADCASTWZ128r, {0, Unknown}}, + {X86::VPBROADCASTWZ128rk, {0, Unknown}}, + {X86::VPBROADCASTWZ128rkz, {0, Unknown}}, + {X86::VPBROADCASTWZ256m, {0, Unknown}}, + {X86::VPBROADCASTWZ256mk, {0, Unknown}}, + {X86::VPBROADCASTWZ256mkz, {0, Unknown}}, + {X86::VPBROADCASTWZ256r, {0, Unknown}}, + {X86::VPBROADCASTWZ256rk, {0, Unknown}}, + {X86::VPBROADCASTWZ256rkz, {0, Unknown}}, + {X86::VPBROADCASTWZm, {0, Unknown}}, + {X86::VPBROADCASTWZmk, {0, Unknown}}, + {X86::VPBROADCASTWZmkz, {0, Unknown}}, + {X86::VPBROADCASTWZr, {0, Unknown}}, + {X86::VPBROADCASTWZrk, {0, Unknown}}, + {X86::VPBROADCASTWZrkz, {0, Unknown}}, + {X86::VPBROADCASTWrZ128r, {0, Unknown}}, + {X86::VPBROADCASTWrZ128rk, {0, Unknown}}, + {X86::VPBROADCASTWrZ128rkz, {0, Unknown}}, + {X86::VPBROADCASTWrZ256r, {0, Unknown}}, + {X86::VPBROADCASTWrZ256rk, {0, Unknown}}, + {X86::VPBROADCASTWrZ256rkz, {0, Unknown}}, + {X86::VPBROADCASTWrZr, {0, Unknown}}, + {X86::VPBROADCASTWrZrk, {0, Unknown}}, + {X86::VPBROADCASTWrZrkz, {0, Unknown}}, + {X86::VPBROADCASTWrm, {0, Unknown}}, + {X86::VPBROADCASTWrr, {0, Unknown}}, + {X86::VPCLMULQDQYrm, {0, Unknown}}, + {X86::VPCLMULQDQYrr, {0, Unknown}}, + {X86::VPCLMULQDQZ128rm, {1, Unknown}}, + {X86::VPCLMULQDQZ128rr, {0, Unknown}}, + {X86::VPCLMULQDQZ256rm, {0, Unknown}}, + {X86::VPCLMULQDQZ256rr, {0, Unknown}}, + {X86::VPCLMULQDQZrm, {0, Unknown}}, + {X86::VPCLMULQDQZrr, {0, Unknown}}, + {X86::VPCLMULQDQrm, {0, Unknown}}, + {X86::VPCLMULQDQrr, {0, Unknown}}, + {X86::VPCMOVYrmr, {0, Unknown}}, + {X86::VPCMOVYrrm, {0, Unknown}}, + {X86::VPCMOVYrrr, {0, Unknown}}, + {X86::VPCMOVYrrr_REV, {0, Unknown}}, + {X86::VPCMOVrmr, {0, Unknown}}, + {X86::VPCMOVrrm, {0, Unknown}}, + {X86::VPCMOVrrr, {0, Unknown}}, + {X86::VPCMOVrrr_REV, {0, Unknown}}, + {X86::VPCMPBZ128rmi, {1, Unknown}}, + {X86::VPCMPBZ128rmi_alt, {1, Unknown}}, + {X86::VPCMPBZ128rmik, {1, Unknown}}, + {X86::VPCMPBZ128rmik_alt, {1, Unknown}}, + {X86::VPCMPBZ128rri, {0, Unknown}}, + {X86::VPCMPBZ128rri_alt, {0, Unknown}}, + {X86::VPCMPBZ128rrik, {0, Unknown}}, + {X86::VPCMPBZ128rrik_alt, {0, Unknown}}, + {X86::VPCMPBZ256rmi, {0, Unknown}}, + {X86::VPCMPBZ256rmi_alt, {0, Unknown}}, + {X86::VPCMPBZ256rmik, {0, Unknown}}, + {X86::VPCMPBZ256rmik_alt, {0, Unknown}}, + {X86::VPCMPBZ256rri, {0, Unknown}}, + {X86::VPCMPBZ256rri_alt, {0, Unknown}}, + {X86::VPCMPBZ256rrik, {0, Unknown}}, + {X86::VPCMPBZ256rrik_alt, {0, Unknown}}, + {X86::VPCMPBZrmi, {0, Unknown}}, + {X86::VPCMPBZrmi_alt, {0, Unknown}}, + {X86::VPCMPBZrmik, {0, Unknown}}, + {X86::VPCMPBZrmik_alt, {0, Unknown}}, + {X86::VPCMPBZrri, {0, Unknown}}, + {X86::VPCMPBZrri_alt, {0, Unknown}}, + {X86::VPCMPBZrrik, {0, Unknown}}, + {X86::VPCMPBZrrik_alt, {0, Unknown}}, + {X86::VPCMPDZ128rmi, {1, Unknown}}, + {X86::VPCMPDZ128rmi_alt, {1, Unknown}}, + {X86::VPCMPDZ128rmib, {1, Unknown}}, + {X86::VPCMPDZ128rmib_alt, {1, Unknown}}, + {X86::VPCMPDZ128rmibk, {1, Unknown}}, + {X86::VPCMPDZ128rmibk_alt, {1, Unknown}}, + {X86::VPCMPDZ128rmik, {1, Unknown}}, + {X86::VPCMPDZ128rmik_alt, {1, Unknown}}, + {X86::VPCMPDZ128rri, {0, Unknown}}, + {X86::VPCMPDZ128rri_alt, {0, Unknown}}, + {X86::VPCMPDZ128rrik, {0, Unknown}}, + {X86::VPCMPDZ128rrik_alt, {0, Unknown}}, + {X86::VPCMPDZ256rmi, {0, Unknown}}, + {X86::VPCMPDZ256rmi_alt, {0, Unknown}}, + {X86::VPCMPDZ256rmib, {0, Unknown}}, + {X86::VPCMPDZ256rmib_alt, {0, Unknown}}, + {X86::VPCMPDZ256rmibk, {0, Unknown}}, + {X86::VPCMPDZ256rmibk_alt, {0, Unknown}}, + {X86::VPCMPDZ256rmik, {0, Unknown}}, + {X86::VPCMPDZ256rmik_alt, {0, Unknown}}, + {X86::VPCMPDZ256rri, {0, Unknown}}, + {X86::VPCMPDZ256rri_alt, {0, Unknown}}, + {X86::VPCMPDZ256rrik, {0, Unknown}}, + {X86::VPCMPDZ256rrik_alt, {0, Unknown}}, + {X86::VPCMPDZrmi, {0, Unknown}}, + {X86::VPCMPDZrmi_alt, {0, Unknown}}, + {X86::VPCMPDZrmib, {0, Unknown}}, + {X86::VPCMPDZrmib_alt, {0, Unknown}}, + {X86::VPCMPDZrmibk, {0, Unknown}}, + {X86::VPCMPDZrmibk_alt, {0, Unknown}}, + {X86::VPCMPDZrmik, {0, Unknown}}, + {X86::VPCMPDZrmik_alt, {0, Unknown}}, + {X86::VPCMPDZrri, {0, Unknown}}, + {X86::VPCMPDZrri_alt, {0, Unknown}}, + {X86::VPCMPDZrrik, {0, Unknown}}, + {X86::VPCMPDZrrik_alt, {0, Unknown}}, + {X86::VPCMPEQBYrm, {0, Unknown}}, + {X86::VPCMPEQBYrr, {0, Unknown}}, + {X86::VPCMPEQBZ128rm, {1, Unknown}}, + {X86::VPCMPEQBZ128rmk, {1, Unknown}}, + {X86::VPCMPEQBZ128rr, {0, Unknown}}, + {X86::VPCMPEQBZ128rrk, {0, Unknown}}, + {X86::VPCMPEQBZ256rm, {0, Unknown}}, + {X86::VPCMPEQBZ256rmk, {0, Unknown}}, + {X86::VPCMPEQBZ256rr, {0, Unknown}}, + {X86::VPCMPEQBZ256rrk, {0, Unknown}}, + {X86::VPCMPEQBZrm, {0, Unknown}}, + {X86::VPCMPEQBZrmk, {0, Unknown}}, + {X86::VPCMPEQBZrr, {0, Unknown}}, + {X86::VPCMPEQBZrrk, {0, Unknown}}, + {X86::VPCMPEQBrm, {0, Unknown}}, + {X86::VPCMPEQBrr, {0, Unknown}}, + {X86::VPCMPEQDYrm, {0, Unknown}}, + {X86::VPCMPEQDYrr, {0, Unknown}}, + {X86::VPCMPEQDZ128rm, {1, Unknown}}, + {X86::VPCMPEQDZ128rmb, {1, Unknown}}, + {X86::VPCMPEQDZ128rmbk, {1, Unknown}}, + {X86::VPCMPEQDZ128rmk, {1, Unknown}}, + {X86::VPCMPEQDZ128rr, {0, Unknown}}, + {X86::VPCMPEQDZ128rrk, {0, Unknown}}, + {X86::VPCMPEQDZ256rm, {0, Unknown}}, + {X86::VPCMPEQDZ256rmb, {0, Unknown}}, + {X86::VPCMPEQDZ256rmbk, {0, Unknown}}, + {X86::VPCMPEQDZ256rmk, {0, Unknown}}, + {X86::VPCMPEQDZ256rr, {0, Unknown}}, + {X86::VPCMPEQDZ256rrk, {0, Unknown}}, + {X86::VPCMPEQDZrm, {0, Unknown}}, + {X86::VPCMPEQDZrmb, {0, Unknown}}, + {X86::VPCMPEQDZrmbk, {0, Unknown}}, + {X86::VPCMPEQDZrmk, {0, Unknown}}, + {X86::VPCMPEQDZrr, {0, Unknown}}, + {X86::VPCMPEQDZrrk, {0, Unknown}}, + {X86::VPCMPEQDrm, {0, Unknown}}, + {X86::VPCMPEQDrr, {0, Unknown}}, + {X86::VPCMPEQQYrm, {0, Unknown}}, + {X86::VPCMPEQQYrr, {0, Unknown}}, + {X86::VPCMPEQQZ128rm, {1, Unknown}}, + {X86::VPCMPEQQZ128rmb, {1, Unknown}}, + {X86::VPCMPEQQZ128rmbk, {1, Unknown}}, + {X86::VPCMPEQQZ128rmk, {1, Unknown}}, + {X86::VPCMPEQQZ128rr, {0, Unknown}}, + {X86::VPCMPEQQZ128rrk, {0, Unknown}}, + {X86::VPCMPEQQZ256rm, {0, Unknown}}, + {X86::VPCMPEQQZ256rmb, {0, Unknown}}, + {X86::VPCMPEQQZ256rmbk, {0, Unknown}}, + {X86::VPCMPEQQZ256rmk, {0, Unknown}}, + {X86::VPCMPEQQZ256rr, {0, Unknown}}, + {X86::VPCMPEQQZ256rrk, {0, Unknown}}, + {X86::VPCMPEQQZrm, {0, Unknown}}, + {X86::VPCMPEQQZrmb, {0, Unknown}}, + {X86::VPCMPEQQZrmbk, {0, Unknown}}, + {X86::VPCMPEQQZrmk, {0, Unknown}}, + {X86::VPCMPEQQZrr, {0, Unknown}}, + {X86::VPCMPEQQZrrk, {0, Unknown}}, + {X86::VPCMPEQQrm, {0, Unknown}}, + {X86::VPCMPEQQrr, {0, Unknown}}, + {X86::VPCMPEQWYrm, {0, Unknown}}, + {X86::VPCMPEQWYrr, {0, Unknown}}, + {X86::VPCMPEQWZ128rm, {1, Unknown}}, + {X86::VPCMPEQWZ128rmk, {1, Unknown}}, + {X86::VPCMPEQWZ128rr, {0, Unknown}}, + {X86::VPCMPEQWZ128rrk, {0, Unknown}}, + {X86::VPCMPEQWZ256rm, {0, Unknown}}, + {X86::VPCMPEQWZ256rmk, {0, Unknown}}, + {X86::VPCMPEQWZ256rr, {0, Unknown}}, + {X86::VPCMPEQWZ256rrk, {0, Unknown}}, + {X86::VPCMPEQWZrm, {0, Unknown}}, + {X86::VPCMPEQWZrmk, {0, Unknown}}, + {X86::VPCMPEQWZrr, {0, Unknown}}, + {X86::VPCMPEQWZrrk, {0, Unknown}}, + {X86::VPCMPEQWrm, {0, Unknown}}, + {X86::VPCMPEQWrr, {0, Unknown}}, + {X86::VPCMPGTBYrm, {0, Unknown}}, + {X86::VPCMPGTBYrr, {0, Unknown}}, + {X86::VPCMPGTBZ128rm, {1, Unknown}}, + {X86::VPCMPGTBZ128rmk, {1, Unknown}}, + {X86::VPCMPGTBZ128rr, {0, Unknown}}, + {X86::VPCMPGTBZ128rrk, {0, Unknown}}, + {X86::VPCMPGTBZ256rm, {0, Unknown}}, + {X86::VPCMPGTBZ256rmk, {0, Unknown}}, + {X86::VPCMPGTBZ256rr, {0, Unknown}}, + {X86::VPCMPGTBZ256rrk, {0, Unknown}}, + {X86::VPCMPGTBZrm, {0, Unknown}}, + {X86::VPCMPGTBZrmk, {0, Unknown}}, + {X86::VPCMPGTBZrr, {0, Unknown}}, + {X86::VPCMPGTBZrrk, {0, Unknown}}, + {X86::VPCMPGTBrm, {0, Unknown}}, + {X86::VPCMPGTBrr, {0, Unknown}}, + {X86::VPCMPGTDYrm, {0, Unknown}}, + {X86::VPCMPGTDYrr, {0, Unknown}}, + {X86::VPCMPGTDZ128rm, {1, Unknown}}, + {X86::VPCMPGTDZ128rmb, {1, Unknown}}, + {X86::VPCMPGTDZ128rmbk, {1, Unknown}}, + {X86::VPCMPGTDZ128rmk, {1, Unknown}}, + {X86::VPCMPGTDZ128rr, {0, Unknown}}, + {X86::VPCMPGTDZ128rrk, {0, Unknown}}, + {X86::VPCMPGTDZ256rm, {0, Unknown}}, + {X86::VPCMPGTDZ256rmb, {0, Unknown}}, + {X86::VPCMPGTDZ256rmbk, {0, Unknown}}, + {X86::VPCMPGTDZ256rmk, {0, Unknown}}, + {X86::VPCMPGTDZ256rr, {0, Unknown}}, + {X86::VPCMPGTDZ256rrk, {0, Unknown}}, + {X86::VPCMPGTDZrm, {0, Unknown}}, + {X86::VPCMPGTDZrmb, {0, Unknown}}, + {X86::VPCMPGTDZrmbk, {0, Unknown}}, + {X86::VPCMPGTDZrmk, {0, Unknown}}, + {X86::VPCMPGTDZrr, {0, Unknown}}, + {X86::VPCMPGTDZrrk, {0, Unknown}}, + {X86::VPCMPGTDrm, {0, Unknown}}, + {X86::VPCMPGTDrr, {0, Unknown}}, + {X86::VPCMPGTQYrm, {0, Unknown}}, + {X86::VPCMPGTQYrr, {0, Unknown}}, + {X86::VPCMPGTQZ128rm, {1, Unknown}}, + {X86::VPCMPGTQZ128rmb, {1, Unknown}}, + {X86::VPCMPGTQZ128rmbk, {1, Unknown}}, + {X86::VPCMPGTQZ128rmk, {1, Unknown}}, + {X86::VPCMPGTQZ128rr, {0, Unknown}}, + {X86::VPCMPGTQZ128rrk, {0, Unknown}}, + {X86::VPCMPGTQZ256rm, {0, Unknown}}, + {X86::VPCMPGTQZ256rmb, {0, Unknown}}, + {X86::VPCMPGTQZ256rmbk, {0, Unknown}}, + {X86::VPCMPGTQZ256rmk, {0, Unknown}}, + {X86::VPCMPGTQZ256rr, {0, Unknown}}, + {X86::VPCMPGTQZ256rrk, {0, Unknown}}, + {X86::VPCMPGTQZrm, {0, Unknown}}, + {X86::VPCMPGTQZrmb, {0, Unknown}}, + {X86::VPCMPGTQZrmbk, {0, Unknown}}, + {X86::VPCMPGTQZrmk, {0, Unknown}}, + {X86::VPCMPGTQZrr, {0, Unknown}}, + {X86::VPCMPGTQZrrk, {0, Unknown}}, + {X86::VPCMPGTQrm, {0, Unknown}}, + {X86::VPCMPGTQrr, {0, Unknown}}, + {X86::VPCMPGTWYrm, {0, Unknown}}, + {X86::VPCMPGTWYrr, {0, Unknown}}, + {X86::VPCMPGTWZ128rm, {1, Unknown}}, + {X86::VPCMPGTWZ128rmk, {1, Unknown}}, + {X86::VPCMPGTWZ128rr, {0, Unknown}}, + {X86::VPCMPGTWZ128rrk, {0, Unknown}}, + {X86::VPCMPGTWZ256rm, {0, Unknown}}, + {X86::VPCMPGTWZ256rmk, {0, Unknown}}, + {X86::VPCMPGTWZ256rr, {0, Unknown}}, + {X86::VPCMPGTWZ256rrk, {0, Unknown}}, + {X86::VPCMPGTWZrm, {0, Unknown}}, + {X86::VPCMPGTWZrmk, {0, Unknown}}, + {X86::VPCMPGTWZrr, {0, Unknown}}, + {X86::VPCMPGTWZrrk, {0, Unknown}}, + {X86::VPCMPGTWrm, {0, Unknown}}, + {X86::VPCMPGTWrr, {0, Unknown}}, + {X86::VPCMPISTRIrm, {0, Unknown}}, + {X86::VPCMPISTRIrr, {0, Unknown}}, + {X86::VPCMPQZ128rmi, {1, Unknown}}, + {X86::VPCMPQZ128rmi_alt, {1, Unknown}}, + {X86::VPCMPQZ128rmib, {1, Unknown}}, + {X86::VPCMPQZ128rmib_alt, {1, Unknown}}, + {X86::VPCMPQZ128rmibk, {1, Unknown}}, + {X86::VPCMPQZ128rmibk_alt, {1, Unknown}}, + {X86::VPCMPQZ128rmik, {1, Unknown}}, + {X86::VPCMPQZ128rmik_alt, {1, Unknown}}, + {X86::VPCMPQZ128rri, {0, Unknown}}, + {X86::VPCMPQZ128rri_alt, {0, Unknown}}, + {X86::VPCMPQZ128rrik, {0, Unknown}}, + {X86::VPCMPQZ128rrik_alt, {0, Unknown}}, + {X86::VPCMPQZ256rmi, {0, Unknown}}, + {X86::VPCMPQZ256rmi_alt, {0, Unknown}}, + {X86::VPCMPQZ256rmib, {0, Unknown}}, + {X86::VPCMPQZ256rmib_alt, {0, Unknown}}, + {X86::VPCMPQZ256rmibk, {0, Unknown}}, + {X86::VPCMPQZ256rmibk_alt, {0, Unknown}}, + {X86::VPCMPQZ256rmik, {0, Unknown}}, + {X86::VPCMPQZ256rmik_alt, {0, Unknown}}, + {X86::VPCMPQZ256rri, {0, Unknown}}, + {X86::VPCMPQZ256rri_alt, {0, Unknown}}, + {X86::VPCMPQZ256rrik, {0, Unknown}}, + {X86::VPCMPQZ256rrik_alt, {0, Unknown}}, + {X86::VPCMPQZrmi, {0, Unknown}}, + {X86::VPCMPQZrmi_alt, {0, Unknown}}, + {X86::VPCMPQZrmib, {0, Unknown}}, + {X86::VPCMPQZrmib_alt, {0, Unknown}}, + {X86::VPCMPQZrmibk, {0, Unknown}}, + {X86::VPCMPQZrmibk_alt, {0, Unknown}}, + {X86::VPCMPQZrmik, {0, Unknown}}, + {X86::VPCMPQZrmik_alt, {0, Unknown}}, + {X86::VPCMPQZrri, {0, Unknown}}, + {X86::VPCMPQZrri_alt, {0, Unknown}}, + {X86::VPCMPQZrrik, {0, Unknown}}, + {X86::VPCMPQZrrik_alt, {0, Unknown}}, + {X86::VPCMPUBZ128rmi, {1, Unknown}}, + {X86::VPCMPUBZ128rmi_alt, {1, Unknown}}, + {X86::VPCMPUBZ128rmik, {1, Unknown}}, + {X86::VPCMPUBZ128rmik_alt, {1, Unknown}}, + {X86::VPCMPUBZ128rri, {0, Unknown}}, + {X86::VPCMPUBZ128rri_alt, {0, Unknown}}, + {X86::VPCMPUBZ128rrik, {0, Unknown}}, + {X86::VPCMPUBZ128rrik_alt, {0, Unknown}}, + {X86::VPCMPUBZ256rmi, {0, Unknown}}, + {X86::VPCMPUBZ256rmi_alt, {0, Unknown}}, + {X86::VPCMPUBZ256rmik, {0, Unknown}}, + {X86::VPCMPUBZ256rmik_alt, {0, Unknown}}, + {X86::VPCMPUBZ256rri, {0, Unknown}}, + {X86::VPCMPUBZ256rri_alt, {0, Unknown}}, + {X86::VPCMPUBZ256rrik, {0, Unknown}}, + {X86::VPCMPUBZ256rrik_alt, {0, Unknown}}, + {X86::VPCMPUBZrmi, {0, Unknown}}, + {X86::VPCMPUBZrmi_alt, {0, Unknown}}, + {X86::VPCMPUBZrmik, {0, Unknown}}, + {X86::VPCMPUBZrmik_alt, {0, Unknown}}, + {X86::VPCMPUBZrri, {0, Unknown}}, + {X86::VPCMPUBZrri_alt, {0, Unknown}}, + {X86::VPCMPUBZrrik, {0, Unknown}}, + {X86::VPCMPUBZrrik_alt, {0, Unknown}}, + {X86::VPCMPUDZ128rmi, {1, Unknown}}, + {X86::VPCMPUDZ128rmi_alt, {1, Unknown}}, + {X86::VPCMPUDZ128rmib, {1, Unknown}}, + {X86::VPCMPUDZ128rmib_alt, {1, Unknown}}, + {X86::VPCMPUDZ128rmibk, {1, Unknown}}, + {X86::VPCMPUDZ128rmibk_alt, {1, Unknown}}, + {X86::VPCMPUDZ128rmik, {1, Unknown}}, + {X86::VPCMPUDZ128rmik_alt, {1, Unknown}}, + {X86::VPCMPUDZ128rri, {0, Unknown}}, + {X86::VPCMPUDZ128rri_alt, {0, Unknown}}, + {X86::VPCMPUDZ128rrik, {0, Unknown}}, + {X86::VPCMPUDZ128rrik_alt, {0, Unknown}}, + {X86::VPCMPUDZ256rmi, {0, Unknown}}, + {X86::VPCMPUDZ256rmi_alt, {0, Unknown}}, + {X86::VPCMPUDZ256rmib, {0, Unknown}}, + {X86::VPCMPUDZ256rmib_alt, {0, Unknown}}, + {X86::VPCMPUDZ256rmibk, {0, Unknown}}, + {X86::VPCMPUDZ256rmibk_alt, {0, Unknown}}, + {X86::VPCMPUDZ256rmik, {0, Unknown}}, + {X86::VPCMPUDZ256rmik_alt, {0, Unknown}}, + {X86::VPCMPUDZ256rri, {0, Unknown}}, + {X86::VPCMPUDZ256rri_alt, {0, Unknown}}, + {X86::VPCMPUDZ256rrik, {0, Unknown}}, + {X86::VPCMPUDZ256rrik_alt, {0, Unknown}}, + {X86::VPCMPUDZrmi, {0, Unknown}}, + {X86::VPCMPUDZrmi_alt, {0, Unknown}}, + {X86::VPCMPUDZrmib, {0, Unknown}}, + {X86::VPCMPUDZrmib_alt, {0, Unknown}}, + {X86::VPCMPUDZrmibk, {0, Unknown}}, + {X86::VPCMPUDZrmibk_alt, {0, Unknown}}, + {X86::VPCMPUDZrmik, {0, Unknown}}, + {X86::VPCMPUDZrmik_alt, {0, Unknown}}, + {X86::VPCMPUDZrri, {0, Unknown}}, + {X86::VPCMPUDZrri_alt, {0, Unknown}}, + {X86::VPCMPUDZrrik, {0, Unknown}}, + {X86::VPCMPUDZrrik_alt, {0, Unknown}}, + {X86::VPCMPUQZ128rmi, {1, Unknown}}, + {X86::VPCMPUQZ128rmi_alt, {1, Unknown}}, + {X86::VPCMPUQZ128rmib, {1, Unknown}}, + {X86::VPCMPUQZ128rmib_alt, {1, Unknown}}, + {X86::VPCMPUQZ128rmibk, {1, Unknown}}, + {X86::VPCMPUQZ128rmibk_alt, {1, Unknown}}, + {X86::VPCMPUQZ128rmik, {1, Unknown}}, + {X86::VPCMPUQZ128rmik_alt, {1, Unknown}}, + {X86::VPCMPUQZ128rri, {0, Unknown}}, + {X86::VPCMPUQZ128rri_alt, {0, Unknown}}, + {X86::VPCMPUQZ128rrik, {0, Unknown}}, + {X86::VPCMPUQZ128rrik_alt, {0, Unknown}}, + {X86::VPCMPUQZ256rmi, {0, Unknown}}, + {X86::VPCMPUQZ256rmi_alt, {0, Unknown}}, + {X86::VPCMPUQZ256rmib, {0, Unknown}}, + {X86::VPCMPUQZ256rmib_alt, {0, Unknown}}, + {X86::VPCMPUQZ256rmibk, {0, Unknown}}, + {X86::VPCMPUQZ256rmibk_alt, {0, Unknown}}, + {X86::VPCMPUQZ256rmik, {0, Unknown}}, + {X86::VPCMPUQZ256rmik_alt, {0, Unknown}}, + {X86::VPCMPUQZ256rri, {0, Unknown}}, + {X86::VPCMPUQZ256rri_alt, {0, Unknown}}, + {X86::VPCMPUQZ256rrik, {0, Unknown}}, + {X86::VPCMPUQZ256rrik_alt, {0, Unknown}}, + {X86::VPCMPUQZrmi, {0, Unknown}}, + {X86::VPCMPUQZrmi_alt, {0, Unknown}}, + {X86::VPCMPUQZrmib, {0, Unknown}}, + {X86::VPCMPUQZrmib_alt, {0, Unknown}}, + {X86::VPCMPUQZrmibk, {0, Unknown}}, + {X86::VPCMPUQZrmibk_alt, {0, Unknown}}, + {X86::VPCMPUQZrmik, {0, Unknown}}, + {X86::VPCMPUQZrmik_alt, {0, Unknown}}, + {X86::VPCMPUQZrri, {0, Unknown}}, + {X86::VPCMPUQZrri_alt, {0, Unknown}}, + {X86::VPCMPUQZrrik, {0, Unknown}}, + {X86::VPCMPUQZrrik_alt, {0, Unknown}}, + {X86::VPCMPUWZ128rmi, {1, Unknown}}, + {X86::VPCMPUWZ128rmi_alt, {1, Unknown}}, + {X86::VPCMPUWZ128rmik, {1, Unknown}}, + {X86::VPCMPUWZ128rmik_alt, {1, Unknown}}, + {X86::VPCMPUWZ128rri, {0, Unknown}}, + {X86::VPCMPUWZ128rri_alt, {0, Unknown}}, + {X86::VPCMPUWZ128rrik, {0, Unknown}}, + {X86::VPCMPUWZ128rrik_alt, {0, Unknown}}, + {X86::VPCMPUWZ256rmi, {0, Unknown}}, + {X86::VPCMPUWZ256rmi_alt, {0, Unknown}}, + {X86::VPCMPUWZ256rmik, {0, Unknown}}, + {X86::VPCMPUWZ256rmik_alt, {0, Unknown}}, + {X86::VPCMPUWZ256rri, {0, Unknown}}, + {X86::VPCMPUWZ256rri_alt, {0, Unknown}}, + {X86::VPCMPUWZ256rrik, {0, Unknown}}, + {X86::VPCMPUWZ256rrik_alt, {0, Unknown}}, + {X86::VPCMPUWZrmi, {0, Unknown}}, + {X86::VPCMPUWZrmi_alt, {0, Unknown}}, + {X86::VPCMPUWZrmik, {0, Unknown}}, + {X86::VPCMPUWZrmik_alt, {0, Unknown}}, + {X86::VPCMPUWZrri, {0, Unknown}}, + {X86::VPCMPUWZrri_alt, {0, Unknown}}, + {X86::VPCMPUWZrrik, {0, Unknown}}, + {X86::VPCMPUWZrrik_alt, {0, Unknown}}, + {X86::VPCMPWZ128rmi, {1, Unknown}}, + {X86::VPCMPWZ128rmi_alt, {1, Unknown}}, + {X86::VPCMPWZ128rmik, {1, Unknown}}, + {X86::VPCMPWZ128rmik_alt, {1, Unknown}}, + {X86::VPCMPWZ128rri, {0, Unknown}}, + {X86::VPCMPWZ128rri_alt, {0, Unknown}}, + {X86::VPCMPWZ128rrik, {0, Unknown}}, + {X86::VPCMPWZ128rrik_alt, {0, Unknown}}, + {X86::VPCMPWZ256rmi, {0, Unknown}}, + {X86::VPCMPWZ256rmi_alt, {0, Unknown}}, + {X86::VPCMPWZ256rmik, {0, Unknown}}, + {X86::VPCMPWZ256rmik_alt, {0, Unknown}}, + {X86::VPCMPWZ256rri, {0, Unknown}}, + {X86::VPCMPWZ256rri_alt, {0, Unknown}}, + {X86::VPCMPWZ256rrik, {0, Unknown}}, + {X86::VPCMPWZ256rrik_alt, {0, Unknown}}, + {X86::VPCMPWZrmi, {0, Unknown}}, + {X86::VPCMPWZrmi_alt, {0, Unknown}}, + {X86::VPCMPWZrmik, {0, Unknown}}, + {X86::VPCMPWZrmik_alt, {0, Unknown}}, + {X86::VPCMPWZrri, {0, Unknown}}, + {X86::VPCMPWZrri_alt, {0, Unknown}}, + {X86::VPCMPWZrrik, {0, Unknown}}, + {X86::VPCMPWZrrik_alt, {0, Unknown}}, + {X86::VPCOMBmi, {0, Unknown}}, + {X86::VPCOMBmi_alt, {0, Unknown}}, + {X86::VPCOMBri, {0, Unknown}}, + {X86::VPCOMBri_alt, {0, Unknown}}, + {X86::VPCOMDmi, {0, Unknown}}, + {X86::VPCOMDmi_alt, {0, Unknown}}, + {X86::VPCOMDri, {0, Unknown}}, + {X86::VPCOMDri_alt, {0, Unknown}}, + {X86::VPCOMPRESSBZ128mr, {1, Unknown}}, + {X86::VPCOMPRESSBZ128mrk, {1, Unknown}}, + {X86::VPCOMPRESSBZ128rr, {0, Unknown}}, + {X86::VPCOMPRESSBZ128rrk, {0, Unknown}}, + {X86::VPCOMPRESSBZ128rrkz, {0, Unknown}}, + {X86::VPCOMPRESSBZ256mr, {0, Unknown}}, + {X86::VPCOMPRESSBZ256mrk, {0, Unknown}}, + {X86::VPCOMPRESSBZ256rr, {0, Unknown}}, + {X86::VPCOMPRESSBZ256rrk, {0, Unknown}}, + {X86::VPCOMPRESSBZ256rrkz, {0, Unknown}}, + {X86::VPCOMPRESSBZmr, {0, Unknown}}, + {X86::VPCOMPRESSBZmrk, {0, Unknown}}, + {X86::VPCOMPRESSBZrr, {0, Unknown}}, + {X86::VPCOMPRESSBZrrk, {0, Unknown}}, + {X86::VPCOMPRESSBZrrkz, {0, Unknown}}, + {X86::VPCOMPRESSDZ128mr, {1, Unknown}}, + {X86::VPCOMPRESSDZ128mrk, {1, Unknown}}, + {X86::VPCOMPRESSDZ128rr, {0, Unknown}}, + {X86::VPCOMPRESSDZ128rrk, {0, Unknown}}, + {X86::VPCOMPRESSDZ128rrkz, {0, Unknown}}, + {X86::VPCOMPRESSDZ256mr, {0, Unknown}}, + {X86::VPCOMPRESSDZ256mrk, {0, Unknown}}, + {X86::VPCOMPRESSDZ256rr, {0, Unknown}}, + {X86::VPCOMPRESSDZ256rrk, {0, Unknown}}, + {X86::VPCOMPRESSDZ256rrkz, {0, Unknown}}, + {X86::VPCOMPRESSDZmr, {0, Unknown}}, + {X86::VPCOMPRESSDZmrk, {0, Unknown}}, + {X86::VPCOMPRESSDZrr, {0, Unknown}}, + {X86::VPCOMPRESSDZrrk, {0, Unknown}}, + {X86::VPCOMPRESSDZrrkz, {0, Unknown}}, + {X86::VPCOMPRESSQZ128mr, {1, Unknown}}, + {X86::VPCOMPRESSQZ128mrk, {1, Unknown}}, + {X86::VPCOMPRESSQZ128rr, {0, Unknown}}, + {X86::VPCOMPRESSQZ128rrk, {0, Unknown}}, + {X86::VPCOMPRESSQZ128rrkz, {0, Unknown}}, + {X86::VPCOMPRESSQZ256mr, {0, Unknown}}, + {X86::VPCOMPRESSQZ256mrk, {0, Unknown}}, + {X86::VPCOMPRESSQZ256rr, {0, Unknown}}, + {X86::VPCOMPRESSQZ256rrk, {0, Unknown}}, + {X86::VPCOMPRESSQZ256rrkz, {0, Unknown}}, + {X86::VPCOMPRESSQZmr, {0, Unknown}}, + {X86::VPCOMPRESSQZmrk, {0, Unknown}}, + {X86::VPCOMPRESSQZrr, {0, Unknown}}, + {X86::VPCOMPRESSQZrrk, {0, Unknown}}, + {X86::VPCOMPRESSQZrrkz, {0, Unknown}}, + {X86::VPCOMPRESSWZ128mr, {1, Unknown}}, + {X86::VPCOMPRESSWZ128mrk, {1, Unknown}}, + {X86::VPCOMPRESSWZ128rr, {0, Unknown}}, + {X86::VPCOMPRESSWZ128rrk, {0, Unknown}}, + {X86::VPCOMPRESSWZ128rrkz, {0, Unknown}}, + {X86::VPCOMPRESSWZ256mr, {0, Unknown}}, + {X86::VPCOMPRESSWZ256mrk, {0, Unknown}}, + {X86::VPCOMPRESSWZ256rr, {0, Unknown}}, + {X86::VPCOMPRESSWZ256rrk, {0, Unknown}}, + {X86::VPCOMPRESSWZ256rrkz, {0, Unknown}}, + {X86::VPCOMPRESSWZmr, {0, Unknown}}, + {X86::VPCOMPRESSWZmrk, {0, Unknown}}, + {X86::VPCOMPRESSWZrr, {0, Unknown}}, + {X86::VPCOMPRESSWZrrk, {0, Unknown}}, + {X86::VPCOMPRESSWZrrkz, {0, Unknown}}, + {X86::VPCOMQmi, {0, Unknown}}, + {X86::VPCOMQmi_alt, {0, Unknown}}, + {X86::VPCOMQri, {0, Unknown}}, + {X86::VPCOMQri_alt, {0, Unknown}}, + {X86::VPCOMUBmi, {0, Unknown}}, + {X86::VPCOMUBmi_alt, {0, Unknown}}, + {X86::VPCOMUBri, {0, Unknown}}, + {X86::VPCOMUBri_alt, {0, Unknown}}, + {X86::VPCOMUDmi, {0, Unknown}}, + {X86::VPCOMUDmi_alt, {0, Unknown}}, + {X86::VPCOMUDri, {0, Unknown}}, + {X86::VPCOMUDri_alt, {0, Unknown}}, + {X86::VPCOMUQmi, {0, Unknown}}, + {X86::VPCOMUQmi_alt, {0, Unknown}}, + {X86::VPCOMUQri, {0, Unknown}}, + {X86::VPCOMUQri_alt, {0, Unknown}}, + {X86::VPCOMUWmi, {0, Unknown}}, + {X86::VPCOMUWmi_alt, {0, Unknown}}, + {X86::VPCOMUWri, {0, Unknown}}, + {X86::VPCOMUWri_alt, {0, Unknown}}, + {X86::VPCOMWmi, {0, Unknown}}, + {X86::VPCOMWmi_alt, {0, Unknown}}, + {X86::VPCOMWri, {0, Unknown}}, + {X86::VPCOMWri_alt, {0, Unknown}}, + {X86::VPCONFLICTDZ128rm, {1, Unknown}}, + {X86::VPCONFLICTDZ128rmb, {1, Unknown}}, + {X86::VPCONFLICTDZ128rmbk, {1, Unknown}}, + {X86::VPCONFLICTDZ128rmbkz, {1, Unknown}}, + {X86::VPCONFLICTDZ128rmk, {1, Unknown}}, + {X86::VPCONFLICTDZ128rmkz, {1, Unknown}}, + {X86::VPCONFLICTDZ128rr, {0, Unknown}}, + {X86::VPCONFLICTDZ128rrk, {0, Unknown}}, + {X86::VPCONFLICTDZ128rrkz, {0, Unknown}}, + {X86::VPCONFLICTDZ256rm, {0, Unknown}}, + {X86::VPCONFLICTDZ256rmb, {0, Unknown}}, + {X86::VPCONFLICTDZ256rmbk, {0, Unknown}}, + {X86::VPCONFLICTDZ256rmbkz, {0, Unknown}}, + {X86::VPCONFLICTDZ256rmk, {0, Unknown}}, + {X86::VPCONFLICTDZ256rmkz, {0, Unknown}}, + {X86::VPCONFLICTDZ256rr, {0, Unknown}}, + {X86::VPCONFLICTDZ256rrk, {0, Unknown}}, + {X86::VPCONFLICTDZ256rrkz, {0, Unknown}}, + {X86::VPCONFLICTDZrm, {0, Unknown}}, + {X86::VPCONFLICTDZrmb, {0, Unknown}}, + {X86::VPCONFLICTDZrmbk, {0, Unknown}}, + {X86::VPCONFLICTDZrmbkz, {0, Unknown}}, + {X86::VPCONFLICTDZrmk, {0, Unknown}}, + {X86::VPCONFLICTDZrmkz, {0, Unknown}}, + {X86::VPCONFLICTDZrr, {0, Unknown}}, + {X86::VPCONFLICTDZrrk, {0, Unknown}}, + {X86::VPCONFLICTDZrrkz, {0, Unknown}}, + {X86::VPCONFLICTQZ128rm, {1, Unknown}}, + {X86::VPCONFLICTQZ128rmb, {1, Unknown}}, + {X86::VPCONFLICTQZ128rmbk, {1, Unknown}}, + {X86::VPCONFLICTQZ128rmbkz, {1, Unknown}}, + {X86::VPCONFLICTQZ128rmk, {1, Unknown}}, + {X86::VPCONFLICTQZ128rmkz, {1, Unknown}}, + {X86::VPCONFLICTQZ128rr, {0, Unknown}}, + {X86::VPCONFLICTQZ128rrk, {0, Unknown}}, + {X86::VPCONFLICTQZ128rrkz, {0, Unknown}}, + {X86::VPCONFLICTQZ256rm, {0, Unknown}}, + {X86::VPCONFLICTQZ256rmb, {0, Unknown}}, + {X86::VPCONFLICTQZ256rmbk, {0, Unknown}}, + {X86::VPCONFLICTQZ256rmbkz, {0, Unknown}}, + {X86::VPCONFLICTQZ256rmk, {0, Unknown}}, + {X86::VPCONFLICTQZ256rmkz, {0, Unknown}}, + {X86::VPCONFLICTQZ256rr, {0, Unknown}}, + {X86::VPCONFLICTQZ256rrk, {0, Unknown}}, + {X86::VPCONFLICTQZ256rrkz, {0, Unknown}}, + {X86::VPCONFLICTQZrm, {0, Unknown}}, + {X86::VPCONFLICTQZrmb, {0, Unknown}}, + {X86::VPCONFLICTQZrmbk, {0, Unknown}}, + {X86::VPCONFLICTQZrmbkz, {0, Unknown}}, + {X86::VPCONFLICTQZrmk, {0, Unknown}}, + {X86::VPCONFLICTQZrmkz, {0, Unknown}}, + {X86::VPCONFLICTQZrr, {0, Unknown}}, + {X86::VPCONFLICTQZrrk, {0, Unknown}}, + {X86::VPCONFLICTQZrrkz, {0, Unknown}}, + {X86::VPDPBUSDSZ128m, {0, Unknown}}, + {X86::VPDPBUSDSZ128mb, {0, Unknown}}, + {X86::VPDPBUSDSZ128mbk, {0, Unknown}}, + {X86::VPDPBUSDSZ128mbkz, {0, Unknown}}, + {X86::VPDPBUSDSZ128mk, {0, Unknown}}, + {X86::VPDPBUSDSZ128mkz, {0, Unknown}}, + {X86::VPDPBUSDSZ128r, {0, Unknown}}, + {X86::VPDPBUSDSZ128rk, {0, Unknown}}, + {X86::VPDPBUSDSZ128rkz, {0, Unknown}}, + {X86::VPDPBUSDSZ256m, {0, Unknown}}, + {X86::VPDPBUSDSZ256mb, {0, Unknown}}, + {X86::VPDPBUSDSZ256mbk, {0, Unknown}}, + {X86::VPDPBUSDSZ256mbkz, {0, Unknown}}, + {X86::VPDPBUSDSZ256mk, {0, Unknown}}, + {X86::VPDPBUSDSZ256mkz, {0, Unknown}}, + {X86::VPDPBUSDSZ256r, {0, Unknown}}, + {X86::VPDPBUSDSZ256rk, {0, Unknown}}, + {X86::VPDPBUSDSZ256rkz, {0, Unknown}}, + {X86::VPDPBUSDSZm, {0, Unknown}}, + {X86::VPDPBUSDSZmb, {0, Unknown}}, + {X86::VPDPBUSDSZmbk, {0, Unknown}}, + {X86::VPDPBUSDSZmbkz, {0, Unknown}}, + {X86::VPDPBUSDSZmk, {0, Unknown}}, + {X86::VPDPBUSDSZmkz, {0, Unknown}}, + {X86::VPDPBUSDSZr, {0, Unknown}}, + {X86::VPDPBUSDSZrk, {0, Unknown}}, + {X86::VPDPBUSDSZrkz, {0, Unknown}}, + {X86::VPDPBUSDZ128m, {0, Unknown}}, + {X86::VPDPBUSDZ128mb, {0, Unknown}}, + {X86::VPDPBUSDZ128mbk, {0, Unknown}}, + {X86::VPDPBUSDZ128mbkz, {0, Unknown}}, + {X86::VPDPBUSDZ128mk, {0, Unknown}}, + {X86::VPDPBUSDZ128mkz, {0, Unknown}}, + {X86::VPDPBUSDZ128r, {0, Unknown}}, + {X86::VPDPBUSDZ128rk, {0, Unknown}}, + {X86::VPDPBUSDZ128rkz, {0, Unknown}}, + {X86::VPDPBUSDZ256m, {0, Unknown}}, + {X86::VPDPBUSDZ256mb, {0, Unknown}}, + {X86::VPDPBUSDZ256mbk, {0, Unknown}}, + {X86::VPDPBUSDZ256mbkz, {0, Unknown}}, + {X86::VPDPBUSDZ256mk, {0, Unknown}}, + {X86::VPDPBUSDZ256mkz, {0, Unknown}}, + {X86::VPDPBUSDZ256r, {0, Unknown}}, + {X86::VPDPBUSDZ256rk, {0, Unknown}}, + {X86::VPDPBUSDZ256rkz, {0, Unknown}}, + {X86::VPDPBUSDZm, {0, Unknown}}, + {X86::VPDPBUSDZmb, {0, Unknown}}, + {X86::VPDPBUSDZmbk, {0, Unknown}}, + {X86::VPDPBUSDZmbkz, {0, Unknown}}, + {X86::VPDPBUSDZmk, {0, Unknown}}, + {X86::VPDPBUSDZmkz, {0, Unknown}}, + {X86::VPDPBUSDZr, {0, Unknown}}, + {X86::VPDPBUSDZrk, {0, Unknown}}, + {X86::VPDPBUSDZrkz, {0, Unknown}}, + {X86::VPDPWSSDSZ128m, {0, Unknown}}, + {X86::VPDPWSSDSZ128mb, {0, Unknown}}, + {X86::VPDPWSSDSZ128mbk, {0, Unknown}}, + {X86::VPDPWSSDSZ128mbkz, {0, Unknown}}, + {X86::VPDPWSSDSZ128mk, {0, Unknown}}, + {X86::VPDPWSSDSZ128mkz, {0, Unknown}}, + {X86::VPDPWSSDSZ128r, {0, Unknown}}, + {X86::VPDPWSSDSZ128rk, {0, Unknown}}, + {X86::VPDPWSSDSZ128rkz, {0, Unknown}}, + {X86::VPDPWSSDSZ256m, {0, Unknown}}, + {X86::VPDPWSSDSZ256mb, {0, Unknown}}, + {X86::VPDPWSSDSZ256mbk, {0, Unknown}}, + {X86::VPDPWSSDSZ256mbkz, {0, Unknown}}, + {X86::VPDPWSSDSZ256mk, {0, Unknown}}, + {X86::VPDPWSSDSZ256mkz, {0, Unknown}}, + {X86::VPDPWSSDSZ256r, {0, Unknown}}, + {X86::VPDPWSSDSZ256rk, {0, Unknown}}, + {X86::VPDPWSSDSZ256rkz, {0, Unknown}}, + {X86::VPDPWSSDSZm, {0, Unknown}}, + {X86::VPDPWSSDSZmb, {0, Unknown}}, + {X86::VPDPWSSDSZmbk, {0, Unknown}}, + {X86::VPDPWSSDSZmbkz, {0, Unknown}}, + {X86::VPDPWSSDSZmk, {0, Unknown}}, + {X86::VPDPWSSDSZmkz, {0, Unknown}}, + {X86::VPDPWSSDSZr, {0, Unknown}}, + {X86::VPDPWSSDSZrk, {0, Unknown}}, + {X86::VPDPWSSDSZrkz, {0, Unknown}}, + {X86::VPDPWSSDZ128m, {0, Unknown}}, + {X86::VPDPWSSDZ128mb, {0, Unknown}}, + {X86::VPDPWSSDZ128mbk, {0, Unknown}}, + {X86::VPDPWSSDZ128mbkz, {0, Unknown}}, + {X86::VPDPWSSDZ128mk, {0, Unknown}}, + {X86::VPDPWSSDZ128mkz, {0, Unknown}}, + {X86::VPDPWSSDZ128r, {0, Unknown}}, + {X86::VPDPWSSDZ128rk, {0, Unknown}}, + {X86::VPDPWSSDZ128rkz, {0, Unknown}}, + {X86::VPDPWSSDZ256m, {0, Unknown}}, + {X86::VPDPWSSDZ256mb, {0, Unknown}}, + {X86::VPDPWSSDZ256mbk, {0, Unknown}}, + {X86::VPDPWSSDZ256mbkz, {0, Unknown}}, + {X86::VPDPWSSDZ256mk, {0, Unknown}}, + {X86::VPDPWSSDZ256mkz, {0, Unknown}}, + {X86::VPDPWSSDZ256r, {0, Unknown}}, + {X86::VPDPWSSDZ256rk, {0, Unknown}}, + {X86::VPDPWSSDZ256rkz, {0, Unknown}}, + {X86::VPDPWSSDZm, {0, Unknown}}, + {X86::VPDPWSSDZmb, {0, Unknown}}, + {X86::VPDPWSSDZmbk, {0, Unknown}}, + {X86::VPDPWSSDZmbkz, {0, Unknown}}, + {X86::VPDPWSSDZmk, {0, Unknown}}, + {X86::VPDPWSSDZmkz, {0, Unknown}}, + {X86::VPDPWSSDZr, {0, Unknown}}, + {X86::VPDPWSSDZrk, {0, Unknown}}, + {X86::VPDPWSSDZrkz, {0, Unknown}}, + {X86::VPERM2F128rm, {1, Unknown}}, + {X86::VPERM2F128rr, {0, Unknown}}, + {X86::VPERM2I128rm, {1, Unknown}}, + {X86::VPERM2I128rr, {0, Unknown}}, + {X86::VPERMBZ128rm, {1, Unknown}}, + {X86::VPERMBZ128rmk, {1, Unknown}}, + {X86::VPERMBZ128rmkz, {1, Unknown}}, + {X86::VPERMBZ128rr, {0, Unknown}}, + {X86::VPERMBZ128rrk, {0, Unknown}}, + {X86::VPERMBZ128rrkz, {0, Unknown}}, + {X86::VPERMBZ256rm, {0, Unknown}}, + {X86::VPERMBZ256rmk, {0, Unknown}}, + {X86::VPERMBZ256rmkz, {0, Unknown}}, + {X86::VPERMBZ256rr, {0, Unknown}}, + {X86::VPERMBZ256rrk, {0, Unknown}}, + {X86::VPERMBZ256rrkz, {0, Unknown}}, + {X86::VPERMBZrm, {0, Unknown}}, + {X86::VPERMBZrmk, {0, Unknown}}, + {X86::VPERMBZrmkz, {0, Unknown}}, + {X86::VPERMBZrr, {0, Unknown}}, + {X86::VPERMBZrrk, {0, Unknown}}, + {X86::VPERMBZrrkz, {0, Unknown}}, + {X86::VPERMDYrm, {0, Unknown}}, + {X86::VPERMDYrr, {0, Unknown}}, + {X86::VPERMDZ256rm, {0, Unknown}}, + {X86::VPERMDZ256rmb, {0, Unknown}}, + {X86::VPERMDZ256rmbk, {0, Unknown}}, + {X86::VPERMDZ256rmbkz, {0, Unknown}}, + {X86::VPERMDZ256rmk, {0, Unknown}}, + {X86::VPERMDZ256rmkz, {0, Unknown}}, + {X86::VPERMDZ256rr, {0, Unknown}}, + {X86::VPERMDZ256rrk, {0, Unknown}}, + {X86::VPERMDZ256rrkz, {0, Unknown}}, + {X86::VPERMDZrm, {0, Unknown}}, + {X86::VPERMDZrmb, {0, Unknown}}, + {X86::VPERMDZrmbk, {0, Unknown}}, + {X86::VPERMDZrmbkz, {0, Unknown}}, + {X86::VPERMDZrmk, {0, Unknown}}, + {X86::VPERMDZrmkz, {0, Unknown}}, + {X86::VPERMDZrr, {0, Unknown}}, + {X86::VPERMDZrrk, {0, Unknown}}, + {X86::VPERMDZrrkz, {0, Unknown}}, + {X86::VPERMI2B128rm, {1, Unknown}}, + {X86::VPERMI2B128rmk, {1, Unknown}}, + {X86::VPERMI2B128rmkz, {1, Unknown}}, + {X86::VPERMI2B128rr, {0, Unknown}}, + {X86::VPERMI2B128rrk, {0, Unknown}}, + {X86::VPERMI2B128rrkz, {0, Unknown}}, + {X86::VPERMI2B256rm, {0, Unknown}}, + {X86::VPERMI2B256rmk, {0, Unknown}}, + {X86::VPERMI2B256rmkz, {0, Unknown}}, + {X86::VPERMI2B256rr, {0, Unknown}}, + {X86::VPERMI2B256rrk, {0, Unknown}}, + {X86::VPERMI2B256rrkz, {0, Unknown}}, + {X86::VPERMI2Brm, {0, Unknown}}, + {X86::VPERMI2Brmk, {0, Unknown}}, + {X86::VPERMI2Brmkz, {0, Unknown}}, + {X86::VPERMI2Brr, {0, Unknown}}, + {X86::VPERMI2Brrk, {0, Unknown}}, + {X86::VPERMI2Brrkz, {0, Unknown}}, + {X86::VPERMI2D128rm, {1, Unknown}}, + {X86::VPERMI2D128rmb, {1, Unknown}}, + {X86::VPERMI2D128rmbk, {1, Unknown}}, + {X86::VPERMI2D128rmbkz, {1, Unknown}}, + {X86::VPERMI2D128rmk, {1, Unknown}}, + {X86::VPERMI2D128rmkz, {1, Unknown}}, + {X86::VPERMI2D128rr, {0, Unknown}}, + {X86::VPERMI2D128rrk, {0, Unknown}}, + {X86::VPERMI2D128rrkz, {0, Unknown}}, + {X86::VPERMI2D256rm, {0, Unknown}}, + {X86::VPERMI2D256rmb, {0, Unknown}}, + {X86::VPERMI2D256rmbk, {0, Unknown}}, + {X86::VPERMI2D256rmbkz, {0, Unknown}}, + {X86::VPERMI2D256rmk, {0, Unknown}}, + {X86::VPERMI2D256rmkz, {0, Unknown}}, + {X86::VPERMI2D256rr, {0, Unknown}}, + {X86::VPERMI2D256rrk, {0, Unknown}}, + {X86::VPERMI2D256rrkz, {0, Unknown}}, + {X86::VPERMI2Drm, {0, Unknown}}, + {X86::VPERMI2Drmb, {0, Unknown}}, + {X86::VPERMI2Drmbk, {0, Unknown}}, + {X86::VPERMI2Drmbkz, {0, Unknown}}, + {X86::VPERMI2Drmk, {0, Unknown}}, + {X86::VPERMI2Drmkz, {0, Unknown}}, + {X86::VPERMI2Drr, {0, Unknown}}, + {X86::VPERMI2Drrk, {0, Unknown}}, + {X86::VPERMI2Drrkz, {0, Unknown}}, + {X86::VPERMI2PD128rm, {1, Unknown}}, + {X86::VPERMI2PD128rmb, {1, Unknown}}, + {X86::VPERMI2PD128rmbk, {1, Unknown}}, + {X86::VPERMI2PD128rmbkz, {1, Unknown}}, + {X86::VPERMI2PD128rmk, {1, Unknown}}, + {X86::VPERMI2PD128rmkz, {1, Unknown}}, + {X86::VPERMI2PD128rr, {0, Unknown}}, + {X86::VPERMI2PD128rrk, {0, Unknown}}, + {X86::VPERMI2PD128rrkz, {0, Unknown}}, + {X86::VPERMI2PD256rm, {0, Unknown}}, + {X86::VPERMI2PD256rmb, {0, Unknown}}, + {X86::VPERMI2PD256rmbk, {0, Unknown}}, + {X86::VPERMI2PD256rmbkz, {0, Unknown}}, + {X86::VPERMI2PD256rmk, {0, Unknown}}, + {X86::VPERMI2PD256rmkz, {0, Unknown}}, + {X86::VPERMI2PD256rr, {0, Unknown}}, + {X86::VPERMI2PD256rrk, {0, Unknown}}, + {X86::VPERMI2PD256rrkz, {0, Unknown}}, + {X86::VPERMI2PDrm, {0, Unknown}}, + {X86::VPERMI2PDrmb, {0, Unknown}}, + {X86::VPERMI2PDrmbk, {0, Unknown}}, + {X86::VPERMI2PDrmbkz, {0, Unknown}}, + {X86::VPERMI2PDrmk, {0, Unknown}}, + {X86::VPERMI2PDrmkz, {0, Unknown}}, + {X86::VPERMI2PDrr, {0, Unknown}}, + {X86::VPERMI2PDrrk, {0, Unknown}}, + {X86::VPERMI2PDrrkz, {0, Unknown}}, + {X86::VPERMI2PS128rm, {1, Unknown}}, + {X86::VPERMI2PS128rmb, {1, Unknown}}, + {X86::VPERMI2PS128rmbk, {1, Unknown}}, + {X86::VPERMI2PS128rmbkz, {1, Unknown}}, + {X86::VPERMI2PS128rmk, {1, Unknown}}, + {X86::VPERMI2PS128rmkz, {1, Unknown}}, + {X86::VPERMI2PS128rr, {0, Unknown}}, + {X86::VPERMI2PS128rrk, {0, Unknown}}, + {X86::VPERMI2PS128rrkz, {0, Unknown}}, + {X86::VPERMI2PS256rm, {0, Unknown}}, + {X86::VPERMI2PS256rmb, {0, Unknown}}, + {X86::VPERMI2PS256rmbk, {0, Unknown}}, + {X86::VPERMI2PS256rmbkz, {0, Unknown}}, + {X86::VPERMI2PS256rmk, {0, Unknown}}, + {X86::VPERMI2PS256rmkz, {0, Unknown}}, + {X86::VPERMI2PS256rr, {0, Unknown}}, + {X86::VPERMI2PS256rrk, {0, Unknown}}, + {X86::VPERMI2PS256rrkz, {0, Unknown}}, + {X86::VPERMI2PSrm, {0, Unknown}}, + {X86::VPERMI2PSrmb, {0, Unknown}}, + {X86::VPERMI2PSrmbk, {0, Unknown}}, + {X86::VPERMI2PSrmbkz, {0, Unknown}}, + {X86::VPERMI2PSrmk, {0, Unknown}}, + {X86::VPERMI2PSrmkz, {0, Unknown}}, + {X86::VPERMI2PSrr, {0, Unknown}}, + {X86::VPERMI2PSrrk, {0, Unknown}}, + {X86::VPERMI2PSrrkz, {0, Unknown}}, + {X86::VPERMI2Q128rm, {1, Unknown}}, + {X86::VPERMI2Q128rmb, {1, Unknown}}, + {X86::VPERMI2Q128rmbk, {1, Unknown}}, + {X86::VPERMI2Q128rmbkz, {1, Unknown}}, + {X86::VPERMI2Q128rmk, {1, Unknown}}, + {X86::VPERMI2Q128rmkz, {1, Unknown}}, + {X86::VPERMI2Q128rr, {0, Unknown}}, + {X86::VPERMI2Q128rrk, {0, Unknown}}, + {X86::VPERMI2Q128rrkz, {0, Unknown}}, + {X86::VPERMI2Q256rm, {0, Unknown}}, + {X86::VPERMI2Q256rmb, {0, Unknown}}, + {X86::VPERMI2Q256rmbk, {0, Unknown}}, + {X86::VPERMI2Q256rmbkz, {0, Unknown}}, + {X86::VPERMI2Q256rmk, {0, Unknown}}, + {X86::VPERMI2Q256rmkz, {0, Unknown}}, + {X86::VPERMI2Q256rr, {0, Unknown}}, + {X86::VPERMI2Q256rrk, {0, Unknown}}, + {X86::VPERMI2Q256rrkz, {0, Unknown}}, + {X86::VPERMI2Qrm, {0, Unknown}}, + {X86::VPERMI2Qrmb, {0, Unknown}}, + {X86::VPERMI2Qrmbk, {0, Unknown}}, + {X86::VPERMI2Qrmbkz, {0, Unknown}}, + {X86::VPERMI2Qrmk, {0, Unknown}}, + {X86::VPERMI2Qrmkz, {0, Unknown}}, + {X86::VPERMI2Qrr, {0, Unknown}}, + {X86::VPERMI2Qrrk, {0, Unknown}}, + {X86::VPERMI2Qrrkz, {0, Unknown}}, + {X86::VPERMI2W128rm, {1, Unknown}}, + {X86::VPERMI2W128rmk, {1, Unknown}}, + {X86::VPERMI2W128rmkz, {1, Unknown}}, + {X86::VPERMI2W128rr, {0, Unknown}}, + {X86::VPERMI2W128rrk, {0, Unknown}}, + {X86::VPERMI2W128rrkz, {0, Unknown}}, + {X86::VPERMI2W256rm, {0, Unknown}}, + {X86::VPERMI2W256rmk, {0, Unknown}}, + {X86::VPERMI2W256rmkz, {0, Unknown}}, + {X86::VPERMI2W256rr, {0, Unknown}}, + {X86::VPERMI2W256rrk, {0, Unknown}}, + {X86::VPERMI2W256rrkz, {0, Unknown}}, + {X86::VPERMI2Wrm, {0, Unknown}}, + {X86::VPERMI2Wrmk, {0, Unknown}}, + {X86::VPERMI2Wrmkz, {0, Unknown}}, + {X86::VPERMI2Wrr, {0, Unknown}}, + {X86::VPERMI2Wrrk, {0, Unknown}}, + {X86::VPERMI2Wrrkz, {0, Unknown}}, + {X86::VPERMIL2PDYmr, {0, Unknown}}, + {X86::VPERMIL2PDYrm, {0, Unknown}}, + {X86::VPERMIL2PDYrr, {0, Unknown}}, + {X86::VPERMIL2PDYrr_REV, {0, Unknown}}, + {X86::VPERMIL2PDmr, {0, Unknown}}, + {X86::VPERMIL2PDrm, {0, Unknown}}, + {X86::VPERMIL2PDrr, {0, Unknown}}, + {X86::VPERMIL2PDrr_REV, {0, Unknown}}, + {X86::VPERMIL2PSYmr, {0, Unknown}}, + {X86::VPERMIL2PSYrm, {0, Unknown}}, + {X86::VPERMIL2PSYrr, {0, Unknown}}, + {X86::VPERMIL2PSYrr_REV, {0, Unknown}}, + {X86::VPERMIL2PSmr, {0, Unknown}}, + {X86::VPERMIL2PSrm, {0, Unknown}}, + {X86::VPERMIL2PSrr, {0, Unknown}}, + {X86::VPERMIL2PSrr_REV, {0, Unknown}}, + {X86::VPERMILPDYmi, {0, Unknown}}, + {X86::VPERMILPDYri, {0, Unknown}}, + {X86::VPERMILPDYrm, {0, Unknown}}, + {X86::VPERMILPDYrr, {0, Unknown}}, + {X86::VPERMILPDZ128mbi, {0, Unknown}}, + {X86::VPERMILPDZ128mbik, {0, Unknown}}, + {X86::VPERMILPDZ128mbikz, {0, Unknown}}, + {X86::VPERMILPDZ128mi, {1, Unknown}}, + {X86::VPERMILPDZ128mik, {1, Unknown}}, + {X86::VPERMILPDZ128mikz, {1, Unknown}}, + {X86::VPERMILPDZ128ri, {0, Unknown}}, + {X86::VPERMILPDZ128rik, {0, Unknown}}, + {X86::VPERMILPDZ128rikz, {0, Unknown}}, + {X86::VPERMILPDZ128rm, {1, Unknown}}, + {X86::VPERMILPDZ128rmb, {1, Unknown}}, + {X86::VPERMILPDZ128rmbk, {1, Unknown}}, + {X86::VPERMILPDZ128rmbkz, {1, Unknown}}, + {X86::VPERMILPDZ128rmk, {1, Unknown}}, + {X86::VPERMILPDZ128rmkz, {1, Unknown}}, + {X86::VPERMILPDZ128rr, {0, Unknown}}, + {X86::VPERMILPDZ128rrk, {0, Unknown}}, + {X86::VPERMILPDZ128rrkz, {0, Unknown}}, + {X86::VPERMILPDZ256mbi, {0, Unknown}}, + {X86::VPERMILPDZ256mbik, {0, Unknown}}, + {X86::VPERMILPDZ256mbikz, {0, Unknown}}, + {X86::VPERMILPDZ256mi, {0, Unknown}}, + {X86::VPERMILPDZ256mik, {0, Unknown}}, + {X86::VPERMILPDZ256mikz, {0, Unknown}}, + {X86::VPERMILPDZ256ri, {0, Unknown}}, + {X86::VPERMILPDZ256rik, {0, Unknown}}, + {X86::VPERMILPDZ256rikz, {0, Unknown}}, + {X86::VPERMILPDZ256rm, {0, Unknown}}, + {X86::VPERMILPDZ256rmb, {0, Unknown}}, + {X86::VPERMILPDZ256rmbk, {0, Unknown}}, + {X86::VPERMILPDZ256rmbkz, {0, Unknown}}, + {X86::VPERMILPDZ256rmk, {0, Unknown}}, + {X86::VPERMILPDZ256rmkz, {0, Unknown}}, + {X86::VPERMILPDZ256rr, {0, Unknown}}, + {X86::VPERMILPDZ256rrk, {0, Unknown}}, + {X86::VPERMILPDZ256rrkz, {0, Unknown}}, + {X86::VPERMILPDZmbi, {0, Unknown}}, + {X86::VPERMILPDZmbik, {0, Unknown}}, + {X86::VPERMILPDZmbikz, {0, Unknown}}, + {X86::VPERMILPDZmi, {0, Unknown}}, + {X86::VPERMILPDZmik, {0, Unknown}}, + {X86::VPERMILPDZmikz, {0, Unknown}}, + {X86::VPERMILPDZri, {0, Unknown}}, + {X86::VPERMILPDZrik, {0, Unknown}}, + {X86::VPERMILPDZrikz, {0, Unknown}}, + {X86::VPERMILPDZrm, {0, Unknown}}, + {X86::VPERMILPDZrmb, {0, Unknown}}, + {X86::VPERMILPDZrmbk, {0, Unknown}}, + {X86::VPERMILPDZrmbkz, {0, Unknown}}, + {X86::VPERMILPDZrmk, {0, Unknown}}, + {X86::VPERMILPDZrmkz, {0, Unknown}}, + {X86::VPERMILPDZrr, {0, Unknown}}, + {X86::VPERMILPDZrrk, {0, Unknown}}, + {X86::VPERMILPDZrrkz, {0, Unknown}}, + {X86::VPERMILPDmi, {0, Unknown}}, + {X86::VPERMILPDri, {0, Unknown}}, + {X86::VPERMILPDrm, {0, Unknown}}, + {X86::VPERMILPDrr, {0, Unknown}}, + {X86::VPERMILPSYmi, {0, Unknown}}, + {X86::VPERMILPSYri, {0, Unknown}}, + {X86::VPERMILPSYrm, {0, Unknown}}, + {X86::VPERMILPSYrr, {0, Unknown}}, + {X86::VPERMILPSZ128mbi, {0, Unknown}}, + {X86::VPERMILPSZ128mbik, {0, Unknown}}, + {X86::VPERMILPSZ128mbikz, {0, Unknown}}, + {X86::VPERMILPSZ128mi, {1, Unknown}}, + {X86::VPERMILPSZ128mik, {1, Unknown}}, + {X86::VPERMILPSZ128mikz, {1, Unknown}}, + {X86::VPERMILPSZ128ri, {0, Unknown}}, + {X86::VPERMILPSZ128rik, {0, Unknown}}, + {X86::VPERMILPSZ128rikz, {0, Unknown}}, + {X86::VPERMILPSZ128rm, {1, Unknown}}, + {X86::VPERMILPSZ128rmb, {1, Unknown}}, + {X86::VPERMILPSZ128rmbk, {1, Unknown}}, + {X86::VPERMILPSZ128rmbkz, {1, Unknown}}, + {X86::VPERMILPSZ128rmk, {1, Unknown}}, + {X86::VPERMILPSZ128rmkz, {1, Unknown}}, + {X86::VPERMILPSZ128rr, {0, Unknown}}, + {X86::VPERMILPSZ128rrk, {0, Unknown}}, + {X86::VPERMILPSZ128rrkz, {0, Unknown}}, + {X86::VPERMILPSZ256mbi, {0, Unknown}}, + {X86::VPERMILPSZ256mbik, {0, Unknown}}, + {X86::VPERMILPSZ256mbikz, {0, Unknown}}, + {X86::VPERMILPSZ256mi, {0, Unknown}}, + {X86::VPERMILPSZ256mik, {0, Unknown}}, + {X86::VPERMILPSZ256mikz, {0, Unknown}}, + {X86::VPERMILPSZ256ri, {0, Unknown}}, + {X86::VPERMILPSZ256rik, {0, Unknown}}, + {X86::VPERMILPSZ256rikz, {0, Unknown}}, + {X86::VPERMILPSZ256rm, {0, Unknown}}, + {X86::VPERMILPSZ256rmb, {0, Unknown}}, + {X86::VPERMILPSZ256rmbk, {0, Unknown}}, + {X86::VPERMILPSZ256rmbkz, {0, Unknown}}, + {X86::VPERMILPSZ256rmk, {0, Unknown}}, + {X86::VPERMILPSZ256rmkz, {0, Unknown}}, + {X86::VPERMILPSZ256rr, {0, Unknown}}, + {X86::VPERMILPSZ256rrk, {0, Unknown}}, + {X86::VPERMILPSZ256rrkz, {0, Unknown}}, + {X86::VPERMILPSZmbi, {0, Unknown}}, + {X86::VPERMILPSZmbik, {0, Unknown}}, + {X86::VPERMILPSZmbikz, {0, Unknown}}, + {X86::VPERMILPSZmi, {0, Unknown}}, + {X86::VPERMILPSZmik, {0, Unknown}}, + {X86::VPERMILPSZmikz, {0, Unknown}}, + {X86::VPERMILPSZri, {0, Unknown}}, + {X86::VPERMILPSZrik, {0, Unknown}}, + {X86::VPERMILPSZrikz, {0, Unknown}}, + {X86::VPERMILPSZrm, {0, Unknown}}, + {X86::VPERMILPSZrmb, {0, Unknown}}, + {X86::VPERMILPSZrmbk, {0, Unknown}}, + {X86::VPERMILPSZrmbkz, {0, Unknown}}, + {X86::VPERMILPSZrmk, {0, Unknown}}, + {X86::VPERMILPSZrmkz, {0, Unknown}}, + {X86::VPERMILPSZrr, {0, Unknown}}, + {X86::VPERMILPSZrrk, {0, Unknown}}, + {X86::VPERMILPSZrrkz, {0, Unknown}}, + {X86::VPERMILPSmi, {0, Unknown}}, + {X86::VPERMILPSri, {0, Unknown}}, + {X86::VPERMILPSrm, {0, Unknown}}, + {X86::VPERMILPSrr, {0, Unknown}}, + {X86::VPERMPDYmi, {0, Unknown}}, + {X86::VPERMPDYri, {0, Unknown}}, + {X86::VPERMPDZ256mbi, {0, Unknown}}, + {X86::VPERMPDZ256mbik, {0, Unknown}}, + {X86::VPERMPDZ256mbikz, {0, Unknown}}, + {X86::VPERMPDZ256mi, {0, Unknown}}, + {X86::VPERMPDZ256mik, {0, Unknown}}, + {X86::VPERMPDZ256mikz, {0, Unknown}}, + {X86::VPERMPDZ256ri, {0, Unknown}}, + {X86::VPERMPDZ256rik, {0, Unknown}}, + {X86::VPERMPDZ256rikz, {0, Unknown}}, + {X86::VPERMPDZ256rm, {0, Unknown}}, + {X86::VPERMPDZ256rmb, {0, Unknown}}, + {X86::VPERMPDZ256rmbk, {0, Unknown}}, + {X86::VPERMPDZ256rmbkz, {0, Unknown}}, + {X86::VPERMPDZ256rmk, {0, Unknown}}, + {X86::VPERMPDZ256rmkz, {0, Unknown}}, + {X86::VPERMPDZ256rr, {0, Unknown}}, + {X86::VPERMPDZ256rrk, {0, Unknown}}, + {X86::VPERMPDZ256rrkz, {0, Unknown}}, + {X86::VPERMPDZmbi, {0, Unknown}}, + {X86::VPERMPDZmbik, {0, Unknown}}, + {X86::VPERMPDZmbikz, {0, Unknown}}, + {X86::VPERMPDZmi, {0, Unknown}}, + {X86::VPERMPDZmik, {0, Unknown}}, + {X86::VPERMPDZmikz, {0, Unknown}}, + {X86::VPERMPDZri, {0, Unknown}}, + {X86::VPERMPDZrik, {0, Unknown}}, + {X86::VPERMPDZrikz, {0, Unknown}}, + {X86::VPERMPDZrm, {0, Unknown}}, + {X86::VPERMPDZrmb, {0, Unknown}}, + {X86::VPERMPDZrmbk, {0, Unknown}}, + {X86::VPERMPDZrmbkz, {0, Unknown}}, + {X86::VPERMPDZrmk, {0, Unknown}}, + {X86::VPERMPDZrmkz, {0, Unknown}}, + {X86::VPERMPDZrr, {0, Unknown}}, + {X86::VPERMPDZrrk, {0, Unknown}}, + {X86::VPERMPDZrrkz, {0, Unknown}}, + {X86::VPERMPSYrm, {0, Unknown}}, + {X86::VPERMPSYrr, {0, Unknown}}, + {X86::VPERMPSZ256rm, {0, Unknown}}, + {X86::VPERMPSZ256rmb, {0, Unknown}}, + {X86::VPERMPSZ256rmbk, {0, Unknown}}, + {X86::VPERMPSZ256rmbkz, {0, Unknown}}, + {X86::VPERMPSZ256rmk, {0, Unknown}}, + {X86::VPERMPSZ256rmkz, {0, Unknown}}, + {X86::VPERMPSZ256rr, {0, Unknown}}, + {X86::VPERMPSZ256rrk, {0, Unknown}}, + {X86::VPERMPSZ256rrkz, {0, Unknown}}, + {X86::VPERMPSZrm, {0, Unknown}}, + {X86::VPERMPSZrmb, {0, Unknown}}, + {X86::VPERMPSZrmbk, {0, Unknown}}, + {X86::VPERMPSZrmbkz, {0, Unknown}}, + {X86::VPERMPSZrmk, {0, Unknown}}, + {X86::VPERMPSZrmkz, {0, Unknown}}, + {X86::VPERMPSZrr, {0, Unknown}}, + {X86::VPERMPSZrrk, {0, Unknown}}, + {X86::VPERMPSZrrkz, {0, Unknown}}, + {X86::VPERMQYmi, {0, Unknown}}, + {X86::VPERMQYri, {0, Unknown}}, + {X86::VPERMQZ256mbi, {0, Unknown}}, + {X86::VPERMQZ256mbik, {0, Unknown}}, + {X86::VPERMQZ256mbikz, {0, Unknown}}, + {X86::VPERMQZ256mi, {0, Unknown}}, + {X86::VPERMQZ256mik, {0, Unknown}}, + {X86::VPERMQZ256mikz, {0, Unknown}}, + {X86::VPERMQZ256ri, {0, Unknown}}, + {X86::VPERMQZ256rik, {0, Unknown}}, + {X86::VPERMQZ256rikz, {0, Unknown}}, + {X86::VPERMQZ256rm, {0, Unknown}}, + {X86::VPERMQZ256rmb, {0, Unknown}}, + {X86::VPERMQZ256rmbk, {0, Unknown}}, + {X86::VPERMQZ256rmbkz, {0, Unknown}}, + {X86::VPERMQZ256rmk, {0, Unknown}}, + {X86::VPERMQZ256rmkz, {0, Unknown}}, + {X86::VPERMQZ256rr, {0, Unknown}}, + {X86::VPERMQZ256rrk, {0, Unknown}}, + {X86::VPERMQZ256rrkz, {0, Unknown}}, + {X86::VPERMQZmbi, {0, Unknown}}, + {X86::VPERMQZmbik, {0, Unknown}}, + {X86::VPERMQZmbikz, {0, Unknown}}, + {X86::VPERMQZmi, {0, Unknown}}, + {X86::VPERMQZmik, {0, Unknown}}, + {X86::VPERMQZmikz, {0, Unknown}}, + {X86::VPERMQZri, {0, Unknown}}, + {X86::VPERMQZrik, {0, Unknown}}, + {X86::VPERMQZrikz, {0, Unknown}}, + {X86::VPERMQZrm, {0, Unknown}}, + {X86::VPERMQZrmb, {0, Unknown}}, + {X86::VPERMQZrmbk, {0, Unknown}}, + {X86::VPERMQZrmbkz, {0, Unknown}}, + {X86::VPERMQZrmk, {0, Unknown}}, + {X86::VPERMQZrmkz, {0, Unknown}}, + {X86::VPERMQZrr, {0, Unknown}}, + {X86::VPERMQZrrk, {0, Unknown}}, + {X86::VPERMQZrrkz, {0, Unknown}}, + {X86::VPERMT2B128rm, {1, Unknown}}, + {X86::VPERMT2B128rmk, {1, Unknown}}, + {X86::VPERMT2B128rmkz, {1, Unknown}}, + {X86::VPERMT2B128rr, {0, Unknown}}, + {X86::VPERMT2B128rrk, {0, Unknown}}, + {X86::VPERMT2B128rrkz, {0, Unknown}}, + {X86::VPERMT2B256rm, {0, Unknown}}, + {X86::VPERMT2B256rmk, {0, Unknown}}, + {X86::VPERMT2B256rmkz, {0, Unknown}}, + {X86::VPERMT2B256rr, {0, Unknown}}, + {X86::VPERMT2B256rrk, {0, Unknown}}, + {X86::VPERMT2B256rrkz, {0, Unknown}}, + {X86::VPERMT2Brm, {0, Unknown}}, + {X86::VPERMT2Brmk, {0, Unknown}}, + {X86::VPERMT2Brmkz, {0, Unknown}}, + {X86::VPERMT2Brr, {0, Unknown}}, + {X86::VPERMT2Brrk, {0, Unknown}}, + {X86::VPERMT2Brrkz, {0, Unknown}}, + {X86::VPERMT2D128rm, {1, Unknown}}, + {X86::VPERMT2D128rmb, {1, Unknown}}, + {X86::VPERMT2D128rmbk, {1, Unknown}}, + {X86::VPERMT2D128rmbkz, {1, Unknown}}, + {X86::VPERMT2D128rmk, {1, Unknown}}, + {X86::VPERMT2D128rmkz, {1, Unknown}}, + {X86::VPERMT2D128rr, {0, Unknown}}, + {X86::VPERMT2D128rrk, {0, Unknown}}, + {X86::VPERMT2D128rrkz, {0, Unknown}}, + {X86::VPERMT2D256rm, {0, Unknown}}, + {X86::VPERMT2D256rmb, {0, Unknown}}, + {X86::VPERMT2D256rmbk, {0, Unknown}}, + {X86::VPERMT2D256rmbkz, {0, Unknown}}, + {X86::VPERMT2D256rmk, {0, Unknown}}, + {X86::VPERMT2D256rmkz, {0, Unknown}}, + {X86::VPERMT2D256rr, {0, Unknown}}, + {X86::VPERMT2D256rrk, {0, Unknown}}, + {X86::VPERMT2D256rrkz, {0, Unknown}}, + {X86::VPERMT2Drm, {0, Unknown}}, + {X86::VPERMT2Drmb, {0, Unknown}}, + {X86::VPERMT2Drmbk, {0, Unknown}}, + {X86::VPERMT2Drmbkz, {0, Unknown}}, + {X86::VPERMT2Drmk, {0, Unknown}}, + {X86::VPERMT2Drmkz, {0, Unknown}}, + {X86::VPERMT2Drr, {0, Unknown}}, + {X86::VPERMT2Drrk, {0, Unknown}}, + {X86::VPERMT2Drrkz, {0, Unknown}}, + {X86::VPERMT2PD128rm, {1, Unknown}}, + {X86::VPERMT2PD128rmb, {1, Unknown}}, + {X86::VPERMT2PD128rmbk, {1, Unknown}}, + {X86::VPERMT2PD128rmbkz, {1, Unknown}}, + {X86::VPERMT2PD128rmk, {1, Unknown}}, + {X86::VPERMT2PD128rmkz, {1, Unknown}}, + {X86::VPERMT2PD128rr, {0, Unknown}}, + {X86::VPERMT2PD128rrk, {0, Unknown}}, + {X86::VPERMT2PD128rrkz, {0, Unknown}}, + {X86::VPERMT2PD256rm, {0, Unknown}}, + {X86::VPERMT2PD256rmb, {0, Unknown}}, + {X86::VPERMT2PD256rmbk, {0, Unknown}}, + {X86::VPERMT2PD256rmbkz, {0, Unknown}}, + {X86::VPERMT2PD256rmk, {0, Unknown}}, + {X86::VPERMT2PD256rmkz, {0, Unknown}}, + {X86::VPERMT2PD256rr, {0, Unknown}}, + {X86::VPERMT2PD256rrk, {0, Unknown}}, + {X86::VPERMT2PD256rrkz, {0, Unknown}}, + {X86::VPERMT2PDrm, {0, Unknown}}, + {X86::VPERMT2PDrmb, {0, Unknown}}, + {X86::VPERMT2PDrmbk, {0, Unknown}}, + {X86::VPERMT2PDrmbkz, {0, Unknown}}, + {X86::VPERMT2PDrmk, {0, Unknown}}, + {X86::VPERMT2PDrmkz, {0, Unknown}}, + {X86::VPERMT2PDrr, {0, Unknown}}, + {X86::VPERMT2PDrrk, {0, Unknown}}, + {X86::VPERMT2PDrrkz, {0, Unknown}}, + {X86::VPERMT2PS128rm, {1, Unknown}}, + {X86::VPERMT2PS128rmb, {1, Unknown}}, + {X86::VPERMT2PS128rmbk, {1, Unknown}}, + {X86::VPERMT2PS128rmbkz, {1, Unknown}}, + {X86::VPERMT2PS128rmk, {1, Unknown}}, + {X86::VPERMT2PS128rmkz, {1, Unknown}}, + {X86::VPERMT2PS128rr, {0, Unknown}}, + {X86::VPERMT2PS128rrk, {0, Unknown}}, + {X86::VPERMT2PS128rrkz, {0, Unknown}}, + {X86::VPERMT2PS256rm, {0, Unknown}}, + {X86::VPERMT2PS256rmb, {0, Unknown}}, + {X86::VPERMT2PS256rmbk, {0, Unknown}}, + {X86::VPERMT2PS256rmbkz, {0, Unknown}}, + {X86::VPERMT2PS256rmk, {0, Unknown}}, + {X86::VPERMT2PS256rmkz, {0, Unknown}}, + {X86::VPERMT2PS256rr, {0, Unknown}}, + {X86::VPERMT2PS256rrk, {0, Unknown}}, + {X86::VPERMT2PS256rrkz, {0, Unknown}}, + {X86::VPERMT2PSrm, {0, Unknown}}, + {X86::VPERMT2PSrmb, {0, Unknown}}, + {X86::VPERMT2PSrmbk, {0, Unknown}}, + {X86::VPERMT2PSrmbkz, {0, Unknown}}, + {X86::VPERMT2PSrmk, {0, Unknown}}, + {X86::VPERMT2PSrmkz, {0, Unknown}}, + {X86::VPERMT2PSrr, {0, Unknown}}, + {X86::VPERMT2PSrrk, {0, Unknown}}, + {X86::VPERMT2PSrrkz, {0, Unknown}}, + {X86::VPERMT2Q128rm, {1, Unknown}}, + {X86::VPERMT2Q128rmb, {1, Unknown}}, + {X86::VPERMT2Q128rmbk, {1, Unknown}}, + {X86::VPERMT2Q128rmbkz, {1, Unknown}}, + {X86::VPERMT2Q128rmk, {1, Unknown}}, + {X86::VPERMT2Q128rmkz, {1, Unknown}}, + {X86::VPERMT2Q128rr, {0, Unknown}}, + {X86::VPERMT2Q128rrk, {0, Unknown}}, + {X86::VPERMT2Q128rrkz, {0, Unknown}}, + {X86::VPERMT2Q256rm, {0, Unknown}}, + {X86::VPERMT2Q256rmb, {0, Unknown}}, + {X86::VPERMT2Q256rmbk, {0, Unknown}}, + {X86::VPERMT2Q256rmbkz, {0, Unknown}}, + {X86::VPERMT2Q256rmk, {0, Unknown}}, + {X86::VPERMT2Q256rmkz, {0, Unknown}}, + {X86::VPERMT2Q256rr, {0, Unknown}}, + {X86::VPERMT2Q256rrk, {0, Unknown}}, + {X86::VPERMT2Q256rrkz, {0, Unknown}}, + {X86::VPERMT2Qrm, {0, Unknown}}, + {X86::VPERMT2Qrmb, {0, Unknown}}, + {X86::VPERMT2Qrmbk, {0, Unknown}}, + {X86::VPERMT2Qrmbkz, {0, Unknown}}, + {X86::VPERMT2Qrmk, {0, Unknown}}, + {X86::VPERMT2Qrmkz, {0, Unknown}}, + {X86::VPERMT2Qrr, {0, Unknown}}, + {X86::VPERMT2Qrrk, {0, Unknown}}, + {X86::VPERMT2Qrrkz, {0, Unknown}}, + {X86::VPERMT2W128rm, {1, Unknown}}, + {X86::VPERMT2W128rmk, {1, Unknown}}, + {X86::VPERMT2W128rmkz, {1, Unknown}}, + {X86::VPERMT2W128rr, {0, Unknown}}, + {X86::VPERMT2W128rrk, {0, Unknown}}, + {X86::VPERMT2W128rrkz, {0, Unknown}}, + {X86::VPERMT2W256rm, {0, Unknown}}, + {X86::VPERMT2W256rmk, {0, Unknown}}, + {X86::VPERMT2W256rmkz, {0, Unknown}}, + {X86::VPERMT2W256rr, {0, Unknown}}, + {X86::VPERMT2W256rrk, {0, Unknown}}, + {X86::VPERMT2W256rrkz, {0, Unknown}}, + {X86::VPERMT2Wrm, {0, Unknown}}, + {X86::VPERMT2Wrmk, {0, Unknown}}, + {X86::VPERMT2Wrmkz, {0, Unknown}}, + {X86::VPERMT2Wrr, {0, Unknown}}, + {X86::VPERMT2Wrrk, {0, Unknown}}, + {X86::VPERMT2Wrrkz, {0, Unknown}}, + {X86::VPERMWZ128rm, {1, Unknown}}, + {X86::VPERMWZ128rmk, {1, Unknown}}, + {X86::VPERMWZ128rmkz, {1, Unknown}}, + {X86::VPERMWZ128rr, {0, Unknown}}, + {X86::VPERMWZ128rrk, {0, Unknown}}, + {X86::VPERMWZ128rrkz, {0, Unknown}}, + {X86::VPERMWZ256rm, {0, Unknown}}, + {X86::VPERMWZ256rmk, {0, Unknown}}, + {X86::VPERMWZ256rmkz, {0, Unknown}}, + {X86::VPERMWZ256rr, {0, Unknown}}, + {X86::VPERMWZ256rrk, {0, Unknown}}, + {X86::VPERMWZ256rrkz, {0, Unknown}}, + {X86::VPERMWZrm, {0, Unknown}}, + {X86::VPERMWZrmk, {0, Unknown}}, + {X86::VPERMWZrmkz, {0, Unknown}}, + {X86::VPERMWZrr, {0, Unknown}}, + {X86::VPERMWZrrk, {0, Unknown}}, + {X86::VPERMWZrrkz, {0, Unknown}}, + {X86::VPEXPANDBZ128rm, {1, Unknown}}, + {X86::VPEXPANDBZ128rmk, {1, Unknown}}, + {X86::VPEXPANDBZ128rmkz, {1, Unknown}}, + {X86::VPEXPANDBZ128rr, {0, Unknown}}, + {X86::VPEXPANDBZ128rrk, {0, Unknown}}, + {X86::VPEXPANDBZ128rrkz, {0, Unknown}}, + {X86::VPEXPANDBZ256rm, {0, Unknown}}, + {X86::VPEXPANDBZ256rmk, {0, Unknown}}, + {X86::VPEXPANDBZ256rmkz, {0, Unknown}}, + {X86::VPEXPANDBZ256rr, {0, Unknown}}, + {X86::VPEXPANDBZ256rrk, {0, Unknown}}, + {X86::VPEXPANDBZ256rrkz, {0, Unknown}}, + {X86::VPEXPANDBZrm, {0, Unknown}}, + {X86::VPEXPANDBZrmk, {0, Unknown}}, + {X86::VPEXPANDBZrmkz, {0, Unknown}}, + {X86::VPEXPANDBZrr, {0, Unknown}}, + {X86::VPEXPANDBZrrk, {0, Unknown}}, + {X86::VPEXPANDBZrrkz, {0, Unknown}}, + {X86::VPEXPANDDZ128rm, {1, Unknown}}, + {X86::VPEXPANDDZ128rmk, {1, Unknown}}, + {X86::VPEXPANDDZ128rmkz, {1, Unknown}}, + {X86::VPEXPANDDZ128rr, {0, Unknown}}, + {X86::VPEXPANDDZ128rrk, {0, Unknown}}, + {X86::VPEXPANDDZ128rrkz, {0, Unknown}}, + {X86::VPEXPANDDZ256rm, {0, Unknown}}, + {X86::VPEXPANDDZ256rmk, {0, Unknown}}, + {X86::VPEXPANDDZ256rmkz, {0, Unknown}}, + {X86::VPEXPANDDZ256rr, {0, Unknown}}, + {X86::VPEXPANDDZ256rrk, {0, Unknown}}, + {X86::VPEXPANDDZ256rrkz, {0, Unknown}}, + {X86::VPEXPANDDZrm, {0, Unknown}}, + {X86::VPEXPANDDZrmk, {0, Unknown}}, + {X86::VPEXPANDDZrmkz, {0, Unknown}}, + {X86::VPEXPANDDZrr, {0, Unknown}}, + {X86::VPEXPANDDZrrk, {0, Unknown}}, + {X86::VPEXPANDDZrrkz, {0, Unknown}}, + {X86::VPEXPANDQZ128rm, {1, Unknown}}, + {X86::VPEXPANDQZ128rmk, {1, Unknown}}, + {X86::VPEXPANDQZ128rmkz, {1, Unknown}}, + {X86::VPEXPANDQZ128rr, {0, Unknown}}, + {X86::VPEXPANDQZ128rrk, {0, Unknown}}, + {X86::VPEXPANDQZ128rrkz, {0, Unknown}}, + {X86::VPEXPANDQZ256rm, {0, Unknown}}, + {X86::VPEXPANDQZ256rmk, {0, Unknown}}, + {X86::VPEXPANDQZ256rmkz, {0, Unknown}}, + {X86::VPEXPANDQZ256rr, {0, Unknown}}, + {X86::VPEXPANDQZ256rrk, {0, Unknown}}, + {X86::VPEXPANDQZ256rrkz, {0, Unknown}}, + {X86::VPEXPANDQZrm, {0, Unknown}}, + {X86::VPEXPANDQZrmk, {0, Unknown}}, + {X86::VPEXPANDQZrmkz, {0, Unknown}}, + {X86::VPEXPANDQZrr, {0, Unknown}}, + {X86::VPEXPANDQZrrk, {0, Unknown}}, + {X86::VPEXPANDQZrrkz, {0, Unknown}}, + {X86::VPEXPANDWZ128rm, {1, Unknown}}, + {X86::VPEXPANDWZ128rmk, {1, Unknown}}, + {X86::VPEXPANDWZ128rmkz, {1, Unknown}}, + {X86::VPEXPANDWZ128rr, {0, Unknown}}, + {X86::VPEXPANDWZ128rrk, {0, Unknown}}, + {X86::VPEXPANDWZ128rrkz, {0, Unknown}}, + {X86::VPEXPANDWZ256rm, {0, Unknown}}, + {X86::VPEXPANDWZ256rmk, {0, Unknown}}, + {X86::VPEXPANDWZ256rmkz, {0, Unknown}}, + {X86::VPEXPANDWZ256rr, {0, Unknown}}, + {X86::VPEXPANDWZ256rrk, {0, Unknown}}, + {X86::VPEXPANDWZ256rrkz, {0, Unknown}}, + {X86::VPEXPANDWZrm, {0, Unknown}}, + {X86::VPEXPANDWZrmk, {0, Unknown}}, + {X86::VPEXPANDWZrmkz, {0, Unknown}}, + {X86::VPEXPANDWZrr, {0, Unknown}}, + {X86::VPEXPANDWZrrk, {0, Unknown}}, + {X86::VPEXPANDWZrrkz, {0, Unknown}}, + {X86::VPEXTRBZmr, {0, Unknown}}, + {X86::VPEXTRBZrr, {0, Unknown}}, + {X86::VPEXTRBmr, {0, Unknown}}, + {X86::VPEXTRBrr, {0, Unknown}}, + {X86::VPEXTRDZmr, {0, Unknown}}, + {X86::VPEXTRDZrr, {0, Unknown}}, + {X86::VPEXTRDmr, {0, Unknown}}, + {X86::VPEXTRDrr, {0, Unknown}}, + {X86::VPEXTRQZmr, {0, Unknown}}, + {X86::VPEXTRQZrr, {0, Unknown}}, + {X86::VPEXTRQmr, {0, Unknown}}, + {X86::VPEXTRQrr, {0, Unknown}}, + {X86::VPEXTRWZmr, {0, Unknown}}, + {X86::VPEXTRWZrr, {0, Unknown}}, + {X86::VPEXTRWZrr_REV, {0, Unknown}}, + {X86::VPEXTRWmr, {0, Unknown}}, + {X86::VPEXTRWrr, {0, Unknown}}, + {X86::VPEXTRWrr_REV, {0, Unknown}}, + {X86::VPGATHERDDYrm, {0, Unknown}}, + {X86::VPGATHERDDZ128rm, {1, Unknown}}, + {X86::VPGATHERDDZ256rm, {0, Unknown}}, + {X86::VPGATHERDDZrm, {0, Unknown}}, + {X86::VPGATHERDDrm, {0, Unknown}}, + {X86::VPGATHERDQYrm, {0, Unknown}}, + {X86::VPGATHERDQZ128rm, {1, Unknown}}, + {X86::VPGATHERDQZ256rm, {0, Unknown}}, + {X86::VPGATHERDQZrm, {0, Unknown}}, + {X86::VPGATHERDQrm, {0, Unknown}}, + {X86::VPGATHERQDYrm, {0, Unknown}}, + {X86::VPGATHERQDZ128rm, {1, Unknown}}, + {X86::VPGATHERQDZ256rm, {0, Unknown}}, + {X86::VPGATHERQDZrm, {0, Unknown}}, + {X86::VPGATHERQDrm, {0, Unknown}}, + {X86::VPGATHERQQYrm, {0, Unknown}}, + {X86::VPGATHERQQZ128rm, {1, Unknown}}, + {X86::VPGATHERQQZ256rm, {0, Unknown}}, + {X86::VPGATHERQQZrm, {0, Unknown}}, + {X86::VPGATHERQQrm, {0, Unknown}}, + {X86::VPHADDBDrm, {0, Unknown}}, + {X86::VPHADDBDrr, {0, Unknown}}, + {X86::VPHADDBQrm, {0, Unknown}}, + {X86::VPHADDBQrr, {0, Unknown}}, + {X86::VPHADDBWrm, {0, Unknown}}, + {X86::VPHADDBWrr, {0, Unknown}}, + {X86::VPHADDDQrm, {0, Unknown}}, + {X86::VPHADDDQrr, {0, Unknown}}, + {X86::VPHADDDYrm, {0, Unknown}}, + {X86::VPHADDDYrr, {0, Unknown}}, + {X86::VPHADDDrm, {0, Unknown}}, + {X86::VPHADDDrr, {0, Unknown}}, + {X86::VPHADDSWYrm, {0, Unknown}}, + {X86::VPHADDSWYrr, {0, Unknown}}, + {X86::VPHADDSWrm, {0, Unknown}}, + {X86::VPHADDSWrr, {0, Unknown}}, + {X86::VPHADDUBDrm, {0, Unknown}}, + {X86::VPHADDUBDrr, {0, Unknown}}, + {X86::VPHADDUBQrm, {0, Unknown}}, + {X86::VPHADDUBQrr, {0, Unknown}}, + {X86::VPHADDUBWrm, {0, Unknown}}, + {X86::VPHADDUBWrr, {0, Unknown}}, + {X86::VPHADDUDQrm, {0, Unknown}}, + {X86::VPHADDUDQrr, {0, Unknown}}, + {X86::VPHADDUWDrm, {0, Unknown}}, + {X86::VPHADDUWDrr, {0, Unknown}}, + {X86::VPHADDUWQrm, {0, Unknown}}, + {X86::VPHADDUWQrr, {0, Unknown}}, + {X86::VPHADDWDrm, {0, Unknown}}, + {X86::VPHADDWDrr, {0, Unknown}}, + {X86::VPHADDWQrm, {0, Unknown}}, + {X86::VPHADDWQrr, {0, Unknown}}, + {X86::VPHADDWYrm, {0, Unknown}}, + {X86::VPHADDWYrr, {0, Unknown}}, + {X86::VPHADDWrm, {0, Unknown}}, + {X86::VPHADDWrr, {0, Unknown}}, + {X86::VPHMINPOSUWrm, {0, Unknown}}, + {X86::VPHMINPOSUWrr, {0, Unknown}}, + {X86::VPHSUBBWrm, {0, Unknown}}, + {X86::VPHSUBBWrr, {0, Unknown}}, + {X86::VPHSUBDQrm, {0, Unknown}}, + {X86::VPHSUBDQrr, {0, Unknown}}, + {X86::VPHSUBDYrm, {0, Unknown}}, + {X86::VPHSUBDYrr, {0, Unknown}}, + {X86::VPHSUBDrm, {0, Unknown}}, + {X86::VPHSUBDrr, {0, Unknown}}, + {X86::VPHSUBSWYrm, {0, Unknown}}, + {X86::VPHSUBSWYrr, {0, Unknown}}, + {X86::VPHSUBSWrm, {0, Unknown}}, + {X86::VPHSUBSWrr, {0, Unknown}}, + {X86::VPHSUBWDrm, {0, Unknown}}, + {X86::VPHSUBWDrr, {0, Unknown}}, + {X86::VPHSUBWYrm, {0, Unknown}}, + {X86::VPHSUBWYrr, {0, Unknown}}, + {X86::VPHSUBWrm, {0, Unknown}}, + {X86::VPHSUBWrr, {0, Unknown}}, + {X86::VPINSRBZrm, {0, Unknown}}, + {X86::VPINSRBZrr, {0, Unknown}}, + {X86::VPINSRBrm, {0, Unknown}}, + {X86::VPINSRBrr, {0, Unknown}}, + {X86::VPINSRDZrm, {0, Unknown}}, + {X86::VPINSRDZrr, {0, Unknown}}, + {X86::VPINSRDrm, {0, Unknown}}, + {X86::VPINSRDrr, {0, Unknown}}, + {X86::VPINSRQZrm, {0, Unknown}}, + {X86::VPINSRQZrr, {0, Unknown}}, + {X86::VPINSRQrm, {0, Unknown}}, + {X86::VPINSRQrr, {0, Unknown}}, + {X86::VPINSRWZrm, {0, Unknown}}, + {X86::VPINSRWZrr, {0, Unknown}}, + {X86::VPINSRWrm, {0, Unknown}}, + {X86::VPINSRWrr, {0, Unknown}}, + {X86::VPLZCNTDZ128rm, {1, Unknown}}, + {X86::VPLZCNTDZ128rmb, {1, Unknown}}, + {X86::VPLZCNTDZ128rmbk, {1, Unknown}}, + {X86::VPLZCNTDZ128rmbkz, {1, Unknown}}, + {X86::VPLZCNTDZ128rmk, {1, Unknown}}, + {X86::VPLZCNTDZ128rmkz, {1, Unknown}}, + {X86::VPLZCNTDZ128rr, {0, Unknown}}, + {X86::VPLZCNTDZ128rrk, {0, Unknown}}, + {X86::VPLZCNTDZ128rrkz, {0, Unknown}}, + {X86::VPLZCNTDZ256rm, {0, Unknown}}, + {X86::VPLZCNTDZ256rmb, {0, Unknown}}, + {X86::VPLZCNTDZ256rmbk, {0, Unknown}}, + {X86::VPLZCNTDZ256rmbkz, {0, Unknown}}, + {X86::VPLZCNTDZ256rmk, {0, Unknown}}, + {X86::VPLZCNTDZ256rmkz, {0, Unknown}}, + {X86::VPLZCNTDZ256rr, {0, Unknown}}, + {X86::VPLZCNTDZ256rrk, {0, Unknown}}, + {X86::VPLZCNTDZ256rrkz, {0, Unknown}}, + {X86::VPLZCNTDZrm, {0, Unknown}}, + {X86::VPLZCNTDZrmb, {0, Unknown}}, + {X86::VPLZCNTDZrmbk, {0, Unknown}}, + {X86::VPLZCNTDZrmbkz, {0, Unknown}}, + {X86::VPLZCNTDZrmk, {0, Unknown}}, + {X86::VPLZCNTDZrmkz, {0, Unknown}}, + {X86::VPLZCNTDZrr, {0, Unknown}}, + {X86::VPLZCNTDZrrk, {0, Unknown}}, + {X86::VPLZCNTDZrrkz, {0, Unknown}}, + {X86::VPLZCNTQZ128rm, {1, Unknown}}, + {X86::VPLZCNTQZ128rmb, {1, Unknown}}, + {X86::VPLZCNTQZ128rmbk, {1, Unknown}}, + {X86::VPLZCNTQZ128rmbkz, {1, Unknown}}, + {X86::VPLZCNTQZ128rmk, {1, Unknown}}, + {X86::VPLZCNTQZ128rmkz, {1, Unknown}}, + {X86::VPLZCNTQZ128rr, {0, Unknown}}, + {X86::VPLZCNTQZ128rrk, {0, Unknown}}, + {X86::VPLZCNTQZ128rrkz, {0, Unknown}}, + {X86::VPLZCNTQZ256rm, {0, Unknown}}, + {X86::VPLZCNTQZ256rmb, {0, Unknown}}, + {X86::VPLZCNTQZ256rmbk, {0, Unknown}}, + {X86::VPLZCNTQZ256rmbkz, {0, Unknown}}, + {X86::VPLZCNTQZ256rmk, {0, Unknown}}, + {X86::VPLZCNTQZ256rmkz, {0, Unknown}}, + {X86::VPLZCNTQZ256rr, {0, Unknown}}, + {X86::VPLZCNTQZ256rrk, {0, Unknown}}, + {X86::VPLZCNTQZ256rrkz, {0, Unknown}}, + {X86::VPLZCNTQZrm, {0, Unknown}}, + {X86::VPLZCNTQZrmb, {0, Unknown}}, + {X86::VPLZCNTQZrmbk, {0, Unknown}}, + {X86::VPLZCNTQZrmbkz, {0, Unknown}}, + {X86::VPLZCNTQZrmk, {0, Unknown}}, + {X86::VPLZCNTQZrmkz, {0, Unknown}}, + {X86::VPLZCNTQZrr, {0, Unknown}}, + {X86::VPLZCNTQZrrk, {0, Unknown}}, + {X86::VPLZCNTQZrrkz, {0, Unknown}}, + {X86::VPMACSDDrm, {0, Unknown}}, + {X86::VPMACSDDrr, {0, Unknown}}, + {X86::VPMACSDQHrm, {0, Unknown}}, + {X86::VPMACSDQHrr, {0, Unknown}}, + {X86::VPMACSDQLrm, {0, Unknown}}, + {X86::VPMACSDQLrr, {0, Unknown}}, + {X86::VPMACSSDDrm, {0, Unknown}}, + {X86::VPMACSSDDrr, {0, Unknown}}, + {X86::VPMACSSDQHrm, {0, Unknown}}, + {X86::VPMACSSDQHrr, {0, Unknown}}, + {X86::VPMACSSDQLrm, {0, Unknown}}, + {X86::VPMACSSDQLrr, {0, Unknown}}, + {X86::VPMACSSWDrm, {0, Unknown}}, + {X86::VPMACSSWDrr, {0, Unknown}}, + {X86::VPMACSSWWrm, {0, Unknown}}, + {X86::VPMACSSWWrr, {0, Unknown}}, + {X86::VPMACSWDrm, {0, Unknown}}, + {X86::VPMACSWDrr, {0, Unknown}}, + {X86::VPMACSWWrm, {0, Unknown}}, + {X86::VPMACSWWrr, {0, Unknown}}, + {X86::VPMADCSSWDrm, {0, Unknown}}, + {X86::VPMADCSSWDrr, {0, Unknown}}, + {X86::VPMADCSWDrm, {0, Unknown}}, + {X86::VPMADCSWDrr, {0, Unknown}}, + {X86::VPMADD52HUQZ128m, {0, Unknown}}, + {X86::VPMADD52HUQZ128mb, {0, Unknown}}, + {X86::VPMADD52HUQZ128mbk, {0, Unknown}}, + {X86::VPMADD52HUQZ128mbkz, {0, Unknown}}, + {X86::VPMADD52HUQZ128mk, {0, Unknown}}, + {X86::VPMADD52HUQZ128mkz, {0, Unknown}}, + {X86::VPMADD52HUQZ128r, {0, Unknown}}, + {X86::VPMADD52HUQZ128rk, {0, Unknown}}, + {X86::VPMADD52HUQZ128rkz, {0, Unknown}}, + {X86::VPMADD52HUQZ256m, {0, Unknown}}, + {X86::VPMADD52HUQZ256mb, {0, Unknown}}, + {X86::VPMADD52HUQZ256mbk, {0, Unknown}}, + {X86::VPMADD52HUQZ256mbkz, {0, Unknown}}, + {X86::VPMADD52HUQZ256mk, {0, Unknown}}, + {X86::VPMADD52HUQZ256mkz, {0, Unknown}}, + {X86::VPMADD52HUQZ256r, {0, Unknown}}, + {X86::VPMADD52HUQZ256rk, {0, Unknown}}, + {X86::VPMADD52HUQZ256rkz, {0, Unknown}}, + {X86::VPMADD52HUQZm, {0, Unknown}}, + {X86::VPMADD52HUQZmb, {0, Unknown}}, + {X86::VPMADD52HUQZmbk, {0, Unknown}}, + {X86::VPMADD52HUQZmbkz, {0, Unknown}}, + {X86::VPMADD52HUQZmk, {0, Unknown}}, + {X86::VPMADD52HUQZmkz, {0, Unknown}}, + {X86::VPMADD52HUQZr, {0, Unknown}}, + {X86::VPMADD52HUQZrk, {0, Unknown}}, + {X86::VPMADD52HUQZrkz, {0, Unknown}}, + {X86::VPMADD52LUQZ128m, {0, Unknown}}, + {X86::VPMADD52LUQZ128mb, {0, Unknown}}, + {X86::VPMADD52LUQZ128mbk, {0, Unknown}}, + {X86::VPMADD52LUQZ128mbkz, {0, Unknown}}, + {X86::VPMADD52LUQZ128mk, {0, Unknown}}, + {X86::VPMADD52LUQZ128mkz, {0, Unknown}}, + {X86::VPMADD52LUQZ128r, {0, Unknown}}, + {X86::VPMADD52LUQZ128rk, {0, Unknown}}, + {X86::VPMADD52LUQZ128rkz, {0, Unknown}}, + {X86::VPMADD52LUQZ256m, {0, Unknown}}, + {X86::VPMADD52LUQZ256mb, {0, Unknown}}, + {X86::VPMADD52LUQZ256mbk, {0, Unknown}}, + {X86::VPMADD52LUQZ256mbkz, {0, Unknown}}, + {X86::VPMADD52LUQZ256mk, {0, Unknown}}, + {X86::VPMADD52LUQZ256mkz, {0, Unknown}}, + {X86::VPMADD52LUQZ256r, {0, Unknown}}, + {X86::VPMADD52LUQZ256rk, {0, Unknown}}, + {X86::VPMADD52LUQZ256rkz, {0, Unknown}}, + {X86::VPMADD52LUQZm, {0, Unknown}}, + {X86::VPMADD52LUQZmb, {0, Unknown}}, + {X86::VPMADD52LUQZmbk, {0, Unknown}}, + {X86::VPMADD52LUQZmbkz, {0, Unknown}}, + {X86::VPMADD52LUQZmk, {0, Unknown}}, + {X86::VPMADD52LUQZmkz, {0, Unknown}}, + {X86::VPMADD52LUQZr, {0, Unknown}}, + {X86::VPMADD52LUQZrk, {0, Unknown}}, + {X86::VPMADD52LUQZrkz, {0, Unknown}}, + {X86::VPMADDUBSWYrm, {0, Unknown}}, + {X86::VPMADDUBSWYrr, {0, Unknown}}, + {X86::VPMADDUBSWZ128rm, {1, Unknown}}, + {X86::VPMADDUBSWZ128rmk, {1, Unknown}}, + {X86::VPMADDUBSWZ128rmkz, {1, Unknown}}, + {X86::VPMADDUBSWZ128rr, {0, Unknown}}, + {X86::VPMADDUBSWZ128rrk, {0, Unknown}}, + {X86::VPMADDUBSWZ128rrkz, {0, Unknown}}, + {X86::VPMADDUBSWZ256rm, {0, Unknown}}, + {X86::VPMADDUBSWZ256rmk, {0, Unknown}}, + {X86::VPMADDUBSWZ256rmkz, {0, Unknown}}, + {X86::VPMADDUBSWZ256rr, {0, Unknown}}, + {X86::VPMADDUBSWZ256rrk, {0, Unknown}}, + {X86::VPMADDUBSWZ256rrkz, {0, Unknown}}, + {X86::VPMADDUBSWZrm, {0, Unknown}}, + {X86::VPMADDUBSWZrmk, {0, Unknown}}, + {X86::VPMADDUBSWZrmkz, {0, Unknown}}, + {X86::VPMADDUBSWZrr, {0, Unknown}}, + {X86::VPMADDUBSWZrrk, {0, Unknown}}, + {X86::VPMADDUBSWZrrkz, {0, Unknown}}, + {X86::VPMADDUBSWrm, {0, Unknown}}, + {X86::VPMADDUBSWrr, {0, Unknown}}, + {X86::VPMADDWDYrm, {0, Unknown}}, + {X86::VPMADDWDYrr, {0, Unknown}}, + {X86::VPMADDWDZ128rm, {1, Unknown}}, + {X86::VPMADDWDZ128rmk, {1, Unknown}}, + {X86::VPMADDWDZ128rmkz, {1, Unknown}}, + {X86::VPMADDWDZ128rr, {0, Unknown}}, + {X86::VPMADDWDZ128rrk, {0, Unknown}}, + {X86::VPMADDWDZ128rrkz, {0, Unknown}}, + {X86::VPMADDWDZ256rm, {0, Unknown}}, + {X86::VPMADDWDZ256rmk, {0, Unknown}}, + {X86::VPMADDWDZ256rmkz, {0, Unknown}}, + {X86::VPMADDWDZ256rr, {0, Unknown}}, + {X86::VPMADDWDZ256rrk, {0, Unknown}}, + {X86::VPMADDWDZ256rrkz, {0, Unknown}}, + {X86::VPMADDWDZrm, {0, Unknown}}, + {X86::VPMADDWDZrmk, {0, Unknown}}, + {X86::VPMADDWDZrmkz, {0, Unknown}}, + {X86::VPMADDWDZrr, {0, Unknown}}, + {X86::VPMADDWDZrrk, {0, Unknown}}, + {X86::VPMADDWDZrrkz, {0, Unknown}}, + {X86::VPMADDWDrm, {0, Unknown}}, + {X86::VPMADDWDrr, {0, Unknown}}, + {X86::VPMASKMOVDYmr, {0, Unknown}}, + {X86::VPMASKMOVDYrm, {0, Unknown}}, + {X86::VPMASKMOVDmr, {0, Unknown}}, + {X86::VPMASKMOVDrm, {0, Unknown}}, + {X86::VPMASKMOVQYmr, {0, Unknown}}, + {X86::VPMASKMOVQYrm, {0, Unknown}}, + {X86::VPMASKMOVQmr, {0, Unknown}}, + {X86::VPMASKMOVQrm, {0, Unknown}}, + {X86::VPMAXSBYrm, {0, Unknown}}, + {X86::VPMAXSBYrr, {0, Unknown}}, + {X86::VPMAXSBZ128rm, {1, Unknown}}, + {X86::VPMAXSBZ128rmk, {1, Unknown}}, + {X86::VPMAXSBZ128rmkz, {1, Unknown}}, + {X86::VPMAXSBZ128rr, {0, Unknown}}, + {X86::VPMAXSBZ128rrk, {0, Unknown}}, + {X86::VPMAXSBZ128rrkz, {0, Unknown}}, + {X86::VPMAXSBZ256rm, {0, Unknown}}, + {X86::VPMAXSBZ256rmk, {0, Unknown}}, + {X86::VPMAXSBZ256rmkz, {0, Unknown}}, + {X86::VPMAXSBZ256rr, {0, Unknown}}, + {X86::VPMAXSBZ256rrk, {0, Unknown}}, + {X86::VPMAXSBZ256rrkz, {0, Unknown}}, + {X86::VPMAXSBZrm, {0, Unknown}}, + {X86::VPMAXSBZrmk, {0, Unknown}}, + {X86::VPMAXSBZrmkz, {0, Unknown}}, + {X86::VPMAXSBZrr, {0, Unknown}}, + {X86::VPMAXSBZrrk, {0, Unknown}}, + {X86::VPMAXSBZrrkz, {0, Unknown}}, + {X86::VPMAXSBrm, {0, Unknown}}, + {X86::VPMAXSBrr, {0, Unknown}}, + {X86::VPMAXSDYrm, {0, Unknown}}, + {X86::VPMAXSDYrr, {0, Unknown}}, + {X86::VPMAXSDZ128rm, {1, Unknown}}, + {X86::VPMAXSDZ128rmb, {1, Unknown}}, + {X86::VPMAXSDZ128rmbk, {1, Unknown}}, + {X86::VPMAXSDZ128rmbkz, {1, Unknown}}, + {X86::VPMAXSDZ128rmk, {1, Unknown}}, + {X86::VPMAXSDZ128rmkz, {1, Unknown}}, + {X86::VPMAXSDZ128rr, {0, Unknown}}, + {X86::VPMAXSDZ128rrk, {0, Unknown}}, + {X86::VPMAXSDZ128rrkz, {0, Unknown}}, + {X86::VPMAXSDZ256rm, {0, Unknown}}, + {X86::VPMAXSDZ256rmb, {0, Unknown}}, + {X86::VPMAXSDZ256rmbk, {0, Unknown}}, + {X86::VPMAXSDZ256rmbkz, {0, Unknown}}, + {X86::VPMAXSDZ256rmk, {0, Unknown}}, + {X86::VPMAXSDZ256rmkz, {0, Unknown}}, + {X86::VPMAXSDZ256rr, {0, Unknown}}, + {X86::VPMAXSDZ256rrk, {0, Unknown}}, + {X86::VPMAXSDZ256rrkz, {0, Unknown}}, + {X86::VPMAXSDZrm, {0, Unknown}}, + {X86::VPMAXSDZrmb, {0, Unknown}}, + {X86::VPMAXSDZrmbk, {0, Unknown}}, + {X86::VPMAXSDZrmbkz, {0, Unknown}}, + {X86::VPMAXSDZrmk, {0, Unknown}}, + {X86::VPMAXSDZrmkz, {0, Unknown}}, + {X86::VPMAXSDZrr, {0, Unknown}}, + {X86::VPMAXSDZrrk, {0, Unknown}}, + {X86::VPMAXSDZrrkz, {0, Unknown}}, + {X86::VPMAXSDrm, {0, Unknown}}, + {X86::VPMAXSDrr, {0, Unknown}}, + {X86::VPMAXSQZ128rm, {1, Unknown}}, + {X86::VPMAXSQZ128rmb, {1, Unknown}}, + {X86::VPMAXSQZ128rmbk, {1, Unknown}}, + {X86::VPMAXSQZ128rmbkz, {1, Unknown}}, + {X86::VPMAXSQZ128rmk, {1, Unknown}}, + {X86::VPMAXSQZ128rmkz, {1, Unknown}}, + {X86::VPMAXSQZ128rr, {0, Unknown}}, + {X86::VPMAXSQZ128rrk, {0, Unknown}}, + {X86::VPMAXSQZ128rrkz, {0, Unknown}}, + {X86::VPMAXSQZ256rm, {0, Unknown}}, + {X86::VPMAXSQZ256rmb, {0, Unknown}}, + {X86::VPMAXSQZ256rmbk, {0, Unknown}}, + {X86::VPMAXSQZ256rmbkz, {0, Unknown}}, + {X86::VPMAXSQZ256rmk, {0, Unknown}}, + {X86::VPMAXSQZ256rmkz, {0, Unknown}}, + {X86::VPMAXSQZ256rr, {0, Unknown}}, + {X86::VPMAXSQZ256rrk, {0, Unknown}}, + {X86::VPMAXSQZ256rrkz, {0, Unknown}}, + {X86::VPMAXSQZrm, {0, Unknown}}, + {X86::VPMAXSQZrmb, {0, Unknown}}, + {X86::VPMAXSQZrmbk, {0, Unknown}}, + {X86::VPMAXSQZrmbkz, {0, Unknown}}, + {X86::VPMAXSQZrmk, {0, Unknown}}, + {X86::VPMAXSQZrmkz, {0, Unknown}}, + {X86::VPMAXSQZrr, {0, Unknown}}, + {X86::VPMAXSQZrrk, {0, Unknown}}, + {X86::VPMAXSQZrrkz, {0, Unknown}}, + {X86::VPMAXSWYrm, {0, Unknown}}, + {X86::VPMAXSWYrr, {0, Unknown}}, + {X86::VPMAXSWZ128rm, {1, Unknown}}, + {X86::VPMAXSWZ128rmk, {1, Unknown}}, + {X86::VPMAXSWZ128rmkz, {1, Unknown}}, + {X86::VPMAXSWZ128rr, {0, Unknown}}, + {X86::VPMAXSWZ128rrk, {0, Unknown}}, + {X86::VPMAXSWZ128rrkz, {0, Unknown}}, + {X86::VPMAXSWZ256rm, {0, Unknown}}, + {X86::VPMAXSWZ256rmk, {0, Unknown}}, + {X86::VPMAXSWZ256rmkz, {0, Unknown}}, + {X86::VPMAXSWZ256rr, {0, Unknown}}, + {X86::VPMAXSWZ256rrk, {0, Unknown}}, + {X86::VPMAXSWZ256rrkz, {0, Unknown}}, + {X86::VPMAXSWZrm, {0, Unknown}}, + {X86::VPMAXSWZrmk, {0, Unknown}}, + {X86::VPMAXSWZrmkz, {0, Unknown}}, + {X86::VPMAXSWZrr, {0, Unknown}}, + {X86::VPMAXSWZrrk, {0, Unknown}}, + {X86::VPMAXSWZrrkz, {0, Unknown}}, + {X86::VPMAXSWrm, {0, Unknown}}, + {X86::VPMAXSWrr, {0, Unknown}}, + {X86::VPMAXUBYrm, {0, Unknown}}, + {X86::VPMAXUBYrr, {0, Unknown}}, + {X86::VPMAXUBZ128rm, {1, Unknown}}, + {X86::VPMAXUBZ128rmk, {1, Unknown}}, + {X86::VPMAXUBZ128rmkz, {1, Unknown}}, + {X86::VPMAXUBZ128rr, {0, Unknown}}, + {X86::VPMAXUBZ128rrk, {0, Unknown}}, + {X86::VPMAXUBZ128rrkz, {0, Unknown}}, + {X86::VPMAXUBZ256rm, {0, Unknown}}, + {X86::VPMAXUBZ256rmk, {0, Unknown}}, + {X86::VPMAXUBZ256rmkz, {0, Unknown}}, + {X86::VPMAXUBZ256rr, {0, Unknown}}, + {X86::VPMAXUBZ256rrk, {0, Unknown}}, + {X86::VPMAXUBZ256rrkz, {0, Unknown}}, + {X86::VPMAXUBZrm, {0, Unknown}}, + {X86::VPMAXUBZrmk, {0, Unknown}}, + {X86::VPMAXUBZrmkz, {0, Unknown}}, + {X86::VPMAXUBZrr, {0, Unknown}}, + {X86::VPMAXUBZrrk, {0, Unknown}}, + {X86::VPMAXUBZrrkz, {0, Unknown}}, + {X86::VPMAXUBrm, {0, Unknown}}, + {X86::VPMAXUBrr, {0, Unknown}}, + {X86::VPMAXUDYrm, {0, Unknown}}, + {X86::VPMAXUDYrr, {0, Unknown}}, + {X86::VPMAXUDZ128rm, {1, Unknown}}, + {X86::VPMAXUDZ128rmb, {1, Unknown}}, + {X86::VPMAXUDZ128rmbk, {1, Unknown}}, + {X86::VPMAXUDZ128rmbkz, {1, Unknown}}, + {X86::VPMAXUDZ128rmk, {1, Unknown}}, + {X86::VPMAXUDZ128rmkz, {1, Unknown}}, + {X86::VPMAXUDZ128rr, {0, Unknown}}, + {X86::VPMAXUDZ128rrk, {0, Unknown}}, + {X86::VPMAXUDZ128rrkz, {0, Unknown}}, + {X86::VPMAXUDZ256rm, {0, Unknown}}, + {X86::VPMAXUDZ256rmb, {0, Unknown}}, + {X86::VPMAXUDZ256rmbk, {0, Unknown}}, + {X86::VPMAXUDZ256rmbkz, {0, Unknown}}, + {X86::VPMAXUDZ256rmk, {0, Unknown}}, + {X86::VPMAXUDZ256rmkz, {0, Unknown}}, + {X86::VPMAXUDZ256rr, {0, Unknown}}, + {X86::VPMAXUDZ256rrk, {0, Unknown}}, + {X86::VPMAXUDZ256rrkz, {0, Unknown}}, + {X86::VPMAXUDZrm, {0, Unknown}}, + {X86::VPMAXUDZrmb, {0, Unknown}}, + {X86::VPMAXUDZrmbk, {0, Unknown}}, + {X86::VPMAXUDZrmbkz, {0, Unknown}}, + {X86::VPMAXUDZrmk, {0, Unknown}}, + {X86::VPMAXUDZrmkz, {0, Unknown}}, + {X86::VPMAXUDZrr, {0, Unknown}}, + {X86::VPMAXUDZrrk, {0, Unknown}}, + {X86::VPMAXUDZrrkz, {0, Unknown}}, + {X86::VPMAXUDrm, {0, Unknown}}, + {X86::VPMAXUDrr, {0, Unknown}}, + {X86::VPMAXUQZ128rm, {1, Unknown}}, + {X86::VPMAXUQZ128rmb, {1, Unknown}}, + {X86::VPMAXUQZ128rmbk, {1, Unknown}}, + {X86::VPMAXUQZ128rmbkz, {1, Unknown}}, + {X86::VPMAXUQZ128rmk, {1, Unknown}}, + {X86::VPMAXUQZ128rmkz, {1, Unknown}}, + {X86::VPMAXUQZ128rr, {0, Unknown}}, + {X86::VPMAXUQZ128rrk, {0, Unknown}}, + {X86::VPMAXUQZ128rrkz, {0, Unknown}}, + {X86::VPMAXUQZ256rm, {0, Unknown}}, + {X86::VPMAXUQZ256rmb, {0, Unknown}}, + {X86::VPMAXUQZ256rmbk, {0, Unknown}}, + {X86::VPMAXUQZ256rmbkz, {0, Unknown}}, + {X86::VPMAXUQZ256rmk, {0, Unknown}}, + {X86::VPMAXUQZ256rmkz, {0, Unknown}}, + {X86::VPMAXUQZ256rr, {0, Unknown}}, + {X86::VPMAXUQZ256rrk, {0, Unknown}}, + {X86::VPMAXUQZ256rrkz, {0, Unknown}}, + {X86::VPMAXUQZrm, {0, Unknown}}, + {X86::VPMAXUQZrmb, {0, Unknown}}, + {X86::VPMAXUQZrmbk, {0, Unknown}}, + {X86::VPMAXUQZrmbkz, {0, Unknown}}, + {X86::VPMAXUQZrmk, {0, Unknown}}, + {X86::VPMAXUQZrmkz, {0, Unknown}}, + {X86::VPMAXUQZrr, {0, Unknown}}, + {X86::VPMAXUQZrrk, {0, Unknown}}, + {X86::VPMAXUQZrrkz, {0, Unknown}}, + {X86::VPMAXUWYrm, {0, Unknown}}, + {X86::VPMAXUWYrr, {0, Unknown}}, + {X86::VPMAXUWZ128rm, {1, Unknown}}, + {X86::VPMAXUWZ128rmk, {1, Unknown}}, + {X86::VPMAXUWZ128rmkz, {1, Unknown}}, + {X86::VPMAXUWZ128rr, {0, Unknown}}, + {X86::VPMAXUWZ128rrk, {0, Unknown}}, + {X86::VPMAXUWZ128rrkz, {0, Unknown}}, + {X86::VPMAXUWZ256rm, {0, Unknown}}, + {X86::VPMAXUWZ256rmk, {0, Unknown}}, + {X86::VPMAXUWZ256rmkz, {0, Unknown}}, + {X86::VPMAXUWZ256rr, {0, Unknown}}, + {X86::VPMAXUWZ256rrk, {0, Unknown}}, + {X86::VPMAXUWZ256rrkz, {0, Unknown}}, + {X86::VPMAXUWZrm, {0, Unknown}}, + {X86::VPMAXUWZrmk, {0, Unknown}}, + {X86::VPMAXUWZrmkz, {0, Unknown}}, + {X86::VPMAXUWZrr, {0, Unknown}}, + {X86::VPMAXUWZrrk, {0, Unknown}}, + {X86::VPMAXUWZrrkz, {0, Unknown}}, + {X86::VPMAXUWrm, {0, Unknown}}, + {X86::VPMAXUWrr, {0, Unknown}}, + {X86::VPMINSBYrm, {0, Unknown}}, + {X86::VPMINSBYrr, {0, Unknown}}, + {X86::VPMINSBZ128rm, {1, Unknown}}, + {X86::VPMINSBZ128rmk, {1, Unknown}}, + {X86::VPMINSBZ128rmkz, {1, Unknown}}, + {X86::VPMINSBZ128rr, {0, Unknown}}, + {X86::VPMINSBZ128rrk, {0, Unknown}}, + {X86::VPMINSBZ128rrkz, {0, Unknown}}, + {X86::VPMINSBZ256rm, {0, Unknown}}, + {X86::VPMINSBZ256rmk, {0, Unknown}}, + {X86::VPMINSBZ256rmkz, {0, Unknown}}, + {X86::VPMINSBZ256rr, {0, Unknown}}, + {X86::VPMINSBZ256rrk, {0, Unknown}}, + {X86::VPMINSBZ256rrkz, {0, Unknown}}, + {X86::VPMINSBZrm, {0, Unknown}}, + {X86::VPMINSBZrmk, {0, Unknown}}, + {X86::VPMINSBZrmkz, {0, Unknown}}, + {X86::VPMINSBZrr, {0, Unknown}}, + {X86::VPMINSBZrrk, {0, Unknown}}, + {X86::VPMINSBZrrkz, {0, Unknown}}, + {X86::VPMINSBrm, {0, Unknown}}, + {X86::VPMINSBrr, {0, Unknown}}, + {X86::VPMINSDYrm, {0, Unknown}}, + {X86::VPMINSDYrr, {0, Unknown}}, + {X86::VPMINSDZ128rm, {1, Unknown}}, + {X86::VPMINSDZ128rmb, {1, Unknown}}, + {X86::VPMINSDZ128rmbk, {1, Unknown}}, + {X86::VPMINSDZ128rmbkz, {1, Unknown}}, + {X86::VPMINSDZ128rmk, {1, Unknown}}, + {X86::VPMINSDZ128rmkz, {1, Unknown}}, + {X86::VPMINSDZ128rr, {0, Unknown}}, + {X86::VPMINSDZ128rrk, {0, Unknown}}, + {X86::VPMINSDZ128rrkz, {0, Unknown}}, + {X86::VPMINSDZ256rm, {0, Unknown}}, + {X86::VPMINSDZ256rmb, {0, Unknown}}, + {X86::VPMINSDZ256rmbk, {0, Unknown}}, + {X86::VPMINSDZ256rmbkz, {0, Unknown}}, + {X86::VPMINSDZ256rmk, {0, Unknown}}, + {X86::VPMINSDZ256rmkz, {0, Unknown}}, + {X86::VPMINSDZ256rr, {0, Unknown}}, + {X86::VPMINSDZ256rrk, {0, Unknown}}, + {X86::VPMINSDZ256rrkz, {0, Unknown}}, + {X86::VPMINSDZrm, {0, Unknown}}, + {X86::VPMINSDZrmb, {0, Unknown}}, + {X86::VPMINSDZrmbk, {0, Unknown}}, + {X86::VPMINSDZrmbkz, {0, Unknown}}, + {X86::VPMINSDZrmk, {0, Unknown}}, + {X86::VPMINSDZrmkz, {0, Unknown}}, + {X86::VPMINSDZrr, {0, Unknown}}, + {X86::VPMINSDZrrk, {0, Unknown}}, + {X86::VPMINSDZrrkz, {0, Unknown}}, + {X86::VPMINSDrm, {0, Unknown}}, + {X86::VPMINSDrr, {0, Unknown}}, + {X86::VPMINSQZ128rm, {1, Unknown}}, + {X86::VPMINSQZ128rmb, {1, Unknown}}, + {X86::VPMINSQZ128rmbk, {1, Unknown}}, + {X86::VPMINSQZ128rmbkz, {1, Unknown}}, + {X86::VPMINSQZ128rmk, {1, Unknown}}, + {X86::VPMINSQZ128rmkz, {1, Unknown}}, + {X86::VPMINSQZ128rr, {0, Unknown}}, + {X86::VPMINSQZ128rrk, {0, Unknown}}, + {X86::VPMINSQZ128rrkz, {0, Unknown}}, + {X86::VPMINSQZ256rm, {0, Unknown}}, + {X86::VPMINSQZ256rmb, {0, Unknown}}, + {X86::VPMINSQZ256rmbk, {0, Unknown}}, + {X86::VPMINSQZ256rmbkz, {0, Unknown}}, + {X86::VPMINSQZ256rmk, {0, Unknown}}, + {X86::VPMINSQZ256rmkz, {0, Unknown}}, + {X86::VPMINSQZ256rr, {0, Unknown}}, + {X86::VPMINSQZ256rrk, {0, Unknown}}, + {X86::VPMINSQZ256rrkz, {0, Unknown}}, + {X86::VPMINSQZrm, {0, Unknown}}, + {X86::VPMINSQZrmb, {0, Unknown}}, + {X86::VPMINSQZrmbk, {0, Unknown}}, + {X86::VPMINSQZrmbkz, {0, Unknown}}, + {X86::VPMINSQZrmk, {0, Unknown}}, + {X86::VPMINSQZrmkz, {0, Unknown}}, + {X86::VPMINSQZrr, {0, Unknown}}, + {X86::VPMINSQZrrk, {0, Unknown}}, + {X86::VPMINSQZrrkz, {0, Unknown}}, + {X86::VPMINSWYrm, {0, Unknown}}, + {X86::VPMINSWYrr, {0, Unknown}}, + {X86::VPMINSWZ128rm, {1, Unknown}}, + {X86::VPMINSWZ128rmk, {1, Unknown}}, + {X86::VPMINSWZ128rmkz, {1, Unknown}}, + {X86::VPMINSWZ128rr, {0, Unknown}}, + {X86::VPMINSWZ128rrk, {0, Unknown}}, + {X86::VPMINSWZ128rrkz, {0, Unknown}}, + {X86::VPMINSWZ256rm, {0, Unknown}}, + {X86::VPMINSWZ256rmk, {0, Unknown}}, + {X86::VPMINSWZ256rmkz, {0, Unknown}}, + {X86::VPMINSWZ256rr, {0, Unknown}}, + {X86::VPMINSWZ256rrk, {0, Unknown}}, + {X86::VPMINSWZ256rrkz, {0, Unknown}}, + {X86::VPMINSWZrm, {0, Unknown}}, + {X86::VPMINSWZrmk, {0, Unknown}}, + {X86::VPMINSWZrmkz, {0, Unknown}}, + {X86::VPMINSWZrr, {0, Unknown}}, + {X86::VPMINSWZrrk, {0, Unknown}}, + {X86::VPMINSWZrrkz, {0, Unknown}}, + {X86::VPMINSWrm, {0, Unknown}}, + {X86::VPMINSWrr, {0, Unknown}}, + {X86::VPMINUBYrm, {0, Unknown}}, + {X86::VPMINUBYrr, {0, Unknown}}, + {X86::VPMINUBZ128rm, {1, Unknown}}, + {X86::VPMINUBZ128rmk, {1, Unknown}}, + {X86::VPMINUBZ128rmkz, {1, Unknown}}, + {X86::VPMINUBZ128rr, {0, Unknown}}, + {X86::VPMINUBZ128rrk, {0, Unknown}}, + {X86::VPMINUBZ128rrkz, {0, Unknown}}, + {X86::VPMINUBZ256rm, {0, Unknown}}, + {X86::VPMINUBZ256rmk, {0, Unknown}}, + {X86::VPMINUBZ256rmkz, {0, Unknown}}, + {X86::VPMINUBZ256rr, {0, Unknown}}, + {X86::VPMINUBZ256rrk, {0, Unknown}}, + {X86::VPMINUBZ256rrkz, {0, Unknown}}, + {X86::VPMINUBZrm, {0, Unknown}}, + {X86::VPMINUBZrmk, {0, Unknown}}, + {X86::VPMINUBZrmkz, {0, Unknown}}, + {X86::VPMINUBZrr, {0, Unknown}}, + {X86::VPMINUBZrrk, {0, Unknown}}, + {X86::VPMINUBZrrkz, {0, Unknown}}, + {X86::VPMINUBrm, {0, Unknown}}, + {X86::VPMINUBrr, {0, Unknown}}, + {X86::VPMINUDYrm, {0, Unknown}}, + {X86::VPMINUDYrr, {0, Unknown}}, + {X86::VPMINUDZ128rm, {1, Unknown}}, + {X86::VPMINUDZ128rmb, {1, Unknown}}, + {X86::VPMINUDZ128rmbk, {1, Unknown}}, + {X86::VPMINUDZ128rmbkz, {1, Unknown}}, + {X86::VPMINUDZ128rmk, {1, Unknown}}, + {X86::VPMINUDZ128rmkz, {1, Unknown}}, + {X86::VPMINUDZ128rr, {0, Unknown}}, + {X86::VPMINUDZ128rrk, {0, Unknown}}, + {X86::VPMINUDZ128rrkz, {0, Unknown}}, + {X86::VPMINUDZ256rm, {0, Unknown}}, + {X86::VPMINUDZ256rmb, {0, Unknown}}, + {X86::VPMINUDZ256rmbk, {0, Unknown}}, + {X86::VPMINUDZ256rmbkz, {0, Unknown}}, + {X86::VPMINUDZ256rmk, {0, Unknown}}, + {X86::VPMINUDZ256rmkz, {0, Unknown}}, + {X86::VPMINUDZ256rr, {0, Unknown}}, + {X86::VPMINUDZ256rrk, {0, Unknown}}, + {X86::VPMINUDZ256rrkz, {0, Unknown}}, + {X86::VPMINUDZrm, {0, Unknown}}, + {X86::VPMINUDZrmb, {0, Unknown}}, + {X86::VPMINUDZrmbk, {0, Unknown}}, + {X86::VPMINUDZrmbkz, {0, Unknown}}, + {X86::VPMINUDZrmk, {0, Unknown}}, + {X86::VPMINUDZrmkz, {0, Unknown}}, + {X86::VPMINUDZrr, {0, Unknown}}, + {X86::VPMINUDZrrk, {0, Unknown}}, + {X86::VPMINUDZrrkz, {0, Unknown}}, + {X86::VPMINUDrm, {0, Unknown}}, + {X86::VPMINUDrr, {0, Unknown}}, + {X86::VPMINUQZ128rm, {1, Unknown}}, + {X86::VPMINUQZ128rmb, {1, Unknown}}, + {X86::VPMINUQZ128rmbk, {1, Unknown}}, + {X86::VPMINUQZ128rmbkz, {1, Unknown}}, + {X86::VPMINUQZ128rmk, {1, Unknown}}, + {X86::VPMINUQZ128rmkz, {1, Unknown}}, + {X86::VPMINUQZ128rr, {0, Unknown}}, + {X86::VPMINUQZ128rrk, {0, Unknown}}, + {X86::VPMINUQZ128rrkz, {0, Unknown}}, + {X86::VPMINUQZ256rm, {0, Unknown}}, + {X86::VPMINUQZ256rmb, {0, Unknown}}, + {X86::VPMINUQZ256rmbk, {0, Unknown}}, + {X86::VPMINUQZ256rmbkz, {0, Unknown}}, + {X86::VPMINUQZ256rmk, {0, Unknown}}, + {X86::VPMINUQZ256rmkz, {0, Unknown}}, + {X86::VPMINUQZ256rr, {0, Unknown}}, + {X86::VPMINUQZ256rrk, {0, Unknown}}, + {X86::VPMINUQZ256rrkz, {0, Unknown}}, + {X86::VPMINUQZrm, {0, Unknown}}, + {X86::VPMINUQZrmb, {0, Unknown}}, + {X86::VPMINUQZrmbk, {0, Unknown}}, + {X86::VPMINUQZrmbkz, {0, Unknown}}, + {X86::VPMINUQZrmk, {0, Unknown}}, + {X86::VPMINUQZrmkz, {0, Unknown}}, + {X86::VPMINUQZrr, {0, Unknown}}, + {X86::VPMINUQZrrk, {0, Unknown}}, + {X86::VPMINUQZrrkz, {0, Unknown}}, + {X86::VPMINUWYrm, {0, Unknown}}, + {X86::VPMINUWYrr, {0, Unknown}}, + {X86::VPMINUWZ128rm, {1, Unknown}}, + {X86::VPMINUWZ128rmk, {1, Unknown}}, + {X86::VPMINUWZ128rmkz, {1, Unknown}}, + {X86::VPMINUWZ128rr, {0, Unknown}}, + {X86::VPMINUWZ128rrk, {0, Unknown}}, + {X86::VPMINUWZ128rrkz, {0, Unknown}}, + {X86::VPMINUWZ256rm, {0, Unknown}}, + {X86::VPMINUWZ256rmk, {0, Unknown}}, + {X86::VPMINUWZ256rmkz, {0, Unknown}}, + {X86::VPMINUWZ256rr, {0, Unknown}}, + {X86::VPMINUWZ256rrk, {0, Unknown}}, + {X86::VPMINUWZ256rrkz, {0, Unknown}}, + {X86::VPMINUWZrm, {0, Unknown}}, + {X86::VPMINUWZrmk, {0, Unknown}}, + {X86::VPMINUWZrmkz, {0, Unknown}}, + {X86::VPMINUWZrr, {0, Unknown}}, + {X86::VPMINUWZrrk, {0, Unknown}}, + {X86::VPMINUWZrrkz, {0, Unknown}}, + {X86::VPMINUWrm, {0, Unknown}}, + {X86::VPMINUWrr, {0, Unknown}}, + {X86::VPMOVB2MZ128rr, {0, Unknown}}, + {X86::VPMOVB2MZ256rr, {0, Unknown}}, + {X86::VPMOVB2MZrr, {0, Unknown}}, + {X86::VPMOVD2MZ128rr, {0, Unknown}}, + {X86::VPMOVD2MZ256rr, {0, Unknown}}, + {X86::VPMOVD2MZrr, {0, Unknown}}, + {X86::VPMOVDBZ128mr, {1, Unknown}}, + {X86::VPMOVDBZ128mrk, {1, Unknown}}, + {X86::VPMOVDBZ128rr, {0, Unknown}}, + {X86::VPMOVDBZ128rrk, {0, Unknown}}, + {X86::VPMOVDBZ128rrkz, {0, Unknown}}, + {X86::VPMOVDBZ256mr, {0, Unknown}}, + {X86::VPMOVDBZ256mrk, {0, Unknown}}, + {X86::VPMOVDBZ256rr, {0, Unknown}}, + {X86::VPMOVDBZ256rrk, {0, Unknown}}, + {X86::VPMOVDBZ256rrkz, {0, Unknown}}, + {X86::VPMOVDBZmr, {0, Unknown}}, + {X86::VPMOVDBZmrk, {0, Unknown}}, + {X86::VPMOVDBZrr, {0, Unknown}}, + {X86::VPMOVDBZrrk, {0, Unknown}}, + {X86::VPMOVDBZrrkz, {0, Unknown}}, + {X86::VPMOVDWZ128mr, {1, Unknown}}, + {X86::VPMOVDWZ128mrk, {1, Unknown}}, + {X86::VPMOVDWZ128rr, {0, Unknown}}, + {X86::VPMOVDWZ128rrk, {0, Unknown}}, + {X86::VPMOVDWZ128rrkz, {0, Unknown}}, + {X86::VPMOVDWZ256mr, {0, Unknown}}, + {X86::VPMOVDWZ256mrk, {0, Unknown}}, + {X86::VPMOVDWZ256rr, {0, Unknown}}, + {X86::VPMOVDWZ256rrk, {0, Unknown}}, + {X86::VPMOVDWZ256rrkz, {0, Unknown}}, + {X86::VPMOVDWZmr, {0, Unknown}}, + {X86::VPMOVDWZmrk, {0, Unknown}}, + {X86::VPMOVDWZrr, {0, Unknown}}, + {X86::VPMOVDWZrrk, {0, Unknown}}, + {X86::VPMOVDWZrrkz, {0, Unknown}}, + {X86::VPMOVM2BZ128rr, {0, Unknown}}, + {X86::VPMOVM2BZ256rr, {0, Unknown}}, + {X86::VPMOVM2BZrr, {0, Unknown}}, + {X86::VPMOVM2DZ128rr, {0, Unknown}}, + {X86::VPMOVM2DZ256rr, {0, Unknown}}, + {X86::VPMOVM2DZrr, {0, Unknown}}, + {X86::VPMOVM2QZ128rr, {0, Unknown}}, + {X86::VPMOVM2QZ256rr, {0, Unknown}}, + {X86::VPMOVM2QZrr, {0, Unknown}}, + {X86::VPMOVM2WZ128rr, {0, Unknown}}, + {X86::VPMOVM2WZ256rr, {0, Unknown}}, + {X86::VPMOVM2WZrr, {0, Unknown}}, + {X86::VPMOVMSKBYrr, {0, Unknown}}, + {X86::VPMOVMSKBrr, {0, Unknown}}, + {X86::VPMOVQ2MZ128rr, {0, Unknown}}, + {X86::VPMOVQ2MZ256rr, {0, Unknown}}, + {X86::VPMOVQ2MZrr, {0, Unknown}}, + {X86::VPMOVQBZ128mr, {1, Unknown}}, + {X86::VPMOVQBZ128mrk, {1, Unknown}}, + {X86::VPMOVQBZ128rr, {0, Unknown}}, + {X86::VPMOVQBZ128rrk, {0, Unknown}}, + {X86::VPMOVQBZ128rrkz, {0, Unknown}}, + {X86::VPMOVQBZ256mr, {0, Unknown}}, + {X86::VPMOVQBZ256mrk, {0, Unknown}}, + {X86::VPMOVQBZ256rr, {0, Unknown}}, + {X86::VPMOVQBZ256rrk, {0, Unknown}}, + {X86::VPMOVQBZ256rrkz, {0, Unknown}}, + {X86::VPMOVQBZmr, {0, Unknown}}, + {X86::VPMOVQBZmrk, {0, Unknown}}, + {X86::VPMOVQBZrr, {0, Unknown}}, + {X86::VPMOVQBZrrk, {0, Unknown}}, + {X86::VPMOVQBZrrkz, {0, Unknown}}, + {X86::VPMOVQDZ128mr, {1, Unknown}}, + {X86::VPMOVQDZ128mrk, {1, Unknown}}, + {X86::VPMOVQDZ128rr, {0, Unknown}}, + {X86::VPMOVQDZ128rrk, {0, Unknown}}, + {X86::VPMOVQDZ128rrkz, {0, Unknown}}, + {X86::VPMOVQDZ256mr, {0, Unknown}}, + {X86::VPMOVQDZ256mrk, {0, Unknown}}, + {X86::VPMOVQDZ256rr, {0, Unknown}}, + {X86::VPMOVQDZ256rrk, {0, Unknown}}, + {X86::VPMOVQDZ256rrkz, {0, Unknown}}, + {X86::VPMOVQDZmr, {0, Unknown}}, + {X86::VPMOVQDZmrk, {0, Unknown}}, + {X86::VPMOVQDZrr, {0, Unknown}}, + {X86::VPMOVQDZrrk, {0, Unknown}}, + {X86::VPMOVQDZrrkz, {0, Unknown}}, + {X86::VPMOVQWZ128mr, {1, Unknown}}, + {X86::VPMOVQWZ128mrk, {1, Unknown}}, + {X86::VPMOVQWZ128rr, {0, Unknown}}, + {X86::VPMOVQWZ128rrk, {0, Unknown}}, + {X86::VPMOVQWZ128rrkz, {0, Unknown}}, + {X86::VPMOVQWZ256mr, {0, Unknown}}, + {X86::VPMOVQWZ256mrk, {0, Unknown}}, + {X86::VPMOVQWZ256rr, {0, Unknown}}, + {X86::VPMOVQWZ256rrk, {0, Unknown}}, + {X86::VPMOVQWZ256rrkz, {0, Unknown}}, + {X86::VPMOVQWZmr, {0, Unknown}}, + {X86::VPMOVQWZmrk, {0, Unknown}}, + {X86::VPMOVQWZrr, {0, Unknown}}, + {X86::VPMOVQWZrrk, {0, Unknown}}, + {X86::VPMOVQWZrrkz, {0, Unknown}}, + {X86::VPMOVSDBZ128mr, {1, Unknown}}, + {X86::VPMOVSDBZ128mrk, {1, Unknown}}, + {X86::VPMOVSDBZ128rr, {0, Unknown}}, + {X86::VPMOVSDBZ128rrk, {0, Unknown}}, + {X86::VPMOVSDBZ128rrkz, {0, Unknown}}, + {X86::VPMOVSDBZ256mr, {0, Unknown}}, + {X86::VPMOVSDBZ256mrk, {0, Unknown}}, + {X86::VPMOVSDBZ256rr, {0, Unknown}}, + {X86::VPMOVSDBZ256rrk, {0, Unknown}}, + {X86::VPMOVSDBZ256rrkz, {0, Unknown}}, + {X86::VPMOVSDBZmr, {0, Unknown}}, + {X86::VPMOVSDBZmrk, {0, Unknown}}, + {X86::VPMOVSDBZrr, {0, Unknown}}, + {X86::VPMOVSDBZrrk, {0, Unknown}}, + {X86::VPMOVSDBZrrkz, {0, Unknown}}, + {X86::VPMOVSDWZ128mr, {1, Unknown}}, + {X86::VPMOVSDWZ128mrk, {1, Unknown}}, + {X86::VPMOVSDWZ128rr, {0, Unknown}}, + {X86::VPMOVSDWZ128rrk, {0, Unknown}}, + {X86::VPMOVSDWZ128rrkz, {0, Unknown}}, + {X86::VPMOVSDWZ256mr, {0, Unknown}}, + {X86::VPMOVSDWZ256mrk, {0, Unknown}}, + {X86::VPMOVSDWZ256rr, {0, Unknown}}, + {X86::VPMOVSDWZ256rrk, {0, Unknown}}, + {X86::VPMOVSDWZ256rrkz, {0, Unknown}}, + {X86::VPMOVSDWZmr, {0, Unknown}}, + {X86::VPMOVSDWZmrk, {0, Unknown}}, + {X86::VPMOVSDWZrr, {0, Unknown}}, + {X86::VPMOVSDWZrrk, {0, Unknown}}, + {X86::VPMOVSDWZrrkz, {0, Unknown}}, + {X86::VPMOVSQBZ128mr, {1, Unknown}}, + {X86::VPMOVSQBZ128mrk, {1, Unknown}}, + {X86::VPMOVSQBZ128rr, {0, Unknown}}, + {X86::VPMOVSQBZ128rrk, {0, Unknown}}, + {X86::VPMOVSQBZ128rrkz, {0, Unknown}}, + {X86::VPMOVSQBZ256mr, {0, Unknown}}, + {X86::VPMOVSQBZ256mrk, {0, Unknown}}, + {X86::VPMOVSQBZ256rr, {0, Unknown}}, + {X86::VPMOVSQBZ256rrk, {0, Unknown}}, + {X86::VPMOVSQBZ256rrkz, {0, Unknown}}, + {X86::VPMOVSQBZmr, {0, Unknown}}, + {X86::VPMOVSQBZmrk, {0, Unknown}}, + {X86::VPMOVSQBZrr, {0, Unknown}}, + {X86::VPMOVSQBZrrk, {0, Unknown}}, + {X86::VPMOVSQBZrrkz, {0, Unknown}}, + {X86::VPMOVSQDZ128mr, {1, Unknown}}, + {X86::VPMOVSQDZ128mrk, {1, Unknown}}, + {X86::VPMOVSQDZ128rr, {0, Unknown}}, + {X86::VPMOVSQDZ128rrk, {0, Unknown}}, + {X86::VPMOVSQDZ128rrkz, {0, Unknown}}, + {X86::VPMOVSQDZ256mr, {0, Unknown}}, + {X86::VPMOVSQDZ256mrk, {0, Unknown}}, + {X86::VPMOVSQDZ256rr, {0, Unknown}}, + {X86::VPMOVSQDZ256rrk, {0, Unknown}}, + {X86::VPMOVSQDZ256rrkz, {0, Unknown}}, + {X86::VPMOVSQDZmr, {0, Unknown}}, + {X86::VPMOVSQDZmrk, {0, Unknown}}, + {X86::VPMOVSQDZrr, {0, Unknown}}, + {X86::VPMOVSQDZrrk, {0, Unknown}}, + {X86::VPMOVSQDZrrkz, {0, Unknown}}, + {X86::VPMOVSQWZ128mr, {1, Unknown}}, + {X86::VPMOVSQWZ128mrk, {1, Unknown}}, + {X86::VPMOVSQWZ128rr, {0, Unknown}}, + {X86::VPMOVSQWZ128rrk, {0, Unknown}}, + {X86::VPMOVSQWZ128rrkz, {0, Unknown}}, + {X86::VPMOVSQWZ256mr, {0, Unknown}}, + {X86::VPMOVSQWZ256mrk, {0, Unknown}}, + {X86::VPMOVSQWZ256rr, {0, Unknown}}, + {X86::VPMOVSQWZ256rrk, {0, Unknown}}, + {X86::VPMOVSQWZ256rrkz, {0, Unknown}}, + {X86::VPMOVSQWZmr, {0, Unknown}}, + {X86::VPMOVSQWZmrk, {0, Unknown}}, + {X86::VPMOVSQWZrr, {0, Unknown}}, + {X86::VPMOVSQWZrrk, {0, Unknown}}, + {X86::VPMOVSQWZrrkz, {0, Unknown}}, + {X86::VPMOVSWBZ128mr, {1, Unknown}}, + {X86::VPMOVSWBZ128mrk, {1, Unknown}}, + {X86::VPMOVSWBZ128rr, {0, Unknown}}, + {X86::VPMOVSWBZ128rrk, {0, Unknown}}, + {X86::VPMOVSWBZ128rrkz, {0, Unknown}}, + {X86::VPMOVSWBZ256mr, {0, Unknown}}, + {X86::VPMOVSWBZ256mrk, {0, Unknown}}, + {X86::VPMOVSWBZ256rr, {0, Unknown}}, + {X86::VPMOVSWBZ256rrk, {0, Unknown}}, + {X86::VPMOVSWBZ256rrkz, {0, Unknown}}, + {X86::VPMOVSWBZmr, {0, Unknown}}, + {X86::VPMOVSWBZmrk, {0, Unknown}}, + {X86::VPMOVSWBZrr, {0, Unknown}}, + {X86::VPMOVSWBZrrk, {0, Unknown}}, + {X86::VPMOVSWBZrrkz, {0, Unknown}}, + {X86::VPMOVSXBDYrm, {0, Unknown}}, + {X86::VPMOVSXBDYrr, {0, Unknown}}, + {X86::VPMOVSXBDZ128rm, {1, Unknown}}, + {X86::VPMOVSXBDZ128rmk, {1, Unknown}}, + {X86::VPMOVSXBDZ128rmkz, {1, Unknown}}, + {X86::VPMOVSXBDZ128rr, {0, Unknown}}, + {X86::VPMOVSXBDZ128rrk, {0, Unknown}}, + {X86::VPMOVSXBDZ128rrkz, {0, Unknown}}, + {X86::VPMOVSXBDZ256rm, {0, Unknown}}, + {X86::VPMOVSXBDZ256rmk, {0, Unknown}}, + {X86::VPMOVSXBDZ256rmkz, {0, Unknown}}, + {X86::VPMOVSXBDZ256rr, {0, Unknown}}, + {X86::VPMOVSXBDZ256rrk, {0, Unknown}}, + {X86::VPMOVSXBDZ256rrkz, {0, Unknown}}, + {X86::VPMOVSXBDZrm, {0, Unknown}}, + {X86::VPMOVSXBDZrmk, {0, Unknown}}, + {X86::VPMOVSXBDZrmkz, {0, Unknown}}, + {X86::VPMOVSXBDZrr, {0, Unknown}}, + {X86::VPMOVSXBDZrrk, {0, Unknown}}, + {X86::VPMOVSXBDZrrkz, {0, Unknown}}, + {X86::VPMOVSXBDrm, {0, Unknown}}, + {X86::VPMOVSXBDrr, {0, Unknown}}, + {X86::VPMOVSXBQYrm, {0, Unknown}}, + {X86::VPMOVSXBQYrr, {0, Unknown}}, + {X86::VPMOVSXBQZ128rm, {1, Unknown}}, + {X86::VPMOVSXBQZ128rmk, {1, Unknown}}, + {X86::VPMOVSXBQZ128rmkz, {1, Unknown}}, + {X86::VPMOVSXBQZ128rr, {0, Unknown}}, + {X86::VPMOVSXBQZ128rrk, {0, Unknown}}, + {X86::VPMOVSXBQZ128rrkz, {0, Unknown}}, + {X86::VPMOVSXBQZ256rm, {0, Unknown}}, + {X86::VPMOVSXBQZ256rmk, {0, Unknown}}, + {X86::VPMOVSXBQZ256rmkz, {0, Unknown}}, + {X86::VPMOVSXBQZ256rr, {0, Unknown}}, + {X86::VPMOVSXBQZ256rrk, {0, Unknown}}, + {X86::VPMOVSXBQZ256rrkz, {0, Unknown}}, + {X86::VPMOVSXBQZrm, {0, Unknown}}, + {X86::VPMOVSXBQZrmk, {0, Unknown}}, + {X86::VPMOVSXBQZrmkz, {0, Unknown}}, + {X86::VPMOVSXBQZrr, {0, Unknown}}, + {X86::VPMOVSXBQZrrk, {0, Unknown}}, + {X86::VPMOVSXBQZrrkz, {0, Unknown}}, + {X86::VPMOVSXBQrm, {0, Unknown}}, + {X86::VPMOVSXBQrr, {0, Unknown}}, + {X86::VPMOVSXBWYrm, {0, Unknown}}, + {X86::VPMOVSXBWYrr, {0, Unknown}}, + {X86::VPMOVSXBWZ128rm, {1, Unknown}}, + {X86::VPMOVSXBWZ128rmk, {1, Unknown}}, + {X86::VPMOVSXBWZ128rmkz, {1, Unknown}}, + {X86::VPMOVSXBWZ128rr, {0, Unknown}}, + {X86::VPMOVSXBWZ128rrk, {0, Unknown}}, + {X86::VPMOVSXBWZ128rrkz, {0, Unknown}}, + {X86::VPMOVSXBWZ256rm, {0, Unknown}}, + {X86::VPMOVSXBWZ256rmk, {0, Unknown}}, + {X86::VPMOVSXBWZ256rmkz, {0, Unknown}}, + {X86::VPMOVSXBWZ256rr, {0, Unknown}}, + {X86::VPMOVSXBWZ256rrk, {0, Unknown}}, + {X86::VPMOVSXBWZ256rrkz, {0, Unknown}}, + {X86::VPMOVSXBWZrm, {0, Unknown}}, + {X86::VPMOVSXBWZrmk, {0, Unknown}}, + {X86::VPMOVSXBWZrmkz, {0, Unknown}}, + {X86::VPMOVSXBWZrr, {0, Unknown}}, + {X86::VPMOVSXBWZrrk, {0, Unknown}}, + {X86::VPMOVSXBWZrrkz, {0, Unknown}}, + {X86::VPMOVSXBWrm, {0, Unknown}}, + {X86::VPMOVSXBWrr, {0, Unknown}}, + {X86::VPMOVSXDQYrm, {0, Unknown}}, + {X86::VPMOVSXDQYrr, {0, Unknown}}, + {X86::VPMOVSXDQZ128rm, {1, Unknown}}, + {X86::VPMOVSXDQZ128rmk, {1, Unknown}}, + {X86::VPMOVSXDQZ128rmkz, {1, Unknown}}, + {X86::VPMOVSXDQZ128rr, {0, Unknown}}, + {X86::VPMOVSXDQZ128rrk, {0, Unknown}}, + {X86::VPMOVSXDQZ128rrkz, {0, Unknown}}, + {X86::VPMOVSXDQZ256rm, {0, Unknown}}, + {X86::VPMOVSXDQZ256rmk, {0, Unknown}}, + {X86::VPMOVSXDQZ256rmkz, {0, Unknown}}, + {X86::VPMOVSXDQZ256rr, {0, Unknown}}, + {X86::VPMOVSXDQZ256rrk, {0, Unknown}}, + {X86::VPMOVSXDQZ256rrkz, {0, Unknown}}, + {X86::VPMOVSXDQZrm, {0, Unknown}}, + {X86::VPMOVSXDQZrmk, {0, Unknown}}, + {X86::VPMOVSXDQZrmkz, {0, Unknown}}, + {X86::VPMOVSXDQZrr, {0, Unknown}}, + {X86::VPMOVSXDQZrrk, {0, Unknown}}, + {X86::VPMOVSXDQZrrkz, {0, Unknown}}, + {X86::VPMOVSXDQrm, {0, Unknown}}, + {X86::VPMOVSXDQrr, {0, Unknown}}, + {X86::VPMOVSXWDYrm, {0, Unknown}}, + {X86::VPMOVSXWDYrr, {0, Unknown}}, + {X86::VPMOVSXWDZ128rm, {1, Unknown}}, + {X86::VPMOVSXWDZ128rmk, {1, Unknown}}, + {X86::VPMOVSXWDZ128rmkz, {1, Unknown}}, + {X86::VPMOVSXWDZ128rr, {0, Unknown}}, + {X86::VPMOVSXWDZ128rrk, {0, Unknown}}, + {X86::VPMOVSXWDZ128rrkz, {0, Unknown}}, + {X86::VPMOVSXWDZ256rm, {0, Unknown}}, + {X86::VPMOVSXWDZ256rmk, {0, Unknown}}, + {X86::VPMOVSXWDZ256rmkz, {0, Unknown}}, + {X86::VPMOVSXWDZ256rr, {0, Unknown}}, + {X86::VPMOVSXWDZ256rrk, {0, Unknown}}, + {X86::VPMOVSXWDZ256rrkz, {0, Unknown}}, + {X86::VPMOVSXWDZrm, {0, Unknown}}, + {X86::VPMOVSXWDZrmk, {0, Unknown}}, + {X86::VPMOVSXWDZrmkz, {0, Unknown}}, + {X86::VPMOVSXWDZrr, {0, Unknown}}, + {X86::VPMOVSXWDZrrk, {0, Unknown}}, + {X86::VPMOVSXWDZrrkz, {0, Unknown}}, + {X86::VPMOVSXWDrm, {0, Unknown}}, + {X86::VPMOVSXWDrr, {0, Unknown}}, + {X86::VPMOVSXWQYrm, {0, Unknown}}, + {X86::VPMOVSXWQYrr, {0, Unknown}}, + {X86::VPMOVSXWQZ128rm, {1, Unknown}}, + {X86::VPMOVSXWQZ128rmk, {1, Unknown}}, + {X86::VPMOVSXWQZ128rmkz, {1, Unknown}}, + {X86::VPMOVSXWQZ128rr, {0, Unknown}}, + {X86::VPMOVSXWQZ128rrk, {0, Unknown}}, + {X86::VPMOVSXWQZ128rrkz, {0, Unknown}}, + {X86::VPMOVSXWQZ256rm, {0, Unknown}}, + {X86::VPMOVSXWQZ256rmk, {0, Unknown}}, + {X86::VPMOVSXWQZ256rmkz, {0, Unknown}}, + {X86::VPMOVSXWQZ256rr, {0, Unknown}}, + {X86::VPMOVSXWQZ256rrk, {0, Unknown}}, + {X86::VPMOVSXWQZ256rrkz, {0, Unknown}}, + {X86::VPMOVSXWQZrm, {0, Unknown}}, + {X86::VPMOVSXWQZrmk, {0, Unknown}}, + {X86::VPMOVSXWQZrmkz, {0, Unknown}}, + {X86::VPMOVSXWQZrr, {0, Unknown}}, + {X86::VPMOVSXWQZrrk, {0, Unknown}}, + {X86::VPMOVSXWQZrrkz, {0, Unknown}}, + {X86::VPMOVSXWQrm, {0, Unknown}}, + {X86::VPMOVSXWQrr, {0, Unknown}}, + {X86::VPMOVUSDBZ128mr, {1, Unknown}}, + {X86::VPMOVUSDBZ128mrk, {1, Unknown}}, + {X86::VPMOVUSDBZ128rr, {0, Unknown}}, + {X86::VPMOVUSDBZ128rrk, {0, Unknown}}, + {X86::VPMOVUSDBZ128rrkz, {0, Unknown}}, + {X86::VPMOVUSDBZ256mr, {0, Unknown}}, + {X86::VPMOVUSDBZ256mrk, {0, Unknown}}, + {X86::VPMOVUSDBZ256rr, {0, Unknown}}, + {X86::VPMOVUSDBZ256rrk, {0, Unknown}}, + {X86::VPMOVUSDBZ256rrkz, {0, Unknown}}, + {X86::VPMOVUSDBZmr, {0, Unknown}}, + {X86::VPMOVUSDBZmrk, {0, Unknown}}, + {X86::VPMOVUSDBZrr, {0, Unknown}}, + {X86::VPMOVUSDBZrrk, {0, Unknown}}, + {X86::VPMOVUSDBZrrkz, {0, Unknown}}, + {X86::VPMOVUSDWZ128mr, {1, Unknown}}, + {X86::VPMOVUSDWZ128mrk, {1, Unknown}}, + {X86::VPMOVUSDWZ128rr, {0, Unknown}}, + {X86::VPMOVUSDWZ128rrk, {0, Unknown}}, + {X86::VPMOVUSDWZ128rrkz, {0, Unknown}}, + {X86::VPMOVUSDWZ256mr, {0, Unknown}}, + {X86::VPMOVUSDWZ256mrk, {0, Unknown}}, + {X86::VPMOVUSDWZ256rr, {0, Unknown}}, + {X86::VPMOVUSDWZ256rrk, {0, Unknown}}, + {X86::VPMOVUSDWZ256rrkz, {0, Unknown}}, + {X86::VPMOVUSDWZmr, {0, Unknown}}, + {X86::VPMOVUSDWZmrk, {0, Unknown}}, + {X86::VPMOVUSDWZrr, {0, Unknown}}, + {X86::VPMOVUSDWZrrk, {0, Unknown}}, + {X86::VPMOVUSDWZrrkz, {0, Unknown}}, + {X86::VPMOVUSQBZ128mr, {1, Unknown}}, + {X86::VPMOVUSQBZ128mrk, {1, Unknown}}, + {X86::VPMOVUSQBZ128rr, {0, Unknown}}, + {X86::VPMOVUSQBZ128rrk, {0, Unknown}}, + {X86::VPMOVUSQBZ128rrkz, {0, Unknown}}, + {X86::VPMOVUSQBZ256mr, {0, Unknown}}, + {X86::VPMOVUSQBZ256mrk, {0, Unknown}}, + {X86::VPMOVUSQBZ256rr, {0, Unknown}}, + {X86::VPMOVUSQBZ256rrk, {0, Unknown}}, + {X86::VPMOVUSQBZ256rrkz, {0, Unknown}}, + {X86::VPMOVUSQBZmr, {0, Unknown}}, + {X86::VPMOVUSQBZmrk, {0, Unknown}}, + {X86::VPMOVUSQBZrr, {0, Unknown}}, + {X86::VPMOVUSQBZrrk, {0, Unknown}}, + {X86::VPMOVUSQBZrrkz, {0, Unknown}}, + {X86::VPMOVUSQDZ128mr, {1, Unknown}}, + {X86::VPMOVUSQDZ128mrk, {1, Unknown}}, + {X86::VPMOVUSQDZ128rr, {0, Unknown}}, + {X86::VPMOVUSQDZ128rrk, {0, Unknown}}, + {X86::VPMOVUSQDZ128rrkz, {0, Unknown}}, + {X86::VPMOVUSQDZ256mr, {0, Unknown}}, + {X86::VPMOVUSQDZ256mrk, {0, Unknown}}, + {X86::VPMOVUSQDZ256rr, {0, Unknown}}, + {X86::VPMOVUSQDZ256rrk, {0, Unknown}}, + {X86::VPMOVUSQDZ256rrkz, {0, Unknown}}, + {X86::VPMOVUSQDZmr, {0, Unknown}}, + {X86::VPMOVUSQDZmrk, {0, Unknown}}, + {X86::VPMOVUSQDZrr, {0, Unknown}}, + {X86::VPMOVUSQDZrrk, {0, Unknown}}, + {X86::VPMOVUSQDZrrkz, {0, Unknown}}, + {X86::VPMOVUSQWZ128mr, {1, Unknown}}, + {X86::VPMOVUSQWZ128mrk, {1, Unknown}}, + {X86::VPMOVUSQWZ128rr, {0, Unknown}}, + {X86::VPMOVUSQWZ128rrk, {0, Unknown}}, + {X86::VPMOVUSQWZ128rrkz, {0, Unknown}}, + {X86::VPMOVUSQWZ256mr, {0, Unknown}}, + {X86::VPMOVUSQWZ256mrk, {0, Unknown}}, + {X86::VPMOVUSQWZ256rr, {0, Unknown}}, + {X86::VPMOVUSQWZ256rrk, {0, Unknown}}, + {X86::VPMOVUSQWZ256rrkz, {0, Unknown}}, + {X86::VPMOVUSQWZmr, {0, Unknown}}, + {X86::VPMOVUSQWZmrk, {0, Unknown}}, + {X86::VPMOVUSQWZrr, {0, Unknown}}, + {X86::VPMOVUSQWZrrk, {0, Unknown}}, + {X86::VPMOVUSQWZrrkz, {0, Unknown}}, + {X86::VPMOVUSWBZ128mr, {1, Unknown}}, + {X86::VPMOVUSWBZ128mrk, {1, Unknown}}, + {X86::VPMOVUSWBZ128rr, {0, Unknown}}, + {X86::VPMOVUSWBZ128rrk, {0, Unknown}}, + {X86::VPMOVUSWBZ128rrkz, {0, Unknown}}, + {X86::VPMOVUSWBZ256mr, {0, Unknown}}, + {X86::VPMOVUSWBZ256mrk, {0, Unknown}}, + {X86::VPMOVUSWBZ256rr, {0, Unknown}}, + {X86::VPMOVUSWBZ256rrk, {0, Unknown}}, + {X86::VPMOVUSWBZ256rrkz, {0, Unknown}}, + {X86::VPMOVUSWBZmr, {0, Unknown}}, + {X86::VPMOVUSWBZmrk, {0, Unknown}}, + {X86::VPMOVUSWBZrr, {0, Unknown}}, + {X86::VPMOVUSWBZrrk, {0, Unknown}}, + {X86::VPMOVUSWBZrrkz, {0, Unknown}}, + {X86::VPMOVW2MZ128rr, {0, Unknown}}, + {X86::VPMOVW2MZ256rr, {0, Unknown}}, + {X86::VPMOVW2MZrr, {0, Unknown}}, + {X86::VPMOVWBZ128mr, {1, Unknown}}, + {X86::VPMOVWBZ128mrk, {1, Unknown}}, + {X86::VPMOVWBZ128rr, {0, Unknown}}, + {X86::VPMOVWBZ128rrk, {0, Unknown}}, + {X86::VPMOVWBZ128rrkz, {0, Unknown}}, + {X86::VPMOVWBZ256mr, {0, Unknown}}, + {X86::VPMOVWBZ256mrk, {0, Unknown}}, + {X86::VPMOVWBZ256rr, {0, Unknown}}, + {X86::VPMOVWBZ256rrk, {0, Unknown}}, + {X86::VPMOVWBZ256rrkz, {0, Unknown}}, + {X86::VPMOVWBZmr, {0, Unknown}}, + {X86::VPMOVWBZmrk, {0, Unknown}}, + {X86::VPMOVWBZrr, {0, Unknown}}, + {X86::VPMOVWBZrrk, {0, Unknown}}, + {X86::VPMOVWBZrrkz, {0, Unknown}}, + {X86::VPMOVZXBDYrm, {0, Unknown}}, + {X86::VPMOVZXBDYrr, {0, Unknown}}, + {X86::VPMOVZXBDZ128rm, {1, Unknown}}, + {X86::VPMOVZXBDZ128rmk, {1, Unknown}}, + {X86::VPMOVZXBDZ128rmkz, {1, Unknown}}, + {X86::VPMOVZXBDZ128rr, {0, Unknown}}, + {X86::VPMOVZXBDZ128rrk, {0, Unknown}}, + {X86::VPMOVZXBDZ128rrkz, {0, Unknown}}, + {X86::VPMOVZXBDZ256rm, {0, Unknown}}, + {X86::VPMOVZXBDZ256rmk, {0, Unknown}}, + {X86::VPMOVZXBDZ256rmkz, {0, Unknown}}, + {X86::VPMOVZXBDZ256rr, {0, Unknown}}, + {X86::VPMOVZXBDZ256rrk, {0, Unknown}}, + {X86::VPMOVZXBDZ256rrkz, {0, Unknown}}, + {X86::VPMOVZXBDZrm, {0, Unknown}}, + {X86::VPMOVZXBDZrmk, {0, Unknown}}, + {X86::VPMOVZXBDZrmkz, {0, Unknown}}, + {X86::VPMOVZXBDZrr, {0, Unknown}}, + {X86::VPMOVZXBDZrrk, {0, Unknown}}, + {X86::VPMOVZXBDZrrkz, {0, Unknown}}, + {X86::VPMOVZXBDrm, {0, Unknown}}, + {X86::VPMOVZXBDrr, {0, Unknown}}, + {X86::VPMOVZXBQYrm, {0, Unknown}}, + {X86::VPMOVZXBQYrr, {0, Unknown}}, + {X86::VPMOVZXBQZ128rm, {1, Unknown}}, + {X86::VPMOVZXBQZ128rmk, {1, Unknown}}, + {X86::VPMOVZXBQZ128rmkz, {1, Unknown}}, + {X86::VPMOVZXBQZ128rr, {0, Unknown}}, + {X86::VPMOVZXBQZ128rrk, {0, Unknown}}, + {X86::VPMOVZXBQZ128rrkz, {0, Unknown}}, + {X86::VPMOVZXBQZ256rm, {0, Unknown}}, + {X86::VPMOVZXBQZ256rmk, {0, Unknown}}, + {X86::VPMOVZXBQZ256rmkz, {0, Unknown}}, + {X86::VPMOVZXBQZ256rr, {0, Unknown}}, + {X86::VPMOVZXBQZ256rrk, {0, Unknown}}, + {X86::VPMOVZXBQZ256rrkz, {0, Unknown}}, + {X86::VPMOVZXBQZrm, {0, Unknown}}, + {X86::VPMOVZXBQZrmk, {0, Unknown}}, + {X86::VPMOVZXBQZrmkz, {0, Unknown}}, + {X86::VPMOVZXBQZrr, {0, Unknown}}, + {X86::VPMOVZXBQZrrk, {0, Unknown}}, + {X86::VPMOVZXBQZrrkz, {0, Unknown}}, + {X86::VPMOVZXBQrm, {0, Unknown}}, + {X86::VPMOVZXBQrr, {0, Unknown}}, + {X86::VPMOVZXBWYrm, {0, Unknown}}, + {X86::VPMOVZXBWYrr, {0, Unknown}}, + {X86::VPMOVZXBWZ128rm, {1, Unknown}}, + {X86::VPMOVZXBWZ128rmk, {1, Unknown}}, + {X86::VPMOVZXBWZ128rmkz, {1, Unknown}}, + {X86::VPMOVZXBWZ128rr, {0, Unknown}}, + {X86::VPMOVZXBWZ128rrk, {0, Unknown}}, + {X86::VPMOVZXBWZ128rrkz, {0, Unknown}}, + {X86::VPMOVZXBWZ256rm, {0, Unknown}}, + {X86::VPMOVZXBWZ256rmk, {0, Unknown}}, + {X86::VPMOVZXBWZ256rmkz, {0, Unknown}}, + {X86::VPMOVZXBWZ256rr, {0, Unknown}}, + {X86::VPMOVZXBWZ256rrk, {0, Unknown}}, + {X86::VPMOVZXBWZ256rrkz, {0, Unknown}}, + {X86::VPMOVZXBWZrm, {0, Unknown}}, + {X86::VPMOVZXBWZrmk, {0, Unknown}}, + {X86::VPMOVZXBWZrmkz, {0, Unknown}}, + {X86::VPMOVZXBWZrr, {0, Unknown}}, + {X86::VPMOVZXBWZrrk, {0, Unknown}}, + {X86::VPMOVZXBWZrrkz, {0, Unknown}}, + {X86::VPMOVZXBWrm, {0, Unknown}}, + {X86::VPMOVZXBWrr, {0, Unknown}}, + {X86::VPMOVZXDQYrm, {0, Unknown}}, + {X86::VPMOVZXDQYrr, {0, Unknown}}, + {X86::VPMOVZXDQZ128rm, {1, Unknown}}, + {X86::VPMOVZXDQZ128rmk, {1, Unknown}}, + {X86::VPMOVZXDQZ128rmkz, {1, Unknown}}, + {X86::VPMOVZXDQZ128rr, {0, Unknown}}, + {X86::VPMOVZXDQZ128rrk, {0, Unknown}}, + {X86::VPMOVZXDQZ128rrkz, {0, Unknown}}, + {X86::VPMOVZXDQZ256rm, {0, Unknown}}, + {X86::VPMOVZXDQZ256rmk, {0, Unknown}}, + {X86::VPMOVZXDQZ256rmkz, {0, Unknown}}, + {X86::VPMOVZXDQZ256rr, {0, Unknown}}, + {X86::VPMOVZXDQZ256rrk, {0, Unknown}}, + {X86::VPMOVZXDQZ256rrkz, {0, Unknown}}, + {X86::VPMOVZXDQZrm, {0, Unknown}}, + {X86::VPMOVZXDQZrmk, {0, Unknown}}, + {X86::VPMOVZXDQZrmkz, {0, Unknown}}, + {X86::VPMOVZXDQZrr, {0, Unknown}}, + {X86::VPMOVZXDQZrrk, {0, Unknown}}, + {X86::VPMOVZXDQZrrkz, {0, Unknown}}, + {X86::VPMOVZXDQrm, {0, Unknown}}, + {X86::VPMOVZXDQrr, {0, Unknown}}, + {X86::VPMOVZXWDYrm, {0, Unknown}}, + {X86::VPMOVZXWDYrr, {0, Unknown}}, + {X86::VPMOVZXWDZ128rm, {1, Unknown}}, + {X86::VPMOVZXWDZ128rmk, {1, Unknown}}, + {X86::VPMOVZXWDZ128rmkz, {1, Unknown}}, + {X86::VPMOVZXWDZ128rr, {0, Unknown}}, + {X86::VPMOVZXWDZ128rrk, {0, Unknown}}, + {X86::VPMOVZXWDZ128rrkz, {0, Unknown}}, + {X86::VPMOVZXWDZ256rm, {0, Unknown}}, + {X86::VPMOVZXWDZ256rmk, {0, Unknown}}, + {X86::VPMOVZXWDZ256rmkz, {0, Unknown}}, + {X86::VPMOVZXWDZ256rr, {0, Unknown}}, + {X86::VPMOVZXWDZ256rrk, {0, Unknown}}, + {X86::VPMOVZXWDZ256rrkz, {0, Unknown}}, + {X86::VPMOVZXWDZrm, {0, Unknown}}, + {X86::VPMOVZXWDZrmk, {0, Unknown}}, + {X86::VPMOVZXWDZrmkz, {0, Unknown}}, + {X86::VPMOVZXWDZrr, {0, Unknown}}, + {X86::VPMOVZXWDZrrk, {0, Unknown}}, + {X86::VPMOVZXWDZrrkz, {0, Unknown}}, + {X86::VPMOVZXWDrm, {0, Unknown}}, + {X86::VPMOVZXWDrr, {0, Unknown}}, + {X86::VPMOVZXWQYrm, {0, Unknown}}, + {X86::VPMOVZXWQYrr, {0, Unknown}}, + {X86::VPMOVZXWQZ128rm, {1, Unknown}}, + {X86::VPMOVZXWQZ128rmk, {1, Unknown}}, + {X86::VPMOVZXWQZ128rmkz, {1, Unknown}}, + {X86::VPMOVZXWQZ128rr, {0, Unknown}}, + {X86::VPMOVZXWQZ128rrk, {0, Unknown}}, + {X86::VPMOVZXWQZ128rrkz, {0, Unknown}}, + {X86::VPMOVZXWQZ256rm, {0, Unknown}}, + {X86::VPMOVZXWQZ256rmk, {0, Unknown}}, + {X86::VPMOVZXWQZ256rmkz, {0, Unknown}}, + {X86::VPMOVZXWQZ256rr, {0, Unknown}}, + {X86::VPMOVZXWQZ256rrk, {0, Unknown}}, + {X86::VPMOVZXWQZ256rrkz, {0, Unknown}}, + {X86::VPMOVZXWQZrm, {0, Unknown}}, + {X86::VPMOVZXWQZrmk, {0, Unknown}}, + {X86::VPMOVZXWQZrmkz, {0, Unknown}}, + {X86::VPMOVZXWQZrr, {0, Unknown}}, + {X86::VPMOVZXWQZrrk, {0, Unknown}}, + {X86::VPMOVZXWQZrrkz, {0, Unknown}}, + {X86::VPMOVZXWQrm, {0, Unknown}}, + {X86::VPMOVZXWQrr, {0, Unknown}}, + {X86::VPMULDQYrm, {0, Unknown}}, + {X86::VPMULDQYrr, {0, Unknown}}, + {X86::VPMULDQZ128rm, {1, Unknown}}, + {X86::VPMULDQZ128rmb, {1, Unknown}}, + {X86::VPMULDQZ128rmbk, {1, Unknown}}, + {X86::VPMULDQZ128rmbkz, {1, Unknown}}, + {X86::VPMULDQZ128rmk, {1, Unknown}}, + {X86::VPMULDQZ128rmkz, {1, Unknown}}, + {X86::VPMULDQZ128rr, {0, Unknown}}, + {X86::VPMULDQZ128rrk, {0, Unknown}}, + {X86::VPMULDQZ128rrkz, {0, Unknown}}, + {X86::VPMULDQZ256rm, {0, Unknown}}, + {X86::VPMULDQZ256rmb, {0, Unknown}}, + {X86::VPMULDQZ256rmbk, {0, Unknown}}, + {X86::VPMULDQZ256rmbkz, {0, Unknown}}, + {X86::VPMULDQZ256rmk, {0, Unknown}}, + {X86::VPMULDQZ256rmkz, {0, Unknown}}, + {X86::VPMULDQZ256rr, {0, Unknown}}, + {X86::VPMULDQZ256rrk, {0, Unknown}}, + {X86::VPMULDQZ256rrkz, {0, Unknown}}, + {X86::VPMULDQZrm, {0, Unknown}}, + {X86::VPMULDQZrmb, {0, Unknown}}, + {X86::VPMULDQZrmbk, {0, Unknown}}, + {X86::VPMULDQZrmbkz, {0, Unknown}}, + {X86::VPMULDQZrmk, {0, Unknown}}, + {X86::VPMULDQZrmkz, {0, Unknown}}, + {X86::VPMULDQZrr, {0, Unknown}}, + {X86::VPMULDQZrrk, {0, Unknown}}, + {X86::VPMULDQZrrkz, {0, Unknown}}, + {X86::VPMULDQrm, {0, Unknown}}, + {X86::VPMULDQrr, {0, Unknown}}, + {X86::VPMULHRSWYrm, {0, Unknown}}, + {X86::VPMULHRSWYrr, {0, Unknown}}, + {X86::VPMULHRSWZ128rm, {1, Unknown}}, + {X86::VPMULHRSWZ128rmk, {1, Unknown}}, + {X86::VPMULHRSWZ128rmkz, {1, Unknown}}, + {X86::VPMULHRSWZ128rr, {0, Unknown}}, + {X86::VPMULHRSWZ128rrk, {0, Unknown}}, + {X86::VPMULHRSWZ128rrkz, {0, Unknown}}, + {X86::VPMULHRSWZ256rm, {0, Unknown}}, + {X86::VPMULHRSWZ256rmk, {0, Unknown}}, + {X86::VPMULHRSWZ256rmkz, {0, Unknown}}, + {X86::VPMULHRSWZ256rr, {0, Unknown}}, + {X86::VPMULHRSWZ256rrk, {0, Unknown}}, + {X86::VPMULHRSWZ256rrkz, {0, Unknown}}, + {X86::VPMULHRSWZrm, {0, Unknown}}, + {X86::VPMULHRSWZrmk, {0, Unknown}}, + {X86::VPMULHRSWZrmkz, {0, Unknown}}, + {X86::VPMULHRSWZrr, {0, Unknown}}, + {X86::VPMULHRSWZrrk, {0, Unknown}}, + {X86::VPMULHRSWZrrkz, {0, Unknown}}, + {X86::VPMULHRSWrm, {0, Unknown}}, + {X86::VPMULHRSWrr, {0, Unknown}}, + {X86::VPMULHUWYrm, {0, Unknown}}, + {X86::VPMULHUWYrr, {0, Unknown}}, + {X86::VPMULHUWZ128rm, {1, Unknown}}, + {X86::VPMULHUWZ128rmk, {1, Unknown}}, + {X86::VPMULHUWZ128rmkz, {1, Unknown}}, + {X86::VPMULHUWZ128rr, {0, Unknown}}, + {X86::VPMULHUWZ128rrk, {0, Unknown}}, + {X86::VPMULHUWZ128rrkz, {0, Unknown}}, + {X86::VPMULHUWZ256rm, {0, Unknown}}, + {X86::VPMULHUWZ256rmk, {0, Unknown}}, + {X86::VPMULHUWZ256rmkz, {0, Unknown}}, + {X86::VPMULHUWZ256rr, {0, Unknown}}, + {X86::VPMULHUWZ256rrk, {0, Unknown}}, + {X86::VPMULHUWZ256rrkz, {0, Unknown}}, + {X86::VPMULHUWZrm, {0, Unknown}}, + {X86::VPMULHUWZrmk, {0, Unknown}}, + {X86::VPMULHUWZrmkz, {0, Unknown}}, + {X86::VPMULHUWZrr, {0, Unknown}}, + {X86::VPMULHUWZrrk, {0, Unknown}}, + {X86::VPMULHUWZrrkz, {0, Unknown}}, + {X86::VPMULHUWrm, {0, Unknown}}, + {X86::VPMULHUWrr, {0, Unknown}}, + {X86::VPMULHWYrm, {0, Unknown}}, + {X86::VPMULHWYrr, {0, Unknown}}, + {X86::VPMULHWZ128rm, {1, Unknown}}, + {X86::VPMULHWZ128rmk, {1, Unknown}}, + {X86::VPMULHWZ128rmkz, {1, Unknown}}, + {X86::VPMULHWZ128rr, {0, Unknown}}, + {X86::VPMULHWZ128rrk, {0, Unknown}}, + {X86::VPMULHWZ128rrkz, {0, Unknown}}, + {X86::VPMULHWZ256rm, {0, Unknown}}, + {X86::VPMULHWZ256rmk, {0, Unknown}}, + {X86::VPMULHWZ256rmkz, {0, Unknown}}, + {X86::VPMULHWZ256rr, {0, Unknown}}, + {X86::VPMULHWZ256rrk, {0, Unknown}}, + {X86::VPMULHWZ256rrkz, {0, Unknown}}, + {X86::VPMULHWZrm, {0, Unknown}}, + {X86::VPMULHWZrmk, {0, Unknown}}, + {X86::VPMULHWZrmkz, {0, Unknown}}, + {X86::VPMULHWZrr, {0, Unknown}}, + {X86::VPMULHWZrrk, {0, Unknown}}, + {X86::VPMULHWZrrkz, {0, Unknown}}, + {X86::VPMULHWrm, {0, Unknown}}, + {X86::VPMULHWrr, {0, Unknown}}, + {X86::VPMULLDYrm, {0, Unknown}}, + {X86::VPMULLDYrr, {0, Unknown}}, + {X86::VPMULLDZ128rm, {1, Unknown}}, + {X86::VPMULLDZ128rmb, {1, Unknown}}, + {X86::VPMULLDZ128rmbk, {1, Unknown}}, + {X86::VPMULLDZ128rmbkz, {1, Unknown}}, + {X86::VPMULLDZ128rmk, {1, Unknown}}, + {X86::VPMULLDZ128rmkz, {1, Unknown}}, + {X86::VPMULLDZ128rr, {0, Unknown}}, + {X86::VPMULLDZ128rrk, {0, Unknown}}, + {X86::VPMULLDZ128rrkz, {0, Unknown}}, + {X86::VPMULLDZ256rm, {0, Unknown}}, + {X86::VPMULLDZ256rmb, {0, Unknown}}, + {X86::VPMULLDZ256rmbk, {0, Unknown}}, + {X86::VPMULLDZ256rmbkz, {0, Unknown}}, + {X86::VPMULLDZ256rmk, {0, Unknown}}, + {X86::VPMULLDZ256rmkz, {0, Unknown}}, + {X86::VPMULLDZ256rr, {0, Unknown}}, + {X86::VPMULLDZ256rrk, {0, Unknown}}, + {X86::VPMULLDZ256rrkz, {0, Unknown}}, + {X86::VPMULLDZrm, {0, Unknown}}, + {X86::VPMULLDZrmb, {0, Unknown}}, + {X86::VPMULLDZrmbk, {0, Unknown}}, + {X86::VPMULLDZrmbkz, {0, Unknown}}, + {X86::VPMULLDZrmk, {0, Unknown}}, + {X86::VPMULLDZrmkz, {0, Unknown}}, + {X86::VPMULLDZrr, {0, Unknown}}, + {X86::VPMULLDZrrk, {0, Unknown}}, + {X86::VPMULLDZrrkz, {0, Unknown}}, + {X86::VPMULLDrm, {0, Unknown}}, + {X86::VPMULLDrr, {0, Unknown}}, + {X86::VPMULLQZ128rm, {1, Unknown}}, + {X86::VPMULLQZ128rmb, {1, Unknown}}, + {X86::VPMULLQZ128rmbk, {1, Unknown}}, + {X86::VPMULLQZ128rmbkz, {1, Unknown}}, + {X86::VPMULLQZ128rmk, {1, Unknown}}, + {X86::VPMULLQZ128rmkz, {1, Unknown}}, + {X86::VPMULLQZ128rr, {0, Unknown}}, + {X86::VPMULLQZ128rrk, {0, Unknown}}, + {X86::VPMULLQZ128rrkz, {0, Unknown}}, + {X86::VPMULLQZ256rm, {0, Unknown}}, + {X86::VPMULLQZ256rmb, {0, Unknown}}, + {X86::VPMULLQZ256rmbk, {0, Unknown}}, + {X86::VPMULLQZ256rmbkz, {0, Unknown}}, + {X86::VPMULLQZ256rmk, {0, Unknown}}, + {X86::VPMULLQZ256rmkz, {0, Unknown}}, + {X86::VPMULLQZ256rr, {0, Unknown}}, + {X86::VPMULLQZ256rrk, {0, Unknown}}, + {X86::VPMULLQZ256rrkz, {0, Unknown}}, + {X86::VPMULLQZrm, {0, Unknown}}, + {X86::VPMULLQZrmb, {0, Unknown}}, + {X86::VPMULLQZrmbk, {0, Unknown}}, + {X86::VPMULLQZrmbkz, {0, Unknown}}, + {X86::VPMULLQZrmk, {0, Unknown}}, + {X86::VPMULLQZrmkz, {0, Unknown}}, + {X86::VPMULLQZrr, {0, Unknown}}, + {X86::VPMULLQZrrk, {0, Unknown}}, + {X86::VPMULLQZrrkz, {0, Unknown}}, + {X86::VPMULLWYrm, {0, Unknown}}, + {X86::VPMULLWYrr, {0, Unknown}}, + {X86::VPMULLWZ128rm, {1, Unknown}}, + {X86::VPMULLWZ128rmk, {1, Unknown}}, + {X86::VPMULLWZ128rmkz, {1, Unknown}}, + {X86::VPMULLWZ128rr, {0, Unknown}}, + {X86::VPMULLWZ128rrk, {0, Unknown}}, + {X86::VPMULLWZ128rrkz, {0, Unknown}}, + {X86::VPMULLWZ256rm, {0, Unknown}}, + {X86::VPMULLWZ256rmk, {0, Unknown}}, + {X86::VPMULLWZ256rmkz, {0, Unknown}}, + {X86::VPMULLWZ256rr, {0, Unknown}}, + {X86::VPMULLWZ256rrk, {0, Unknown}}, + {X86::VPMULLWZ256rrkz, {0, Unknown}}, + {X86::VPMULLWZrm, {0, Unknown}}, + {X86::VPMULLWZrmk, {0, Unknown}}, + {X86::VPMULLWZrmkz, {0, Unknown}}, + {X86::VPMULLWZrr, {0, Unknown}}, + {X86::VPMULLWZrrk, {0, Unknown}}, + {X86::VPMULLWZrrkz, {0, Unknown}}, + {X86::VPMULLWrm, {0, Unknown}}, + {X86::VPMULLWrr, {0, Unknown}}, + {X86::VPMULTISHIFTQBZ128rm, {1, Unknown}}, + {X86::VPMULTISHIFTQBZ128rmb, {1, Unknown}}, + {X86::VPMULTISHIFTQBZ128rmbk, {1, Unknown}}, + {X86::VPMULTISHIFTQBZ128rmbkz, {1, Unknown}}, + {X86::VPMULTISHIFTQBZ128rmk, {1, Unknown}}, + {X86::VPMULTISHIFTQBZ128rmkz, {1, Unknown}}, + {X86::VPMULTISHIFTQBZ128rr, {0, Unknown}}, + {X86::VPMULTISHIFTQBZ128rrk, {0, Unknown}}, + {X86::VPMULTISHIFTQBZ128rrkz, {0, Unknown}}, + {X86::VPMULTISHIFTQBZ256rm, {0, Unknown}}, + {X86::VPMULTISHIFTQBZ256rmb, {0, Unknown}}, + {X86::VPMULTISHIFTQBZ256rmbk, {0, Unknown}}, + {X86::VPMULTISHIFTQBZ256rmbkz, {0, Unknown}}, + {X86::VPMULTISHIFTQBZ256rmk, {0, Unknown}}, + {X86::VPMULTISHIFTQBZ256rmkz, {0, Unknown}}, + {X86::VPMULTISHIFTQBZ256rr, {0, Unknown}}, + {X86::VPMULTISHIFTQBZ256rrk, {0, Unknown}}, + {X86::VPMULTISHIFTQBZ256rrkz, {0, Unknown}}, + {X86::VPMULTISHIFTQBZrm, {0, Unknown}}, + {X86::VPMULTISHIFTQBZrmb, {0, Unknown}}, + {X86::VPMULTISHIFTQBZrmbk, {0, Unknown}}, + {X86::VPMULTISHIFTQBZrmbkz, {0, Unknown}}, + {X86::VPMULTISHIFTQBZrmk, {0, Unknown}}, + {X86::VPMULTISHIFTQBZrmkz, {0, Unknown}}, + {X86::VPMULTISHIFTQBZrr, {0, Unknown}}, + {X86::VPMULTISHIFTQBZrrk, {0, Unknown}}, + {X86::VPMULTISHIFTQBZrrkz, {0, Unknown}}, + {X86::VPMULUDQYrm, {0, Unknown}}, + {X86::VPMULUDQYrr, {0, Unknown}}, + {X86::VPMULUDQZ128rm, {1, Unknown}}, + {X86::VPMULUDQZ128rmb, {1, Unknown}}, + {X86::VPMULUDQZ128rmbk, {1, Unknown}}, + {X86::VPMULUDQZ128rmbkz, {1, Unknown}}, + {X86::VPMULUDQZ128rmk, {1, Unknown}}, + {X86::VPMULUDQZ128rmkz, {1, Unknown}}, + {X86::VPMULUDQZ128rr, {0, Unknown}}, + {X86::VPMULUDQZ128rrk, {0, Unknown}}, + {X86::VPMULUDQZ128rrkz, {0, Unknown}}, + {X86::VPMULUDQZ256rm, {0, Unknown}}, + {X86::VPMULUDQZ256rmb, {0, Unknown}}, + {X86::VPMULUDQZ256rmbk, {0, Unknown}}, + {X86::VPMULUDQZ256rmbkz, {0, Unknown}}, + {X86::VPMULUDQZ256rmk, {0, Unknown}}, + {X86::VPMULUDQZ256rmkz, {0, Unknown}}, + {X86::VPMULUDQZ256rr, {0, Unknown}}, + {X86::VPMULUDQZ256rrk, {0, Unknown}}, + {X86::VPMULUDQZ256rrkz, {0, Unknown}}, + {X86::VPMULUDQZrm, {0, Unknown}}, + {X86::VPMULUDQZrmb, {0, Unknown}}, + {X86::VPMULUDQZrmbk, {0, Unknown}}, + {X86::VPMULUDQZrmbkz, {0, Unknown}}, + {X86::VPMULUDQZrmk, {0, Unknown}}, + {X86::VPMULUDQZrmkz, {0, Unknown}}, + {X86::VPMULUDQZrr, {0, Unknown}}, + {X86::VPMULUDQZrrk, {0, Unknown}}, + {X86::VPMULUDQZrrkz, {0, Unknown}}, + {X86::VPMULUDQrm, {0, Unknown}}, + {X86::VPMULUDQrr, {0, Unknown}}, + {X86::VPOPCNTBZ128rm, {1, Unknown}}, + {X86::VPOPCNTBZ128rmk, {1, Unknown}}, + {X86::VPOPCNTBZ128rmkz, {1, Unknown}}, + {X86::VPOPCNTBZ128rr, {0, Unknown}}, + {X86::VPOPCNTBZ128rrk, {0, Unknown}}, + {X86::VPOPCNTBZ128rrkz, {0, Unknown}}, + {X86::VPOPCNTBZ256rm, {0, Unknown}}, + {X86::VPOPCNTBZ256rmk, {0, Unknown}}, + {X86::VPOPCNTBZ256rmkz, {0, Unknown}}, + {X86::VPOPCNTBZ256rr, {0, Unknown}}, + {X86::VPOPCNTBZ256rrk, {0, Unknown}}, + {X86::VPOPCNTBZ256rrkz, {0, Unknown}}, + {X86::VPOPCNTBZrm, {0, Unknown}}, + {X86::VPOPCNTBZrmk, {0, Unknown}}, + {X86::VPOPCNTBZrmkz, {0, Unknown}}, + {X86::VPOPCNTBZrr, {0, Unknown}}, + {X86::VPOPCNTBZrrk, {0, Unknown}}, + {X86::VPOPCNTBZrrkz, {0, Unknown}}, + {X86::VPOPCNTDZ128rm, {1, Unknown}}, + {X86::VPOPCNTDZ128rmb, {1, Unknown}}, + {X86::VPOPCNTDZ128rmbk, {1, Unknown}}, + {X86::VPOPCNTDZ128rmbkz, {1, Unknown}}, + {X86::VPOPCNTDZ128rmk, {1, Unknown}}, + {X86::VPOPCNTDZ128rmkz, {1, Unknown}}, + {X86::VPOPCNTDZ128rr, {0, Unknown}}, + {X86::VPOPCNTDZ128rrk, {0, Unknown}}, + {X86::VPOPCNTDZ128rrkz, {0, Unknown}}, + {X86::VPOPCNTDZ256rm, {0, Unknown}}, + {X86::VPOPCNTDZ256rmb, {0, Unknown}}, + {X86::VPOPCNTDZ256rmbk, {0, Unknown}}, + {X86::VPOPCNTDZ256rmbkz, {0, Unknown}}, + {X86::VPOPCNTDZ256rmk, {0, Unknown}}, + {X86::VPOPCNTDZ256rmkz, {0, Unknown}}, + {X86::VPOPCNTDZ256rr, {0, Unknown}}, + {X86::VPOPCNTDZ256rrk, {0, Unknown}}, + {X86::VPOPCNTDZ256rrkz, {0, Unknown}}, + {X86::VPOPCNTDZrm, {0, Unknown}}, + {X86::VPOPCNTDZrmb, {0, Unknown}}, + {X86::VPOPCNTDZrmbk, {0, Unknown}}, + {X86::VPOPCNTDZrmbkz, {0, Unknown}}, + {X86::VPOPCNTDZrmk, {0, Unknown}}, + {X86::VPOPCNTDZrmkz, {0, Unknown}}, + {X86::VPOPCNTDZrr, {0, Unknown}}, + {X86::VPOPCNTDZrrk, {0, Unknown}}, + {X86::VPOPCNTDZrrkz, {0, Unknown}}, + {X86::VPOPCNTQZ128rm, {1, Unknown}}, + {X86::VPOPCNTQZ128rmb, {1, Unknown}}, + {X86::VPOPCNTQZ128rmbk, {1, Unknown}}, + {X86::VPOPCNTQZ128rmbkz, {1, Unknown}}, + {X86::VPOPCNTQZ128rmk, {1, Unknown}}, + {X86::VPOPCNTQZ128rmkz, {1, Unknown}}, + {X86::VPOPCNTQZ128rr, {0, Unknown}}, + {X86::VPOPCNTQZ128rrk, {0, Unknown}}, + {X86::VPOPCNTQZ128rrkz, {0, Unknown}}, + {X86::VPOPCNTQZ256rm, {0, Unknown}}, + {X86::VPOPCNTQZ256rmb, {0, Unknown}}, + {X86::VPOPCNTQZ256rmbk, {0, Unknown}}, + {X86::VPOPCNTQZ256rmbkz, {0, Unknown}}, + {X86::VPOPCNTQZ256rmk, {0, Unknown}}, + {X86::VPOPCNTQZ256rmkz, {0, Unknown}}, + {X86::VPOPCNTQZ256rr, {0, Unknown}}, + {X86::VPOPCNTQZ256rrk, {0, Unknown}}, + {X86::VPOPCNTQZ256rrkz, {0, Unknown}}, + {X86::VPOPCNTQZrm, {0, Unknown}}, + {X86::VPOPCNTQZrmb, {0, Unknown}}, + {X86::VPOPCNTQZrmbk, {0, Unknown}}, + {X86::VPOPCNTQZrmbkz, {0, Unknown}}, + {X86::VPOPCNTQZrmk, {0, Unknown}}, + {X86::VPOPCNTQZrmkz, {0, Unknown}}, + {X86::VPOPCNTQZrr, {0, Unknown}}, + {X86::VPOPCNTQZrrk, {0, Unknown}}, + {X86::VPOPCNTQZrrkz, {0, Unknown}}, + {X86::VPOPCNTWZ128rm, {1, Unknown}}, + {X86::VPOPCNTWZ128rmk, {1, Unknown}}, + {X86::VPOPCNTWZ128rmkz, {1, Unknown}}, + {X86::VPOPCNTWZ128rr, {0, Unknown}}, + {X86::VPOPCNTWZ128rrk, {0, Unknown}}, + {X86::VPOPCNTWZ128rrkz, {0, Unknown}}, + {X86::VPOPCNTWZ256rm, {0, Unknown}}, + {X86::VPOPCNTWZ256rmk, {0, Unknown}}, + {X86::VPOPCNTWZ256rmkz, {0, Unknown}}, + {X86::VPOPCNTWZ256rr, {0, Unknown}}, + {X86::VPOPCNTWZ256rrk, {0, Unknown}}, + {X86::VPOPCNTWZ256rrkz, {0, Unknown}}, + {X86::VPOPCNTWZrm, {0, Unknown}}, + {X86::VPOPCNTWZrmk, {0, Unknown}}, + {X86::VPOPCNTWZrmkz, {0, Unknown}}, + {X86::VPOPCNTWZrr, {0, Unknown}}, + {X86::VPOPCNTWZrrk, {0, Unknown}}, + {X86::VPOPCNTWZrrkz, {0, Unknown}}, + {X86::VPORDZ128rm, {1, Unknown}}, + {X86::VPORDZ128rmb, {1, Unknown}}, + {X86::VPORDZ128rmbk, {1, Unknown}}, + {X86::VPORDZ128rmbkz, {1, Unknown}}, + {X86::VPORDZ128rmk, {1, Unknown}}, + {X86::VPORDZ128rmkz, {1, Unknown}}, + {X86::VPORDZ128rr, {0, Unknown}}, + {X86::VPORDZ128rrk, {0, Unknown}}, + {X86::VPORDZ128rrkz, {0, Unknown}}, + {X86::VPORDZ256rm, {0, Unknown}}, + {X86::VPORDZ256rmb, {0, Unknown}}, + {X86::VPORDZ256rmbk, {0, Unknown}}, + {X86::VPORDZ256rmbkz, {0, Unknown}}, + {X86::VPORDZ256rmk, {0, Unknown}}, + {X86::VPORDZ256rmkz, {0, Unknown}}, + {X86::VPORDZ256rr, {0, Unknown}}, + {X86::VPORDZ256rrk, {0, Unknown}}, + {X86::VPORDZ256rrkz, {0, Unknown}}, + {X86::VPORDZrm, {0, Unknown}}, + {X86::VPORDZrmb, {0, Unknown}}, + {X86::VPORDZrmbk, {0, Unknown}}, + {X86::VPORDZrmbkz, {0, Unknown}}, + {X86::VPORDZrmk, {0, Unknown}}, + {X86::VPORDZrmkz, {0, Unknown}}, + {X86::VPORDZrr, {0, Unknown}}, + {X86::VPORDZrrk, {0, Unknown}}, + {X86::VPORDZrrkz, {0, Unknown}}, + {X86::VPORQZ128rm, {1, Unknown}}, + {X86::VPORQZ128rmb, {1, Unknown}}, + {X86::VPORQZ128rmbk, {1, Unknown}}, + {X86::VPORQZ128rmbkz, {1, Unknown}}, + {X86::VPORQZ128rmk, {1, Unknown}}, + {X86::VPORQZ128rmkz, {1, Unknown}}, + {X86::VPORQZ128rr, {0, Unknown}}, + {X86::VPORQZ128rrk, {0, Unknown}}, + {X86::VPORQZ128rrkz, {0, Unknown}}, + {X86::VPORQZ256rm, {0, Unknown}}, + {X86::VPORQZ256rmb, {0, Unknown}}, + {X86::VPORQZ256rmbk, {0, Unknown}}, + {X86::VPORQZ256rmbkz, {0, Unknown}}, + {X86::VPORQZ256rmk, {0, Unknown}}, + {X86::VPORQZ256rmkz, {0, Unknown}}, + {X86::VPORQZ256rr, {0, Unknown}}, + {X86::VPORQZ256rrk, {0, Unknown}}, + {X86::VPORQZ256rrkz, {0, Unknown}}, + {X86::VPORQZrm, {0, Unknown}}, + {X86::VPORQZrmb, {0, Unknown}}, + {X86::VPORQZrmbk, {0, Unknown}}, + {X86::VPORQZrmbkz, {0, Unknown}}, + {X86::VPORQZrmk, {0, Unknown}}, + {X86::VPORQZrmkz, {0, Unknown}}, + {X86::VPORQZrr, {0, Unknown}}, + {X86::VPORQZrrk, {0, Unknown}}, + {X86::VPORQZrrkz, {0, Unknown}}, + {X86::VPORYrm, {0, Unknown}}, + {X86::VPORYrr, {0, Unknown}}, + {X86::VPORrm, {0, Unknown}}, + {X86::VPORrr, {0, Unknown}}, + {X86::VPPERMrmr, {0, Unknown}}, + {X86::VPPERMrrm, {0, Unknown}}, + {X86::VPPERMrrr, {0, Unknown}}, + {X86::VPPERMrrr_REV, {0, Unknown}}, + {X86::VPROLDZ128mbi, {0, Unknown}}, + {X86::VPROLDZ128mbik, {0, Unknown}}, + {X86::VPROLDZ128mbikz, {0, Unknown}}, + {X86::VPROLDZ128mi, {1, Unknown}}, + {X86::VPROLDZ128mik, {1, Unknown}}, + {X86::VPROLDZ128mikz, {1, Unknown}}, + {X86::VPROLDZ128ri, {0, Unknown}}, + {X86::VPROLDZ128rik, {0, Unknown}}, + {X86::VPROLDZ128rikz, {0, Unknown}}, + {X86::VPROLDZ256mbi, {0, Unknown}}, + {X86::VPROLDZ256mbik, {0, Unknown}}, + {X86::VPROLDZ256mbikz, {0, Unknown}}, + {X86::VPROLDZ256mi, {0, Unknown}}, + {X86::VPROLDZ256mik, {0, Unknown}}, + {X86::VPROLDZ256mikz, {0, Unknown}}, + {X86::VPROLDZ256ri, {0, Unknown}}, + {X86::VPROLDZ256rik, {0, Unknown}}, + {X86::VPROLDZ256rikz, {0, Unknown}}, + {X86::VPROLDZmbi, {0, Unknown}}, + {X86::VPROLDZmbik, {0, Unknown}}, + {X86::VPROLDZmbikz, {0, Unknown}}, + {X86::VPROLDZmi, {0, Unknown}}, + {X86::VPROLDZmik, {0, Unknown}}, + {X86::VPROLDZmikz, {0, Unknown}}, + {X86::VPROLDZri, {0, Unknown}}, + {X86::VPROLDZrik, {0, Unknown}}, + {X86::VPROLDZrikz, {0, Unknown}}, + {X86::VPROLQZ128mbi, {0, Unknown}}, + {X86::VPROLQZ128mbik, {0, Unknown}}, + {X86::VPROLQZ128mbikz, {0, Unknown}}, + {X86::VPROLQZ128mi, {1, Unknown}}, + {X86::VPROLQZ128mik, {1, Unknown}}, + {X86::VPROLQZ128mikz, {1, Unknown}}, + {X86::VPROLQZ128ri, {0, Unknown}}, + {X86::VPROLQZ128rik, {0, Unknown}}, + {X86::VPROLQZ128rikz, {0, Unknown}}, + {X86::VPROLQZ256mbi, {0, Unknown}}, + {X86::VPROLQZ256mbik, {0, Unknown}}, + {X86::VPROLQZ256mbikz, {0, Unknown}}, + {X86::VPROLQZ256mi, {0, Unknown}}, + {X86::VPROLQZ256mik, {0, Unknown}}, + {X86::VPROLQZ256mikz, {0, Unknown}}, + {X86::VPROLQZ256ri, {0, Unknown}}, + {X86::VPROLQZ256rik, {0, Unknown}}, + {X86::VPROLQZ256rikz, {0, Unknown}}, + {X86::VPROLQZmbi, {0, Unknown}}, + {X86::VPROLQZmbik, {0, Unknown}}, + {X86::VPROLQZmbikz, {0, Unknown}}, + {X86::VPROLQZmi, {0, Unknown}}, + {X86::VPROLQZmik, {0, Unknown}}, + {X86::VPROLQZmikz, {0, Unknown}}, + {X86::VPROLQZri, {0, Unknown}}, + {X86::VPROLQZrik, {0, Unknown}}, + {X86::VPROLQZrikz, {0, Unknown}}, + {X86::VPROLVDZ128rm, {1, Unknown}}, + {X86::VPROLVDZ128rmb, {1, Unknown}}, + {X86::VPROLVDZ128rmbk, {1, Unknown}}, + {X86::VPROLVDZ128rmbkz, {1, Unknown}}, + {X86::VPROLVDZ128rmk, {1, Unknown}}, + {X86::VPROLVDZ128rmkz, {1, Unknown}}, + {X86::VPROLVDZ128rr, {0, Unknown}}, + {X86::VPROLVDZ128rrk, {0, Unknown}}, + {X86::VPROLVDZ128rrkz, {0, Unknown}}, + {X86::VPROLVDZ256rm, {0, Unknown}}, + {X86::VPROLVDZ256rmb, {0, Unknown}}, + {X86::VPROLVDZ256rmbk, {0, Unknown}}, + {X86::VPROLVDZ256rmbkz, {0, Unknown}}, + {X86::VPROLVDZ256rmk, {0, Unknown}}, + {X86::VPROLVDZ256rmkz, {0, Unknown}}, + {X86::VPROLVDZ256rr, {0, Unknown}}, + {X86::VPROLVDZ256rrk, {0, Unknown}}, + {X86::VPROLVDZ256rrkz, {0, Unknown}}, + {X86::VPROLVDZrm, {0, Unknown}}, + {X86::VPROLVDZrmb, {0, Unknown}}, + {X86::VPROLVDZrmbk, {0, Unknown}}, + {X86::VPROLVDZrmbkz, {0, Unknown}}, + {X86::VPROLVDZrmk, {0, Unknown}}, + {X86::VPROLVDZrmkz, {0, Unknown}}, + {X86::VPROLVDZrr, {0, Unknown}}, + {X86::VPROLVDZrrk, {0, Unknown}}, + {X86::VPROLVDZrrkz, {0, Unknown}}, + {X86::VPROLVQZ128rm, {1, Unknown}}, + {X86::VPROLVQZ128rmb, {1, Unknown}}, + {X86::VPROLVQZ128rmbk, {1, Unknown}}, + {X86::VPROLVQZ128rmbkz, {1, Unknown}}, + {X86::VPROLVQZ128rmk, {1, Unknown}}, + {X86::VPROLVQZ128rmkz, {1, Unknown}}, + {X86::VPROLVQZ128rr, {0, Unknown}}, + {X86::VPROLVQZ128rrk, {0, Unknown}}, + {X86::VPROLVQZ128rrkz, {0, Unknown}}, + {X86::VPROLVQZ256rm, {0, Unknown}}, + {X86::VPROLVQZ256rmb, {0, Unknown}}, + {X86::VPROLVQZ256rmbk, {0, Unknown}}, + {X86::VPROLVQZ256rmbkz, {0, Unknown}}, + {X86::VPROLVQZ256rmk, {0, Unknown}}, + {X86::VPROLVQZ256rmkz, {0, Unknown}}, + {X86::VPROLVQZ256rr, {0, Unknown}}, + {X86::VPROLVQZ256rrk, {0, Unknown}}, + {X86::VPROLVQZ256rrkz, {0, Unknown}}, + {X86::VPROLVQZrm, {0, Unknown}}, + {X86::VPROLVQZrmb, {0, Unknown}}, + {X86::VPROLVQZrmbk, {0, Unknown}}, + {X86::VPROLVQZrmbkz, {0, Unknown}}, + {X86::VPROLVQZrmk, {0, Unknown}}, + {X86::VPROLVQZrmkz, {0, Unknown}}, + {X86::VPROLVQZrr, {0, Unknown}}, + {X86::VPROLVQZrrk, {0, Unknown}}, + {X86::VPROLVQZrrkz, {0, Unknown}}, + {X86::VPRORDZ128mbi, {0, Unknown}}, + {X86::VPRORDZ128mbik, {0, Unknown}}, + {X86::VPRORDZ128mbikz, {0, Unknown}}, + {X86::VPRORDZ128mi, {1, Unknown}}, + {X86::VPRORDZ128mik, {1, Unknown}}, + {X86::VPRORDZ128mikz, {1, Unknown}}, + {X86::VPRORDZ128ri, {0, Unknown}}, + {X86::VPRORDZ128rik, {0, Unknown}}, + {X86::VPRORDZ128rikz, {0, Unknown}}, + {X86::VPRORDZ256mbi, {0, Unknown}}, + {X86::VPRORDZ256mbik, {0, Unknown}}, + {X86::VPRORDZ256mbikz, {0, Unknown}}, + {X86::VPRORDZ256mi, {0, Unknown}}, + {X86::VPRORDZ256mik, {0, Unknown}}, + {X86::VPRORDZ256mikz, {0, Unknown}}, + {X86::VPRORDZ256ri, {0, Unknown}}, + {X86::VPRORDZ256rik, {0, Unknown}}, + {X86::VPRORDZ256rikz, {0, Unknown}}, + {X86::VPRORDZmbi, {0, Unknown}}, + {X86::VPRORDZmbik, {0, Unknown}}, + {X86::VPRORDZmbikz, {0, Unknown}}, + {X86::VPRORDZmi, {0, Unknown}}, + {X86::VPRORDZmik, {0, Unknown}}, + {X86::VPRORDZmikz, {0, Unknown}}, + {X86::VPRORDZri, {0, Unknown}}, + {X86::VPRORDZrik, {0, Unknown}}, + {X86::VPRORDZrikz, {0, Unknown}}, + {X86::VPRORQZ128mbi, {0, Unknown}}, + {X86::VPRORQZ128mbik, {0, Unknown}}, + {X86::VPRORQZ128mbikz, {0, Unknown}}, + {X86::VPRORQZ128mi, {1, Unknown}}, + {X86::VPRORQZ128mik, {1, Unknown}}, + {X86::VPRORQZ128mikz, {1, Unknown}}, + {X86::VPRORQZ128ri, {0, Unknown}}, + {X86::VPRORQZ128rik, {0, Unknown}}, + {X86::VPRORQZ128rikz, {0, Unknown}}, + {X86::VPRORQZ256mbi, {0, Unknown}}, + {X86::VPRORQZ256mbik, {0, Unknown}}, + {X86::VPRORQZ256mbikz, {0, Unknown}}, + {X86::VPRORQZ256mi, {0, Unknown}}, + {X86::VPRORQZ256mik, {0, Unknown}}, + {X86::VPRORQZ256mikz, {0, Unknown}}, + {X86::VPRORQZ256ri, {0, Unknown}}, + {X86::VPRORQZ256rik, {0, Unknown}}, + {X86::VPRORQZ256rikz, {0, Unknown}}, + {X86::VPRORQZmbi, {0, Unknown}}, + {X86::VPRORQZmbik, {0, Unknown}}, + {X86::VPRORQZmbikz, {0, Unknown}}, + {X86::VPRORQZmi, {0, Unknown}}, + {X86::VPRORQZmik, {0, Unknown}}, + {X86::VPRORQZmikz, {0, Unknown}}, + {X86::VPRORQZri, {0, Unknown}}, + {X86::VPRORQZrik, {0, Unknown}}, + {X86::VPRORQZrikz, {0, Unknown}}, + {X86::VPRORVDZ128rm, {1, Unknown}}, + {X86::VPRORVDZ128rmb, {1, Unknown}}, + {X86::VPRORVDZ128rmbk, {1, Unknown}}, + {X86::VPRORVDZ128rmbkz, {1, Unknown}}, + {X86::VPRORVDZ128rmk, {1, Unknown}}, + {X86::VPRORVDZ128rmkz, {1, Unknown}}, + {X86::VPRORVDZ128rr, {0, Unknown}}, + {X86::VPRORVDZ128rrk, {0, Unknown}}, + {X86::VPRORVDZ128rrkz, {0, Unknown}}, + {X86::VPRORVDZ256rm, {0, Unknown}}, + {X86::VPRORVDZ256rmb, {0, Unknown}}, + {X86::VPRORVDZ256rmbk, {0, Unknown}}, + {X86::VPRORVDZ256rmbkz, {0, Unknown}}, + {X86::VPRORVDZ256rmk, {0, Unknown}}, + {X86::VPRORVDZ256rmkz, {0, Unknown}}, + {X86::VPRORVDZ256rr, {0, Unknown}}, + {X86::VPRORVDZ256rrk, {0, Unknown}}, + {X86::VPRORVDZ256rrkz, {0, Unknown}}, + {X86::VPRORVDZrm, {0, Unknown}}, + {X86::VPRORVDZrmb, {0, Unknown}}, + {X86::VPRORVDZrmbk, {0, Unknown}}, + {X86::VPRORVDZrmbkz, {0, Unknown}}, + {X86::VPRORVDZrmk, {0, Unknown}}, + {X86::VPRORVDZrmkz, {0, Unknown}}, + {X86::VPRORVDZrr, {0, Unknown}}, + {X86::VPRORVDZrrk, {0, Unknown}}, + {X86::VPRORVDZrrkz, {0, Unknown}}, + {X86::VPRORVQZ128rm, {1, Unknown}}, + {X86::VPRORVQZ128rmb, {1, Unknown}}, + {X86::VPRORVQZ128rmbk, {1, Unknown}}, + {X86::VPRORVQZ128rmbkz, {1, Unknown}}, + {X86::VPRORVQZ128rmk, {1, Unknown}}, + {X86::VPRORVQZ128rmkz, {1, Unknown}}, + {X86::VPRORVQZ128rr, {0, Unknown}}, + {X86::VPRORVQZ128rrk, {0, Unknown}}, + {X86::VPRORVQZ128rrkz, {0, Unknown}}, + {X86::VPRORVQZ256rm, {0, Unknown}}, + {X86::VPRORVQZ256rmb, {0, Unknown}}, + {X86::VPRORVQZ256rmbk, {0, Unknown}}, + {X86::VPRORVQZ256rmbkz, {0, Unknown}}, + {X86::VPRORVQZ256rmk, {0, Unknown}}, + {X86::VPRORVQZ256rmkz, {0, Unknown}}, + {X86::VPRORVQZ256rr, {0, Unknown}}, + {X86::VPRORVQZ256rrk, {0, Unknown}}, + {X86::VPRORVQZ256rrkz, {0, Unknown}}, + {X86::VPRORVQZrm, {0, Unknown}}, + {X86::VPRORVQZrmb, {0, Unknown}}, + {X86::VPRORVQZrmbk, {0, Unknown}}, + {X86::VPRORVQZrmbkz, {0, Unknown}}, + {X86::VPRORVQZrmk, {0, Unknown}}, + {X86::VPRORVQZrmkz, {0, Unknown}}, + {X86::VPRORVQZrr, {0, Unknown}}, + {X86::VPRORVQZrrk, {0, Unknown}}, + {X86::VPRORVQZrrkz, {0, Unknown}}, + {X86::VPROTBmi, {0, Unknown}}, + {X86::VPROTBmr, {0, Unknown}}, + {X86::VPROTBri, {0, Unknown}}, + {X86::VPROTBrm, {0, Unknown}}, + {X86::VPROTBrr, {0, Unknown}}, + {X86::VPROTBrr_REV, {0, Unknown}}, + {X86::VPROTDmi, {0, Unknown}}, + {X86::VPROTDmr, {0, Unknown}}, + {X86::VPROTDri, {0, Unknown}}, + {X86::VPROTDrm, {0, Unknown}}, + {X86::VPROTDrr, {0, Unknown}}, + {X86::VPROTDrr_REV, {0, Unknown}}, + {X86::VPROTQmi, {0, Unknown}}, + {X86::VPROTQmr, {0, Unknown}}, + {X86::VPROTQri, {0, Unknown}}, + {X86::VPROTQrm, {0, Unknown}}, + {X86::VPROTQrr, {0, Unknown}}, + {X86::VPROTQrr_REV, {0, Unknown}}, + {X86::VPROTWmi, {0, Unknown}}, + {X86::VPROTWmr, {0, Unknown}}, + {X86::VPROTWri, {0, Unknown}}, + {X86::VPROTWrm, {0, Unknown}}, + {X86::VPROTWrr, {0, Unknown}}, + {X86::VPROTWrr_REV, {0, Unknown}}, + {X86::VPSADBWYrm, {0, Unknown}}, + {X86::VPSADBWYrr, {0, Unknown}}, + {X86::VPSADBWZ128rm, {1, Unknown}}, + {X86::VPSADBWZ128rr, {0, Unknown}}, + {X86::VPSADBWZ256rm, {0, Unknown}}, + {X86::VPSADBWZ256rr, {0, Unknown}}, + {X86::VPSADBWZrm, {0, Unknown}}, + {X86::VPSADBWZrr, {0, Unknown}}, + {X86::VPSADBWrm, {0, Unknown}}, + {X86::VPSADBWrr, {0, Unknown}}, + {X86::VPSCATTERDDZ128mr, {1, Unknown}}, + {X86::VPSCATTERDDZ256mr, {0, Unknown}}, + {X86::VPSCATTERDDZmr, {0, Unknown}}, + {X86::VPSCATTERDQZ128mr, {1, Unknown}}, + {X86::VPSCATTERDQZ256mr, {0, Unknown}}, + {X86::VPSCATTERDQZmr, {0, Unknown}}, + {X86::VPSCATTERQDZ128mr, {1, Unknown}}, + {X86::VPSCATTERQDZ256mr, {0, Unknown}}, + {X86::VPSCATTERQDZmr, {0, Unknown}}, + {X86::VPSCATTERQQZ128mr, {1, Unknown}}, + {X86::VPSCATTERQQZ256mr, {0, Unknown}}, + {X86::VPSCATTERQQZmr, {0, Unknown}}, + {X86::VPSHABmr, {0, Unknown}}, + {X86::VPSHABrm, {0, Unknown}}, + {X86::VPSHABrr, {0, Unknown}}, + {X86::VPSHABrr_REV, {0, Unknown}}, + {X86::VPSHADmr, {0, Unknown}}, + {X86::VPSHADrm, {0, Unknown}}, + {X86::VPSHADrr, {0, Unknown}}, + {X86::VPSHADrr_REV, {0, Unknown}}, + {X86::VPSHAQmr, {0, Unknown}}, + {X86::VPSHAQrm, {0, Unknown}}, + {X86::VPSHAQrr, {0, Unknown}}, + {X86::VPSHAQrr_REV, {0, Unknown}}, + {X86::VPSHAWmr, {0, Unknown}}, + {X86::VPSHAWrm, {0, Unknown}}, + {X86::VPSHAWrr, {0, Unknown}}, + {X86::VPSHAWrr_REV, {0, Unknown}}, + {X86::VPSHLBmr, {0, Unknown}}, + {X86::VPSHLBrm, {0, Unknown}}, + {X86::VPSHLBrr, {0, Unknown}}, + {X86::VPSHLBrr_REV, {0, Unknown}}, + {X86::VPSHLDDZ128rmbi, {1, Unknown}}, + {X86::VPSHLDDZ128rmbik, {1, Unknown}}, + {X86::VPSHLDDZ128rmbikz, {1, Unknown}}, + {X86::VPSHLDDZ128rmi, {1, Unknown}}, + {X86::VPSHLDDZ128rmik, {1, Unknown}}, + {X86::VPSHLDDZ128rmikz, {1, Unknown}}, + {X86::VPSHLDDZ128rri, {0, Unknown}}, + {X86::VPSHLDDZ128rrik, {0, Unknown}}, + {X86::VPSHLDDZ128rrikz, {0, Unknown}}, + {X86::VPSHLDDZ256rmbi, {0, Unknown}}, + {X86::VPSHLDDZ256rmbik, {0, Unknown}}, + {X86::VPSHLDDZ256rmbikz, {0, Unknown}}, + {X86::VPSHLDDZ256rmi, {0, Unknown}}, + {X86::VPSHLDDZ256rmik, {0, Unknown}}, + {X86::VPSHLDDZ256rmikz, {0, Unknown}}, + {X86::VPSHLDDZ256rri, {0, Unknown}}, + {X86::VPSHLDDZ256rrik, {0, Unknown}}, + {X86::VPSHLDDZ256rrikz, {0, Unknown}}, + {X86::VPSHLDDZrmbi, {0, Unknown}}, + {X86::VPSHLDDZrmbik, {0, Unknown}}, + {X86::VPSHLDDZrmbikz, {0, Unknown}}, + {X86::VPSHLDDZrmi, {0, Unknown}}, + {X86::VPSHLDDZrmik, {0, Unknown}}, + {X86::VPSHLDDZrmikz, {0, Unknown}}, + {X86::VPSHLDDZrri, {0, Unknown}}, + {X86::VPSHLDDZrrik, {0, Unknown}}, + {X86::VPSHLDDZrrikz, {0, Unknown}}, + {X86::VPSHLDQZ128rmbi, {1, Unknown}}, + {X86::VPSHLDQZ128rmbik, {1, Unknown}}, + {X86::VPSHLDQZ128rmbikz, {1, Unknown}}, + {X86::VPSHLDQZ128rmi, {1, Unknown}}, + {X86::VPSHLDQZ128rmik, {1, Unknown}}, + {X86::VPSHLDQZ128rmikz, {1, Unknown}}, + {X86::VPSHLDQZ128rri, {0, Unknown}}, + {X86::VPSHLDQZ128rrik, {0, Unknown}}, + {X86::VPSHLDQZ128rrikz, {0, Unknown}}, + {X86::VPSHLDQZ256rmbi, {0, Unknown}}, + {X86::VPSHLDQZ256rmbik, {0, Unknown}}, + {X86::VPSHLDQZ256rmbikz, {0, Unknown}}, + {X86::VPSHLDQZ256rmi, {0, Unknown}}, + {X86::VPSHLDQZ256rmik, {0, Unknown}}, + {X86::VPSHLDQZ256rmikz, {0, Unknown}}, + {X86::VPSHLDQZ256rri, {0, Unknown}}, + {X86::VPSHLDQZ256rrik, {0, Unknown}}, + {X86::VPSHLDQZ256rrikz, {0, Unknown}}, + {X86::VPSHLDQZrmbi, {0, Unknown}}, + {X86::VPSHLDQZrmbik, {0, Unknown}}, + {X86::VPSHLDQZrmbikz, {0, Unknown}}, + {X86::VPSHLDQZrmi, {0, Unknown}}, + {X86::VPSHLDQZrmik, {0, Unknown}}, + {X86::VPSHLDQZrmikz, {0, Unknown}}, + {X86::VPSHLDQZrri, {0, Unknown}}, + {X86::VPSHLDQZrrik, {0, Unknown}}, + {X86::VPSHLDQZrrikz, {0, Unknown}}, + {X86::VPSHLDVDZ128m, {0, Unknown}}, + {X86::VPSHLDVDZ128mb, {0, Unknown}}, + {X86::VPSHLDVDZ128mbk, {0, Unknown}}, + {X86::VPSHLDVDZ128mbkz, {0, Unknown}}, + {X86::VPSHLDVDZ128mk, {0, Unknown}}, + {X86::VPSHLDVDZ128mkz, {0, Unknown}}, + {X86::VPSHLDVDZ128r, {0, Unknown}}, + {X86::VPSHLDVDZ128rk, {0, Unknown}}, + {X86::VPSHLDVDZ128rkz, {0, Unknown}}, + {X86::VPSHLDVDZ256m, {0, Unknown}}, + {X86::VPSHLDVDZ256mb, {0, Unknown}}, + {X86::VPSHLDVDZ256mbk, {0, Unknown}}, + {X86::VPSHLDVDZ256mbkz, {0, Unknown}}, + {X86::VPSHLDVDZ256mk, {0, Unknown}}, + {X86::VPSHLDVDZ256mkz, {0, Unknown}}, + {X86::VPSHLDVDZ256r, {0, Unknown}}, + {X86::VPSHLDVDZ256rk, {0, Unknown}}, + {X86::VPSHLDVDZ256rkz, {0, Unknown}}, + {X86::VPSHLDVDZm, {0, Unknown}}, + {X86::VPSHLDVDZmb, {0, Unknown}}, + {X86::VPSHLDVDZmbk, {0, Unknown}}, + {X86::VPSHLDVDZmbkz, {0, Unknown}}, + {X86::VPSHLDVDZmk, {0, Unknown}}, + {X86::VPSHLDVDZmkz, {0, Unknown}}, + {X86::VPSHLDVDZr, {0, Unknown}}, + {X86::VPSHLDVDZrk, {0, Unknown}}, + {X86::VPSHLDVDZrkz, {0, Unknown}}, + {X86::VPSHLDVQZ128m, {0, Unknown}}, + {X86::VPSHLDVQZ128mb, {0, Unknown}}, + {X86::VPSHLDVQZ128mbk, {0, Unknown}}, + {X86::VPSHLDVQZ128mbkz, {0, Unknown}}, + {X86::VPSHLDVQZ128mk, {0, Unknown}}, + {X86::VPSHLDVQZ128mkz, {0, Unknown}}, + {X86::VPSHLDVQZ128r, {0, Unknown}}, + {X86::VPSHLDVQZ128rk, {0, Unknown}}, + {X86::VPSHLDVQZ128rkz, {0, Unknown}}, + {X86::VPSHLDVQZ256m, {0, Unknown}}, + {X86::VPSHLDVQZ256mb, {0, Unknown}}, + {X86::VPSHLDVQZ256mbk, {0, Unknown}}, + {X86::VPSHLDVQZ256mbkz, {0, Unknown}}, + {X86::VPSHLDVQZ256mk, {0, Unknown}}, + {X86::VPSHLDVQZ256mkz, {0, Unknown}}, + {X86::VPSHLDVQZ256r, {0, Unknown}}, + {X86::VPSHLDVQZ256rk, {0, Unknown}}, + {X86::VPSHLDVQZ256rkz, {0, Unknown}}, + {X86::VPSHLDVQZm, {0, Unknown}}, + {X86::VPSHLDVQZmb, {0, Unknown}}, + {X86::VPSHLDVQZmbk, {0, Unknown}}, + {X86::VPSHLDVQZmbkz, {0, Unknown}}, + {X86::VPSHLDVQZmk, {0, Unknown}}, + {X86::VPSHLDVQZmkz, {0, Unknown}}, + {X86::VPSHLDVQZr, {0, Unknown}}, + {X86::VPSHLDVQZrk, {0, Unknown}}, + {X86::VPSHLDVQZrkz, {0, Unknown}}, + {X86::VPSHLDVWZ128m, {0, Unknown}}, + {X86::VPSHLDVWZ128mk, {0, Unknown}}, + {X86::VPSHLDVWZ128mkz, {0, Unknown}}, + {X86::VPSHLDVWZ128r, {0, Unknown}}, + {X86::VPSHLDVWZ128rk, {0, Unknown}}, + {X86::VPSHLDVWZ128rkz, {0, Unknown}}, + {X86::VPSHLDVWZ256m, {0, Unknown}}, + {X86::VPSHLDVWZ256mk, {0, Unknown}}, + {X86::VPSHLDVWZ256mkz, {0, Unknown}}, + {X86::VPSHLDVWZ256r, {0, Unknown}}, + {X86::VPSHLDVWZ256rk, {0, Unknown}}, + {X86::VPSHLDVWZ256rkz, {0, Unknown}}, + {X86::VPSHLDVWZm, {0, Unknown}}, + {X86::VPSHLDVWZmk, {0, Unknown}}, + {X86::VPSHLDVWZmkz, {0, Unknown}}, + {X86::VPSHLDVWZr, {0, Unknown}}, + {X86::VPSHLDVWZrk, {0, Unknown}}, + {X86::VPSHLDVWZrkz, {0, Unknown}}, + {X86::VPSHLDWZ128rmi, {1, Unknown}}, + {X86::VPSHLDWZ128rmik, {1, Unknown}}, + {X86::VPSHLDWZ128rmikz, {1, Unknown}}, + {X86::VPSHLDWZ128rri, {0, Unknown}}, + {X86::VPSHLDWZ128rrik, {0, Unknown}}, + {X86::VPSHLDWZ128rrikz, {0, Unknown}}, + {X86::VPSHLDWZ256rmi, {0, Unknown}}, + {X86::VPSHLDWZ256rmik, {0, Unknown}}, + {X86::VPSHLDWZ256rmikz, {0, Unknown}}, + {X86::VPSHLDWZ256rri, {0, Unknown}}, + {X86::VPSHLDWZ256rrik, {0, Unknown}}, + {X86::VPSHLDWZ256rrikz, {0, Unknown}}, + {X86::VPSHLDWZrmi, {0, Unknown}}, + {X86::VPSHLDWZrmik, {0, Unknown}}, + {X86::VPSHLDWZrmikz, {0, Unknown}}, + {X86::VPSHLDWZrri, {0, Unknown}}, + {X86::VPSHLDWZrrik, {0, Unknown}}, + {X86::VPSHLDWZrrikz, {0, Unknown}}, + {X86::VPSHLDmr, {0, Unknown}}, + {X86::VPSHLDrm, {0, Unknown}}, + {X86::VPSHLDrr, {0, Unknown}}, + {X86::VPSHLDrr_REV, {0, Unknown}}, + {X86::VPSHLQmr, {0, Unknown}}, + {X86::VPSHLQrm, {0, Unknown}}, + {X86::VPSHLQrr, {0, Unknown}}, + {X86::VPSHLQrr_REV, {0, Unknown}}, + {X86::VPSHLWmr, {0, Unknown}}, + {X86::VPSHLWrm, {0, Unknown}}, + {X86::VPSHLWrr, {0, Unknown}}, + {X86::VPSHLWrr_REV, {0, Unknown}}, + {X86::VPSHRDDZ128rmbi, {1, Unknown}}, + {X86::VPSHRDDZ128rmbik, {1, Unknown}}, + {X86::VPSHRDDZ128rmbikz, {1, Unknown}}, + {X86::VPSHRDDZ128rmi, {1, Unknown}}, + {X86::VPSHRDDZ128rmik, {1, Unknown}}, + {X86::VPSHRDDZ128rmikz, {1, Unknown}}, + {X86::VPSHRDDZ128rri, {0, Unknown}}, + {X86::VPSHRDDZ128rrik, {0, Unknown}}, + {X86::VPSHRDDZ128rrikz, {0, Unknown}}, + {X86::VPSHRDDZ256rmbi, {0, Unknown}}, + {X86::VPSHRDDZ256rmbik, {0, Unknown}}, + {X86::VPSHRDDZ256rmbikz, {0, Unknown}}, + {X86::VPSHRDDZ256rmi, {0, Unknown}}, + {X86::VPSHRDDZ256rmik, {0, Unknown}}, + {X86::VPSHRDDZ256rmikz, {0, Unknown}}, + {X86::VPSHRDDZ256rri, {0, Unknown}}, + {X86::VPSHRDDZ256rrik, {0, Unknown}}, + {X86::VPSHRDDZ256rrikz, {0, Unknown}}, + {X86::VPSHRDDZrmbi, {0, Unknown}}, + {X86::VPSHRDDZrmbik, {0, Unknown}}, + {X86::VPSHRDDZrmbikz, {0, Unknown}}, + {X86::VPSHRDDZrmi, {0, Unknown}}, + {X86::VPSHRDDZrmik, {0, Unknown}}, + {X86::VPSHRDDZrmikz, {0, Unknown}}, + {X86::VPSHRDDZrri, {0, Unknown}}, + {X86::VPSHRDDZrrik, {0, Unknown}}, + {X86::VPSHRDDZrrikz, {0, Unknown}}, + {X86::VPSHRDQZ128rmbi, {1, Unknown}}, + {X86::VPSHRDQZ128rmbik, {1, Unknown}}, + {X86::VPSHRDQZ128rmbikz, {1, Unknown}}, + {X86::VPSHRDQZ128rmi, {1, Unknown}}, + {X86::VPSHRDQZ128rmik, {1, Unknown}}, + {X86::VPSHRDQZ128rmikz, {1, Unknown}}, + {X86::VPSHRDQZ128rri, {0, Unknown}}, + {X86::VPSHRDQZ128rrik, {0, Unknown}}, + {X86::VPSHRDQZ128rrikz, {0, Unknown}}, + {X86::VPSHRDQZ256rmbi, {0, Unknown}}, + {X86::VPSHRDQZ256rmbik, {0, Unknown}}, + {X86::VPSHRDQZ256rmbikz, {0, Unknown}}, + {X86::VPSHRDQZ256rmi, {0, Unknown}}, + {X86::VPSHRDQZ256rmik, {0, Unknown}}, + {X86::VPSHRDQZ256rmikz, {0, Unknown}}, + {X86::VPSHRDQZ256rri, {0, Unknown}}, + {X86::VPSHRDQZ256rrik, {0, Unknown}}, + {X86::VPSHRDQZ256rrikz, {0, Unknown}}, + {X86::VPSHRDQZrmbi, {0, Unknown}}, + {X86::VPSHRDQZrmbik, {0, Unknown}}, + {X86::VPSHRDQZrmbikz, {0, Unknown}}, + {X86::VPSHRDQZrmi, {0, Unknown}}, + {X86::VPSHRDQZrmik, {0, Unknown}}, + {X86::VPSHRDQZrmikz, {0, Unknown}}, + {X86::VPSHRDQZrri, {0, Unknown}}, + {X86::VPSHRDQZrrik, {0, Unknown}}, + {X86::VPSHRDQZrrikz, {0, Unknown}}, + {X86::VPSHRDVDZ128m, {0, Unknown}}, + {X86::VPSHRDVDZ128mb, {0, Unknown}}, + {X86::VPSHRDVDZ128mbk, {0, Unknown}}, + {X86::VPSHRDVDZ128mbkz, {0, Unknown}}, + {X86::VPSHRDVDZ128mk, {0, Unknown}}, + {X86::VPSHRDVDZ128mkz, {0, Unknown}}, + {X86::VPSHRDVDZ128r, {0, Unknown}}, + {X86::VPSHRDVDZ128rk, {0, Unknown}}, + {X86::VPSHRDVDZ128rkz, {0, Unknown}}, + {X86::VPSHRDVDZ256m, {0, Unknown}}, + {X86::VPSHRDVDZ256mb, {0, Unknown}}, + {X86::VPSHRDVDZ256mbk, {0, Unknown}}, + {X86::VPSHRDVDZ256mbkz, {0, Unknown}}, + {X86::VPSHRDVDZ256mk, {0, Unknown}}, + {X86::VPSHRDVDZ256mkz, {0, Unknown}}, + {X86::VPSHRDVDZ256r, {0, Unknown}}, + {X86::VPSHRDVDZ256rk, {0, Unknown}}, + {X86::VPSHRDVDZ256rkz, {0, Unknown}}, + {X86::VPSHRDVDZm, {0, Unknown}}, + {X86::VPSHRDVDZmb, {0, Unknown}}, + {X86::VPSHRDVDZmbk, {0, Unknown}}, + {X86::VPSHRDVDZmbkz, {0, Unknown}}, + {X86::VPSHRDVDZmk, {0, Unknown}}, + {X86::VPSHRDVDZmkz, {0, Unknown}}, + {X86::VPSHRDVDZr, {0, Unknown}}, + {X86::VPSHRDVDZrk, {0, Unknown}}, + {X86::VPSHRDVDZrkz, {0, Unknown}}, + {X86::VPSHRDVQZ128m, {0, Unknown}}, + {X86::VPSHRDVQZ128mb, {0, Unknown}}, + {X86::VPSHRDVQZ128mbk, {0, Unknown}}, + {X86::VPSHRDVQZ128mbkz, {0, Unknown}}, + {X86::VPSHRDVQZ128mk, {0, Unknown}}, + {X86::VPSHRDVQZ128mkz, {0, Unknown}}, + {X86::VPSHRDVQZ128r, {0, Unknown}}, + {X86::VPSHRDVQZ128rk, {0, Unknown}}, + {X86::VPSHRDVQZ128rkz, {0, Unknown}}, + {X86::VPSHRDVQZ256m, {0, Unknown}}, + {X86::VPSHRDVQZ256mb, {0, Unknown}}, + {X86::VPSHRDVQZ256mbk, {0, Unknown}}, + {X86::VPSHRDVQZ256mbkz, {0, Unknown}}, + {X86::VPSHRDVQZ256mk, {0, Unknown}}, + {X86::VPSHRDVQZ256mkz, {0, Unknown}}, + {X86::VPSHRDVQZ256r, {0, Unknown}}, + {X86::VPSHRDVQZ256rk, {0, Unknown}}, + {X86::VPSHRDVQZ256rkz, {0, Unknown}}, + {X86::VPSHRDVQZm, {0, Unknown}}, + {X86::VPSHRDVQZmb, {0, Unknown}}, + {X86::VPSHRDVQZmbk, {0, Unknown}}, + {X86::VPSHRDVQZmbkz, {0, Unknown}}, + {X86::VPSHRDVQZmk, {0, Unknown}}, + {X86::VPSHRDVQZmkz, {0, Unknown}}, + {X86::VPSHRDVQZr, {0, Unknown}}, + {X86::VPSHRDVQZrk, {0, Unknown}}, + {X86::VPSHRDVQZrkz, {0, Unknown}}, + {X86::VPSHRDVWZ128m, {0, Unknown}}, + {X86::VPSHRDVWZ128mk, {0, Unknown}}, + {X86::VPSHRDVWZ128mkz, {0, Unknown}}, + {X86::VPSHRDVWZ128r, {0, Unknown}}, + {X86::VPSHRDVWZ128rk, {0, Unknown}}, + {X86::VPSHRDVWZ128rkz, {0, Unknown}}, + {X86::VPSHRDVWZ256m, {0, Unknown}}, + {X86::VPSHRDVWZ256mk, {0, Unknown}}, + {X86::VPSHRDVWZ256mkz, {0, Unknown}}, + {X86::VPSHRDVWZ256r, {0, Unknown}}, + {X86::VPSHRDVWZ256rk, {0, Unknown}}, + {X86::VPSHRDVWZ256rkz, {0, Unknown}}, + {X86::VPSHRDVWZm, {0, Unknown}}, + {X86::VPSHRDVWZmk, {0, Unknown}}, + {X86::VPSHRDVWZmkz, {0, Unknown}}, + {X86::VPSHRDVWZr, {0, Unknown}}, + {X86::VPSHRDVWZrk, {0, Unknown}}, + {X86::VPSHRDVWZrkz, {0, Unknown}}, + {X86::VPSHRDWZ128rmi, {1, Unknown}}, + {X86::VPSHRDWZ128rmik, {1, Unknown}}, + {X86::VPSHRDWZ128rmikz, {1, Unknown}}, + {X86::VPSHRDWZ128rri, {0, Unknown}}, + {X86::VPSHRDWZ128rrik, {0, Unknown}}, + {X86::VPSHRDWZ128rrikz, {0, Unknown}}, + {X86::VPSHRDWZ256rmi, {0, Unknown}}, + {X86::VPSHRDWZ256rmik, {0, Unknown}}, + {X86::VPSHRDWZ256rmikz, {0, Unknown}}, + {X86::VPSHRDWZ256rri, {0, Unknown}}, + {X86::VPSHRDWZ256rrik, {0, Unknown}}, + {X86::VPSHRDWZ256rrikz, {0, Unknown}}, + {X86::VPSHRDWZrmi, {0, Unknown}}, + {X86::VPSHRDWZrmik, {0, Unknown}}, + {X86::VPSHRDWZrmikz, {0, Unknown}}, + {X86::VPSHRDWZrri, {0, Unknown}}, + {X86::VPSHRDWZrrik, {0, Unknown}}, + {X86::VPSHRDWZrrikz, {0, Unknown}}, + {X86::VPSHUFBITQMBZ128rm, {1, Unknown}}, + {X86::VPSHUFBITQMBZ128rmk, {1, Unknown}}, + {X86::VPSHUFBITQMBZ128rr, {0, Unknown}}, + {X86::VPSHUFBITQMBZ128rrk, {0, Unknown}}, + {X86::VPSHUFBITQMBZ256rm, {0, Unknown}}, + {X86::VPSHUFBITQMBZ256rmk, {0, Unknown}}, + {X86::VPSHUFBITQMBZ256rr, {0, Unknown}}, + {X86::VPSHUFBITQMBZ256rrk, {0, Unknown}}, + {X86::VPSHUFBITQMBZrm, {0, Unknown}}, + {X86::VPSHUFBITQMBZrmk, {0, Unknown}}, + {X86::VPSHUFBITQMBZrr, {0, Unknown}}, + {X86::VPSHUFBITQMBZrrk, {0, Unknown}}, + {X86::VPSHUFBYrm, {0, Unknown}}, + {X86::VPSHUFBYrr, {0, Unknown}}, + {X86::VPSHUFBZ128rm, {1, Unknown}}, + {X86::VPSHUFBZ128rmk, {1, Unknown}}, + {X86::VPSHUFBZ128rmkz, {1, Unknown}}, + {X86::VPSHUFBZ128rr, {0, Unknown}}, + {X86::VPSHUFBZ128rrk, {0, Unknown}}, + {X86::VPSHUFBZ128rrkz, {0, Unknown}}, + {X86::VPSHUFBZ256rm, {0, Unknown}}, + {X86::VPSHUFBZ256rmk, {0, Unknown}}, + {X86::VPSHUFBZ256rmkz, {0, Unknown}}, + {X86::VPSHUFBZ256rr, {0, Unknown}}, + {X86::VPSHUFBZ256rrk, {0, Unknown}}, + {X86::VPSHUFBZ256rrkz, {0, Unknown}}, + {X86::VPSHUFBZrm, {0, Unknown}}, + {X86::VPSHUFBZrmk, {0, Unknown}}, + {X86::VPSHUFBZrmkz, {0, Unknown}}, + {X86::VPSHUFBZrr, {0, Unknown}}, + {X86::VPSHUFBZrrk, {0, Unknown}}, + {X86::VPSHUFBZrrkz, {0, Unknown}}, + {X86::VPSHUFBrm, {0, Unknown}}, + {X86::VPSHUFBrr, {0, Unknown}}, + {X86::VPSHUFDYmi, {0, Unknown}}, + {X86::VPSHUFDYri, {0, Unknown}}, + {X86::VPSHUFDZ128mbi, {0, Unknown}}, + {X86::VPSHUFDZ128mbik, {0, Unknown}}, + {X86::VPSHUFDZ128mbikz, {0, Unknown}}, + {X86::VPSHUFDZ128mi, {1, Unknown}}, + {X86::VPSHUFDZ128mik, {1, Unknown}}, + {X86::VPSHUFDZ128mikz, {1, Unknown}}, + {X86::VPSHUFDZ128ri, {0, Unknown}}, + {X86::VPSHUFDZ128rik, {0, Unknown}}, + {X86::VPSHUFDZ128rikz, {0, Unknown}}, + {X86::VPSHUFDZ256mbi, {0, Unknown}}, + {X86::VPSHUFDZ256mbik, {0, Unknown}}, + {X86::VPSHUFDZ256mbikz, {0, Unknown}}, + {X86::VPSHUFDZ256mi, {0, Unknown}}, + {X86::VPSHUFDZ256mik, {0, Unknown}}, + {X86::VPSHUFDZ256mikz, {0, Unknown}}, + {X86::VPSHUFDZ256ri, {0, Unknown}}, + {X86::VPSHUFDZ256rik, {0, Unknown}}, + {X86::VPSHUFDZ256rikz, {0, Unknown}}, + {X86::VPSHUFDZmbi, {0, Unknown}}, + {X86::VPSHUFDZmbik, {0, Unknown}}, + {X86::VPSHUFDZmbikz, {0, Unknown}}, + {X86::VPSHUFDZmi, {0, Unknown}}, + {X86::VPSHUFDZmik, {0, Unknown}}, + {X86::VPSHUFDZmikz, {0, Unknown}}, + {X86::VPSHUFDZri, {0, Unknown}}, + {X86::VPSHUFDZrik, {0, Unknown}}, + {X86::VPSHUFDZrikz, {0, Unknown}}, + {X86::VPSHUFDmi, {0, Unknown}}, + {X86::VPSHUFDri, {0, Unknown}}, + {X86::VPSHUFHWYmi, {0, Unknown}}, + {X86::VPSHUFHWYri, {0, Unknown}}, + {X86::VPSHUFHWZ128mi, {1, Unknown}}, + {X86::VPSHUFHWZ128mik, {1, Unknown}}, + {X86::VPSHUFHWZ128mikz, {1, Unknown}}, + {X86::VPSHUFHWZ128ri, {0, Unknown}}, + {X86::VPSHUFHWZ128rik, {0, Unknown}}, + {X86::VPSHUFHWZ128rikz, {0, Unknown}}, + {X86::VPSHUFHWZ256mi, {0, Unknown}}, + {X86::VPSHUFHWZ256mik, {0, Unknown}}, + {X86::VPSHUFHWZ256mikz, {0, Unknown}}, + {X86::VPSHUFHWZ256ri, {0, Unknown}}, + {X86::VPSHUFHWZ256rik, {0, Unknown}}, + {X86::VPSHUFHWZ256rikz, {0, Unknown}}, + {X86::VPSHUFHWZmi, {0, Unknown}}, + {X86::VPSHUFHWZmik, {0, Unknown}}, + {X86::VPSHUFHWZmikz, {0, Unknown}}, + {X86::VPSHUFHWZri, {0, Unknown}}, + {X86::VPSHUFHWZrik, {0, Unknown}}, + {X86::VPSHUFHWZrikz, {0, Unknown}}, + {X86::VPSHUFHWmi, {0, Unknown}}, + {X86::VPSHUFHWri, {0, Unknown}}, + {X86::VPSHUFLWYmi, {0, Unknown}}, + {X86::VPSHUFLWYri, {0, Unknown}}, + {X86::VPSHUFLWZ128mi, {1, Unknown}}, + {X86::VPSHUFLWZ128mik, {1, Unknown}}, + {X86::VPSHUFLWZ128mikz, {1, Unknown}}, + {X86::VPSHUFLWZ128ri, {0, Unknown}}, + {X86::VPSHUFLWZ128rik, {0, Unknown}}, + {X86::VPSHUFLWZ128rikz, {0, Unknown}}, + {X86::VPSHUFLWZ256mi, {0, Unknown}}, + {X86::VPSHUFLWZ256mik, {0, Unknown}}, + {X86::VPSHUFLWZ256mikz, {0, Unknown}}, + {X86::VPSHUFLWZ256ri, {0, Unknown}}, + {X86::VPSHUFLWZ256rik, {0, Unknown}}, + {X86::VPSHUFLWZ256rikz, {0, Unknown}}, + {X86::VPSHUFLWZmi, {0, Unknown}}, + {X86::VPSHUFLWZmik, {0, Unknown}}, + {X86::VPSHUFLWZmikz, {0, Unknown}}, + {X86::VPSHUFLWZri, {0, Unknown}}, + {X86::VPSHUFLWZrik, {0, Unknown}}, + {X86::VPSHUFLWZrikz, {0, Unknown}}, + {X86::VPSHUFLWmi, {0, Unknown}}, + {X86::VPSHUFLWri, {0, Unknown}}, + {X86::VPSIGNBYrm, {0, Unknown}}, + {X86::VPSIGNBYrr, {0, Unknown}}, + {X86::VPSIGNBrm, {0, Unknown}}, + {X86::VPSIGNBrr, {0, Unknown}}, + {X86::VPSIGNDYrm, {0, Unknown}}, + {X86::VPSIGNDYrr, {0, Unknown}}, + {X86::VPSIGNDrm, {0, Unknown}}, + {X86::VPSIGNDrr, {0, Unknown}}, + {X86::VPSIGNWYrm, {0, Unknown}}, + {X86::VPSIGNWYrr, {0, Unknown}}, + {X86::VPSIGNWrm, {0, Unknown}}, + {X86::VPSIGNWrr, {0, Unknown}}, + {X86::VPSLLDQYri, {0, Unknown}}, + {X86::VPSLLDQZ128rm, {1, Unknown}}, + {X86::VPSLLDQZ128rr, {0, Unknown}}, + {X86::VPSLLDQZ256rm, {0, Unknown}}, + {X86::VPSLLDQZ256rr, {0, Unknown}}, + {X86::VPSLLDQZrm, {0, Unknown}}, + {X86::VPSLLDQZrr, {0, Unknown}}, + {X86::VPSLLDQri, {0, Unknown}}, + {X86::VPSLLDYri, {0, Unknown}}, + {X86::VPSLLDYrm, {0, Unknown}}, + {X86::VPSLLDYrr, {0, Unknown}}, + {X86::VPSLLDZ128mbi, {0, Unknown}}, + {X86::VPSLLDZ128mbik, {0, Unknown}}, + {X86::VPSLLDZ128mbikz, {0, Unknown}}, + {X86::VPSLLDZ128mi, {1, Unknown}}, + {X86::VPSLLDZ128mik, {1, Unknown}}, + {X86::VPSLLDZ128mikz, {1, Unknown}}, + {X86::VPSLLDZ128ri, {0, Unknown}}, + {X86::VPSLLDZ128rik, {0, Unknown}}, + {X86::VPSLLDZ128rikz, {0, Unknown}}, + {X86::VPSLLDZ128rm, {1, Unknown}}, + {X86::VPSLLDZ128rmk, {1, Unknown}}, + {X86::VPSLLDZ128rmkz, {1, Unknown}}, + {X86::VPSLLDZ128rr, {0, Unknown}}, + {X86::VPSLLDZ128rrk, {0, Unknown}}, + {X86::VPSLLDZ128rrkz, {0, Unknown}}, + {X86::VPSLLDZ256mbi, {0, Unknown}}, + {X86::VPSLLDZ256mbik, {0, Unknown}}, + {X86::VPSLLDZ256mbikz, {0, Unknown}}, + {X86::VPSLLDZ256mi, {0, Unknown}}, + {X86::VPSLLDZ256mik, {0, Unknown}}, + {X86::VPSLLDZ256mikz, {0, Unknown}}, + {X86::VPSLLDZ256ri, {0, Unknown}}, + {X86::VPSLLDZ256rik, {0, Unknown}}, + {X86::VPSLLDZ256rikz, {0, Unknown}}, + {X86::VPSLLDZ256rm, {0, Unknown}}, + {X86::VPSLLDZ256rmk, {0, Unknown}}, + {X86::VPSLLDZ256rmkz, {0, Unknown}}, + {X86::VPSLLDZ256rr, {0, Unknown}}, + {X86::VPSLLDZ256rrk, {0, Unknown}}, + {X86::VPSLLDZ256rrkz, {0, Unknown}}, + {X86::VPSLLDZmbi, {0, Unknown}}, + {X86::VPSLLDZmbik, {0, Unknown}}, + {X86::VPSLLDZmbikz, {0, Unknown}}, + {X86::VPSLLDZmi, {0, Unknown}}, + {X86::VPSLLDZmik, {0, Unknown}}, + {X86::VPSLLDZmikz, {0, Unknown}}, + {X86::VPSLLDZri, {0, Unknown}}, + {X86::VPSLLDZrik, {0, Unknown}}, + {X86::VPSLLDZrikz, {0, Unknown}}, + {X86::VPSLLDZrm, {0, Unknown}}, + {X86::VPSLLDZrmk, {0, Unknown}}, + {X86::VPSLLDZrmkz, {0, Unknown}}, + {X86::VPSLLDZrr, {0, Unknown}}, + {X86::VPSLLDZrrk, {0, Unknown}}, + {X86::VPSLLDZrrkz, {0, Unknown}}, + {X86::VPSLLDri, {0, Unknown}}, + {X86::VPSLLDrm, {0, Unknown}}, + {X86::VPSLLDrr, {0, Unknown}}, + {X86::VPSLLQYri, {0, Unknown}}, + {X86::VPSLLQYrm, {0, Unknown}}, + {X86::VPSLLQYrr, {0, Unknown}}, + {X86::VPSLLQZ128mbi, {0, Unknown}}, + {X86::VPSLLQZ128mbik, {0, Unknown}}, + {X86::VPSLLQZ128mbikz, {0, Unknown}}, + {X86::VPSLLQZ128mi, {1, Unknown}}, + {X86::VPSLLQZ128mik, {1, Unknown}}, + {X86::VPSLLQZ128mikz, {1, Unknown}}, + {X86::VPSLLQZ128ri, {0, Unknown}}, + {X86::VPSLLQZ128rik, {0, Unknown}}, + {X86::VPSLLQZ128rikz, {0, Unknown}}, + {X86::VPSLLQZ128rm, {1, Unknown}}, + {X86::VPSLLQZ128rmk, {1, Unknown}}, + {X86::VPSLLQZ128rmkz, {1, Unknown}}, + {X86::VPSLLQZ128rr, {0, Unknown}}, + {X86::VPSLLQZ128rrk, {0, Unknown}}, + {X86::VPSLLQZ128rrkz, {0, Unknown}}, + {X86::VPSLLQZ256mbi, {0, Unknown}}, + {X86::VPSLLQZ256mbik, {0, Unknown}}, + {X86::VPSLLQZ256mbikz, {0, Unknown}}, + {X86::VPSLLQZ256mi, {0, Unknown}}, + {X86::VPSLLQZ256mik, {0, Unknown}}, + {X86::VPSLLQZ256mikz, {0, Unknown}}, + {X86::VPSLLQZ256ri, {0, Unknown}}, + {X86::VPSLLQZ256rik, {0, Unknown}}, + {X86::VPSLLQZ256rikz, {0, Unknown}}, + {X86::VPSLLQZ256rm, {0, Unknown}}, + {X86::VPSLLQZ256rmk, {0, Unknown}}, + {X86::VPSLLQZ256rmkz, {0, Unknown}}, + {X86::VPSLLQZ256rr, {0, Unknown}}, + {X86::VPSLLQZ256rrk, {0, Unknown}}, + {X86::VPSLLQZ256rrkz, {0, Unknown}}, + {X86::VPSLLQZmbi, {0, Unknown}}, + {X86::VPSLLQZmbik, {0, Unknown}}, + {X86::VPSLLQZmbikz, {0, Unknown}}, + {X86::VPSLLQZmi, {0, Unknown}}, + {X86::VPSLLQZmik, {0, Unknown}}, + {X86::VPSLLQZmikz, {0, Unknown}}, + {X86::VPSLLQZri, {0, Unknown}}, + {X86::VPSLLQZrik, {0, Unknown}}, + {X86::VPSLLQZrikz, {0, Unknown}}, + {X86::VPSLLQZrm, {0, Unknown}}, + {X86::VPSLLQZrmk, {0, Unknown}}, + {X86::VPSLLQZrmkz, {0, Unknown}}, + {X86::VPSLLQZrr, {0, Unknown}}, + {X86::VPSLLQZrrk, {0, Unknown}}, + {X86::VPSLLQZrrkz, {0, Unknown}}, + {X86::VPSLLQri, {0, Unknown}}, + {X86::VPSLLQrm, {0, Unknown}}, + {X86::VPSLLQrr, {0, Unknown}}, + {X86::VPSLLVDYrm, {0, Unknown}}, + {X86::VPSLLVDYrr, {0, Unknown}}, + {X86::VPSLLVDZ128rm, {1, Unknown}}, + {X86::VPSLLVDZ128rmb, {1, Unknown}}, + {X86::VPSLLVDZ128rmbk, {1, Unknown}}, + {X86::VPSLLVDZ128rmbkz, {1, Unknown}}, + {X86::VPSLLVDZ128rmk, {1, Unknown}}, + {X86::VPSLLVDZ128rmkz, {1, Unknown}}, + {X86::VPSLLVDZ128rr, {0, Unknown}}, + {X86::VPSLLVDZ128rrk, {0, Unknown}}, + {X86::VPSLLVDZ128rrkz, {0, Unknown}}, + {X86::VPSLLVDZ256rm, {0, Unknown}}, + {X86::VPSLLVDZ256rmb, {0, Unknown}}, + {X86::VPSLLVDZ256rmbk, {0, Unknown}}, + {X86::VPSLLVDZ256rmbkz, {0, Unknown}}, + {X86::VPSLLVDZ256rmk, {0, Unknown}}, + {X86::VPSLLVDZ256rmkz, {0, Unknown}}, + {X86::VPSLLVDZ256rr, {0, Unknown}}, + {X86::VPSLLVDZ256rrk, {0, Unknown}}, + {X86::VPSLLVDZ256rrkz, {0, Unknown}}, + {X86::VPSLLVDZrm, {0, Unknown}}, + {X86::VPSLLVDZrmb, {0, Unknown}}, + {X86::VPSLLVDZrmbk, {0, Unknown}}, + {X86::VPSLLVDZrmbkz, {0, Unknown}}, + {X86::VPSLLVDZrmk, {0, Unknown}}, + {X86::VPSLLVDZrmkz, {0, Unknown}}, + {X86::VPSLLVDZrr, {0, Unknown}}, + {X86::VPSLLVDZrrk, {0, Unknown}}, + {X86::VPSLLVDZrrkz, {0, Unknown}}, + {X86::VPSLLVDrm, {0, Unknown}}, + {X86::VPSLLVDrr, {0, Unknown}}, + {X86::VPSLLVQYrm, {0, Unknown}}, + {X86::VPSLLVQYrr, {0, Unknown}}, + {X86::VPSLLVQZ128rm, {1, Unknown}}, + {X86::VPSLLVQZ128rmb, {1, Unknown}}, + {X86::VPSLLVQZ128rmbk, {1, Unknown}}, + {X86::VPSLLVQZ128rmbkz, {1, Unknown}}, + {X86::VPSLLVQZ128rmk, {1, Unknown}}, + {X86::VPSLLVQZ128rmkz, {1, Unknown}}, + {X86::VPSLLVQZ128rr, {0, Unknown}}, + {X86::VPSLLVQZ128rrk, {0, Unknown}}, + {X86::VPSLLVQZ128rrkz, {0, Unknown}}, + {X86::VPSLLVQZ256rm, {0, Unknown}}, + {X86::VPSLLVQZ256rmb, {0, Unknown}}, + {X86::VPSLLVQZ256rmbk, {0, Unknown}}, + {X86::VPSLLVQZ256rmbkz, {0, Unknown}}, + {X86::VPSLLVQZ256rmk, {0, Unknown}}, + {X86::VPSLLVQZ256rmkz, {0, Unknown}}, + {X86::VPSLLVQZ256rr, {0, Unknown}}, + {X86::VPSLLVQZ256rrk, {0, Unknown}}, + {X86::VPSLLVQZ256rrkz, {0, Unknown}}, + {X86::VPSLLVQZrm, {0, Unknown}}, + {X86::VPSLLVQZrmb, {0, Unknown}}, + {X86::VPSLLVQZrmbk, {0, Unknown}}, + {X86::VPSLLVQZrmbkz, {0, Unknown}}, + {X86::VPSLLVQZrmk, {0, Unknown}}, + {X86::VPSLLVQZrmkz, {0, Unknown}}, + {X86::VPSLLVQZrr, {0, Unknown}}, + {X86::VPSLLVQZrrk, {0, Unknown}}, + {X86::VPSLLVQZrrkz, {0, Unknown}}, + {X86::VPSLLVQrm, {0, Unknown}}, + {X86::VPSLLVQrr, {0, Unknown}}, + {X86::VPSLLVWZ128rm, {1, Unknown}}, + {X86::VPSLLVWZ128rmk, {1, Unknown}}, + {X86::VPSLLVWZ128rmkz, {1, Unknown}}, + {X86::VPSLLVWZ128rr, {0, Unknown}}, + {X86::VPSLLVWZ128rrk, {0, Unknown}}, + {X86::VPSLLVWZ128rrkz, {0, Unknown}}, + {X86::VPSLLVWZ256rm, {0, Unknown}}, + {X86::VPSLLVWZ256rmk, {0, Unknown}}, + {X86::VPSLLVWZ256rmkz, {0, Unknown}}, + {X86::VPSLLVWZ256rr, {0, Unknown}}, + {X86::VPSLLVWZ256rrk, {0, Unknown}}, + {X86::VPSLLVWZ256rrkz, {0, Unknown}}, + {X86::VPSLLVWZrm, {0, Unknown}}, + {X86::VPSLLVWZrmk, {0, Unknown}}, + {X86::VPSLLVWZrmkz, {0, Unknown}}, + {X86::VPSLLVWZrr, {0, Unknown}}, + {X86::VPSLLVWZrrk, {0, Unknown}}, + {X86::VPSLLVWZrrkz, {0, Unknown}}, + {X86::VPSLLWYri, {0, Unknown}}, + {X86::VPSLLWYrm, {0, Unknown}}, + {X86::VPSLLWYrr, {0, Unknown}}, + {X86::VPSLLWZ128mi, {1, Unknown}}, + {X86::VPSLLWZ128mik, {1, Unknown}}, + {X86::VPSLLWZ128mikz, {1, Unknown}}, + {X86::VPSLLWZ128ri, {0, Unknown}}, + {X86::VPSLLWZ128rik, {0, Unknown}}, + {X86::VPSLLWZ128rikz, {0, Unknown}}, + {X86::VPSLLWZ128rm, {1, Unknown}}, + {X86::VPSLLWZ128rmk, {1, Unknown}}, + {X86::VPSLLWZ128rmkz, {1, Unknown}}, + {X86::VPSLLWZ128rr, {0, Unknown}}, + {X86::VPSLLWZ128rrk, {0, Unknown}}, + {X86::VPSLLWZ128rrkz, {0, Unknown}}, + {X86::VPSLLWZ256mi, {0, Unknown}}, + {X86::VPSLLWZ256mik, {0, Unknown}}, + {X86::VPSLLWZ256mikz, {0, Unknown}}, + {X86::VPSLLWZ256ri, {0, Unknown}}, + {X86::VPSLLWZ256rik, {0, Unknown}}, + {X86::VPSLLWZ256rikz, {0, Unknown}}, + {X86::VPSLLWZ256rm, {0, Unknown}}, + {X86::VPSLLWZ256rmk, {0, Unknown}}, + {X86::VPSLLWZ256rmkz, {0, Unknown}}, + {X86::VPSLLWZ256rr, {0, Unknown}}, + {X86::VPSLLWZ256rrk, {0, Unknown}}, + {X86::VPSLLWZ256rrkz, {0, Unknown}}, + {X86::VPSLLWZmi, {0, Unknown}}, + {X86::VPSLLWZmik, {0, Unknown}}, + {X86::VPSLLWZmikz, {0, Unknown}}, + {X86::VPSLLWZri, {0, Unknown}}, + {X86::VPSLLWZrik, {0, Unknown}}, + {X86::VPSLLWZrikz, {0, Unknown}}, + {X86::VPSLLWZrm, {0, Unknown}}, + {X86::VPSLLWZrmk, {0, Unknown}}, + {X86::VPSLLWZrmkz, {0, Unknown}}, + {X86::VPSLLWZrr, {0, Unknown}}, + {X86::VPSLLWZrrk, {0, Unknown}}, + {X86::VPSLLWZrrkz, {0, Unknown}}, + {X86::VPSLLWri, {0, Unknown}}, + {X86::VPSLLWrm, {0, Unknown}}, + {X86::VPSLLWrr, {0, Unknown}}, + {X86::VPSRADYri, {0, Unknown}}, + {X86::VPSRADYrm, {0, Unknown}}, + {X86::VPSRADYrr, {0, Unknown}}, + {X86::VPSRADZ128mbi, {0, Unknown}}, + {X86::VPSRADZ128mbik, {0, Unknown}}, + {X86::VPSRADZ128mbikz, {0, Unknown}}, + {X86::VPSRADZ128mi, {1, Unknown}}, + {X86::VPSRADZ128mik, {1, Unknown}}, + {X86::VPSRADZ128mikz, {1, Unknown}}, + {X86::VPSRADZ128ri, {0, Unknown}}, + {X86::VPSRADZ128rik, {0, Unknown}}, + {X86::VPSRADZ128rikz, {0, Unknown}}, + {X86::VPSRADZ128rm, {1, Unknown}}, + {X86::VPSRADZ128rmk, {1, Unknown}}, + {X86::VPSRADZ128rmkz, {1, Unknown}}, + {X86::VPSRADZ128rr, {0, Unknown}}, + {X86::VPSRADZ128rrk, {0, Unknown}}, + {X86::VPSRADZ128rrkz, {0, Unknown}}, + {X86::VPSRADZ256mbi, {0, Unknown}}, + {X86::VPSRADZ256mbik, {0, Unknown}}, + {X86::VPSRADZ256mbikz, {0, Unknown}}, + {X86::VPSRADZ256mi, {0, Unknown}}, + {X86::VPSRADZ256mik, {0, Unknown}}, + {X86::VPSRADZ256mikz, {0, Unknown}}, + {X86::VPSRADZ256ri, {0, Unknown}}, + {X86::VPSRADZ256rik, {0, Unknown}}, + {X86::VPSRADZ256rikz, {0, Unknown}}, + {X86::VPSRADZ256rm, {0, Unknown}}, + {X86::VPSRADZ256rmk, {0, Unknown}}, + {X86::VPSRADZ256rmkz, {0, Unknown}}, + {X86::VPSRADZ256rr, {0, Unknown}}, + {X86::VPSRADZ256rrk, {0, Unknown}}, + {X86::VPSRADZ256rrkz, {0, Unknown}}, + {X86::VPSRADZmbi, {0, Unknown}}, + {X86::VPSRADZmbik, {0, Unknown}}, + {X86::VPSRADZmbikz, {0, Unknown}}, + {X86::VPSRADZmi, {0, Unknown}}, + {X86::VPSRADZmik, {0, Unknown}}, + {X86::VPSRADZmikz, {0, Unknown}}, + {X86::VPSRADZri, {0, Unknown}}, + {X86::VPSRADZrik, {0, Unknown}}, + {X86::VPSRADZrikz, {0, Unknown}}, + {X86::VPSRADZrm, {0, Unknown}}, + {X86::VPSRADZrmk, {0, Unknown}}, + {X86::VPSRADZrmkz, {0, Unknown}}, + {X86::VPSRADZrr, {0, Unknown}}, + {X86::VPSRADZrrk, {0, Unknown}}, + {X86::VPSRADZrrkz, {0, Unknown}}, + {X86::VPSRADri, {0, Unknown}}, + {X86::VPSRADrm, {0, Unknown}}, + {X86::VPSRADrr, {0, Unknown}}, + {X86::VPSRAQZ128mbi, {0, Unknown}}, + {X86::VPSRAQZ128mbik, {0, Unknown}}, + {X86::VPSRAQZ128mbikz, {0, Unknown}}, + {X86::VPSRAQZ128mi, {1, Unknown}}, + {X86::VPSRAQZ128mik, {1, Unknown}}, + {X86::VPSRAQZ128mikz, {1, Unknown}}, + {X86::VPSRAQZ128ri, {0, Unknown}}, + {X86::VPSRAQZ128rik, {0, Unknown}}, + {X86::VPSRAQZ128rikz, {0, Unknown}}, + {X86::VPSRAQZ128rm, {1, Unknown}}, + {X86::VPSRAQZ128rmk, {1, Unknown}}, + {X86::VPSRAQZ128rmkz, {1, Unknown}}, + {X86::VPSRAQZ128rr, {0, Unknown}}, + {X86::VPSRAQZ128rrk, {0, Unknown}}, + {X86::VPSRAQZ128rrkz, {0, Unknown}}, + {X86::VPSRAQZ256mbi, {0, Unknown}}, + {X86::VPSRAQZ256mbik, {0, Unknown}}, + {X86::VPSRAQZ256mbikz, {0, Unknown}}, + {X86::VPSRAQZ256mi, {0, Unknown}}, + {X86::VPSRAQZ256mik, {0, Unknown}}, + {X86::VPSRAQZ256mikz, {0, Unknown}}, + {X86::VPSRAQZ256ri, {0, Unknown}}, + {X86::VPSRAQZ256rik, {0, Unknown}}, + {X86::VPSRAQZ256rikz, {0, Unknown}}, + {X86::VPSRAQZ256rm, {0, Unknown}}, + {X86::VPSRAQZ256rmk, {0, Unknown}}, + {X86::VPSRAQZ256rmkz, {0, Unknown}}, + {X86::VPSRAQZ256rr, {0, Unknown}}, + {X86::VPSRAQZ256rrk, {0, Unknown}}, + {X86::VPSRAQZ256rrkz, {0, Unknown}}, + {X86::VPSRAQZmbi, {0, Unknown}}, + {X86::VPSRAQZmbik, {0, Unknown}}, + {X86::VPSRAQZmbikz, {0, Unknown}}, + {X86::VPSRAQZmi, {0, Unknown}}, + {X86::VPSRAQZmik, {0, Unknown}}, + {X86::VPSRAQZmikz, {0, Unknown}}, + {X86::VPSRAQZri, {0, Unknown}}, + {X86::VPSRAQZrik, {0, Unknown}}, + {X86::VPSRAQZrikz, {0, Unknown}}, + {X86::VPSRAQZrm, {0, Unknown}}, + {X86::VPSRAQZrmk, {0, Unknown}}, + {X86::VPSRAQZrmkz, {0, Unknown}}, + {X86::VPSRAQZrr, {0, Unknown}}, + {X86::VPSRAQZrrk, {0, Unknown}}, + {X86::VPSRAQZrrkz, {0, Unknown}}, + {X86::VPSRAVDYrm, {0, Unknown}}, + {X86::VPSRAVDYrr, {0, Unknown}}, + {X86::VPSRAVDZ128rm, {1, Unknown}}, + {X86::VPSRAVDZ128rmb, {1, Unknown}}, + {X86::VPSRAVDZ128rmbk, {1, Unknown}}, + {X86::VPSRAVDZ128rmbkz, {1, Unknown}}, + {X86::VPSRAVDZ128rmk, {1, Unknown}}, + {X86::VPSRAVDZ128rmkz, {1, Unknown}}, + {X86::VPSRAVDZ128rr, {0, Unknown}}, + {X86::VPSRAVDZ128rrk, {0, Unknown}}, + {X86::VPSRAVDZ128rrkz, {0, Unknown}}, + {X86::VPSRAVDZ256rm, {0, Unknown}}, + {X86::VPSRAVDZ256rmb, {0, Unknown}}, + {X86::VPSRAVDZ256rmbk, {0, Unknown}}, + {X86::VPSRAVDZ256rmbkz, {0, Unknown}}, + {X86::VPSRAVDZ256rmk, {0, Unknown}}, + {X86::VPSRAVDZ256rmkz, {0, Unknown}}, + {X86::VPSRAVDZ256rr, {0, Unknown}}, + {X86::VPSRAVDZ256rrk, {0, Unknown}}, + {X86::VPSRAVDZ256rrkz, {0, Unknown}}, + {X86::VPSRAVDZrm, {0, Unknown}}, + {X86::VPSRAVDZrmb, {0, Unknown}}, + {X86::VPSRAVDZrmbk, {0, Unknown}}, + {X86::VPSRAVDZrmbkz, {0, Unknown}}, + {X86::VPSRAVDZrmk, {0, Unknown}}, + {X86::VPSRAVDZrmkz, {0, Unknown}}, + {X86::VPSRAVDZrr, {0, Unknown}}, + {X86::VPSRAVDZrrk, {0, Unknown}}, + {X86::VPSRAVDZrrkz, {0, Unknown}}, + {X86::VPSRAVDrm, {0, Unknown}}, + {X86::VPSRAVDrr, {0, Unknown}}, + {X86::VPSRAVQZ128rm, {1, Unknown}}, + {X86::VPSRAVQZ128rmb, {1, Unknown}}, + {X86::VPSRAVQZ128rmbk, {1, Unknown}}, + {X86::VPSRAVQZ128rmbkz, {1, Unknown}}, + {X86::VPSRAVQZ128rmk, {1, Unknown}}, + {X86::VPSRAVQZ128rmkz, {1, Unknown}}, + {X86::VPSRAVQZ128rr, {0, Unknown}}, + {X86::VPSRAVQZ128rrk, {0, Unknown}}, + {X86::VPSRAVQZ128rrkz, {0, Unknown}}, + {X86::VPSRAVQZ256rm, {0, Unknown}}, + {X86::VPSRAVQZ256rmb, {0, Unknown}}, + {X86::VPSRAVQZ256rmbk, {0, Unknown}}, + {X86::VPSRAVQZ256rmbkz, {0, Unknown}}, + {X86::VPSRAVQZ256rmk, {0, Unknown}}, + {X86::VPSRAVQZ256rmkz, {0, Unknown}}, + {X86::VPSRAVQZ256rr, {0, Unknown}}, + {X86::VPSRAVQZ256rrk, {0, Unknown}}, + {X86::VPSRAVQZ256rrkz, {0, Unknown}}, + {X86::VPSRAVQZrm, {0, Unknown}}, + {X86::VPSRAVQZrmb, {0, Unknown}}, + {X86::VPSRAVQZrmbk, {0, Unknown}}, + {X86::VPSRAVQZrmbkz, {0, Unknown}}, + {X86::VPSRAVQZrmk, {0, Unknown}}, + {X86::VPSRAVQZrmkz, {0, Unknown}}, + {X86::VPSRAVQZrr, {0, Unknown}}, + {X86::VPSRAVQZrrk, {0, Unknown}}, + {X86::VPSRAVQZrrkz, {0, Unknown}}, + {X86::VPSRAVWZ128rm, {1, Unknown}}, + {X86::VPSRAVWZ128rmk, {1, Unknown}}, + {X86::VPSRAVWZ128rmkz, {1, Unknown}}, + {X86::VPSRAVWZ128rr, {0, Unknown}}, + {X86::VPSRAVWZ128rrk, {0, Unknown}}, + {X86::VPSRAVWZ128rrkz, {0, Unknown}}, + {X86::VPSRAVWZ256rm, {0, Unknown}}, + {X86::VPSRAVWZ256rmk, {0, Unknown}}, + {X86::VPSRAVWZ256rmkz, {0, Unknown}}, + {X86::VPSRAVWZ256rr, {0, Unknown}}, + {X86::VPSRAVWZ256rrk, {0, Unknown}}, + {X86::VPSRAVWZ256rrkz, {0, Unknown}}, + {X86::VPSRAVWZrm, {0, Unknown}}, + {X86::VPSRAVWZrmk, {0, Unknown}}, + {X86::VPSRAVWZrmkz, {0, Unknown}}, + {X86::VPSRAVWZrr, {0, Unknown}}, + {X86::VPSRAVWZrrk, {0, Unknown}}, + {X86::VPSRAVWZrrkz, {0, Unknown}}, + {X86::VPSRAWYri, {0, Unknown}}, + {X86::VPSRAWYrm, {0, Unknown}}, + {X86::VPSRAWYrr, {0, Unknown}}, + {X86::VPSRAWZ128mi, {1, Unknown}}, + {X86::VPSRAWZ128mik, {1, Unknown}}, + {X86::VPSRAWZ128mikz, {1, Unknown}}, + {X86::VPSRAWZ128ri, {0, Unknown}}, + {X86::VPSRAWZ128rik, {0, Unknown}}, + {X86::VPSRAWZ128rikz, {0, Unknown}}, + {X86::VPSRAWZ128rm, {1, Unknown}}, + {X86::VPSRAWZ128rmk, {1, Unknown}}, + {X86::VPSRAWZ128rmkz, {1, Unknown}}, + {X86::VPSRAWZ128rr, {0, Unknown}}, + {X86::VPSRAWZ128rrk, {0, Unknown}}, + {X86::VPSRAWZ128rrkz, {0, Unknown}}, + {X86::VPSRAWZ256mi, {0, Unknown}}, + {X86::VPSRAWZ256mik, {0, Unknown}}, + {X86::VPSRAWZ256mikz, {0, Unknown}}, + {X86::VPSRAWZ256ri, {0, Unknown}}, + {X86::VPSRAWZ256rik, {0, Unknown}}, + {X86::VPSRAWZ256rikz, {0, Unknown}}, + {X86::VPSRAWZ256rm, {0, Unknown}}, + {X86::VPSRAWZ256rmk, {0, Unknown}}, + {X86::VPSRAWZ256rmkz, {0, Unknown}}, + {X86::VPSRAWZ256rr, {0, Unknown}}, + {X86::VPSRAWZ256rrk, {0, Unknown}}, + {X86::VPSRAWZ256rrkz, {0, Unknown}}, + {X86::VPSRAWZmi, {0, Unknown}}, + {X86::VPSRAWZmik, {0, Unknown}}, + {X86::VPSRAWZmikz, {0, Unknown}}, + {X86::VPSRAWZri, {0, Unknown}}, + {X86::VPSRAWZrik, {0, Unknown}}, + {X86::VPSRAWZrikz, {0, Unknown}}, + {X86::VPSRAWZrm, {0, Unknown}}, + {X86::VPSRAWZrmk, {0, Unknown}}, + {X86::VPSRAWZrmkz, {0, Unknown}}, + {X86::VPSRAWZrr, {0, Unknown}}, + {X86::VPSRAWZrrk, {0, Unknown}}, + {X86::VPSRAWZrrkz, {0, Unknown}}, + {X86::VPSRAWri, {0, Unknown}}, + {X86::VPSRAWrm, {0, Unknown}}, + {X86::VPSRAWrr, {0, Unknown}}, + {X86::VPSRLDQYri, {0, Unknown}}, + {X86::VPSRLDQZ128rm, {1, Unknown}}, + {X86::VPSRLDQZ128rr, {0, Unknown}}, + {X86::VPSRLDQZ256rm, {0, Unknown}}, + {X86::VPSRLDQZ256rr, {0, Unknown}}, + {X86::VPSRLDQZrm, {0, Unknown}}, + {X86::VPSRLDQZrr, {0, Unknown}}, + {X86::VPSRLDQri, {0, Unknown}}, + {X86::VPSRLDYri, {0, Unknown}}, + {X86::VPSRLDYrm, {0, Unknown}}, + {X86::VPSRLDYrr, {0, Unknown}}, + {X86::VPSRLDZ128mbi, {0, Unknown}}, + {X86::VPSRLDZ128mbik, {0, Unknown}}, + {X86::VPSRLDZ128mbikz, {0, Unknown}}, + {X86::VPSRLDZ128mi, {1, Unknown}}, + {X86::VPSRLDZ128mik, {1, Unknown}}, + {X86::VPSRLDZ128mikz, {1, Unknown}}, + {X86::VPSRLDZ128ri, {0, Unknown}}, + {X86::VPSRLDZ128rik, {0, Unknown}}, + {X86::VPSRLDZ128rikz, {0, Unknown}}, + {X86::VPSRLDZ128rm, {1, Unknown}}, + {X86::VPSRLDZ128rmk, {1, Unknown}}, + {X86::VPSRLDZ128rmkz, {1, Unknown}}, + {X86::VPSRLDZ128rr, {0, Unknown}}, + {X86::VPSRLDZ128rrk, {0, Unknown}}, + {X86::VPSRLDZ128rrkz, {0, Unknown}}, + {X86::VPSRLDZ256mbi, {0, Unknown}}, + {X86::VPSRLDZ256mbik, {0, Unknown}}, + {X86::VPSRLDZ256mbikz, {0, Unknown}}, + {X86::VPSRLDZ256mi, {0, Unknown}}, + {X86::VPSRLDZ256mik, {0, Unknown}}, + {X86::VPSRLDZ256mikz, {0, Unknown}}, + {X86::VPSRLDZ256ri, {0, Unknown}}, + {X86::VPSRLDZ256rik, {0, Unknown}}, + {X86::VPSRLDZ256rikz, {0, Unknown}}, + {X86::VPSRLDZ256rm, {0, Unknown}}, + {X86::VPSRLDZ256rmk, {0, Unknown}}, + {X86::VPSRLDZ256rmkz, {0, Unknown}}, + {X86::VPSRLDZ256rr, {0, Unknown}}, + {X86::VPSRLDZ256rrk, {0, Unknown}}, + {X86::VPSRLDZ256rrkz, {0, Unknown}}, + {X86::VPSRLDZmbi, {0, Unknown}}, + {X86::VPSRLDZmbik, {0, Unknown}}, + {X86::VPSRLDZmbikz, {0, Unknown}}, + {X86::VPSRLDZmi, {0, Unknown}}, + {X86::VPSRLDZmik, {0, Unknown}}, + {X86::VPSRLDZmikz, {0, Unknown}}, + {X86::VPSRLDZri, {0, Unknown}}, + {X86::VPSRLDZrik, {0, Unknown}}, + {X86::VPSRLDZrikz, {0, Unknown}}, + {X86::VPSRLDZrm, {0, Unknown}}, + {X86::VPSRLDZrmk, {0, Unknown}}, + {X86::VPSRLDZrmkz, {0, Unknown}}, + {X86::VPSRLDZrr, {0, Unknown}}, + {X86::VPSRLDZrrk, {0, Unknown}}, + {X86::VPSRLDZrrkz, {0, Unknown}}, + {X86::VPSRLDri, {0, Unknown}}, + {X86::VPSRLDrm, {0, Unknown}}, + {X86::VPSRLDrr, {0, Unknown}}, + {X86::VPSRLQYri, {0, Unknown}}, + {X86::VPSRLQYrm, {0, Unknown}}, + {X86::VPSRLQYrr, {0, Unknown}}, + {X86::VPSRLQZ128mbi, {0, Unknown}}, + {X86::VPSRLQZ128mbik, {0, Unknown}}, + {X86::VPSRLQZ128mbikz, {0, Unknown}}, + {X86::VPSRLQZ128mi, {1, Unknown}}, + {X86::VPSRLQZ128mik, {1, Unknown}}, + {X86::VPSRLQZ128mikz, {1, Unknown}}, + {X86::VPSRLQZ128ri, {0, Unknown}}, + {X86::VPSRLQZ128rik, {0, Unknown}}, + {X86::VPSRLQZ128rikz, {0, Unknown}}, + {X86::VPSRLQZ128rm, {1, Unknown}}, + {X86::VPSRLQZ128rmk, {1, Unknown}}, + {X86::VPSRLQZ128rmkz, {1, Unknown}}, + {X86::VPSRLQZ128rr, {0, Unknown}}, + {X86::VPSRLQZ128rrk, {0, Unknown}}, + {X86::VPSRLQZ128rrkz, {0, Unknown}}, + {X86::VPSRLQZ256mbi, {0, Unknown}}, + {X86::VPSRLQZ256mbik, {0, Unknown}}, + {X86::VPSRLQZ256mbikz, {0, Unknown}}, + {X86::VPSRLQZ256mi, {0, Unknown}}, + {X86::VPSRLQZ256mik, {0, Unknown}}, + {X86::VPSRLQZ256mikz, {0, Unknown}}, + {X86::VPSRLQZ256ri, {0, Unknown}}, + {X86::VPSRLQZ256rik, {0, Unknown}}, + {X86::VPSRLQZ256rikz, {0, Unknown}}, + {X86::VPSRLQZ256rm, {0, Unknown}}, + {X86::VPSRLQZ256rmk, {0, Unknown}}, + {X86::VPSRLQZ256rmkz, {0, Unknown}}, + {X86::VPSRLQZ256rr, {0, Unknown}}, + {X86::VPSRLQZ256rrk, {0, Unknown}}, + {X86::VPSRLQZ256rrkz, {0, Unknown}}, + {X86::VPSRLQZmbi, {0, Unknown}}, + {X86::VPSRLQZmbik, {0, Unknown}}, + {X86::VPSRLQZmbikz, {0, Unknown}}, + {X86::VPSRLQZmi, {0, Unknown}}, + {X86::VPSRLQZmik, {0, Unknown}}, + {X86::VPSRLQZmikz, {0, Unknown}}, + {X86::VPSRLQZri, {0, Unknown}}, + {X86::VPSRLQZrik, {0, Unknown}}, + {X86::VPSRLQZrikz, {0, Unknown}}, + {X86::VPSRLQZrm, {0, Unknown}}, + {X86::VPSRLQZrmk, {0, Unknown}}, + {X86::VPSRLQZrmkz, {0, Unknown}}, + {X86::VPSRLQZrr, {0, Unknown}}, + {X86::VPSRLQZrrk, {0, Unknown}}, + {X86::VPSRLQZrrkz, {0, Unknown}}, + {X86::VPSRLQri, {0, Unknown}}, + {X86::VPSRLQrm, {0, Unknown}}, + {X86::VPSRLQrr, {0, Unknown}}, + {X86::VPSRLVDYrm, {0, Unknown}}, + {X86::VPSRLVDYrr, {0, Unknown}}, + {X86::VPSRLVDZ128rm, {1, Unknown}}, + {X86::VPSRLVDZ128rmb, {1, Unknown}}, + {X86::VPSRLVDZ128rmbk, {1, Unknown}}, + {X86::VPSRLVDZ128rmbkz, {1, Unknown}}, + {X86::VPSRLVDZ128rmk, {1, Unknown}}, + {X86::VPSRLVDZ128rmkz, {1, Unknown}}, + {X86::VPSRLVDZ128rr, {0, Unknown}}, + {X86::VPSRLVDZ128rrk, {0, Unknown}}, + {X86::VPSRLVDZ128rrkz, {0, Unknown}}, + {X86::VPSRLVDZ256rm, {0, Unknown}}, + {X86::VPSRLVDZ256rmb, {0, Unknown}}, + {X86::VPSRLVDZ256rmbk, {0, Unknown}}, + {X86::VPSRLVDZ256rmbkz, {0, Unknown}}, + {X86::VPSRLVDZ256rmk, {0, Unknown}}, + {X86::VPSRLVDZ256rmkz, {0, Unknown}}, + {X86::VPSRLVDZ256rr, {0, Unknown}}, + {X86::VPSRLVDZ256rrk, {0, Unknown}}, + {X86::VPSRLVDZ256rrkz, {0, Unknown}}, + {X86::VPSRLVDZrm, {0, Unknown}}, + {X86::VPSRLVDZrmb, {0, Unknown}}, + {X86::VPSRLVDZrmbk, {0, Unknown}}, + {X86::VPSRLVDZrmbkz, {0, Unknown}}, + {X86::VPSRLVDZrmk, {0, Unknown}}, + {X86::VPSRLVDZrmkz, {0, Unknown}}, + {X86::VPSRLVDZrr, {0, Unknown}}, + {X86::VPSRLVDZrrk, {0, Unknown}}, + {X86::VPSRLVDZrrkz, {0, Unknown}}, + {X86::VPSRLVDrm, {0, Unknown}}, + {X86::VPSRLVDrr, {0, Unknown}}, + {X86::VPSRLVQYrm, {0, Unknown}}, + {X86::VPSRLVQYrr, {0, Unknown}}, + {X86::VPSRLVQZ128rm, {1, Unknown}}, + {X86::VPSRLVQZ128rmb, {1, Unknown}}, + {X86::VPSRLVQZ128rmbk, {1, Unknown}}, + {X86::VPSRLVQZ128rmbkz, {1, Unknown}}, + {X86::VPSRLVQZ128rmk, {1, Unknown}}, + {X86::VPSRLVQZ128rmkz, {1, Unknown}}, + {X86::VPSRLVQZ128rr, {0, Unknown}}, + {X86::VPSRLVQZ128rrk, {0, Unknown}}, + {X86::VPSRLVQZ128rrkz, {0, Unknown}}, + {X86::VPSRLVQZ256rm, {0, Unknown}}, + {X86::VPSRLVQZ256rmb, {0, Unknown}}, + {X86::VPSRLVQZ256rmbk, {0, Unknown}}, + {X86::VPSRLVQZ256rmbkz, {0, Unknown}}, + {X86::VPSRLVQZ256rmk, {0, Unknown}}, + {X86::VPSRLVQZ256rmkz, {0, Unknown}}, + {X86::VPSRLVQZ256rr, {0, Unknown}}, + {X86::VPSRLVQZ256rrk, {0, Unknown}}, + {X86::VPSRLVQZ256rrkz, {0, Unknown}}, + {X86::VPSRLVQZrm, {0, Unknown}}, + {X86::VPSRLVQZrmb, {0, Unknown}}, + {X86::VPSRLVQZrmbk, {0, Unknown}}, + {X86::VPSRLVQZrmbkz, {0, Unknown}}, + {X86::VPSRLVQZrmk, {0, Unknown}}, + {X86::VPSRLVQZrmkz, {0, Unknown}}, + {X86::VPSRLVQZrr, {0, Unknown}}, + {X86::VPSRLVQZrrk, {0, Unknown}}, + {X86::VPSRLVQZrrkz, {0, Unknown}}, + {X86::VPSRLVQrm, {0, Unknown}}, + {X86::VPSRLVQrr, {0, Unknown}}, + {X86::VPSRLVWZ128rm, {1, Unknown}}, + {X86::VPSRLVWZ128rmk, {1, Unknown}}, + {X86::VPSRLVWZ128rmkz, {1, Unknown}}, + {X86::VPSRLVWZ128rr, {0, Unknown}}, + {X86::VPSRLVWZ128rrk, {0, Unknown}}, + {X86::VPSRLVWZ128rrkz, {0, Unknown}}, + {X86::VPSRLVWZ256rm, {0, Unknown}}, + {X86::VPSRLVWZ256rmk, {0, Unknown}}, + {X86::VPSRLVWZ256rmkz, {0, Unknown}}, + {X86::VPSRLVWZ256rr, {0, Unknown}}, + {X86::VPSRLVWZ256rrk, {0, Unknown}}, + {X86::VPSRLVWZ256rrkz, {0, Unknown}}, + {X86::VPSRLVWZrm, {0, Unknown}}, + {X86::VPSRLVWZrmk, {0, Unknown}}, + {X86::VPSRLVWZrmkz, {0, Unknown}}, + {X86::VPSRLVWZrr, {0, Unknown}}, + {X86::VPSRLVWZrrk, {0, Unknown}}, + {X86::VPSRLVWZrrkz, {0, Unknown}}, + {X86::VPSRLWYri, {0, Unknown}}, + {X86::VPSRLWYrm, {0, Unknown}}, + {X86::VPSRLWYrr, {0, Unknown}}, + {X86::VPSRLWZ128mi, {1, Unknown}}, + {X86::VPSRLWZ128mik, {1, Unknown}}, + {X86::VPSRLWZ128mikz, {1, Unknown}}, + {X86::VPSRLWZ128ri, {0, Unknown}}, + {X86::VPSRLWZ128rik, {0, Unknown}}, + {X86::VPSRLWZ128rikz, {0, Unknown}}, + {X86::VPSRLWZ128rm, {1, Unknown}}, + {X86::VPSRLWZ128rmk, {1, Unknown}}, + {X86::VPSRLWZ128rmkz, {1, Unknown}}, + {X86::VPSRLWZ128rr, {0, Unknown}}, + {X86::VPSRLWZ128rrk, {0, Unknown}}, + {X86::VPSRLWZ128rrkz, {0, Unknown}}, + {X86::VPSRLWZ256mi, {0, Unknown}}, + {X86::VPSRLWZ256mik, {0, Unknown}}, + {X86::VPSRLWZ256mikz, {0, Unknown}}, + {X86::VPSRLWZ256ri, {0, Unknown}}, + {X86::VPSRLWZ256rik, {0, Unknown}}, + {X86::VPSRLWZ256rikz, {0, Unknown}}, + {X86::VPSRLWZ256rm, {0, Unknown}}, + {X86::VPSRLWZ256rmk, {0, Unknown}}, + {X86::VPSRLWZ256rmkz, {0, Unknown}}, + {X86::VPSRLWZ256rr, {0, Unknown}}, + {X86::VPSRLWZ256rrk, {0, Unknown}}, + {X86::VPSRLWZ256rrkz, {0, Unknown}}, + {X86::VPSRLWZmi, {0, Unknown}}, + {X86::VPSRLWZmik, {0, Unknown}}, + {X86::VPSRLWZmikz, {0, Unknown}}, + {X86::VPSRLWZri, {0, Unknown}}, + {X86::VPSRLWZrik, {0, Unknown}}, + {X86::VPSRLWZrikz, {0, Unknown}}, + {X86::VPSRLWZrm, {0, Unknown}}, + {X86::VPSRLWZrmk, {0, Unknown}}, + {X86::VPSRLWZrmkz, {0, Unknown}}, + {X86::VPSRLWZrr, {0, Unknown}}, + {X86::VPSRLWZrrk, {0, Unknown}}, + {X86::VPSRLWZrrkz, {0, Unknown}}, + {X86::VPSRLWri, {0, Unknown}}, + {X86::VPSRLWrm, {0, Unknown}}, + {X86::VPSRLWrr, {0, Unknown}}, + {X86::VPSUBBYrm, {0, Unknown}}, + {X86::VPSUBBYrr, {0, Unknown}}, + {X86::VPSUBBZ128rm, {1, Unknown}}, + {X86::VPSUBBZ128rmk, {1, Unknown}}, + {X86::VPSUBBZ128rmkz, {1, Unknown}}, + {X86::VPSUBBZ128rr, {0, Unknown}}, + {X86::VPSUBBZ128rrk, {0, Unknown}}, + {X86::VPSUBBZ128rrkz, {0, Unknown}}, + {X86::VPSUBBZ256rm, {0, Unknown}}, + {X86::VPSUBBZ256rmk, {0, Unknown}}, + {X86::VPSUBBZ256rmkz, {0, Unknown}}, + {X86::VPSUBBZ256rr, {0, Unknown}}, + {X86::VPSUBBZ256rrk, {0, Unknown}}, + {X86::VPSUBBZ256rrkz, {0, Unknown}}, + {X86::VPSUBBZrm, {0, Unknown}}, + {X86::VPSUBBZrmk, {0, Unknown}}, + {X86::VPSUBBZrmkz, {0, Unknown}}, + {X86::VPSUBBZrr, {0, Unknown}}, + {X86::VPSUBBZrrk, {0, Unknown}}, + {X86::VPSUBBZrrkz, {0, Unknown}}, + {X86::VPSUBBrm, {0, Unknown}}, + {X86::VPSUBBrr, {0, Unknown}}, + {X86::VPSUBDYrm, {0, Unknown}}, + {X86::VPSUBDYrr, {0, Unknown}}, + {X86::VPSUBDZ128rm, {1, Unknown}}, + {X86::VPSUBDZ128rmb, {1, Unknown}}, + {X86::VPSUBDZ128rmbk, {1, Unknown}}, + {X86::VPSUBDZ128rmbkz, {1, Unknown}}, + {X86::VPSUBDZ128rmk, {1, Unknown}}, + {X86::VPSUBDZ128rmkz, {1, Unknown}}, + {X86::VPSUBDZ128rr, {0, Unknown}}, + {X86::VPSUBDZ128rrk, {0, Unknown}}, + {X86::VPSUBDZ128rrkz, {0, Unknown}}, + {X86::VPSUBDZ256rm, {0, Unknown}}, + {X86::VPSUBDZ256rmb, {0, Unknown}}, + {X86::VPSUBDZ256rmbk, {0, Unknown}}, + {X86::VPSUBDZ256rmbkz, {0, Unknown}}, + {X86::VPSUBDZ256rmk, {0, Unknown}}, + {X86::VPSUBDZ256rmkz, {0, Unknown}}, + {X86::VPSUBDZ256rr, {0, Unknown}}, + {X86::VPSUBDZ256rrk, {0, Unknown}}, + {X86::VPSUBDZ256rrkz, {0, Unknown}}, + {X86::VPSUBDZrm, {0, Unknown}}, + {X86::VPSUBDZrmb, {0, Unknown}}, + {X86::VPSUBDZrmbk, {0, Unknown}}, + {X86::VPSUBDZrmbkz, {0, Unknown}}, + {X86::VPSUBDZrmk, {0, Unknown}}, + {X86::VPSUBDZrmkz, {0, Unknown}}, + {X86::VPSUBDZrr, {0, Unknown}}, + {X86::VPSUBDZrrk, {0, Unknown}}, + {X86::VPSUBDZrrkz, {0, Unknown}}, + {X86::VPSUBDrm, {0, Unknown}}, + {X86::VPSUBDrr, {0, Unknown}}, + {X86::VPSUBQYrm, {0, Unknown}}, + {X86::VPSUBQYrr, {0, Unknown}}, + {X86::VPSUBQZ128rm, {1, Unknown}}, + {X86::VPSUBQZ128rmb, {1, Unknown}}, + {X86::VPSUBQZ128rmbk, {1, Unknown}}, + {X86::VPSUBQZ128rmbkz, {1, Unknown}}, + {X86::VPSUBQZ128rmk, {1, Unknown}}, + {X86::VPSUBQZ128rmkz, {1, Unknown}}, + {X86::VPSUBQZ128rr, {0, Unknown}}, + {X86::VPSUBQZ128rrk, {0, Unknown}}, + {X86::VPSUBQZ128rrkz, {0, Unknown}}, + {X86::VPSUBQZ256rm, {0, Unknown}}, + {X86::VPSUBQZ256rmb, {0, Unknown}}, + {X86::VPSUBQZ256rmbk, {0, Unknown}}, + {X86::VPSUBQZ256rmbkz, {0, Unknown}}, + {X86::VPSUBQZ256rmk, {0, Unknown}}, + {X86::VPSUBQZ256rmkz, {0, Unknown}}, + {X86::VPSUBQZ256rr, {0, Unknown}}, + {X86::VPSUBQZ256rrk, {0, Unknown}}, + {X86::VPSUBQZ256rrkz, {0, Unknown}}, + {X86::VPSUBQZrm, {0, Unknown}}, + {X86::VPSUBQZrmb, {0, Unknown}}, + {X86::VPSUBQZrmbk, {0, Unknown}}, + {X86::VPSUBQZrmbkz, {0, Unknown}}, + {X86::VPSUBQZrmk, {0, Unknown}}, + {X86::VPSUBQZrmkz, {0, Unknown}}, + {X86::VPSUBQZrr, {0, Unknown}}, + {X86::VPSUBQZrrk, {0, Unknown}}, + {X86::VPSUBQZrrkz, {0, Unknown}}, + {X86::VPSUBQrm, {0, Unknown}}, + {X86::VPSUBQrr, {0, Unknown}}, + {X86::VPSUBSBYrm, {0, Unknown}}, + {X86::VPSUBSBYrr, {0, Unknown}}, + {X86::VPSUBSBZ128rm, {1, Unknown}}, + {X86::VPSUBSBZ128rmk, {1, Unknown}}, + {X86::VPSUBSBZ128rmkz, {1, Unknown}}, + {X86::VPSUBSBZ128rr, {0, Unknown}}, + {X86::VPSUBSBZ128rrk, {0, Unknown}}, + {X86::VPSUBSBZ128rrkz, {0, Unknown}}, + {X86::VPSUBSBZ256rm, {0, Unknown}}, + {X86::VPSUBSBZ256rmk, {0, Unknown}}, + {X86::VPSUBSBZ256rmkz, {0, Unknown}}, + {X86::VPSUBSBZ256rr, {0, Unknown}}, + {X86::VPSUBSBZ256rrk, {0, Unknown}}, + {X86::VPSUBSBZ256rrkz, {0, Unknown}}, + {X86::VPSUBSBZrm, {0, Unknown}}, + {X86::VPSUBSBZrmk, {0, Unknown}}, + {X86::VPSUBSBZrmkz, {0, Unknown}}, + {X86::VPSUBSBZrr, {0, Unknown}}, + {X86::VPSUBSBZrrk, {0, Unknown}}, + {X86::VPSUBSBZrrkz, {0, Unknown}}, + {X86::VPSUBSBrm, {0, Unknown}}, + {X86::VPSUBSBrr, {0, Unknown}}, + {X86::VPSUBSWYrm, {0, Unknown}}, + {X86::VPSUBSWYrr, {0, Unknown}}, + {X86::VPSUBSWZ128rm, {1, Unknown}}, + {X86::VPSUBSWZ128rmk, {1, Unknown}}, + {X86::VPSUBSWZ128rmkz, {1, Unknown}}, + {X86::VPSUBSWZ128rr, {0, Unknown}}, + {X86::VPSUBSWZ128rrk, {0, Unknown}}, + {X86::VPSUBSWZ128rrkz, {0, Unknown}}, + {X86::VPSUBSWZ256rm, {0, Unknown}}, + {X86::VPSUBSWZ256rmk, {0, Unknown}}, + {X86::VPSUBSWZ256rmkz, {0, Unknown}}, + {X86::VPSUBSWZ256rr, {0, Unknown}}, + {X86::VPSUBSWZ256rrk, {0, Unknown}}, + {X86::VPSUBSWZ256rrkz, {0, Unknown}}, + {X86::VPSUBSWZrm, {0, Unknown}}, + {X86::VPSUBSWZrmk, {0, Unknown}}, + {X86::VPSUBSWZrmkz, {0, Unknown}}, + {X86::VPSUBSWZrr, {0, Unknown}}, + {X86::VPSUBSWZrrk, {0, Unknown}}, + {X86::VPSUBSWZrrkz, {0, Unknown}}, + {X86::VPSUBSWrm, {0, Unknown}}, + {X86::VPSUBSWrr, {0, Unknown}}, + {X86::VPSUBUSBYrm, {0, Unknown}}, + {X86::VPSUBUSBYrr, {0, Unknown}}, + {X86::VPSUBUSBZ128rm, {1, Unknown}}, + {X86::VPSUBUSBZ128rmk, {1, Unknown}}, + {X86::VPSUBUSBZ128rmkz, {1, Unknown}}, + {X86::VPSUBUSBZ128rr, {0, Unknown}}, + {X86::VPSUBUSBZ128rrk, {0, Unknown}}, + {X86::VPSUBUSBZ128rrkz, {0, Unknown}}, + {X86::VPSUBUSBZ256rm, {0, Unknown}}, + {X86::VPSUBUSBZ256rmk, {0, Unknown}}, + {X86::VPSUBUSBZ256rmkz, {0, Unknown}}, + {X86::VPSUBUSBZ256rr, {0, Unknown}}, + {X86::VPSUBUSBZ256rrk, {0, Unknown}}, + {X86::VPSUBUSBZ256rrkz, {0, Unknown}}, + {X86::VPSUBUSBZrm, {0, Unknown}}, + {X86::VPSUBUSBZrmk, {0, Unknown}}, + {X86::VPSUBUSBZrmkz, {0, Unknown}}, + {X86::VPSUBUSBZrr, {0, Unknown}}, + {X86::VPSUBUSBZrrk, {0, Unknown}}, + {X86::VPSUBUSBZrrkz, {0, Unknown}}, + {X86::VPSUBUSBrm, {0, Unknown}}, + {X86::VPSUBUSBrr, {0, Unknown}}, + {X86::VPSUBUSWYrm, {0, Unknown}}, + {X86::VPSUBUSWYrr, {0, Unknown}}, + {X86::VPSUBUSWZ128rm, {1, Unknown}}, + {X86::VPSUBUSWZ128rmk, {1, Unknown}}, + {X86::VPSUBUSWZ128rmkz, {1, Unknown}}, + {X86::VPSUBUSWZ128rr, {0, Unknown}}, + {X86::VPSUBUSWZ128rrk, {0, Unknown}}, + {X86::VPSUBUSWZ128rrkz, {0, Unknown}}, + {X86::VPSUBUSWZ256rm, {0, Unknown}}, + {X86::VPSUBUSWZ256rmk, {0, Unknown}}, + {X86::VPSUBUSWZ256rmkz, {0, Unknown}}, + {X86::VPSUBUSWZ256rr, {0, Unknown}}, + {X86::VPSUBUSWZ256rrk, {0, Unknown}}, + {X86::VPSUBUSWZ256rrkz, {0, Unknown}}, + {X86::VPSUBUSWZrm, {0, Unknown}}, + {X86::VPSUBUSWZrmk, {0, Unknown}}, + {X86::VPSUBUSWZrmkz, {0, Unknown}}, + {X86::VPSUBUSWZrr, {0, Unknown}}, + {X86::VPSUBUSWZrrk, {0, Unknown}}, + {X86::VPSUBUSWZrrkz, {0, Unknown}}, + {X86::VPSUBUSWrm, {0, Unknown}}, + {X86::VPSUBUSWrr, {0, Unknown}}, + {X86::VPSUBWYrm, {0, Unknown}}, + {X86::VPSUBWYrr, {0, Unknown}}, + {X86::VPSUBWZ128rm, {1, Unknown}}, + {X86::VPSUBWZ128rmk, {1, Unknown}}, + {X86::VPSUBWZ128rmkz, {1, Unknown}}, + {X86::VPSUBWZ128rr, {0, Unknown}}, + {X86::VPSUBWZ128rrk, {0, Unknown}}, + {X86::VPSUBWZ128rrkz, {0, Unknown}}, + {X86::VPSUBWZ256rm, {0, Unknown}}, + {X86::VPSUBWZ256rmk, {0, Unknown}}, + {X86::VPSUBWZ256rmkz, {0, Unknown}}, + {X86::VPSUBWZ256rr, {0, Unknown}}, + {X86::VPSUBWZ256rrk, {0, Unknown}}, + {X86::VPSUBWZ256rrkz, {0, Unknown}}, + {X86::VPSUBWZrm, {0, Unknown}}, + {X86::VPSUBWZrmk, {0, Unknown}}, + {X86::VPSUBWZrmkz, {0, Unknown}}, + {X86::VPSUBWZrr, {0, Unknown}}, + {X86::VPSUBWZrrk, {0, Unknown}}, + {X86::VPSUBWZrrkz, {0, Unknown}}, + {X86::VPSUBWrm, {0, Unknown}}, + {X86::VPSUBWrr, {0, Unknown}}, + {X86::VPTERNLOGDZ128rmbi, {1, Unknown}}, + {X86::VPTERNLOGDZ128rmbik, {1, Unknown}}, + {X86::VPTERNLOGDZ128rmbikz, {1, Unknown}}, + {X86::VPTERNLOGDZ128rmi, {1, Unknown}}, + {X86::VPTERNLOGDZ128rmik, {1, Unknown}}, + {X86::VPTERNLOGDZ128rmikz, {1, Unknown}}, + {X86::VPTERNLOGDZ128rri, {0, Unknown}}, + {X86::VPTERNLOGDZ128rrik, {0, Unknown}}, + {X86::VPTERNLOGDZ128rrikz, {0, Unknown}}, + {X86::VPTERNLOGDZ256rmbi, {0, Unknown}}, + {X86::VPTERNLOGDZ256rmbik, {0, Unknown}}, + {X86::VPTERNLOGDZ256rmbikz, {0, Unknown}}, + {X86::VPTERNLOGDZ256rmi, {0, Unknown}}, + {X86::VPTERNLOGDZ256rmik, {0, Unknown}}, + {X86::VPTERNLOGDZ256rmikz, {0, Unknown}}, + {X86::VPTERNLOGDZ256rri, {0, Unknown}}, + {X86::VPTERNLOGDZ256rrik, {0, Unknown}}, + {X86::VPTERNLOGDZ256rrikz, {0, Unknown}}, + {X86::VPTERNLOGDZrmbi, {0, Unknown}}, + {X86::VPTERNLOGDZrmbik, {0, Unknown}}, + {X86::VPTERNLOGDZrmbikz, {0, Unknown}}, + {X86::VPTERNLOGDZrmi, {0, Unknown}}, + {X86::VPTERNLOGDZrmik, {0, Unknown}}, + {X86::VPTERNLOGDZrmikz, {0, Unknown}}, + {X86::VPTERNLOGDZrri, {0, Unknown}}, + {X86::VPTERNLOGDZrrik, {0, Unknown}}, + {X86::VPTERNLOGDZrrikz, {0, Unknown}}, + {X86::VPTERNLOGQZ128rmbi, {1, Unknown}}, + {X86::VPTERNLOGQZ128rmbik, {1, Unknown}}, + {X86::VPTERNLOGQZ128rmbikz, {1, Unknown}}, + {X86::VPTERNLOGQZ128rmi, {1, Unknown}}, + {X86::VPTERNLOGQZ128rmik, {1, Unknown}}, + {X86::VPTERNLOGQZ128rmikz, {1, Unknown}}, + {X86::VPTERNLOGQZ128rri, {0, Unknown}}, + {X86::VPTERNLOGQZ128rrik, {0, Unknown}}, + {X86::VPTERNLOGQZ128rrikz, {0, Unknown}}, + {X86::VPTERNLOGQZ256rmbi, {0, Unknown}}, + {X86::VPTERNLOGQZ256rmbik, {0, Unknown}}, + {X86::VPTERNLOGQZ256rmbikz, {0, Unknown}}, + {X86::VPTERNLOGQZ256rmi, {0, Unknown}}, + {X86::VPTERNLOGQZ256rmik, {0, Unknown}}, + {X86::VPTERNLOGQZ256rmikz, {0, Unknown}}, + {X86::VPTERNLOGQZ256rri, {0, Unknown}}, + {X86::VPTERNLOGQZ256rrik, {0, Unknown}}, + {X86::VPTERNLOGQZ256rrikz, {0, Unknown}}, + {X86::VPTERNLOGQZrmbi, {0, Unknown}}, + {X86::VPTERNLOGQZrmbik, {0, Unknown}}, + {X86::VPTERNLOGQZrmbikz, {0, Unknown}}, + {X86::VPTERNLOGQZrmi, {0, Unknown}}, + {X86::VPTERNLOGQZrmik, {0, Unknown}}, + {X86::VPTERNLOGQZrmikz, {0, Unknown}}, + {X86::VPTERNLOGQZrri, {0, Unknown}}, + {X86::VPTERNLOGQZrrik, {0, Unknown}}, + {X86::VPTERNLOGQZrrikz, {0, Unknown}}, + {X86::VPTESTMBZ128rm, {1, Unknown}}, + {X86::VPTESTMBZ128rmk, {1, Unknown}}, + {X86::VPTESTMBZ128rr, {0, Unknown}}, + {X86::VPTESTMBZ128rrk, {0, Unknown}}, + {X86::VPTESTMBZ256rm, {0, Unknown}}, + {X86::VPTESTMBZ256rmk, {0, Unknown}}, + {X86::VPTESTMBZ256rr, {0, Unknown}}, + {X86::VPTESTMBZ256rrk, {0, Unknown}}, + {X86::VPTESTMBZrm, {0, Unknown}}, + {X86::VPTESTMBZrmk, {0, Unknown}}, + {X86::VPTESTMBZrr, {0, Unknown}}, + {X86::VPTESTMBZrrk, {0, Unknown}}, + {X86::VPTESTMDZ128rm, {1, Unknown}}, + {X86::VPTESTMDZ128rmb, {1, Unknown}}, + {X86::VPTESTMDZ128rmbk, {1, Unknown}}, + {X86::VPTESTMDZ128rmk, {1, Unknown}}, + {X86::VPTESTMDZ128rr, {0, Unknown}}, + {X86::VPTESTMDZ128rrk, {0, Unknown}}, + {X86::VPTESTMDZ256rm, {0, Unknown}}, + {X86::VPTESTMDZ256rmb, {0, Unknown}}, + {X86::VPTESTMDZ256rmbk, {0, Unknown}}, + {X86::VPTESTMDZ256rmk, {0, Unknown}}, + {X86::VPTESTMDZ256rr, {0, Unknown}}, + {X86::VPTESTMDZ256rrk, {0, Unknown}}, + {X86::VPTESTMDZrm, {0, Unknown}}, + {X86::VPTESTMDZrmb, {0, Unknown}}, + {X86::VPTESTMDZrmbk, {0, Unknown}}, + {X86::VPTESTMDZrmk, {0, Unknown}}, + {X86::VPTESTMDZrr, {0, Unknown}}, + {X86::VPTESTMDZrrk, {0, Unknown}}, + {X86::VPTESTMQZ128rm, {1, Unknown}}, + {X86::VPTESTMQZ128rmb, {1, Unknown}}, + {X86::VPTESTMQZ128rmbk, {1, Unknown}}, + {X86::VPTESTMQZ128rmk, {1, Unknown}}, + {X86::VPTESTMQZ128rr, {0, Unknown}}, + {X86::VPTESTMQZ128rrk, {0, Unknown}}, + {X86::VPTESTMQZ256rm, {0, Unknown}}, + {X86::VPTESTMQZ256rmb, {0, Unknown}}, + {X86::VPTESTMQZ256rmbk, {0, Unknown}}, + {X86::VPTESTMQZ256rmk, {0, Unknown}}, + {X86::VPTESTMQZ256rr, {0, Unknown}}, + {X86::VPTESTMQZ256rrk, {0, Unknown}}, + {X86::VPTESTMQZrm, {0, Unknown}}, + {X86::VPTESTMQZrmb, {0, Unknown}}, + {X86::VPTESTMQZrmbk, {0, Unknown}}, + {X86::VPTESTMQZrmk, {0, Unknown}}, + {X86::VPTESTMQZrr, {0, Unknown}}, + {X86::VPTESTMQZrrk, {0, Unknown}}, + {X86::VPTESTMWZ128rm, {1, Unknown}}, + {X86::VPTESTMWZ128rmk, {1, Unknown}}, + {X86::VPTESTMWZ128rr, {0, Unknown}}, + {X86::VPTESTMWZ128rrk, {0, Unknown}}, + {X86::VPTESTMWZ256rm, {0, Unknown}}, + {X86::VPTESTMWZ256rmk, {0, Unknown}}, + {X86::VPTESTMWZ256rr, {0, Unknown}}, + {X86::VPTESTMWZ256rrk, {0, Unknown}}, + {X86::VPTESTMWZrm, {0, Unknown}}, + {X86::VPTESTMWZrmk, {0, Unknown}}, + {X86::VPTESTMWZrr, {0, Unknown}}, + {X86::VPTESTMWZrrk, {0, Unknown}}, + {X86::VPTESTNMBZ128rm, {1, Unknown}}, + {X86::VPTESTNMBZ128rmk, {1, Unknown}}, + {X86::VPTESTNMBZ128rr, {0, Unknown}}, + {X86::VPTESTNMBZ128rrk, {0, Unknown}}, + {X86::VPTESTNMBZ256rm, {0, Unknown}}, + {X86::VPTESTNMBZ256rmk, {0, Unknown}}, + {X86::VPTESTNMBZ256rr, {0, Unknown}}, + {X86::VPTESTNMBZ256rrk, {0, Unknown}}, + {X86::VPTESTNMBZrm, {0, Unknown}}, + {X86::VPTESTNMBZrmk, {0, Unknown}}, + {X86::VPTESTNMBZrr, {0, Unknown}}, + {X86::VPTESTNMBZrrk, {0, Unknown}}, + {X86::VPTESTNMDZ128rm, {1, Unknown}}, + {X86::VPTESTNMDZ128rmb, {1, Unknown}}, + {X86::VPTESTNMDZ128rmbk, {1, Unknown}}, + {X86::VPTESTNMDZ128rmk, {1, Unknown}}, + {X86::VPTESTNMDZ128rr, {0, Unknown}}, + {X86::VPTESTNMDZ128rrk, {0, Unknown}}, + {X86::VPTESTNMDZ256rm, {0, Unknown}}, + {X86::VPTESTNMDZ256rmb, {0, Unknown}}, + {X86::VPTESTNMDZ256rmbk, {0, Unknown}}, + {X86::VPTESTNMDZ256rmk, {0, Unknown}}, + {X86::VPTESTNMDZ256rr, {0, Unknown}}, + {X86::VPTESTNMDZ256rrk, {0, Unknown}}, + {X86::VPTESTNMDZrm, {0, Unknown}}, + {X86::VPTESTNMDZrmb, {0, Unknown}}, + {X86::VPTESTNMDZrmbk, {0, Unknown}}, + {X86::VPTESTNMDZrmk, {0, Unknown}}, + {X86::VPTESTNMDZrr, {0, Unknown}}, + {X86::VPTESTNMDZrrk, {0, Unknown}}, + {X86::VPTESTNMQZ128rm, {1, Unknown}}, + {X86::VPTESTNMQZ128rmb, {1, Unknown}}, + {X86::VPTESTNMQZ128rmbk, {1, Unknown}}, + {X86::VPTESTNMQZ128rmk, {1, Unknown}}, + {X86::VPTESTNMQZ128rr, {0, Unknown}}, + {X86::VPTESTNMQZ128rrk, {0, Unknown}}, + {X86::VPTESTNMQZ256rm, {0, Unknown}}, + {X86::VPTESTNMQZ256rmb, {0, Unknown}}, + {X86::VPTESTNMQZ256rmbk, {0, Unknown}}, + {X86::VPTESTNMQZ256rmk, {0, Unknown}}, + {X86::VPTESTNMQZ256rr, {0, Unknown}}, + {X86::VPTESTNMQZ256rrk, {0, Unknown}}, + {X86::VPTESTNMQZrm, {0, Unknown}}, + {X86::VPTESTNMQZrmb, {0, Unknown}}, + {X86::VPTESTNMQZrmbk, {0, Unknown}}, + {X86::VPTESTNMQZrmk, {0, Unknown}}, + {X86::VPTESTNMQZrr, {0, Unknown}}, + {X86::VPTESTNMQZrrk, {0, Unknown}}, + {X86::VPTESTNMWZ128rm, {1, Unknown}}, + {X86::VPTESTNMWZ128rmk, {1, Unknown}}, + {X86::VPTESTNMWZ128rr, {0, Unknown}}, + {X86::VPTESTNMWZ128rrk, {0, Unknown}}, + {X86::VPTESTNMWZ256rm, {0, Unknown}}, + {X86::VPTESTNMWZ256rmk, {0, Unknown}}, + {X86::VPTESTNMWZ256rr, {0, Unknown}}, + {X86::VPTESTNMWZ256rrk, {0, Unknown}}, + {X86::VPTESTNMWZrm, {0, Unknown}}, + {X86::VPTESTNMWZrmk, {0, Unknown}}, + {X86::VPTESTNMWZrr, {0, Unknown}}, + {X86::VPTESTNMWZrrk, {0, Unknown}}, + {X86::VPTESTYrm, {0, Unknown}}, + {X86::VPTESTYrr, {0, Unknown}}, + {X86::VPTESTrm, {0, Unknown}}, + {X86::VPTESTrr, {0, Unknown}}, + {X86::VPUNPCKHBWYrm, {0, Unknown}}, + {X86::VPUNPCKHBWYrr, {0, Unknown}}, + {X86::VPUNPCKHBWZ128rm, {1, Unknown}}, + {X86::VPUNPCKHBWZ128rmk, {1, Unknown}}, + {X86::VPUNPCKHBWZ128rmkz, {1, Unknown}}, + {X86::VPUNPCKHBWZ128rr, {0, Unknown}}, + {X86::VPUNPCKHBWZ128rrk, {0, Unknown}}, + {X86::VPUNPCKHBWZ128rrkz, {0, Unknown}}, + {X86::VPUNPCKHBWZ256rm, {0, Unknown}}, + {X86::VPUNPCKHBWZ256rmk, {0, Unknown}}, + {X86::VPUNPCKHBWZ256rmkz, {0, Unknown}}, + {X86::VPUNPCKHBWZ256rr, {0, Unknown}}, + {X86::VPUNPCKHBWZ256rrk, {0, Unknown}}, + {X86::VPUNPCKHBWZ256rrkz, {0, Unknown}}, + {X86::VPUNPCKHBWZrm, {0, Unknown}}, + {X86::VPUNPCKHBWZrmk, {0, Unknown}}, + {X86::VPUNPCKHBWZrmkz, {0, Unknown}}, + {X86::VPUNPCKHBWZrr, {0, Unknown}}, + {X86::VPUNPCKHBWZrrk, {0, Unknown}}, + {X86::VPUNPCKHBWZrrkz, {0, Unknown}}, + {X86::VPUNPCKHBWrm, {0, Unknown}}, + {X86::VPUNPCKHBWrr, {0, Unknown}}, + {X86::VPUNPCKHDQYrm, {0, Unknown}}, + {X86::VPUNPCKHDQYrr, {0, Unknown}}, + {X86::VPUNPCKHDQZ128rm, {1, Unknown}}, + {X86::VPUNPCKHDQZ128rmb, {1, Unknown}}, + {X86::VPUNPCKHDQZ128rmbk, {1, Unknown}}, + {X86::VPUNPCKHDQZ128rmbkz, {1, Unknown}}, + {X86::VPUNPCKHDQZ128rmk, {1, Unknown}}, + {X86::VPUNPCKHDQZ128rmkz, {1, Unknown}}, + {X86::VPUNPCKHDQZ128rr, {0, Unknown}}, + {X86::VPUNPCKHDQZ128rrk, {0, Unknown}}, + {X86::VPUNPCKHDQZ128rrkz, {0, Unknown}}, + {X86::VPUNPCKHDQZ256rm, {0, Unknown}}, + {X86::VPUNPCKHDQZ256rmb, {0, Unknown}}, + {X86::VPUNPCKHDQZ256rmbk, {0, Unknown}}, + {X86::VPUNPCKHDQZ256rmbkz, {0, Unknown}}, + {X86::VPUNPCKHDQZ256rmk, {0, Unknown}}, + {X86::VPUNPCKHDQZ256rmkz, {0, Unknown}}, + {X86::VPUNPCKHDQZ256rr, {0, Unknown}}, + {X86::VPUNPCKHDQZ256rrk, {0, Unknown}}, + {X86::VPUNPCKHDQZ256rrkz, {0, Unknown}}, + {X86::VPUNPCKHDQZrm, {0, Unknown}}, + {X86::VPUNPCKHDQZrmb, {0, Unknown}}, + {X86::VPUNPCKHDQZrmbk, {0, Unknown}}, + {X86::VPUNPCKHDQZrmbkz, {0, Unknown}}, + {X86::VPUNPCKHDQZrmk, {0, Unknown}}, + {X86::VPUNPCKHDQZrmkz, {0, Unknown}}, + {X86::VPUNPCKHDQZrr, {0, Unknown}}, + {X86::VPUNPCKHDQZrrk, {0, Unknown}}, + {X86::VPUNPCKHDQZrrkz, {0, Unknown}}, + {X86::VPUNPCKHDQrm, {0, Unknown}}, + {X86::VPUNPCKHDQrr, {0, Unknown}}, + {X86::VPUNPCKHQDQYrm, {0, Unknown}}, + {X86::VPUNPCKHQDQYrr, {0, Unknown}}, + {X86::VPUNPCKHQDQZ128rm, {1, Unknown}}, + {X86::VPUNPCKHQDQZ128rmb, {1, Unknown}}, + {X86::VPUNPCKHQDQZ128rmbk, {1, Unknown}}, + {X86::VPUNPCKHQDQZ128rmbkz, {1, Unknown}}, + {X86::VPUNPCKHQDQZ128rmk, {1, Unknown}}, + {X86::VPUNPCKHQDQZ128rmkz, {1, Unknown}}, + {X86::VPUNPCKHQDQZ128rr, {0, Unknown}}, + {X86::VPUNPCKHQDQZ128rrk, {0, Unknown}}, + {X86::VPUNPCKHQDQZ128rrkz, {0, Unknown}}, + {X86::VPUNPCKHQDQZ256rm, {0, Unknown}}, + {X86::VPUNPCKHQDQZ256rmb, {0, Unknown}}, + {X86::VPUNPCKHQDQZ256rmbk, {0, Unknown}}, + {X86::VPUNPCKHQDQZ256rmbkz, {0, Unknown}}, + {X86::VPUNPCKHQDQZ256rmk, {0, Unknown}}, + {X86::VPUNPCKHQDQZ256rmkz, {0, Unknown}}, + {X86::VPUNPCKHQDQZ256rr, {0, Unknown}}, + {X86::VPUNPCKHQDQZ256rrk, {0, Unknown}}, + {X86::VPUNPCKHQDQZ256rrkz, {0, Unknown}}, + {X86::VPUNPCKHQDQZrm, {0, Unknown}}, + {X86::VPUNPCKHQDQZrmb, {0, Unknown}}, + {X86::VPUNPCKHQDQZrmbk, {0, Unknown}}, + {X86::VPUNPCKHQDQZrmbkz, {0, Unknown}}, + {X86::VPUNPCKHQDQZrmk, {0, Unknown}}, + {X86::VPUNPCKHQDQZrmkz, {0, Unknown}}, + {X86::VPUNPCKHQDQZrr, {0, Unknown}}, + {X86::VPUNPCKHQDQZrrk, {0, Unknown}}, + {X86::VPUNPCKHQDQZrrkz, {0, Unknown}}, + {X86::VPUNPCKHQDQrm, {0, Unknown}}, + {X86::VPUNPCKHQDQrr, {0, Unknown}}, + {X86::VPUNPCKHWDYrm, {0, Unknown}}, + {X86::VPUNPCKHWDYrr, {0, Unknown}}, + {X86::VPUNPCKHWDZ128rm, {1, Unknown}}, + {X86::VPUNPCKHWDZ128rmk, {1, Unknown}}, + {X86::VPUNPCKHWDZ128rmkz, {1, Unknown}}, + {X86::VPUNPCKHWDZ128rr, {0, Unknown}}, + {X86::VPUNPCKHWDZ128rrk, {0, Unknown}}, + {X86::VPUNPCKHWDZ128rrkz, {0, Unknown}}, + {X86::VPUNPCKHWDZ256rm, {0, Unknown}}, + {X86::VPUNPCKHWDZ256rmk, {0, Unknown}}, + {X86::VPUNPCKHWDZ256rmkz, {0, Unknown}}, + {X86::VPUNPCKHWDZ256rr, {0, Unknown}}, + {X86::VPUNPCKHWDZ256rrk, {0, Unknown}}, + {X86::VPUNPCKHWDZ256rrkz, {0, Unknown}}, + {X86::VPUNPCKHWDZrm, {0, Unknown}}, + {X86::VPUNPCKHWDZrmk, {0, Unknown}}, + {X86::VPUNPCKHWDZrmkz, {0, Unknown}}, + {X86::VPUNPCKHWDZrr, {0, Unknown}}, + {X86::VPUNPCKHWDZrrk, {0, Unknown}}, + {X86::VPUNPCKHWDZrrkz, {0, Unknown}}, + {X86::VPUNPCKHWDrm, {0, Unknown}}, + {X86::VPUNPCKHWDrr, {0, Unknown}}, + {X86::VPUNPCKLBWYrm, {0, Unknown}}, + {X86::VPUNPCKLBWYrr, {0, Unknown}}, + {X86::VPUNPCKLBWZ128rm, {1, Unknown}}, + {X86::VPUNPCKLBWZ128rmk, {1, Unknown}}, + {X86::VPUNPCKLBWZ128rmkz, {1, Unknown}}, + {X86::VPUNPCKLBWZ128rr, {0, Unknown}}, + {X86::VPUNPCKLBWZ128rrk, {0, Unknown}}, + {X86::VPUNPCKLBWZ128rrkz, {0, Unknown}}, + {X86::VPUNPCKLBWZ256rm, {0, Unknown}}, + {X86::VPUNPCKLBWZ256rmk, {0, Unknown}}, + {X86::VPUNPCKLBWZ256rmkz, {0, Unknown}}, + {X86::VPUNPCKLBWZ256rr, {0, Unknown}}, + {X86::VPUNPCKLBWZ256rrk, {0, Unknown}}, + {X86::VPUNPCKLBWZ256rrkz, {0, Unknown}}, + {X86::VPUNPCKLBWZrm, {0, Unknown}}, + {X86::VPUNPCKLBWZrmk, {0, Unknown}}, + {X86::VPUNPCKLBWZrmkz, {0, Unknown}}, + {X86::VPUNPCKLBWZrr, {0, Unknown}}, + {X86::VPUNPCKLBWZrrk, {0, Unknown}}, + {X86::VPUNPCKLBWZrrkz, {0, Unknown}}, + {X86::VPUNPCKLBWrm, {0, Unknown}}, + {X86::VPUNPCKLBWrr, {0, Unknown}}, + {X86::VPUNPCKLDQYrm, {0, Unknown}}, + {X86::VPUNPCKLDQYrr, {0, Unknown}}, + {X86::VPUNPCKLDQZ128rm, {1, Unknown}}, + {X86::VPUNPCKLDQZ128rmb, {1, Unknown}}, + {X86::VPUNPCKLDQZ128rmbk, {1, Unknown}}, + {X86::VPUNPCKLDQZ128rmbkz, {1, Unknown}}, + {X86::VPUNPCKLDQZ128rmk, {1, Unknown}}, + {X86::VPUNPCKLDQZ128rmkz, {1, Unknown}}, + {X86::VPUNPCKLDQZ128rr, {0, Unknown}}, + {X86::VPUNPCKLDQZ128rrk, {0, Unknown}}, + {X86::VPUNPCKLDQZ128rrkz, {0, Unknown}}, + {X86::VPUNPCKLDQZ256rm, {0, Unknown}}, + {X86::VPUNPCKLDQZ256rmb, {0, Unknown}}, + {X86::VPUNPCKLDQZ256rmbk, {0, Unknown}}, + {X86::VPUNPCKLDQZ256rmbkz, {0, Unknown}}, + {X86::VPUNPCKLDQZ256rmk, {0, Unknown}}, + {X86::VPUNPCKLDQZ256rmkz, {0, Unknown}}, + {X86::VPUNPCKLDQZ256rr, {0, Unknown}}, + {X86::VPUNPCKLDQZ256rrk, {0, Unknown}}, + {X86::VPUNPCKLDQZ256rrkz, {0, Unknown}}, + {X86::VPUNPCKLDQZrm, {0, Unknown}}, + {X86::VPUNPCKLDQZrmb, {0, Unknown}}, + {X86::VPUNPCKLDQZrmbk, {0, Unknown}}, + {X86::VPUNPCKLDQZrmbkz, {0, Unknown}}, + {X86::VPUNPCKLDQZrmk, {0, Unknown}}, + {X86::VPUNPCKLDQZrmkz, {0, Unknown}}, + {X86::VPUNPCKLDQZrr, {0, Unknown}}, + {X86::VPUNPCKLDQZrrk, {0, Unknown}}, + {X86::VPUNPCKLDQZrrkz, {0, Unknown}}, + {X86::VPUNPCKLDQrm, {0, Unknown}}, + {X86::VPUNPCKLDQrr, {0, Unknown}}, + {X86::VPUNPCKLQDQYrm, {0, Unknown}}, + {X86::VPUNPCKLQDQYrr, {0, Unknown}}, + {X86::VPUNPCKLQDQZ128rm, {1, Unknown}}, + {X86::VPUNPCKLQDQZ128rmb, {1, Unknown}}, + {X86::VPUNPCKLQDQZ128rmbk, {1, Unknown}}, + {X86::VPUNPCKLQDQZ128rmbkz, {1, Unknown}}, + {X86::VPUNPCKLQDQZ128rmk, {1, Unknown}}, + {X86::VPUNPCKLQDQZ128rmkz, {1, Unknown}}, + {X86::VPUNPCKLQDQZ128rr, {0, Unknown}}, + {X86::VPUNPCKLQDQZ128rrk, {0, Unknown}}, + {X86::VPUNPCKLQDQZ128rrkz, {0, Unknown}}, + {X86::VPUNPCKLQDQZ256rm, {0, Unknown}}, + {X86::VPUNPCKLQDQZ256rmb, {0, Unknown}}, + {X86::VPUNPCKLQDQZ256rmbk, {0, Unknown}}, + {X86::VPUNPCKLQDQZ256rmbkz, {0, Unknown}}, + {X86::VPUNPCKLQDQZ256rmk, {0, Unknown}}, + {X86::VPUNPCKLQDQZ256rmkz, {0, Unknown}}, + {X86::VPUNPCKLQDQZ256rr, {0, Unknown}}, + {X86::VPUNPCKLQDQZ256rrk, {0, Unknown}}, + {X86::VPUNPCKLQDQZ256rrkz, {0, Unknown}}, + {X86::VPUNPCKLQDQZrm, {0, Unknown}}, + {X86::VPUNPCKLQDQZrmb, {0, Unknown}}, + {X86::VPUNPCKLQDQZrmbk, {0, Unknown}}, + {X86::VPUNPCKLQDQZrmbkz, {0, Unknown}}, + {X86::VPUNPCKLQDQZrmk, {0, Unknown}}, + {X86::VPUNPCKLQDQZrmkz, {0, Unknown}}, + {X86::VPUNPCKLQDQZrr, {0, Unknown}}, + {X86::VPUNPCKLQDQZrrk, {0, Unknown}}, + {X86::VPUNPCKLQDQZrrkz, {0, Unknown}}, + {X86::VPUNPCKLQDQrm, {0, Unknown}}, + {X86::VPUNPCKLQDQrr, {0, Unknown}}, + {X86::VPUNPCKLWDYrm, {0, Unknown}}, + {X86::VPUNPCKLWDYrr, {0, Unknown}}, + {X86::VPUNPCKLWDZ128rm, {1, Unknown}}, + {X86::VPUNPCKLWDZ128rmk, {1, Unknown}}, + {X86::VPUNPCKLWDZ128rmkz, {1, Unknown}}, + {X86::VPUNPCKLWDZ128rr, {0, Unknown}}, + {X86::VPUNPCKLWDZ128rrk, {0, Unknown}}, + {X86::VPUNPCKLWDZ128rrkz, {0, Unknown}}, + {X86::VPUNPCKLWDZ256rm, {0, Unknown}}, + {X86::VPUNPCKLWDZ256rmk, {0, Unknown}}, + {X86::VPUNPCKLWDZ256rmkz, {0, Unknown}}, + {X86::VPUNPCKLWDZ256rr, {0, Unknown}}, + {X86::VPUNPCKLWDZ256rrk, {0, Unknown}}, + {X86::VPUNPCKLWDZ256rrkz, {0, Unknown}}, + {X86::VPUNPCKLWDZrm, {0, Unknown}}, + {X86::VPUNPCKLWDZrmk, {0, Unknown}}, + {X86::VPUNPCKLWDZrmkz, {0, Unknown}}, + {X86::VPUNPCKLWDZrr, {0, Unknown}}, + {X86::VPUNPCKLWDZrrk, {0, Unknown}}, + {X86::VPUNPCKLWDZrrkz, {0, Unknown}}, + {X86::VPUNPCKLWDrm, {0, Unknown}}, + {X86::VPUNPCKLWDrr, {0, Unknown}}, + {X86::VPXORDZ128rm, {1, Unknown}}, + {X86::VPXORDZ128rmb, {1, Unknown}}, + {X86::VPXORDZ128rmbk, {1, Unknown}}, + {X86::VPXORDZ128rmbkz, {1, Unknown}}, + {X86::VPXORDZ128rmk, {1, Unknown}}, + {X86::VPXORDZ128rmkz, {1, Unknown}}, + {X86::VPXORDZ128rr, {0, Unknown}}, + {X86::VPXORDZ128rrk, {0, Unknown}}, + {X86::VPXORDZ128rrkz, {0, Unknown}}, + {X86::VPXORDZ256rm, {0, Unknown}}, + {X86::VPXORDZ256rmb, {0, Unknown}}, + {X86::VPXORDZ256rmbk, {0, Unknown}}, + {X86::VPXORDZ256rmbkz, {0, Unknown}}, + {X86::VPXORDZ256rmk, {0, Unknown}}, + {X86::VPXORDZ256rmkz, {0, Unknown}}, + {X86::VPXORDZ256rr, {0, Unknown}}, + {X86::VPXORDZ256rrk, {0, Unknown}}, + {X86::VPXORDZ256rrkz, {0, Unknown}}, + {X86::VPXORDZrm, {0, Unknown}}, + {X86::VPXORDZrmb, {0, Unknown}}, + {X86::VPXORDZrmbk, {0, Unknown}}, + {X86::VPXORDZrmbkz, {0, Unknown}}, + {X86::VPXORDZrmk, {0, Unknown}}, + {X86::VPXORDZrmkz, {0, Unknown}}, + {X86::VPXORDZrr, {0, Unknown}}, + {X86::VPXORDZrrk, {0, Unknown}}, + {X86::VPXORDZrrkz, {0, Unknown}}, + {X86::VPXORQZ128rm, {1, Unknown}}, + {X86::VPXORQZ128rmb, {1, Unknown}}, + {X86::VPXORQZ128rmbk, {1, Unknown}}, + {X86::VPXORQZ128rmbkz, {1, Unknown}}, + {X86::VPXORQZ128rmk, {1, Unknown}}, + {X86::VPXORQZ128rmkz, {1, Unknown}}, + {X86::VPXORQZ128rr, {0, Unknown}}, + {X86::VPXORQZ128rrk, {0, Unknown}}, + {X86::VPXORQZ128rrkz, {0, Unknown}}, + {X86::VPXORQZ256rm, {0, Unknown}}, + {X86::VPXORQZ256rmb, {0, Unknown}}, + {X86::VPXORQZ256rmbk, {0, Unknown}}, + {X86::VPXORQZ256rmbkz, {0, Unknown}}, + {X86::VPXORQZ256rmk, {0, Unknown}}, + {X86::VPXORQZ256rmkz, {0, Unknown}}, + {X86::VPXORQZ256rr, {0, Unknown}}, + {X86::VPXORQZ256rrk, {0, Unknown}}, + {X86::VPXORQZ256rrkz, {0, Unknown}}, + {X86::VPXORQZrm, {0, Unknown}}, + {X86::VPXORQZrmb, {0, Unknown}}, + {X86::VPXORQZrmbk, {0, Unknown}}, + {X86::VPXORQZrmbkz, {0, Unknown}}, + {X86::VPXORQZrmk, {0, Unknown}}, + {X86::VPXORQZrmkz, {0, Unknown}}, + {X86::VPXORQZrr, {0, Unknown}}, + {X86::VPXORQZrrk, {0, Unknown}}, + {X86::VPXORQZrrkz, {0, Unknown}}, + {X86::VPXORYrm, {0, Unknown}}, + {X86::VPXORYrr, {0, Unknown}}, + {X86::VPXORrm, {0, Unknown}}, + {X86::VPXORrr, {0, Unknown}}, + {X86::VRCPPSYm, {0, Unknown}}, + {X86::VRCPPSYr, {0, Unknown}}, + {X86::VRCPPSm, {0, Unknown}}, + {X86::VRCPPSr, {0, Unknown}}, + {X86::VRCPSSm, {0, Unknown}}, + {X86::VRCPSSm_Int, {0, Unknown}}, + {X86::VRCPSSr, {0, Unknown}}, + {X86::VRCPSSr_Int, {0, Unknown}}, + {X86::VROUNDPDYm, {0, Unknown}}, + {X86::VROUNDPDYr, {0, Unknown}}, + {X86::VROUNDPDm, {0, Unknown}}, + {X86::VROUNDPDr, {0, Unknown}}, + {X86::VROUNDPSYm, {0, Unknown}}, + {X86::VROUNDPSYr, {0, Unknown}}, + {X86::VROUNDPSm, {0, Unknown}}, + {X86::VROUNDPSr, {0, Unknown}}, + {X86::VROUNDSDm, {0, Unknown}}, + {X86::VROUNDSDm_Int, {0, Unknown}}, + {X86::VROUNDSDr, {0, Unknown}}, + {X86::VROUNDSDr_Int, {0, Unknown}}, + {X86::VROUNDSSm, {0, Unknown}}, + {X86::VROUNDSSm_Int, {0, Unknown}}, + {X86::VROUNDSSr, {0, Unknown}}, + {X86::VROUNDSSr_Int, {0, Unknown}}, + {X86::VSCATTERDPDZ128mr, {1, Unknown}}, + {X86::VSCATTERDPDZ256mr, {0, Unknown}}, + {X86::VSCATTERDPDZmr, {0, Unknown}}, + {X86::VSCATTERDPSZ128mr, {1, Unknown}}, + {X86::VSCATTERDPSZ256mr, {0, Unknown}}, + {X86::VSCATTERDPSZmr, {0, Unknown}}, + {X86::VSCATTERPF0DPDm, {0, Unknown}}, + {X86::VSCATTERPF0DPSm, {0, Unknown}}, + {X86::VSCATTERPF0QPDm, {0, Unknown}}, + {X86::VSCATTERPF0QPSm, {0, Unknown}}, + {X86::VSCATTERPF1DPDm, {0, Unknown}}, + {X86::VSCATTERPF1DPSm, {0, Unknown}}, + {X86::VSCATTERPF1QPDm, {0, Unknown}}, + {X86::VSCATTERPF1QPSm, {0, Unknown}}, + {X86::VSCATTERQPDZ128mr, {1, Unknown}}, + {X86::VSCATTERQPDZ256mr, {0, Unknown}}, + {X86::VSCATTERQPDZmr, {0, Unknown}}, + {X86::VSCATTERQPSZ128mr, {1, Unknown}}, + {X86::VSCATTERQPSZ256mr, {0, Unknown}}, + {X86::VSCATTERQPSZmr, {0, Unknown}}, + {X86::VSHUFF32X4Z256rmbi, {0, Unknown}}, + {X86::VSHUFF32X4Z256rmbik, {0, Unknown}}, + {X86::VSHUFF32X4Z256rmbikz, {0, Unknown}}, + {X86::VSHUFF32X4Z256rmi, {0, Unknown}}, + {X86::VSHUFF32X4Z256rmik, {0, Unknown}}, + {X86::VSHUFF32X4Z256rmikz, {0, Unknown}}, + {X86::VSHUFF32X4Z256rri, {0, Unknown}}, + {X86::VSHUFF32X4Z256rrik, {0, Unknown}}, + {X86::VSHUFF32X4Z256rrikz, {0, Unknown}}, + {X86::VSHUFF32X4Zrmbi, {0, Unknown}}, + {X86::VSHUFF32X4Zrmbik, {0, Unknown}}, + {X86::VSHUFF32X4Zrmbikz, {0, Unknown}}, + {X86::VSHUFF32X4Zrmi, {0, Unknown}}, + {X86::VSHUFF32X4Zrmik, {0, Unknown}}, + {X86::VSHUFF32X4Zrmikz, {0, Unknown}}, + {X86::VSHUFF32X4Zrri, {0, Unknown}}, + {X86::VSHUFF32X4Zrrik, {0, Unknown}}, + {X86::VSHUFF32X4Zrrikz, {0, Unknown}}, + {X86::VSHUFF64X2Z256rmbi, {0, Unknown}}, + {X86::VSHUFF64X2Z256rmbik, {0, Unknown}}, + {X86::VSHUFF64X2Z256rmbikz, {0, Unknown}}, + {X86::VSHUFF64X2Z256rmi, {0, Unknown}}, + {X86::VSHUFF64X2Z256rmik, {0, Unknown}}, + {X86::VSHUFF64X2Z256rmikz, {0, Unknown}}, + {X86::VSHUFF64X2Z256rri, {0, Unknown}}, + {X86::VSHUFF64X2Z256rrik, {0, Unknown}}, + {X86::VSHUFF64X2Z256rrikz, {0, Unknown}}, + {X86::VSHUFF64X2Zrmbi, {0, Unknown}}, + {X86::VSHUFF64X2Zrmbik, {0, Unknown}}, + {X86::VSHUFF64X2Zrmbikz, {0, Unknown}}, + {X86::VSHUFF64X2Zrmi, {0, Unknown}}, + {X86::VSHUFF64X2Zrmik, {0, Unknown}}, + {X86::VSHUFF64X2Zrmikz, {0, Unknown}}, + {X86::VSHUFF64X2Zrri, {0, Unknown}}, + {X86::VSHUFF64X2Zrrik, {0, Unknown}}, + {X86::VSHUFF64X2Zrrikz, {0, Unknown}}, + {X86::VSHUFI32X4Z256rmbi, {0, Unknown}}, + {X86::VSHUFI32X4Z256rmbik, {0, Unknown}}, + {X86::VSHUFI32X4Z256rmbikz, {0, Unknown}}, + {X86::VSHUFI32X4Z256rmi, {0, Unknown}}, + {X86::VSHUFI32X4Z256rmik, {0, Unknown}}, + {X86::VSHUFI32X4Z256rmikz, {0, Unknown}}, + {X86::VSHUFI32X4Z256rri, {0, Unknown}}, + {X86::VSHUFI32X4Z256rrik, {0, Unknown}}, + {X86::VSHUFI32X4Z256rrikz, {0, Unknown}}, + {X86::VSHUFI32X4Zrmbi, {0, Unknown}}, + {X86::VSHUFI32X4Zrmbik, {0, Unknown}}, + {X86::VSHUFI32X4Zrmbikz, {0, Unknown}}, + {X86::VSHUFI32X4Zrmi, {0, Unknown}}, + {X86::VSHUFI32X4Zrmik, {0, Unknown}}, + {X86::VSHUFI32X4Zrmikz, {0, Unknown}}, + {X86::VSHUFI32X4Zrri, {0, Unknown}}, + {X86::VSHUFI32X4Zrrik, {0, Unknown}}, + {X86::VSHUFI32X4Zrrikz, {0, Unknown}}, + {X86::VSHUFI64X2Z256rmbi, {0, Unknown}}, + {X86::VSHUFI64X2Z256rmbik, {0, Unknown}}, + {X86::VSHUFI64X2Z256rmbikz, {0, Unknown}}, + {X86::VSHUFI64X2Z256rmi, {0, Unknown}}, + {X86::VSHUFI64X2Z256rmik, {0, Unknown}}, + {X86::VSHUFI64X2Z256rmikz, {0, Unknown}}, + {X86::VSHUFI64X2Z256rri, {0, Unknown}}, + {X86::VSHUFI64X2Z256rrik, {0, Unknown}}, + {X86::VSHUFI64X2Z256rrikz, {0, Unknown}}, + {X86::VSHUFI64X2Zrmbi, {0, Unknown}}, + {X86::VSHUFI64X2Zrmbik, {0, Unknown}}, + {X86::VSHUFI64X2Zrmbikz, {0, Unknown}}, + {X86::VSHUFI64X2Zrmi, {0, Unknown}}, + {X86::VSHUFI64X2Zrmik, {0, Unknown}}, + {X86::VSHUFI64X2Zrmikz, {0, Unknown}}, + {X86::VSHUFI64X2Zrri, {0, Unknown}}, + {X86::VSHUFI64X2Zrrik, {0, Unknown}}, + {X86::VSHUFI64X2Zrrikz, {0, Unknown}}, + {X86::VSHUFPDYrmi, {0, Unknown}}, + {X86::VSHUFPDYrri, {0, Unknown}}, + {X86::VSHUFPDZ128rmbi, {1, Unknown}}, + {X86::VSHUFPDZ128rmbik, {1, Unknown}}, + {X86::VSHUFPDZ128rmbikz, {1, Unknown}}, + {X86::VSHUFPDZ128rmi, {1, Unknown}}, + {X86::VSHUFPDZ128rmik, {1, Unknown}}, + {X86::VSHUFPDZ128rmikz, {1, Unknown}}, + {X86::VSHUFPDZ128rri, {0, Unknown}}, + {X86::VSHUFPDZ128rrik, {0, Unknown}}, + {X86::VSHUFPDZ128rrikz, {0, Unknown}}, + {X86::VSHUFPDZ256rmbi, {0, Unknown}}, + {X86::VSHUFPDZ256rmbik, {0, Unknown}}, + {X86::VSHUFPDZ256rmbikz, {0, Unknown}}, + {X86::VSHUFPDZ256rmi, {0, Unknown}}, + {X86::VSHUFPDZ256rmik, {0, Unknown}}, + {X86::VSHUFPDZ256rmikz, {0, Unknown}}, + {X86::VSHUFPDZ256rri, {0, Unknown}}, + {X86::VSHUFPDZ256rrik, {0, Unknown}}, + {X86::VSHUFPDZ256rrikz, {0, Unknown}}, + {X86::VSHUFPDZrmbi, {0, Unknown}}, + {X86::VSHUFPDZrmbik, {0, Unknown}}, + {X86::VSHUFPDZrmbikz, {0, Unknown}}, + {X86::VSHUFPDZrmi, {0, Unknown}}, + {X86::VSHUFPDZrmik, {0, Unknown}}, + {X86::VSHUFPDZrmikz, {0, Unknown}}, + {X86::VSHUFPDZrri, {0, Unknown}}, + {X86::VSHUFPDZrrik, {0, Unknown}}, + {X86::VSHUFPDZrrikz, {0, Unknown}}, + {X86::VSHUFPDrmi, {0, Unknown}}, + {X86::VSHUFPDrri, {0, Unknown}}, + {X86::VSHUFPSYrmi, {0, Unknown}}, + {X86::VSHUFPSYrri, {0, Unknown}}, + {X86::VSHUFPSZ128rmbi, {1, Unknown}}, + {X86::VSHUFPSZ128rmbik, {1, Unknown}}, + {X86::VSHUFPSZ128rmbikz, {1, Unknown}}, + {X86::VSHUFPSZ128rmi, {1, Unknown}}, + {X86::VSHUFPSZ128rmik, {1, Unknown}}, + {X86::VSHUFPSZ128rmikz, {1, Unknown}}, + {X86::VSHUFPSZ128rri, {0, Unknown}}, + {X86::VSHUFPSZ128rrik, {0, Unknown}}, + {X86::VSHUFPSZ128rrikz, {0, Unknown}}, + {X86::VSHUFPSZ256rmbi, {0, Unknown}}, + {X86::VSHUFPSZ256rmbik, {0, Unknown}}, + {X86::VSHUFPSZ256rmbikz, {0, Unknown}}, + {X86::VSHUFPSZ256rmi, {0, Unknown}}, + {X86::VSHUFPSZ256rmik, {0, Unknown}}, + {X86::VSHUFPSZ256rmikz, {0, Unknown}}, + {X86::VSHUFPSZ256rri, {0, Unknown}}, + {X86::VSHUFPSZ256rrik, {0, Unknown}}, + {X86::VSHUFPSZ256rrikz, {0, Unknown}}, + {X86::VSHUFPSZrmbi, {0, Unknown}}, + {X86::VSHUFPSZrmbik, {0, Unknown}}, + {X86::VSHUFPSZrmbikz, {0, Unknown}}, + {X86::VSHUFPSZrmi, {0, Unknown}}, + {X86::VSHUFPSZrmik, {0, Unknown}}, + {X86::VSHUFPSZrmikz, {0, Unknown}}, + {X86::VSHUFPSZrri, {0, Unknown}}, + {X86::VSHUFPSZrrik, {0, Unknown}}, + {X86::VSHUFPSZrrikz, {0, Unknown}}, + {X86::VSHUFPSrmi, {0, Unknown}}, + {X86::VSHUFPSrri, {0, Unknown}}, + {X86::VSQRTPDYm, {0, Unknown}}, + {X86::VSQRTPDYr, {0, Unknown}}, + {X86::VSQRTPDZ128m, {0, Unknown}}, + {X86::VSQRTPDZ128mb, {0, Unknown}}, + {X86::VSQRTPDZ128mbk, {0, Unknown}}, + {X86::VSQRTPDZ128mbkz, {0, Unknown}}, + {X86::VSQRTPDZ128mk, {0, Unknown}}, + {X86::VSQRTPDZ128mkz, {0, Unknown}}, + {X86::VSQRTPDZ128r, {0, Unknown}}, + {X86::VSQRTPDZ128rk, {0, Unknown}}, + {X86::VSQRTPDZ128rkz, {0, Unknown}}, + {X86::VSQRTPDZ256m, {0, Unknown}}, + {X86::VSQRTPDZ256mb, {0, Unknown}}, + {X86::VSQRTPDZ256mbk, {0, Unknown}}, + {X86::VSQRTPDZ256mbkz, {0, Unknown}}, + {X86::VSQRTPDZ256mk, {0, Unknown}}, + {X86::VSQRTPDZ256mkz, {0, Unknown}}, + {X86::VSQRTPDZ256r, {0, Unknown}}, + {X86::VSQRTPDZ256rk, {0, Unknown}}, + {X86::VSQRTPDZ256rkz, {0, Unknown}}, + {X86::VSQRTPDZm, {0, Unknown}}, + {X86::VSQRTPDZmb, {0, Unknown}}, + {X86::VSQRTPDZmbk, {0, Unknown}}, + {X86::VSQRTPDZmbkz, {0, Unknown}}, + {X86::VSQRTPDZmk, {0, Unknown}}, + {X86::VSQRTPDZmkz, {0, Unknown}}, + {X86::VSQRTPDZr, {0, Unknown}}, + {X86::VSQRTPDZrb, {0, Unknown}}, + {X86::VSQRTPDZrbk, {0, Unknown}}, + {X86::VSQRTPDZrbkz, {0, Unknown}}, + {X86::VSQRTPDZrk, {0, Unknown}}, + {X86::VSQRTPDZrkz, {0, Unknown}}, + {X86::VSQRTPDm, {0, Unknown}}, + {X86::VSQRTPDr, {0, Unknown}}, + {X86::VSQRTPSYm, {0, Unknown}}, + {X86::VSQRTPSYr, {0, Unknown}}, + {X86::VSQRTPSZ128m, {0, Unknown}}, + {X86::VSQRTPSZ128mb, {0, Unknown}}, + {X86::VSQRTPSZ128mbk, {0, Unknown}}, + {X86::VSQRTPSZ128mbkz, {0, Unknown}}, + {X86::VSQRTPSZ128mk, {0, Unknown}}, + {X86::VSQRTPSZ128mkz, {0, Unknown}}, + {X86::VSQRTPSZ128r, {0, Unknown}}, + {X86::VSQRTPSZ128rk, {0, Unknown}}, + {X86::VSQRTPSZ128rkz, {0, Unknown}}, + {X86::VSQRTPSZ256m, {0, Unknown}}, + {X86::VSQRTPSZ256mb, {0, Unknown}}, + {X86::VSQRTPSZ256mbk, {0, Unknown}}, + {X86::VSQRTPSZ256mbkz, {0, Unknown}}, + {X86::VSQRTPSZ256mk, {0, Unknown}}, + {X86::VSQRTPSZ256mkz, {0, Unknown}}, + {X86::VSQRTPSZ256r, {0, Unknown}}, + {X86::VSQRTPSZ256rk, {0, Unknown}}, + {X86::VSQRTPSZ256rkz, {0, Unknown}}, + {X86::VSQRTPSZm, {0, Unknown}}, + {X86::VSQRTPSZmb, {0, Unknown}}, + {X86::VSQRTPSZmbk, {0, Unknown}}, + {X86::VSQRTPSZmbkz, {0, Unknown}}, + {X86::VSQRTPSZmk, {0, Unknown}}, + {X86::VSQRTPSZmkz, {0, Unknown}}, + {X86::VSQRTPSZr, {0, Unknown}}, + {X86::VSQRTPSZrb, {0, Unknown}}, + {X86::VSQRTPSZrbk, {0, Unknown}}, + {X86::VSQRTPSZrbkz, {0, Unknown}}, + {X86::VSQRTPSZrk, {0, Unknown}}, + {X86::VSQRTPSZrkz, {0, Unknown}}, + {X86::VSQRTPSm, {0, Unknown}}, + {X86::VSQRTPSr, {0, Unknown}}, + {X86::VSQRTSDZm, {0, Unknown}}, + {X86::VSQRTSDZm_Int, {0, Unknown}}, + {X86::VSQRTSDZm_Intk, {0, Unknown}}, + {X86::VSQRTSDZm_Intkz, {0, Unknown}}, + {X86::VSQRTSDZr, {0, Unknown}}, + {X86::VSQRTSDZr_Int, {0, Unknown}}, + {X86::VSQRTSDZr_Intk, {0, Unknown}}, + {X86::VSQRTSDZr_Intkz, {0, Unknown}}, + {X86::VSQRTSDZrb_Int, {0, Unknown}}, + {X86::VSQRTSDZrb_Intk, {0, Unknown}}, + {X86::VSQRTSDZrb_Intkz, {0, Unknown}}, + {X86::VSQRTSDm, {0, Unknown}}, + {X86::VSQRTSDm_Int, {0, Unknown}}, + {X86::VSQRTSDr, {0, Unknown}}, + {X86::VSQRTSDr_Int, {0, Unknown}}, + {X86::VSQRTSSZm, {0, Unknown}}, + {X86::VSQRTSSZm_Int, {0, Unknown}}, + {X86::VSQRTSSZm_Intk, {0, Unknown}}, + {X86::VSQRTSSZm_Intkz, {0, Unknown}}, + {X86::VSQRTSSZr, {0, Unknown}}, + {X86::VSQRTSSZr_Int, {0, Unknown}}, + {X86::VSQRTSSZr_Intk, {0, Unknown}}, + {X86::VSQRTSSZr_Intkz, {0, Unknown}}, + {X86::VSQRTSSZrb_Int, {0, Unknown}}, + {X86::VSQRTSSZrb_Intk, {0, Unknown}}, + {X86::VSQRTSSZrb_Intkz, {0, Unknown}}, + {X86::VSQRTSSm, {0, Unknown}}, + {X86::VSQRTSSm_Int, {0, Unknown}}, + {X86::VSQRTSSr, {0, Unknown}}, + {X86::VSQRTSSr_Int, {0, Unknown}}, + {X86::VSTMXCSR, {0, Unknown}}, + {X86::VSUBPDYrm, {0, Unknown}}, + {X86::VSUBPDYrr, {0, Unknown}}, + {X86::VSUBPDZ128rm, {1, Unknown}}, + {X86::VSUBPDZ128rmb, {1, Unknown}}, + {X86::VSUBPDZ128rmbk, {1, Unknown}}, + {X86::VSUBPDZ128rmbkz, {1, Unknown}}, + {X86::VSUBPDZ128rmk, {1, Unknown}}, + {X86::VSUBPDZ128rmkz, {1, Unknown}}, + {X86::VSUBPDZ128rr, {0, Unknown}}, + {X86::VSUBPDZ128rrk, {0, Unknown}}, + {X86::VSUBPDZ128rrkz, {0, Unknown}}, + {X86::VSUBPDZ256rm, {0, Unknown}}, + {X86::VSUBPDZ256rmb, {0, Unknown}}, + {X86::VSUBPDZ256rmbk, {0, Unknown}}, + {X86::VSUBPDZ256rmbkz, {0, Unknown}}, + {X86::VSUBPDZ256rmk, {0, Unknown}}, + {X86::VSUBPDZ256rmkz, {0, Unknown}}, + {X86::VSUBPDZ256rr, {0, Unknown}}, + {X86::VSUBPDZ256rrk, {0, Unknown}}, + {X86::VSUBPDZ256rrkz, {0, Unknown}}, + {X86::VSUBPDZrm, {0, Unknown}}, + {X86::VSUBPDZrmb, {0, Unknown}}, + {X86::VSUBPDZrmbk, {0, Unknown}}, + {X86::VSUBPDZrmbkz, {0, Unknown}}, + {X86::VSUBPDZrmk, {0, Unknown}}, + {X86::VSUBPDZrmkz, {0, Unknown}}, + {X86::VSUBPDZrr, {0, Unknown}}, + {X86::VSUBPDZrrb, {0, Unknown}}, + {X86::VSUBPDZrrbk, {0, Unknown}}, + {X86::VSUBPDZrrbkz, {0, Unknown}}, + {X86::VSUBPDZrrk, {0, Unknown}}, + {X86::VSUBPDZrrkz, {0, Unknown}}, + {X86::VSUBPDrm, {0, Unknown}}, + {X86::VSUBPDrr, {0, Unknown}}, + {X86::VSUBPSYrm, {0, Unknown}}, + {X86::VSUBPSYrr, {0, Unknown}}, + {X86::VSUBPSZ128rm, {1, Unknown}}, + {X86::VSUBPSZ128rmb, {1, Unknown}}, + {X86::VSUBPSZ128rmbk, {1, Unknown}}, + {X86::VSUBPSZ128rmbkz, {1, Unknown}}, + {X86::VSUBPSZ128rmk, {1, Unknown}}, + {X86::VSUBPSZ128rmkz, {1, Unknown}}, + {X86::VSUBPSZ128rr, {0, Unknown}}, + {X86::VSUBPSZ128rrk, {0, Unknown}}, + {X86::VSUBPSZ128rrkz, {0, Unknown}}, + {X86::VSUBPSZ256rm, {0, Unknown}}, + {X86::VSUBPSZ256rmb, {0, Unknown}}, + {X86::VSUBPSZ256rmbk, {0, Unknown}}, + {X86::VSUBPSZ256rmbkz, {0, Unknown}}, + {X86::VSUBPSZ256rmk, {0, Unknown}}, + {X86::VSUBPSZ256rmkz, {0, Unknown}}, + {X86::VSUBPSZ256rr, {0, Unknown}}, + {X86::VSUBPSZ256rrk, {0, Unknown}}, + {X86::VSUBPSZ256rrkz, {0, Unknown}}, + {X86::VSUBPSZrm, {0, Unknown}}, + {X86::VSUBPSZrmb, {0, Unknown}}, + {X86::VSUBPSZrmbk, {0, Unknown}}, + {X86::VSUBPSZrmbkz, {0, Unknown}}, + {X86::VSUBPSZrmk, {0, Unknown}}, + {X86::VSUBPSZrmkz, {0, Unknown}}, + {X86::VSUBPSZrr, {0, Unknown}}, + {X86::VSUBPSZrrb, {0, Unknown}}, + {X86::VSUBPSZrrbk, {0, Unknown}}, + {X86::VSUBPSZrrbkz, {0, Unknown}}, + {X86::VSUBPSZrrk, {0, Unknown}}, + {X86::VSUBPSZrrkz, {0, Unknown}}, + {X86::VSUBPSrm, {0, Unknown}}, + {X86::VSUBPSrr, {0, Unknown}}, + {X86::VSUBSDZrm, {0, Unknown}}, + {X86::VSUBSDZrm_Int, {0, Unknown}}, + {X86::VSUBSDZrm_Intk, {0, Unknown}}, + {X86::VSUBSDZrm_Intkz, {0, Unknown}}, + {X86::VSUBSDZrr, {0, Unknown}}, + {X86::VSUBSDZrr_Int, {0, Unknown}}, + {X86::VSUBSDZrr_Intk, {0, Unknown}}, + {X86::VSUBSDZrr_Intkz, {0, Unknown}}, + {X86::VSUBSDZrrb_Int, {0, Unknown}}, + {X86::VSUBSDZrrb_Intk, {0, Unknown}}, + {X86::VSUBSDZrrb_Intkz, {0, Unknown}}, + {X86::VSUBSDrm, {0, Unknown}}, + {X86::VSUBSDrm_Int, {0, Unknown}}, + {X86::VSUBSDrr, {0, Unknown}}, + {X86::VSUBSDrr_Int, {0, Unknown}}, + {X86::VSUBSSZrm, {0, Unknown}}, + {X86::VSUBSSZrm_Int, {0, Unknown}}, + {X86::VSUBSSZrm_Intk, {0, Unknown}}, + {X86::VSUBSSZrm_Intkz, {0, Unknown}}, + {X86::VSUBSSZrr, {0, Unknown}}, + {X86::VSUBSSZrr_Int, {0, Unknown}}, + {X86::VSUBSSZrr_Intk, {0, Unknown}}, + {X86::VSUBSSZrr_Intkz, {0, Unknown}}, + {X86::VSUBSSZrrb_Int, {0, Unknown}}, + {X86::VSUBSSZrrb_Intk, {0, Unknown}}, + {X86::VSUBSSZrrb_Intkz, {0, Unknown}}, + {X86::VSUBSSrm, {0, Unknown}}, + {X86::VSUBSSrm_Int, {0, Unknown}}, + {X86::VSUBSSrr, {0, Unknown}}, + {X86::VSUBSSrr_Int, {0, Unknown}}, + {X86::VTESTPDYrm, {0, Unknown}}, + {X86::VTESTPDYrr, {0, Unknown}}, + {X86::VTESTPDrm, {0, Unknown}}, + {X86::VTESTPDrr, {0, Unknown}}, + {X86::VTESTPSYrm, {0, Unknown}}, + {X86::VTESTPSYrr, {0, Unknown}}, + {X86::VTESTPSrm, {0, Unknown}}, + {X86::VTESTPSrr, {0, Unknown}}, + {X86::VUCOMISDZrm, {0, Unknown}}, + {X86::VUCOMISDZrm_Int, {0, Unknown}}, + {X86::VUCOMISDZrr, {0, Unknown}}, + {X86::VUCOMISDZrr_Int, {0, Unknown}}, + {X86::VUCOMISDZrrb, {0, Unknown}}, + {X86::VUCOMISDrm, {0, Unknown}}, + {X86::VUCOMISDrm_Int, {0, Unknown}}, + {X86::VUCOMISDrr, {0, Unknown}}, + {X86::VUCOMISDrr_Int, {0, Unknown}}, + {X86::VUCOMISSZrm, {0, Unknown}}, + {X86::VUCOMISSZrm_Int, {0, Unknown}}, + {X86::VUCOMISSZrr, {0, Unknown}}, + {X86::VUCOMISSZrr_Int, {0, Unknown}}, + {X86::VUCOMISSZrrb, {0, Unknown}}, + {X86::VUCOMISSrm, {0, Unknown}}, + {X86::VUCOMISSrm_Int, {0, Unknown}}, + {X86::VUCOMISSrr, {0, Unknown}}, + {X86::VUCOMISSrr_Int, {0, Unknown}}, + {X86::VUNPCKHPDYrm, {0, Unknown}}, + {X86::VUNPCKHPDYrr, {0, Unknown}}, + {X86::VUNPCKHPDZ128rm, {1, Unknown}}, + {X86::VUNPCKHPDZ128rmb, {1, Unknown}}, + {X86::VUNPCKHPDZ128rmbk, {1, Unknown}}, + {X86::VUNPCKHPDZ128rmbkz, {1, Unknown}}, + {X86::VUNPCKHPDZ128rmk, {1, Unknown}}, + {X86::VUNPCKHPDZ128rmkz, {1, Unknown}}, + {X86::VUNPCKHPDZ128rr, {0, Unknown}}, + {X86::VUNPCKHPDZ128rrk, {0, Unknown}}, + {X86::VUNPCKHPDZ128rrkz, {0, Unknown}}, + {X86::VUNPCKHPDZ256rm, {0, Unknown}}, + {X86::VUNPCKHPDZ256rmb, {0, Unknown}}, + {X86::VUNPCKHPDZ256rmbk, {0, Unknown}}, + {X86::VUNPCKHPDZ256rmbkz, {0, Unknown}}, + {X86::VUNPCKHPDZ256rmk, {0, Unknown}}, + {X86::VUNPCKHPDZ256rmkz, {0, Unknown}}, + {X86::VUNPCKHPDZ256rr, {0, Unknown}}, + {X86::VUNPCKHPDZ256rrk, {0, Unknown}}, + {X86::VUNPCKHPDZ256rrkz, {0, Unknown}}, + {X86::VUNPCKHPDZrm, {0, Unknown}}, + {X86::VUNPCKHPDZrmb, {0, Unknown}}, + {X86::VUNPCKHPDZrmbk, {0, Unknown}}, + {X86::VUNPCKHPDZrmbkz, {0, Unknown}}, + {X86::VUNPCKHPDZrmk, {0, Unknown}}, + {X86::VUNPCKHPDZrmkz, {0, Unknown}}, + {X86::VUNPCKHPDZrr, {0, Unknown}}, + {X86::VUNPCKHPDZrrk, {0, Unknown}}, + {X86::VUNPCKHPDZrrkz, {0, Unknown}}, + {X86::VUNPCKHPDrm, {0, Unknown}}, + {X86::VUNPCKHPDrr, {0, Unknown}}, + {X86::VUNPCKHPSYrm, {0, Unknown}}, + {X86::VUNPCKHPSYrr, {0, Unknown}}, + {X86::VUNPCKHPSZ128rm, {1, Unknown}}, + {X86::VUNPCKHPSZ128rmb, {1, Unknown}}, + {X86::VUNPCKHPSZ128rmbk, {1, Unknown}}, + {X86::VUNPCKHPSZ128rmbkz, {1, Unknown}}, + {X86::VUNPCKHPSZ128rmk, {1, Unknown}}, + {X86::VUNPCKHPSZ128rmkz, {1, Unknown}}, + {X86::VUNPCKHPSZ128rr, {0, Unknown}}, + {X86::VUNPCKHPSZ128rrk, {0, Unknown}}, + {X86::VUNPCKHPSZ128rrkz, {0, Unknown}}, + {X86::VUNPCKHPSZ256rm, {0, Unknown}}, + {X86::VUNPCKHPSZ256rmb, {0, Unknown}}, + {X86::VUNPCKHPSZ256rmbk, {0, Unknown}}, + {X86::VUNPCKHPSZ256rmbkz, {0, Unknown}}, + {X86::VUNPCKHPSZ256rmk, {0, Unknown}}, + {X86::VUNPCKHPSZ256rmkz, {0, Unknown}}, + {X86::VUNPCKHPSZ256rr, {0, Unknown}}, + {X86::VUNPCKHPSZ256rrk, {0, Unknown}}, + {X86::VUNPCKHPSZ256rrkz, {0, Unknown}}, + {X86::VUNPCKHPSZrm, {0, Unknown}}, + {X86::VUNPCKHPSZrmb, {0, Unknown}}, + {X86::VUNPCKHPSZrmbk, {0, Unknown}}, + {X86::VUNPCKHPSZrmbkz, {0, Unknown}}, + {X86::VUNPCKHPSZrmk, {0, Unknown}}, + {X86::VUNPCKHPSZrmkz, {0, Unknown}}, + {X86::VUNPCKHPSZrr, {0, Unknown}}, + {X86::VUNPCKHPSZrrk, {0, Unknown}}, + {X86::VUNPCKHPSZrrkz, {0, Unknown}}, + {X86::VUNPCKHPSrm, {0, Unknown}}, + {X86::VUNPCKHPSrr, {0, Unknown}}, + {X86::VUNPCKLPDYrm, {0, Unknown}}, + {X86::VUNPCKLPDYrr, {0, Unknown}}, + {X86::VUNPCKLPDZ128rm, {1, Unknown}}, + {X86::VUNPCKLPDZ128rmb, {1, Unknown}}, + {X86::VUNPCKLPDZ128rmbk, {1, Unknown}}, + {X86::VUNPCKLPDZ128rmbkz, {1, Unknown}}, + {X86::VUNPCKLPDZ128rmk, {1, Unknown}}, + {X86::VUNPCKLPDZ128rmkz, {1, Unknown}}, + {X86::VUNPCKLPDZ128rr, {0, Unknown}}, + {X86::VUNPCKLPDZ128rrk, {0, Unknown}}, + {X86::VUNPCKLPDZ128rrkz, {0, Unknown}}, + {X86::VUNPCKLPDZ256rm, {0, Unknown}}, + {X86::VUNPCKLPDZ256rmb, {0, Unknown}}, + {X86::VUNPCKLPDZ256rmbk, {0, Unknown}}, + {X86::VUNPCKLPDZ256rmbkz, {0, Unknown}}, + {X86::VUNPCKLPDZ256rmk, {0, Unknown}}, + {X86::VUNPCKLPDZ256rmkz, {0, Unknown}}, + {X86::VUNPCKLPDZ256rr, {0, Unknown}}, + {X86::VUNPCKLPDZ256rrk, {0, Unknown}}, + {X86::VUNPCKLPDZ256rrkz, {0, Unknown}}, + {X86::VUNPCKLPDZrm, {0, Unknown}}, + {X86::VUNPCKLPDZrmb, {0, Unknown}}, + {X86::VUNPCKLPDZrmbk, {0, Unknown}}, + {X86::VUNPCKLPDZrmbkz, {0, Unknown}}, + {X86::VUNPCKLPDZrmk, {0, Unknown}}, + {X86::VUNPCKLPDZrmkz, {0, Unknown}}, + {X86::VUNPCKLPDZrr, {0, Unknown}}, + {X86::VUNPCKLPDZrrk, {0, Unknown}}, + {X86::VUNPCKLPDZrrkz, {0, Unknown}}, + {X86::VUNPCKLPDrm, {0, Unknown}}, + {X86::VUNPCKLPDrr, {0, Unknown}}, + {X86::VUNPCKLPSYrm, {0, Unknown}}, + {X86::VUNPCKLPSYrr, {0, Unknown}}, + {X86::VUNPCKLPSZ128rm, {1, Unknown}}, + {X86::VUNPCKLPSZ128rmb, {1, Unknown}}, + {X86::VUNPCKLPSZ128rmbk, {1, Unknown}}, + {X86::VUNPCKLPSZ128rmbkz, {1, Unknown}}, + {X86::VUNPCKLPSZ128rmk, {1, Unknown}}, + {X86::VUNPCKLPSZ128rmkz, {1, Unknown}}, + {X86::VUNPCKLPSZ128rr, {0, Unknown}}, + {X86::VUNPCKLPSZ128rrk, {0, Unknown}}, + {X86::VUNPCKLPSZ128rrkz, {0, Unknown}}, + {X86::VUNPCKLPSZ256rm, {0, Unknown}}, + {X86::VUNPCKLPSZ256rmb, {0, Unknown}}, + {X86::VUNPCKLPSZ256rmbk, {0, Unknown}}, + {X86::VUNPCKLPSZ256rmbkz, {0, Unknown}}, + {X86::VUNPCKLPSZ256rmk, {0, Unknown}}, + {X86::VUNPCKLPSZ256rmkz, {0, Unknown}}, + {X86::VUNPCKLPSZ256rr, {0, Unknown}}, + {X86::VUNPCKLPSZ256rrk, {0, Unknown}}, + {X86::VUNPCKLPSZ256rrkz, {0, Unknown}}, + {X86::VUNPCKLPSZrm, {0, Unknown}}, + {X86::VUNPCKLPSZrmb, {0, Unknown}}, + {X86::VUNPCKLPSZrmbk, {0, Unknown}}, + {X86::VUNPCKLPSZrmbkz, {0, Unknown}}, + {X86::VUNPCKLPSZrmk, {0, Unknown}}, + {X86::VUNPCKLPSZrmkz, {0, Unknown}}, + {X86::VUNPCKLPSZrr, {0, Unknown}}, + {X86::VUNPCKLPSZrrk, {0, Unknown}}, + {X86::VUNPCKLPSZrrkz, {0, Unknown}}, + {X86::VUNPCKLPSrm, {0, Unknown}}, + {X86::VUNPCKLPSrr, {0, Unknown}}, + {X86::VXORPDYrm, {0, Unknown}}, + {X86::VXORPDYrr, {0, Unknown}}, + {X86::VXORPDZ128rm, {1, Unknown}}, + {X86::VXORPDZ128rmb, {1, Unknown}}, + {X86::VXORPDZ128rmbk, {1, Unknown}}, + {X86::VXORPDZ128rmbkz, {1, Unknown}}, + {X86::VXORPDZ128rmk, {1, Unknown}}, + {X86::VXORPDZ128rmkz, {1, Unknown}}, + {X86::VXORPDZ128rr, {0, Unknown}}, + {X86::VXORPDZ128rrk, {0, Unknown}}, + {X86::VXORPDZ128rrkz, {0, Unknown}}, + {X86::VXORPDZ256rm, {0, Unknown}}, + {X86::VXORPDZ256rmb, {0, Unknown}}, + {X86::VXORPDZ256rmbk, {0, Unknown}}, + {X86::VXORPDZ256rmbkz, {0, Unknown}}, + {X86::VXORPDZ256rmk, {0, Unknown}}, + {X86::VXORPDZ256rmkz, {0, Unknown}}, + {X86::VXORPDZ256rr, {0, Unknown}}, + {X86::VXORPDZ256rrk, {0, Unknown}}, + {X86::VXORPDZ256rrkz, {0, Unknown}}, + {X86::VXORPDZrm, {0, Unknown}}, + {X86::VXORPDZrmb, {0, Unknown}}, + {X86::VXORPDZrmbk, {0, Unknown}}, + {X86::VXORPDZrmbkz, {0, Unknown}}, + {X86::VXORPDZrmk, {0, Unknown}}, + {X86::VXORPDZrmkz, {0, Unknown}}, + {X86::VXORPDZrr, {0, Unknown}}, + {X86::VXORPDZrrk, {0, Unknown}}, + {X86::VXORPDZrrkz, {0, Unknown}}, + {X86::VXORPDrm, {0, Unknown}}, + {X86::VXORPDrr, {0, Unknown}}, + {X86::VXORPSYrm, {0, Unknown}}, + {X86::VXORPSYrr, {0, Unknown}}, + {X86::VXORPSZ128rm, {1, Unknown}}, + {X86::VXORPSZ128rmb, {1, Unknown}}, + {X86::VXORPSZ128rmbk, {1, Unknown}}, + {X86::VXORPSZ128rmbkz, {1, Unknown}}, + {X86::VXORPSZ128rmk, {1, Unknown}}, + {X86::VXORPSZ128rmkz, {1, Unknown}}, + {X86::VXORPSZ128rr, {0, Unknown}}, + {X86::VXORPSZ128rrk, {0, Unknown}}, + {X86::VXORPSZ128rrkz, {0, Unknown}}, + {X86::VXORPSZ256rm, {0, Unknown}}, + {X86::VXORPSZ256rmb, {0, Unknown}}, + {X86::VXORPSZ256rmbk, {0, Unknown}}, + {X86::VXORPSZ256rmbkz, {0, Unknown}}, + {X86::VXORPSZ256rmk, {0, Unknown}}, + {X86::VXORPSZ256rmkz, {0, Unknown}}, + {X86::VXORPSZ256rr, {0, Unknown}}, + {X86::VXORPSZ256rrk, {0, Unknown}}, + {X86::VXORPSZ256rrkz, {0, Unknown}}, + {X86::VXORPSZrm, {0, Unknown}}, + {X86::VXORPSZrmb, {0, Unknown}}, + {X86::VXORPSZrmbk, {0, Unknown}}, + {X86::VXORPSZrmbkz, {0, Unknown}}, + {X86::VXORPSZrmk, {0, Unknown}}, + {X86::VXORPSZrmkz, {0, Unknown}}, + {X86::VXORPSZrr, {0, Unknown}}, + {X86::VXORPSZrrk, {0, Unknown}}, + {X86::VXORPSZrrkz, {0, Unknown}}, + {X86::VXORPSrm, {0, Unknown}}, + {X86::VXORPSrr, {0, Unknown}}, + {X86::VZEROALL, {0, Unknown}}, + {X86::VZEROUPPER, {0, Unknown}}, + {X86::V_SET0, {0, Unknown}}, + {X86::V_SETALLONES, {0, Unknown}}, + {X86::WAIT, {0, Unknown}}, + {X86::WBINVD, {0, Unknown}}, + {X86::WIN_ALLOCA_32, {0, Unknown}}, + {X86::WIN_ALLOCA_64, {0, Unknown}}, + {X86::WRFLAGS32, {0, Unknown}}, + {X86::WRFLAGS64, {0, Unknown}}, + {X86::WRFSBASE, {0, Unknown}}, + {X86::WRFSBASE64, {0, Unknown}}, + {X86::WRGSBASE, {0, Unknown}}, + {X86::WRGSBASE64, {0, Unknown}}, + {X86::WRMSR, {0, Unknown}}, + {X86::WRPKRU, {0, Unknown}}, + {X86::WRPKRUr, {0, Unknown}}, + {X86::WRSSD, {0, Unknown}}, + {X86::WRSSQ, {0, Unknown}}, + {X86::WRUSSD, {0, Unknown}}, + {X86::WRUSSQ, {0, Unknown}}, + {X86::XABORT, {0, Unknown}}, + {X86::XABORT_DEF, {0, Unknown}}, + {X86::XACQUIRE_PREFIX, {0, Unknown}}, + {X86::XADD16rm, {2, Unknown}}, + {X86::XADD16rr, {0, Unknown}}, + {X86::XADD32rm, {4, Unknown}}, + {X86::XADD32rr, {0, Unknown}}, + {X86::XADD64rm, {8, Unknown}}, + {X86::XADD64rr, {0, Unknown}}, + {X86::XADD8rm, {1, Unknown}}, + {X86::XADD8rr, {0, Unknown}}, + {X86::XBEGIN, {0, Unknown}}, + {X86::XBEGIN_2, {0, Unknown}}, + {X86::XBEGIN_4, {0, Unknown}}, + {X86::XCHG16ar, {0, Unknown}}, + {X86::XCHG16rm, {2, Unknown}}, + {X86::XCHG16rr, {0, Unknown}}, + {X86::XCHG32ar, {0, Unknown}}, + {X86::XCHG32rm, {4, Unknown}}, + {X86::XCHG32rr, {0, Unknown}}, + {X86::XCHG64ar, {0, Unknown}}, + {X86::XCHG64rm, {8, Unknown}}, + {X86::XCHG64rr, {0, Unknown}}, + {X86::XCHG8rm, {1, Unknown}}, + {X86::XCHG8rr, {0, Unknown}}, + {X86::XCH_F, {0, Unknown}}, + {X86::XCRYPTCBC, {0, Unknown}}, + {X86::XCRYPTCFB, {0, Unknown}}, + {X86::XCRYPTCTR, {0, Unknown}}, + {X86::XCRYPTECB, {0, Unknown}}, + {X86::XCRYPTOFB, {0, Unknown}}, + {X86::XEND, {0, Unknown}}, + {X86::XGETBV, {0, Unknown}}, + {X86::XLAT, {0, Unknown}}, + {X86::XOR16i16, {0, Unknown}}, + {X86::XOR16mi, {2, Unknown}}, + {X86::XOR16mi8, {2, Unknown}}, + {X86::XOR16mr, {2, Unknown}}, + {X86::XOR16ri, {0, Unknown}}, + {X86::XOR16ri8, {0, Unknown}}, + {X86::XOR16rm, {2, Unknown}}, + {X86::XOR16rr, {0, Unknown}}, + {X86::XOR16rr_REV, {0, Unknown}}, + {X86::XOR32_FP, {0, Unknown}}, + {X86::XOR32i32, {0, Unknown}}, + {X86::XOR32mi, {4, Unknown}}, + {X86::XOR32mi8, {4, Unknown}}, + {X86::XOR32mr, {4, Unknown}}, + {X86::XOR32ri, {0, Unknown}}, + {X86::XOR32ri8, {0, Unknown}}, + {X86::XOR32rm, {4, Unknown}}, + {X86::XOR32rr, {0, BINARY_OP_RR}}, + {X86::XOR32rr_REV, {0, Unknown}}, + {X86::XOR64_FP, {0, Unknown}}, + {X86::XOR64i32, {0, Unknown}}, + {X86::XOR64mi32, {8, Unknown}}, + {X86::XOR64mi8, {8, Unknown}}, + {X86::XOR64mr, {8, Unknown}}, + {X86::XOR64ri32, {0, Unknown}}, + {X86::XOR64ri8, {0, Unknown}}, + {X86::XOR64rm, {8, Unknown}}, + {X86::XOR64rr, {0, BINARY_OP_RR}}, + {X86::XOR64rr_REV, {0, Unknown}}, + {X86::XOR8i8, {0, Unknown}}, + {X86::XOR8mi, {1, Unknown}}, + {X86::XOR8mi8, {1, Unknown}}, + {X86::XOR8mr, {1, Unknown}}, + {X86::XOR8ri, {0, BINARY_OP_WITH_IMM}}, + {X86::XOR8ri8, {0, Unknown}}, + {X86::XOR8rm, {1, Unknown}}, + {X86::XOR8rr, {0, Unknown}}, + {X86::XOR8rr_REV, {0, Unknown}}, + {X86::XORPDrm, {0, Unknown}}, + {X86::XORPDrr, {0, Unknown}}, + {X86::XORPSrm, {0, Unknown}}, + {X86::XORPSrr, {0, Unknown}}, + {X86::XRELEASE_PREFIX, {0, Unknown}}, + {X86::XRSTOR, {0, Unknown}}, + {X86::XRSTOR64, {0, Unknown}}, + {X86::XRSTORS, {0, Unknown}}, + {X86::XRSTORS64, {0, Unknown}}, + {X86::XSAVE, {0, Unknown}}, + {X86::XSAVE64, {0, Unknown}}, + {X86::XSAVEC, {0, Unknown}}, + {X86::XSAVEC64, {0, Unknown}}, + {X86::XSAVEOPT, {0, Unknown}}, + {X86::XSAVEOPT64, {0, Unknown}}, + {X86::XSAVES, {0, Unknown}}, + {X86::XSAVES64, {0, Unknown}}, + {X86::XSETBV, {0, Unknown}}, + {X86::XSHA1, {0, Unknown}}, + {X86::XSHA256, {0, Unknown}}, + {X86::XSTORE, {0, Unknown}}, + {X86::XTEST, {0, Unknown}}}; + +static inline InstructionKind getInstructionKind(unsigned int opc) { + auto iter = mctoll::X86AddlInstrInfo.find(opc); + assert(iter != mctoll::X86AddlInstrInfo.end() && "Unknown opcode "); + return iter->second.InstKind; +} + +static inline unsigned short getInstructionMemOpSize(unsigned int opc) { + auto iter = mctoll::X86AddlInstrInfo.find(opc); + assert(iter != mctoll::X86AddlInstrInfo.end() && "Unknown opcode "); + return iter->second.MemOpSize; +} + +static inline bool isNoop(unsigned int opc) { + return (getInstructionKind(opc) == mctoll::InstructionKind::NOOP); +} + +} // namespace mctoll + +#endif // LLVM_TOOLS_LLVM_MCTOLL_X86_X86ADDITIONALINSTRINFO_H Index: tools/llvm-mctoll/X86/X86MachineInstructionRaiser.h =================================================================== --- /dev/null +++ tools/llvm-mctoll/X86/X86MachineInstructionRaiser.h @@ -0,0 +1,162 @@ +//==-- X86MachineInstructionRaiser.h - Binary raiser utility llvm-mctoll =====// +// +// The LLVM Compiler Infrastructure +// +// This file is distributed under the University of Illinois Open Source +// License. See LICENSE.TXT for details. +// +//===----------------------------------------------------------------------===// +// +// This file contains the declaration of X86MachineInstructionRaiser +// class for use by llvm-mctoll. +// +//===----------------------------------------------------------------------===// +#ifndef LLVM_TOOLS_LLVM_MCTOLL_X86_X86MACHINEINSTRUCTIONRAISER_H +#define LLVM_TOOLS_LLVM_MCTOLL_X86_X86MACHINEINSTRUCTIONRAISER_H + +#include "MachineInstructionRaiser.h" +#include "X86AdditionalInstrInfo.h" + +// X86AddressMode is a struct. So provide a Compare operator. +struct X86AddressModeCompare { + bool operator()(const X86AddressMode &lhs, const X86AddressMode &rhs) const { + return ((lhs.Scale < rhs.Scale) || (lhs.IndexReg < rhs.IndexReg) || + (lhs.Disp < rhs.Disp)); + } +}; + +using MemRefToFrameIndexMapType = + std::map; +using MemRefToFrameIndexMapTypeIter = MemRefToFrameIndexMapType::iterator; + +using MBBNumToBBMap = std::map; + +class X86MachineInstructionRaiser : public MachineInstructionRaiser { +public: + X86MachineInstructionRaiser() = delete; + X86MachineInstructionRaiser(MachineFunction &machFunc, Module &m, + const ModuleRaiser *mr, MCInstRaiser *mcir); + bool raise(); + +private: + // Bit positions used for individual status flags of EFLAGS register. + // Note : only those that are currently used are represented here. + enum { + EFLAGS_CF = 0, + EFLAGS_PF = 2, + EFLAGS_AF = 4, + EFLAGS_ZF = 6, + EFLAGS_SF = 7, + EFLAGS_OF = 11, + EFLAGS_UNDEFINED = 32 + }; + // Map of physical registers -> virtual registers + std::map physToVirtMap; + + // Map of physical registers -> Value * created + std::map physToValueMap; + // std::stack FPURegisterStack; + static const uint8_t FPUSTACK_SZ = 8; + struct { + int8_t TOP; + Value *Regs[FPUSTACK_SZ]; + } FPUStack; + // A map of memory references in the MachineFunction code to stack + // frame slot index + MemRefToFrameIndexMapType memRefToFrameIndexMap; + + // A map of memory references in the MachineFunction code to + // global variables + + // A map of MachineFunctionBlock number to BasicBlock * + MBBNumToBBMap mbbToBBMap; + + // Commonly used LLVM data structures during this phase + MachineRegisterInfo &machineRegInfo; + const X86Subtarget &x86TargetInfo; + const X86InstrInfo *x86InstrInfo; + const X86RegisterInfo *x86RegisterInfo; + + bool raiseMachineFunction(); + FunctionType *getRaisedFunctionPrototype(); + // This raises MachineInstr to MachineInstruction + bool raiseMachineInstr(MachineInstr &, BasicBlock *); + // Cleanup MachineBasicBlocks + bool deleteNOOPInstrMI(MachineBasicBlock &, MachineBasicBlock::iterator); + bool deleteNOOPInstrMF(); + + // Raise specific classes of instructions + bool raisePushInstruction(const MachineInstr &); + bool raisePopInstruction(const MachineInstr &); + + bool raiseMemRefMachineInstr(const MachineInstr &, BasicBlock *); + bool raiseReturnMachineInstr(const MachineInstr &, BasicBlock *); + bool raiseGenericMachineInstr(const MachineInstr &, BasicBlock *); + + bool raiseConvertBWWDDQMachineInstr(const MachineInstr &, BasicBlock *); + bool raiseConvertWDDQQOMachineInstr(const MachineInstr &, BasicBlock *); + bool raiseLEAMachineInstr(const MachineInstr &, BasicBlock *); + bool raiseMoveRegToRegMachineInstr(const MachineInstr &, BasicBlock *); + bool raiseMoveImmToRegMachineInstr(const MachineInstr &, BasicBlock *); + bool raiseBinaryOpRegToRegMachineInstr(const MachineInstr &, BasicBlock *); + bool raiseBinaryOpImmToRegMachineInstr(const MachineInstr &, BasicBlock *); + bool raiseSetCCMachineInstr(const MachineInstr &, BasicBlock *); + + bool raiseCompareMachineInstr(const MachineInstr &, BasicBlock *, bool, + Value *); + + bool raiseCallMachineInstr(const MachineInstr &, BasicBlock *); + + bool raiseMoveToMemInstr(const MachineInstr &, BasicBlock *, Value *); + bool raiseMoveFromMemInstr(const MachineInstr &, BasicBlock *, Value *); + bool raiseBinaryOpMemToRegInstr(const MachineInstr &, BasicBlock *, Value *); + bool raiseDivideInstr(const MachineInstr &, BasicBlock *, Value *); + bool raiseLoadIntToFloatRegInstr(const MachineInstr &, BasicBlock *, Value *); + bool raiseStoreIntToFloatRegInstr(const MachineInstr &, BasicBlock *, + Value *); + bool raiseFPURegisterOpInstr(const MachineInstr &, BasicBlock *); + + bool raiseBranchMachineInstrs(); + bool raiseDirectBranchMachineInstr(ControlTransferInfo *); + bool raiseIndirectBranchMachineInstr(ControlTransferInfo *); + + // Method to record information that is used in a second pass + // to raise control transfer instructions in a second pass. + bool recordMachineInstrInfo(const MachineInstr &, BasicBlock *); + + bool insertAllocaInEntryBlock(Instruction *alloca); + + // FPU Stack access functions + void FPURegisterStackPush(Value *); + void FPURegisterStackPop(); + Value *FPURegisterStackGetValueAt(int8_t); + void FPURegisterStackSetValueAt(int8_t, Value *); + Value *FPURegisterStackTop(); + + // Helper functions + int getMemoryRefOpIndex(const MachineInstr &); + Value *getGlobalVariableValueAt(const MachineInstr &, uint64_t); + const Value *getOrCreateGlobalRODataValueAtAt(const MachineInstr &, uint64_t); + Value *getMemoryAddressExprValue(const MachineInstr &, BasicBlock *); + Value *createPCRelativeAccesssValue(const MachineInstr &, BasicBlock *); + + bool changePhysRegToVirtReg(MachineInstr &); + + unsigned int find64BitSuperReg(unsigned int); + Value *findPhysRegSSAValue(unsigned int); + Value *matchSSAValueToSrcRegSize(const MachineInstr &mi, unsigned SrcOpIndex, + BasicBlock *curBlock); + + std::pair::iterator, bool> + updatePhysRegSSAValue(unsigned int PhysReg, Value *); + Type *getFunctionReturnType(); + Type *getReturnTypeFromMBB(MachineBasicBlock &MBB); + Function *getTargetFunctionAtPLTOffset(const MachineInstr &, uint64_t); + Value *getStackAllocatedValue(const MachineInstr &, BasicBlock *, int); + int getArgumentNumber(unsigned PReg); + bool buildFuncArgTypeVector(const std::set &, + std::vector &); + + Value *getRegValue(unsigned); +}; +#endif // LLVM_TOOLS_LLVM_MCTOLL_X86_X86ELIMINATEPROLOGEPILOG_H Index: tools/llvm-mctoll/X86/X86MachineInstructionRaiser.cpp =================================================================== --- /dev/null +++ tools/llvm-mctoll/X86/X86MachineInstructionRaiser.cpp @@ -0,0 +1,4091 @@ +//==-- X86MachineInstructionRaiser.cpp - Binary raiser utility llvm-mctoll -==// +// +// The LLVM Compiler Infrastructure +// +// This file is distributed under the University of Illinois Open Source +// License. See LICENSE.TXT for details. +// +//===----------------------------------------------------------------------===// +// +// This file contains the implementation of X86MachineInstructionRaiser class +// for use by llvm-mctoll. +// +//===----------------------------------------------------------------------===// +#include "X86MachineInstructionRaiser.h" +#include "ExternalFunctions.h" +#include "X86InstrBuilder.h" +#include "llvm/ADT/SmallVector.h" +#include "llvm/CodeGen/LivePhysRegs.h" +#include "llvm/CodeGen/MachineInstr.h" +#include "llvm/CodeGen/MachineRegisterInfo.h" +#include "llvm/CodeGen/TargetInstrInfo.h" +#include "llvm/CodeGen/TargetRegisterInfo.h" +#include "llvm/CodeGen/TargetSubtargetInfo.h" +#include "llvm/IR/Instructions.h" +#include "llvm/Object/ELF.h" +#include "llvm/Object/ELFObjectFile.h" +#include "llvm/Support/raw_ostream.h" +#include "llvm/Target/TargetMachine.h" +#include +#include + +using namespace llvm; +using namespace mctoll; + +// Constructor + +X86MachineInstructionRaiser::X86MachineInstructionRaiser( + MachineFunction &machFunc, Module &m, const ModuleRaiser *mr, + MCInstRaiser *mcir) + : MachineInstructionRaiser(machFunc, m, mr, mcir), + machineRegInfo(MF.getRegInfo()), + x86TargetInfo(MF.getSubtarget()) { + x86InstrInfo = x86TargetInfo.getInstrInfo(); + x86RegisterInfo = x86TargetInfo.getRegisterInfo(); + PrintPass = + (cl::getRegisteredOptions()["print-after-all"]->getNumOccurrences() > 0); + FPUStack.TOP = 0; + for (int i = 0; i < FPUSTACK_SZ; i++) { + FPUStack.Regs[i] = nullptr; + } +} + +/* Delete noop instructions */ + +bool X86MachineInstructionRaiser::deleteNOOPInstrMI( + MachineBasicBlock &MBB, MachineBasicBlock::iterator MBBI) { + MachineInstr &MI = *MBBI; + if (isNoop(MI.getOpcode())) { + MBB.remove(&MI); + return true; + } + return false; +} + +bool X86MachineInstructionRaiser::deleteNOOPInstrMF() { + bool modified = false; + for (MachineBasicBlock &MBB : MF) { + // MBBI may be invalidated by the raising operation. + MachineBasicBlock::iterator MBBI = MBB.begin(), E = MBB.end(); + while (MBBI != E) { + MachineBasicBlock::iterator NMBBI = std::next(MBBI); + modified |= deleteNOOPInstrMI(MBB, MBBI); + MBBI = NMBBI; + } + } + return modified; +} + +/* Function prototype discovery */ + +// Unfortunately, tablegen does not have an interface to query +// information about argument registers used for calling +// convention used. +static const std::vector GPR64ArgRegs64Bit({X86::RDI, X86::RSI, + X86::RDX, X86::RCX, + X86::R8, X86::R9}); + +static const std::vector GPR64ArgRegs32Bit({X86::EDI, X86::ESI, + X86::EDX, X86::ECX, + X86::R8D, X86::R9D}); + +static const std::vector + GPR64ArgRegs16Bit({X86::DI, X86::SI, X86::DX, X86::CX, X86::R8W, X86::R9W}); + +static const std::vector GPR64ArgRegs8Bit({X86::DIL, X86::SIL, + X86::DL, X86::CL, + X86::R8B, X86::R9B}); + +// static const ArrayRef GPR64ArgRegsWin64({X86::RCX, X86::RDX, +// X86::R8, +// X86::R9}); + +static inline bool is64BitPhysReg(unsigned int PReg) { + return X86MCRegisterClasses[X86::GR64RegClassID].contains(PReg); +} + +static bool inline is32BitPhysReg(unsigned int PReg) { + return X86MCRegisterClasses[X86::GR32RegClassID].contains(PReg); +} + +static bool inline is16BitPhysReg(unsigned int PReg) { + return X86MCRegisterClasses[X86::GR16RegClassID].contains(PReg); +} + +static bool inline is8BitPhysReg(unsigned int PReg) { + return X86MCRegisterClasses[X86::GR8RegClassID].contains(PReg); +} + +static inline Type *getImmOperandType(const MachineInstr &mi, + unsigned int OpIndex) { + LLVMContext &llvmContext(mi.getMF()->getFunction().getContext()); + MachineOperand Op = mi.getOperand(OpIndex); + assert(Op.isImm() && "Attempt to get size of non-immediate operand"); + // Initialize to nullptr - unknown + Type *ImmType = nullptr; + uint8_t ImmSize = X86II::getSizeOfImm(mi.getDesc().TSFlags); + + switch (ImmSize) { + case 8: + ImmType = Type::getInt64Ty(llvmContext); + break; + case 4: + ImmType = Type::getInt32Ty(llvmContext); + break; + case 2: + ImmType = Type::getInt16Ty(llvmContext); + break; + case 1: + ImmType = Type::getInt8Ty(llvmContext); + break; + default: + assert(false && "Immediate operand of unknown size"); + break; + } + return ImmType; +} + +static inline uint8_t getPhysRegOperandSize(const MachineInstr &mi, + unsigned int OpIndex) { + MCOperandInfo OpInfo = mi.getDesc().OpInfo[OpIndex]; + MachineOperand Op = mi.getOperand(OpIndex); + // Initialize to 0 - unknown + uint8_t RegSize = 0; + assert(Op.isReg() && "Attempt to get size of non-register operand"); + if (TargetRegisterInfo::isPhysicalRegister(Op.getReg())) { + switch (OpInfo.RegClass) { + case X86::GR64RegClassID: + RegSize = 8; + break; + case X86::GR32RegClassID: + RegSize = 4; + break; + case X86::GR16RegClassID: + RegSize = 2; + break; + case X86::GR8RegClassID: + RegSize = 1; + break; + default: + assert(false && "Register operand of unknown register class"); + break; + } + } else { + assert(false && + "Unexpected non-physical register found in store instruction"); + } + return RegSize; +} + +static inline Type *getPhysRegOperandType(const MachineInstr &mi, + unsigned int OpIndex) { + LLVMContext &llvmContext(mi.getMF()->getFunction().getContext()); + MachineOperand Op = mi.getOperand(OpIndex); + MCOperandInfo OpInfo = mi.getDesc().OpInfo[OpIndex]; + // Initialize to nullptr - unknown + Type *RegTy = nullptr; + + assert(Op.isReg() && "Attempt to get type of non-register operand"); + if (TargetRegisterInfo::isPhysicalRegister(Op.getReg())) { + switch (OpInfo.RegClass) { + case X86::GR64RegClassID: + RegTy = Type::getInt64Ty(llvmContext); + break; + case X86::GR32RegClassID: + RegTy = Type::getInt32Ty(llvmContext); + break; + case X86::GR16RegClassID: + RegTy = Type::getInt16Ty(llvmContext); + break; + case X86::GR8RegClassID: + RegTy = Type::getInt8Ty(llvmContext); + break; + default: + assert(false && "Register operand of unknown register class"); + break; + } + } else { + assert(false && + "Unexpected non-physical register found in store instruction"); + } + + return RegTy; +} + +static inline bool isPushToStack(const MachineInstr &mi) { + unsigned char BaseOpcode = X86II::getBaseOpcodeFor(mi.getDesc().TSFlags); + // Note : Encoding of PUSH [CS | DS | ES | SS | FS | GS] not checked. + return ((BaseOpcode == 0x50) || (BaseOpcode == 0x6A) || + (BaseOpcode == 0x68) || (BaseOpcode == 0xFF) || + (BaseOpcode == 0x60) || (BaseOpcode == 0x9c)); +} + +static inline bool isPopFromStack(const MachineInstr &mi) { + unsigned char BaseOpcode = X86II::getBaseOpcodeFor(mi.getDesc().TSFlags); + // Note : Encoding of POP [DS | ES | SS | FS | GS] not checked. + return ((BaseOpcode == 0x58) || (BaseOpcode == 0x8F) || + (BaseOpcode == 0x9D) || (BaseOpcode == 0x61) || + // or LEAVE + (BaseOpcode == 0xC9)); +} + +static inline bool isEffectiveAddrValue(Value *val) { + if (isa(val)) { + return true; + } else if (isa(val)) { + BinaryOperator *binOpVal = dyn_cast(val); + if (binOpVal->isBinaryOp(BinaryOperator::Add) || + binOpVal->isBinaryOp(BinaryOperator::Mul)) { + return true; + } + } + return false; +} + +// FPU Access functions +void X86MachineInstructionRaiser::FPURegisterStackPush(Value *val) { + assert(val->getType()->isFloatingPointTy() && + "Attempt to push non-FP type value on FPU register stack"); + assert((FPUStack.TOP < FPUSTACK_SZ) && (FPUStack.TOP >= 0) && + "Incorrect initial FPU Register Stack top in push"); + + int8_t PushIndex = (FPUSTACK_SZ + FPUStack.TOP - 1) % FPUSTACK_SZ; + + assert((PushIndex < FPUSTACK_SZ) && (PushIndex >= 0) && + "Incorrect FPU Register Stack index computed in push"); + FPUStack.Regs[PushIndex] = val; + FPUStack.TOP = PushIndex; +} + +void X86MachineInstructionRaiser::FPURegisterStackPop() { + assert((FPUStack.TOP < FPUSTACK_SZ) && (FPUStack.TOP >= 0) && + "Incorrect initial FPU Register Stack top in pop"); + + int8_t PostPopIndex = (FPUSTACK_SZ + FPUStack.TOP + 1) % FPUSTACK_SZ; + + assert((PostPopIndex < FPUSTACK_SZ) && (PostPopIndex >= 0) && + "Incorrect FPU Register Stack index computed in pop"); + // Clear the value at current TOP + FPUStack.Regs[FPUStack.TOP] = nullptr; + // Adjust TOP value + FPUStack.TOP = PostPopIndex; +} + +// Get value at index +Value *X86MachineInstructionRaiser::FPURegisterStackGetValueAt(int8_t index) { + assert((FPUStack.TOP < FPUSTACK_SZ) && (FPUStack.TOP >= 0) && + "Incorrect initial FPU Register Stack top in FPU register access"); + + int8_t AccessIndex = (FPUSTACK_SZ + FPUStack.TOP + index) % FPUSTACK_SZ; + + assert((AccessIndex < FPUSTACK_SZ) && (AccessIndex >= 0) && + "Incorrect FPU Register Stack index computed in FPU register access"); + + return FPUStack.Regs[AccessIndex]; +} + +// Set value at index to val +void X86MachineInstructionRaiser::FPURegisterStackSetValueAt(int8_t index, + Value *val) { + assert(val->getType()->isFloatingPointTy() && + "Attempt to insert non-FP type value in FPU register stack"); + assert((FPUStack.TOP < FPUSTACK_SZ) && (FPUStack.TOP >= 0) && + "Incorrect initial FPU Register Stack top in FPU register access"); + + int8_t AccessIndex = (FPUSTACK_SZ + FPUStack.TOP + index) % FPUSTACK_SZ; + + assert((AccessIndex < FPUSTACK_SZ) && (AccessIndex >= 0) && + "Incorrect FPU Register Stack index computed in FPU register access"); + + FPUStack.Regs[AccessIndex] = val; +} + +Value *X86MachineInstructionRaiser::FPURegisterStackTop() { + return FPURegisterStackGetValueAt(0); +} + +// Construct argument type vector from the physical register vector. +// Requirements : PhysRegs is a set of registers each with no super or +// sub-registers. +bool X86MachineInstructionRaiser::buildFuncArgTypeVector( + const std::set &PhysRegs, std::vector &ArgTyVec) { + // A map of argument number and type as discovered + std::map argNumTypeMap; + llvm::LLVMContext &funcLLVMContext = MF.getFunction().getContext(); + + for (MCPhysReg PReg : PhysRegs) { + // If Reg is an argument register per C standard calling convention + // construct function argument. + int argNum = getArgumentNumber(PReg); + + if (argNum > 0) { + // Make sure each argument position is discovered only once + assert(argNumTypeMap.find(argNum) == argNumTypeMap.end()); + if (is8BitPhysReg(PReg)) { + argNumTypeMap.insert( + std::make_pair(argNum, Type::getInt8Ty(funcLLVMContext))); + } else if (is16BitPhysReg(PReg)) { + argNumTypeMap.insert( + std::make_pair(argNum, Type::getInt16Ty(funcLLVMContext))); + } else if (is32BitPhysReg(PReg)) { + argNumTypeMap.insert( + std::make_pair(argNum, Type::getInt32Ty(funcLLVMContext))); + } else if (is64BitPhysReg(PReg)) { + argNumTypeMap.insert( + std::make_pair(argNum, Type::getInt64Ty(funcLLVMContext))); + } else { + outs() << x86RegisterInfo->getRegAsmName(PReg) << "\n"; + assert(false && "Unhandled register type encountered in binary"); + } + } + } + + // Build argument type vector that will be used to build FunctionType + // while sanity checking arguments discovered + for (unsigned int i = 1; i <= argNumTypeMap.size(); i++) { + // If the function has arguments, we assume that the conventional + // argument registers are used in order. If the arg register + // corresponding to position i is not a live in, it implies that the + // function has i-1 arguments. + if (argNumTypeMap.find(i) == argNumTypeMap.end()) { + break; + } + auto Ty = argNumTypeMap.find(i)->second; + ArgTyVec.push_back(Ty); + } + return true; +} + +// Return argument number associated with physical +// register PReg according to C calling convention. + +int X86MachineInstructionRaiser::getArgumentNumber(unsigned PReg) { + int pos = -1; + if (is8BitPhysReg(PReg)) { + int diff = std::distance( + GPR64ArgRegs8Bit.begin(), + std::find(GPR64ArgRegs8Bit.begin(), GPR64ArgRegs8Bit.end(), PReg)); + if ((diff >= 0) && (diff < (int)GPR64ArgRegs8Bit.size())) { + pos = diff + 1; + } + } else if (is16BitPhysReg(PReg)) { + int diff = std::distance( + GPR64ArgRegs16Bit.begin(), + std::find(GPR64ArgRegs16Bit.begin(), GPR64ArgRegs16Bit.end(), PReg)); + if ((diff >= 0) && (diff < (int)GPR64ArgRegs16Bit.size())) { + pos = diff + 1; + } + } else if (is32BitPhysReg(PReg)) { + int diff = std::distance( + GPR64ArgRegs32Bit.begin(), + std::find(GPR64ArgRegs32Bit.begin(), GPR64ArgRegs32Bit.end(), PReg)); + if ((diff >= 0) && (diff < (int)GPR64ArgRegs32Bit.size())) { + pos = diff + 1; + } + } else if (is64BitPhysReg(PReg)) { + int diff = std::distance( + GPR64ArgRegs64Bit.begin(), + std::find(GPR64ArgRegs64Bit.begin(), GPR64ArgRegs64Bit.end(), PReg)); + if ((diff >= 0) && (diff < (int)GPR64ArgRegs64Bit.size())) { + pos = diff + 1; + } + } + return pos; +} + +// Return a Value representing stack-allocated object +Value *X86MachineInstructionRaiser::createPCRelativeAccesssValue( + const MachineInstr &mi, BasicBlock *curBlock) { + Value *memrefValue = nullptr; + // Get index of memory reference in the instruction. + int memoryRefOpIndex = getMemoryRefOpIndex(mi); + // Should have found the index of the memory reference operand + assert(memoryRefOpIndex != -1 && + "Unable to find memory reference operand of a load/store instruction"); + X86AddressMode memRef = llvm::getAddressFromInstr(&mi, memoryRefOpIndex); + + // LLVM represents memory operands using 5 operands + // viz., BaseReg, ScaleAmt, IndexReg, Disp, Segment, ... + // The disassembly in AT&T syntax is shown as + // Segment:Disp(BaseReg, IndexReg, ScaleAmt). + // or as + // Segment:[BaseReg + Disp + IndexReg * ScaleAmt] + // in Intel syntax. + // effective address is calculated to be Segment:[BaseReg + IndexReg * + // ScaleAmt + Disp] Segment is typically X86::NoRegister. + + assert(mi.getOperand(memoryRefOpIndex + X86::AddrSegmentReg).getReg() == + X86::NoRegister && + "Expect no segment register"); + // Construct non-stack memory referencing value + unsigned BaseReg = memRef.Base.Reg; + unsigned IndexReg = memRef.IndexReg; + unsigned ScaleAmt = memRef.Scale; + int Disp = memRef.Disp; + const MachineOperand &SegRegOperand = + mi.getOperand(memoryRefOpIndex + X86::AddrSegmentReg); + // For now, we assume default segment DS (and hence no specification of + // Segment register. + assert(SegRegOperand.isReg() && (SegRegOperand.getReg() == X86::NoRegister) && + "Unhandled memory reference instruction with non-zero segment " + "register"); + // Also assume that PC-relative addressing does not involve index register + assert(IndexReg == X86::NoRegister && + "Unhandled index register in PC-relative memory addressing " + "instruction"); + assert(ScaleAmt == 1 && "Unhandled value of scale amount in PC-relative " + "memory addressing instruction"); + + // Non-stack memory address is supported by this function. + uint64_t BaseSupReg = find64BitSuperReg(BaseReg); + assert(((BaseSupReg == X86::RIP) || (BaseSupReg == X86::NoRegister)) && + "Base register that is not PC encountered in memory access " + "instruction"); + + // 1. Get the text section address + int64_t TextSectionAddress = MR->getTextSectionAddress(); + + assert(TextSectionAddress >= 0 && "Failed to find text section address"); + + // 2. Get MCInst offset - the offset of machine instruction in the binary + // and instruction size + MCInstRaiser *MCIRaiser = getMCInstRaiser(); + uint64_t MCInstOffset = MCIRaiser->getMCInstIndex(mi); + uint64_t MCInstSz = MCIRaiser->getMCInstSize(MCInstOffset); + + // 3. Compute the PC-relative offset. + + const ELF64LEObjectFile *Elf64LEObjFile = + dyn_cast(MR->getObjectFile()); + assert(Elf64LEObjFile != nullptr && + "Only 64-bit ELF binaries supported at present."); + + auto EType = Elf64LEObjFile->getELFFile()->getHeader()->e_type; + if ((EType == ELF::ET_DYN) || (EType == ELF::ET_EXEC)) { + uint64_t PCOffset = TextSectionAddress + MCInstOffset + MCInstSz + Disp; + const RelocationRef *DynReloc = MR->getDynRelocAtOffset(PCOffset); + + // assert(DynReloc && + // "Failed to get dynamic relocation for pc-relative offset"); + // If there is a dynamic relocation for the PCOffset + if (DynReloc) { + if (DynReloc->getType() == ELF::R_X86_64_GLOB_DAT) { + Expected Symname = DynReloc->getSymbol()->getName(); + assert(Symname && + "Failed to find symbol associated with dynamic relocation."); + // Find if a global value associated with symbol name is already + // created + for (GlobalVariable &gv : MR->getModule().globals()) { + if (gv.getName().compare(Symname.get()) == 0) { + memrefValue = &gv; + } + } + if (memrefValue == nullptr) { + // Get all necessary information about the global symbol. + llvm::LLVMContext &llvmContext(MF.getFunction().getContext()); + DataRefImpl symbImpl = DynReloc->getSymbol()->getRawDataRefImpl(); + // get symbol + auto symb = Elf64LEObjFile->getSymbol(symbImpl); + // get symbol size + uint64_t symbSize = symb->st_size; + GlobalValue::LinkageTypes linkage; + switch (symb->getBinding()) { + case ELF::STB_GLOBAL: + linkage = GlobalValue::ExternalLinkage; + break; + default: + assert(false && "Unhandled dynamic symbol"); + } + + // Check that symbol type is data object, representing a variable or + // array etc. + assert((symb->getType() == ELF::STT_OBJECT) && + "Function symbol type expected. Not found"); + Type *GlobalValTy = nullptr; + switch (symbSize) { + case 8: + GlobalValTy = Type::getInt64Ty(llvmContext); + break; + case 4: + GlobalValTy = Type::getInt32Ty(llvmContext); + break; + case 2: + GlobalValTy = Type::getInt16Ty(llvmContext); + break; + case 1: + GlobalValTy = Type::getInt8Ty(llvmContext); + break; + default: + assert(false && "Unexpected symbol size"); + } + // get symbol value - this is the virtual address of symbol's value + uint64_t symVirtualAddr = symb->st_value; + + // get the initial value of the global data symbol at symVirtualAddr + // from the section that contains the virtual address symVirtualAddr. + // In executable and shared object files, st_value holds a virtual + // address. + uint64_t symbVal = 0; + for (section_iterator SecIter : Elf64LEObjFile->sections()) { + uint64_t SecStart = SecIter->getAddress(); + uint64_t SecEnd = SecStart + SecIter->getSize(); + if ((SecStart <= symVirtualAddr) && (SecEnd >= symVirtualAddr)) { + // Get the initial symbol value only if this is not a bss section. + // Else, symVal is already initialized to 0. + if (SecIter->isBSS()) { + linkage = GlobalValue::CommonLinkage; + } else { + StringRef SecData; + SecIter->getContents(SecData); + unsigned index = symVirtualAddr - SecStart; + const unsigned char *beg = SecData.bytes_begin() + index; + char shift = 0; + while (symbSize-- > 0) { + // We know this is little-endian + symbVal = ((*beg++) << shift) | symbVal; + shift += 8; + } + } + break; + } + } + Constant *GlobalInit = ConstantInt::get(GlobalValTy, symbVal); + auto GlobalVal = new GlobalVariable(MR->getModule(), GlobalValTy, + false /* isConstant */, linkage, + GlobalInit, Symname->data()); + // Don't use symbSize as it was modified. + GlobalVal->setAlignment(symb->st_size); + GlobalVal->setDSOLocal(true); + memrefValue = GlobalVal; + } + } else { + assert(false && "Unexpected relocation type referenced in PC-relative " + "memory access instruction."); + } + } else { + memrefValue = getGlobalVariableValueAt(mi, PCOffset); + } + } else if (EType == ELF::ET_REL) { + const RelocationRef *TextReloc = + MR->getTextRelocAtOffset(MCInstOffset, MCInstSz); + + assert(TextReloc && + "Failed to get dynamic relocation for pc-relative offset"); + + if (TextReloc->getType() == ELF::R_X86_64_32S) { + Expected Symname = TextReloc->getSymbol()->getName(); + assert(Symname && + "Failed to find symbol associated with text relocation."); + // Find if a global value associated with symbol name is already + // created + for (GlobalVariable &gv : MR->getModule().globals()) { + if (gv.getName().compare(Symname.get()) == 0) { + memrefValue = &gv; + } + } + if (memrefValue == nullptr) { + // Get all necessary information about the text relocation symbol + // which is most likely global. + + llvm::LLVMContext &llvmContext(MF.getFunction().getContext()); + DataRefImpl symbImpl = TextReloc->getSymbol()->getRawDataRefImpl(); + // get symbol + auto symb = Elf64LEObjFile->getSymbol(symbImpl); + // get symbol size + uint64_t symSize = symb->st_size; + GlobalValue::LinkageTypes linkage; + switch (symb->getBinding()) { + case ELF::STB_GLOBAL: + linkage = GlobalValue::ExternalLinkage; + break; + default: + assert(false && "Unhandled dynamic symbol"); + } + + // get symbol value - this is the offset from the beginning of the + // section st_shndex identifies. + uint64_t symVal = symb->st_value; + + uint64_t symValSecIndex = symb->st_shndx; + uint8_t symAlignment = 0; + uint64_t symInitVal = 0; + if (((symValSecIndex >= ELF::SHN_LORESERVE) && + (symValSecIndex <= ELF::SHN_HIRESERVE)) || + (symValSecIndex == ELF::SHN_UNDEF)) { + if (symValSecIndex == ELF::SHN_COMMON) { + // st_value holds symbol alignment constraints + symAlignment = symVal; + linkage = GlobalValue::CommonLinkage; + } + } else { + // get the initial value of the global data symbol at offset symVal + // in section with index symValSecIndex + + for (section_iterator SecIter : Elf64LEObjFile->sections()) { + if (SecIter->getIndex() == symValSecIndex) { + StringRef SecData; + SecIter->getContents(SecData); + const unsigned char *beg = SecData.bytes_begin() + symVal; + char shift = 0; + while (symSize-- > 0) { + // We know this is little-endian + symInitVal = ((*beg++) << shift) | symInitVal; + shift += 8; + } + break; + } + } + // REVISIT : Set symbol alignment to be the same as symbol size + // NOTE : Do not use symSize since it has been modified in the while + // loop above. + symAlignment = symb->st_size; + } + Type *GlobalValTy = nullptr; + + switch (symAlignment) { + case 8: + GlobalValTy = Type::getInt64Ty(llvmContext); + break; + case 4: + GlobalValTy = Type::getInt32Ty(llvmContext); + break; + case 2: + GlobalValTy = Type::getInt16Ty(llvmContext); + break; + case 1: + GlobalValTy = Type::getInt8Ty(llvmContext); + break; + default: + assert(false && "Unexpected symbol size"); + } + + Constant *GlobalInit = ConstantInt::get(GlobalValTy, symInitVal); + auto GlobalVal = new GlobalVariable(MR->getModule(), GlobalValTy, + false /* isConstant */, linkage, + GlobalInit, Symname->data()); + // Don't use symSize as it was modified. + GlobalVal->setAlignment(symAlignment); + GlobalVal->setDSOLocal(true); + memrefValue = GlobalVal; + } + } else { + assert(false && "Unexpected relocation type referenced in PC-relative " + "memory access instruction."); + } + } else { + assert(false && "Unhandled binary type. Only object files and shared " + "libraries supported"); + } + return memrefValue; +} + +unsigned int +X86MachineInstructionRaiser::find64BitSuperReg(unsigned int PhysReg) { + unsigned int SuperReg; + bool SuperRegFound = false; + + // No super register for 0 register + if (PhysReg == X86::NoRegister) { + return X86::NoRegister; + } + + // Nothing to do if PhysReg is EFLAGS + if (PhysReg == X86::EFLAGS) { + return PhysReg; + } + + if (is64BitPhysReg(PhysReg)) { + SuperReg = PhysReg; + SuperRegFound = true; + } else { + for (MCSuperRegIterator SuperRegs(PhysReg, x86RegisterInfo); + SuperRegs.isValid(); ++SuperRegs) { + SuperReg = *SuperRegs; + if (is64BitPhysReg(SuperReg)) { + assert(SuperRegFound != true && + "Expect only one 64-bit super register"); + SuperRegFound = true; + } + } + } + assert(SuperRegFound && "Super register not found"); + return SuperReg; +} + +Value *X86MachineInstructionRaiser::findPhysRegSSAValue(unsigned int PhysReg) { + // Always convert PhysReg to the 64-bit version. + unsigned int SuperReg = find64BitSuperReg(PhysReg); + + // Get the Value associated with SuperReg + std::map::iterator physToValueMapIter = + physToValueMap.find(SuperReg); + if (physToValueMapIter != physToValueMap.end()) { + return physToValueMapIter->second; + } + return nullptr; +} + +Value *X86MachineInstructionRaiser::getStackAllocatedValue( + const MachineInstr &mi, BasicBlock *, int ldOrStOpIndex) { + Value *memoryRefValue = nullptr; + unsigned int stackFrameIndex; + // Need to separate the stackFrameIndex value and that it is set since + // stackFrameIndex can be any value (can't use a special value like -1). + bool stackFrameIndexSet = false; + + // Get index of memory reference in the instruction. + int memoryRefOpIndex = getMemoryRefOpIndex(mi); + // Should have found the index of the memory reference operand + assert(memoryRefOpIndex != -1 && + "Unable to find memory reference operand of a load/store instruction"); + X86AddressMode memRef = llvm::getAddressFromInstr(&mi, memoryRefOpIndex); + // If this is a new stack reference + MemRefToFrameIndexMapType::iterator mapIter = + memRefToFrameIndexMap.find(memRef); + if (mapIter == memRefToFrameIndexMap.end()) { + // Create an alloca instruction since this memory reference is + // encountered for the first time. + // TODO : Memory references outside of stack are checked for at the + // beginning of this function and not handled. At this point we know + // that this is a stack reference. + Type *Ty = nullptr; + // Uninitialized stack object size + uint64_t stackObjectSize = 0; + unsigned int typeAlignment; + LLVMContext &llvmContext(MF.getFunction().getContext()); + const DataLayout &dataLayout = MR->getModule().getDataLayout(); + unsigned allocaAddrSpace = dataLayout.getAllocaAddrSpace(); + const MCInstrDesc &MIDesc = mi.getDesc(); + + assert((ldOrStOpIndex >= 0) && "Uninitialized load/store operand index"); + + stackObjectSize = getInstructionMemOpSize(mi.getOpcode()); + switch (stackObjectSize) { + case 8: + Ty = Type::getInt64Ty(llvmContext); + break; + case 4: + Ty = Type::getInt32Ty(llvmContext); + break; + case 2: + Ty = Type::getInt16Ty(llvmContext); + break; + case 1: + Ty = Type::getInt8Ty(llvmContext); + break; + default: + assert(false && "Encountered unexpected memory operand size "); + break; + } + + assert(stackObjectSize != 0 && Ty != nullptr && + "Unknown type of operand in memory referencing instruction"); + typeAlignment = dataLayout.getPrefTypeAlignment(Ty); + + // Create alloca instruction to allocate stack slot + AllocaInst *alloca = new AllocaInst(Ty, allocaAddrSpace, 0, typeAlignment); + + // Create a stack slot associated with the alloca instruction + stackFrameIndex = MF.getFrameInfo().CreateStackObject( + stackObjectSize, dataLayout.getPrefTypeAlignment(Ty), + false /* isSpillSlot */, alloca); + + // Note that stack frame index corresponding to memory reference + // has now been created and exists. + stackFrameIndexSet = true; + MF.getFrameInfo().setObjectOffset(stackFrameIndex, memRef.Disp); + + // Book-keeping: Add memory reference to the map + memRefToFrameIndexMap.emplace(memRef, stackFrameIndex); + + // If the instruction is not an FPU load/store, check if operand stored to + // is an argument or return register, set its name to reference arg.addr + // (the name decoration is primarily for aesthetics). + auto InstKind = getInstructionKind(mi.getOpcode()); + if ((InstKind != InstructionKind::LOAD_FPU_REG) && + (InstKind != InstructionKind::STORE_FPU_REG)) { + const MachineOperand &loadOrStoreOp = mi.getOperand(ldOrStOpIndex); + if (loadOrStoreOp.isReg()) { + unsigned int storeReg = loadOrStoreOp.getReg(); + + // Set name of alloca instruction only if this is the first use of + // argument or return register. + if (findPhysRegSSAValue(storeReg) == nullptr) { + int argNum = -1; + argNum = getArgumentNumber(storeReg); + // If the register is an argument register + if ((argNum > 0) && (argNum <= (int)raisedFunction->arg_size())) { + Function::arg_iterator argIter = + raisedFunction->arg_begin() + argNum - 1; + alloca->setName(argIter->getName() + ".addr"); + } + // storeReg not an argument. Is it return register? + else if ((storeReg == X86::EAX) || (storeReg == X86::RAX)) { + alloca->setName("retval"); + // If this is a store instruction, create the store instruction + // to store to the stack slot. + if (MIDesc.mayStore()) { + assert(false && "Unhandled situation where rax/eax are stored on " + "stack before intialization"); + } + } + } + } + } + // Add the alloca instruction to entry block + insertAllocaInEntryBlock(alloca); + } + // Stack frame slot already allocated for this memRef + else { + stackFrameIndex = (*mapIter).second; + stackFrameIndexSet = true; + } + assert(stackFrameIndexSet && "Undefined stack slot"); + memoryRefValue = const_cast( + MF.getFrameInfo().getObjectAllocation(stackFrameIndex)); + + return memoryRefValue; +} +// Return the Function * referenced by the PLT entry at offset +Function *X86MachineInstructionRaiser::getTargetFunctionAtPLTOffset( + const MachineInstr &mi, uint64_t pltEntOff) { + Function *CalledFunc = nullptr; + const ELF64LEObjectFile *Elf64LEObjFile = + dyn_cast(MR->getObjectFile()); + assert(Elf64LEObjFile != nullptr && + "Only 64-bit ELF binaries supported at present."); + unsigned char ExecType = Elf64LEObjFile->getELFFile()->getHeader()->e_type; + assert((ExecType == ELF::ET_DYN) || (ExecType == ELF::ET_EXEC)); + // Find the section that contains the offset. That must be the PLT section + for (section_iterator SecIter : Elf64LEObjFile->sections()) { + uint64_t SecStart = SecIter->getAddress(); + uint64_t SecEnd = SecStart + SecIter->getSize(); + if ((SecStart <= pltEntOff) && (SecEnd >= pltEntOff)) { + StringRef SecName; + if (SecIter->getName(SecName)) { + assert(false && "Failed to get section name with PLT offset"); + } + if (SecName.compare(".plt") != 0) { + assert(false && "Unexpected section name of PLT offset"); + } + StringRef SecData; + SecIter->getContents(SecData); + // StringRef BytesStr; + // error(Section.getContents(BytesStr)); + ArrayRef Bytes(reinterpret_cast(SecData.data()), + SecData.size()); + // Disassemble the first instruction at the offset + MCInst Inst; + uint64_t InstSz; + bool Success = MR->getMCDisassembler()->getInstruction( + Inst, InstSz, Bytes.slice(pltEntOff - SecStart), pltEntOff, nulls(), + nulls()); + assert(Success && "Failed to disassemble instruction in PLT"); + unsigned int Opcode = Inst.getOpcode(); + MCInstrDesc MCID = MR->getMCInstrInfo()->get(Opcode); + if ((Opcode != X86::JMP64m) || (MCID.getNumOperands() != 5)) { + assert(false && "Unexpected non-jump instruction or number of operands " + "of jmp instruction in PLT entry"); + } + MCOperand Oprnd = Inst.getOperand(0); + int64_t PCOffset = 0; + + // First operand should be PC + if (Oprnd.isReg()) { + if (Oprnd.getReg() != X86::RIP) { + assert(false && "PC-relative jmp instruction expected in PLT entry"); + } + } else { + assert(false && "PC operand expected in jmp instruction of PLT entry"); + } + + Oprnd = Inst.getOperand(1); + // Second operand should be 1 + if (Oprnd.isImm()) { + if (Oprnd.getImm() != 1) { + assert(false && "Unexpected immediate second operand in jmp " + "instruction of PLT entry"); + } + } else { + assert(false && "Unexpected non-immediate second operand in jmp " + "instruction of PLT entry"); + } + + Oprnd = Inst.getOperand(2); + // Third operand should be X86::No_Register + if (Oprnd.isReg()) { + if (Oprnd.getReg() != X86::NoRegister) { + assert(false && "Unexpected third operand - non-zero register in jmp " + "instruction of PLT entry"); + } + } else { + assert(false && "Unexpected third operand - non-register in jmp " + "instruction of PLT entry"); + } + + Oprnd = Inst.getOperand(3); + // Fourth operand should be an immediate + if (!Oprnd.isImm()) { + assert(false && "Unexpected non-immediate fourth operand in jmp " + "instruction of PLT entry"); + } + // Get the pc offset + PCOffset = Oprnd.getImm(); + + Oprnd = Inst.getOperand(4); + // Fifth operand should be X86::No_Register + if (Oprnd.isReg()) { + if (Oprnd.getReg() != X86::NoRegister) { + assert(false && "Unexpected fifth operand - non-zero register in jmp " + "instruction of PLT entry"); + } + } else { + assert(false && "Unexpected fifth operand - non-register in jmp " + "instruction of PLT entry"); + } + + // Get dynamic relocation in .got.plt section corresponding to the PLT + // entry. The relocation offset is calculated by adding the following: + // a) offset of jmp instruction + size of the instruction + // (representing pc-related addressing) b) jmp target offset in the + // instruction + uint64_t GotPltRelocOffset = pltEntOff + InstSz + PCOffset; + const RelocationRef *GotPltReloc = + MR->getDynRelocAtOffset(GotPltRelocOffset); + assert(GotPltReloc != nullptr && + "Failed to get dynamic relocation for jmp target of PLT entry"); + + assert((GotPltReloc->getType() == ELF::R_X86_64_JUMP_SLOT) && + "Unexpected relocation type for PLT jmp instruction"); + symbol_iterator CalledFuncSym = GotPltReloc->getSymbol(); + assert(CalledFuncSym != Elf64LEObjFile->symbol_end() && + "Failed to find relocation symbol for PLT entry"); + Expected CalledFuncSymName = CalledFuncSym->getName(); + assert(CalledFuncSymName && + "Failed to find symbol associated with dynamic " + "relocation of PLT jmp target."); + Expected CalledFuncSymAddr = CalledFuncSym->getAddress(); + assert(CalledFuncSymAddr && + "Failed to get called function address of PLT entry"); + CalledFunc = MR->getFunctionAt(CalledFuncSymAddr.get()); + + if (CalledFunc == nullptr) { + // This is an undefined function symbol. Look through the list of + // known glibc interfaces and construct a Function accordingly. + CalledFunc = + ExternalFunctions::Create(*CalledFuncSymName, MR->getModule()); + } + // Found the section we are looking for + break; + } + } + return CalledFunc; +} +// Return a global value corresponding to read-only data. + +const Value *X86MachineInstructionRaiser::getOrCreateGlobalRODataValueAtAt( + const MachineInstr &mi, uint64_t Offset) { + const Value *RODataValue = MR->getRODataValueAt(Offset); + if (RODataValue == nullptr) { + // Only if the imm value is a positive value + const ELF64LEObjectFile *Elf64LEObjFile = + dyn_cast(MR->getObjectFile()); + assert(Elf64LEObjFile != nullptr && + "Only 64-bit ELF binaries supported at present."); + LLVMContext &llvmContext(MF.getFunction().getContext()); + // Check if this is an address in .rodata + for (section_iterator SecIter : Elf64LEObjFile->sections()) { + uint64_t SecStart = SecIter->getAddress(); + uint64_t SecEnd = SecStart + SecIter->getSize(); + // We know that SrcImm is a positive value. So, casting it is OK. + if ((SecStart <= (uint64_t)Offset) && (SecEnd >= (uint64_t)Offset)) { + if (SecIter->isData()) { + StringRef SecData; + SecIter->getContents(SecData); + unsigned DataOffset = Offset - SecStart; + const unsigned char *RODataBegin = SecData.bytes_begin() + DataOffset; + StringRef ROStringRef(reinterpret_cast(RODataBegin)); + Constant *StrConstant = + ConstantDataArray::getString(llvmContext, ROStringRef); + auto GlobalStrConstVal = new GlobalVariable( + MR->getModule(), StrConstant->getType(), true /* isConstant */, + GlobalValue::PrivateLinkage, StrConstant, "rostr"); + // Record the mapping between offset and global value + MR->addRODataValueAt(GlobalStrConstVal, Offset); + RODataValue = GlobalStrConstVal; + } else if (SecIter->isBSS()) { + // Get symbol name associated with the address + // Find symbol at Offset + SymbolRef GlobalDataSym; + for (auto Symbol : Elf64LEObjFile->symbols()) { + if (Symbol.getELFType() == ELF::STT_OBJECT) { + auto SymAddr = Symbol.getAddress(); + assert(SymAddr && "Failed to lookup symbol for global address"); + uint64_t SymAddrVal = SymAddr.get(); + // We have established that Offset is not negative above. + // So, OK to cast. Check if the memory address Offset is + // SymAddrVal + if (SymAddrVal == (unsigned)Offset) { + GlobalDataSym = Symbol; + break; + } + } + } + assert((GlobalDataSym.getObject() != nullptr) && + "Failed to find symbol for global address."); + Expected GlobalDataSymName = GlobalDataSym.getName(); + assert(GlobalDataSymName && + "Failed to find symbol name for global address"); + // Find if a global value associated with symbol name is + // already created + for (GlobalVariable &gv : MR->getModule().globals()) { + if (gv.getName().compare(GlobalDataSymName.get()) == 0) { + RODataValue = &gv; + } + } + if (RODataValue == nullptr) { + Type *ImmType = nullptr; + uint8_t ImmSize = X86II::getSizeOfImm(mi.getDesc().TSFlags); + + switch (ImmSize) { + case 8: + ImmType = Type::getInt64Ty(llvmContext); + break; + case 4: + ImmType = Type::getInt32Ty(llvmContext); + break; + case 2: + ImmType = Type::getInt16Ty(llvmContext); + break; + case 1: + ImmType = Type::getInt8Ty(llvmContext); + break; + default: + assert(false && "Immediate operand of unknown size"); + break; + } + Constant *GlobalInit = ConstantInt::get(ImmType, 0); + auto GlobalVal = new GlobalVariable( + MR->getModule(), ImmType, false /* isConstant */, + GlobalValue::PrivateLinkage, GlobalInit, + GlobalDataSymName->data()); + GlobalVal->setAlignment(getInstructionMemOpSize(mi.getOpcode())); + GlobalVal->setDSOLocal(true); + RODataValue = GlobalVal; + } + } else { + assert(false && "Section corresponding to referenced data not found"); + } + break; + } + } + } + return RODataValue; +} + +// Return a value corresponding to global symbol at Offset referenced in +// MachineInst mi. +Value * +X86MachineInstructionRaiser::getGlobalVariableValueAt(const MachineInstr &mi, + uint64_t Offset) { + Value *GlobalVariableValue = nullptr; + const ELF64LEObjectFile *Elf64LEObjFile = + dyn_cast(MR->getObjectFile()); + assert(Elf64LEObjFile != nullptr && + "Only 64-bit ELF binaries supported at present."); + assert((Offset > 0) && + "Unhandled non-positive displacement global variable value"); + // Find symbol at Offset + SymbolRef GlobalDataSym; + bool GlobalDataSymFound = false; + unsigned GlobalDataOffset = 0; + for (auto Symbol : Elf64LEObjFile->symbols()) { + if (Symbol.getELFType() == ELF::STT_OBJECT) { + auto SymAddr = Symbol.getAddress(); + auto SymSize = Symbol.getSize(); + assert(SymAddr && "Failed to lookup symbol for global address"); + uint64_t SymAddrVal = SymAddr.get(); + // We have established that Offset is not negative above. So, OK to + // cast. + // Check if the memory address Offset is in the range [SymAddrVal, + // SymAddrVal+SymSize) + if ((SymAddrVal <= (unsigned)Offset) && + ((SymAddrVal + SymSize) > (unsigned)Offset)) { + GlobalDataSym = Symbol; + GlobalDataOffset = Offset - SymAddrVal; + GlobalDataSymFound = true; + break; + } + } + } + if (GlobalDataSymFound) { + Expected GlobalDataSymName = GlobalDataSym.getName(); + assert(GlobalDataSymName && "Failed to find global symbol name."); + // If this location is an offset from the start of GlobalDataSym, consider + // it to be a new global variable with the offset as suffix. + std::string DataSymNameIndexStr(GlobalDataSymName.get().data()); + if (GlobalDataOffset) { + DataSymNameIndexStr.append(std::to_string(GlobalDataOffset)); + } + // Find if a global value associated with symbol name is already + // created + StringRef GlobalDataSymNameIndexStrRef(DataSymNameIndexStr); + for (GlobalVariable &gv : MR->getModule().globals()) { + if (gv.getName().compare(GlobalDataSymNameIndexStrRef) == 0) { + GlobalVariableValue = &gv; + } + } + if (GlobalVariableValue == nullptr) { + // Get all necessary information about the global symbol. + llvm::LLVMContext &llvmContext(MF.getFunction().getContext()); + DataRefImpl symbImpl = GlobalDataSym.getRawDataRefImpl(); + // get symbol + auto symb = Elf64LEObjFile->getSymbol(symbImpl); + // get symbol size + uint64_t symbSize = symb->st_size; + GlobalValue::LinkageTypes linkage; + switch (symb->getBinding()) { + case ELF::STB_GLOBAL: + linkage = GlobalValue::ExternalLinkage; + break; + default: + assert(false && "Unhandled global symbol binding type"); + } + + // Check that symbol type is data object, representing a variable or + // array etc. + assert((symb->getType() == ELF::STT_OBJECT) && + "Function symbol type expected. Not found"); + Type *GlobalValTy = nullptr; + unsigned short MemOpSize = getInstructionMemOpSize(mi.getOpcode()); + switch (MemOpSize) { + case 8: + GlobalValTy = Type::getInt64Ty(llvmContext); + break; + case 4: + GlobalValTy = Type::getInt32Ty(llvmContext); + break; + case 2: + GlobalValTy = Type::getInt16Ty(llvmContext); + break; + case 1: + GlobalValTy = Type::getInt8Ty(llvmContext); + break; + default: + assert(false && "Unexpected symbol size"); + } + // get symbol value - this is the virtual address of symbol's value + uint64_t symVirtualAddr = symb->st_value; + + // get the initial value of the global data symbol at symVirtualAddr + // from the section that contains the virtual address symVirtualAddr. + // In executable and shared object files, st_value holds a virtual + // address. + uint64_t symbVal = 0; + for (section_iterator SecIter : Elf64LEObjFile->sections()) { + uint64_t SecStart = SecIter->getAddress(); + uint64_t SecEnd = SecStart + SecIter->getSize(); + if ((SecStart <= symVirtualAddr) && (SecEnd >= symVirtualAddr)) { + // Get the initial symbol value only if this is not a bss section. + // Else, symVal is already initialized to 0. + if (SecIter->isBSS()) { + linkage = GlobalValue::CommonLinkage; + } else { + StringRef SecData; + SecIter->getContents(SecData); + unsigned index = symVirtualAddr - SecStart; + const unsigned char *beg = SecData.bytes_begin() + index; + char shift = 0; + while (symbSize-- > 0) { + // We know this is little-endian + symbVal = ((*beg++) << shift) | symbVal; + shift += 8; + } + } + break; + } + } + Constant *GlobalInit = ConstantInt::get(GlobalValTy, symbVal); + auto GlobalVal = new GlobalVariable( + MR->getModule(), GlobalValTy, false /* isConstant */, linkage, + GlobalInit, GlobalDataSymNameIndexStrRef); + GlobalVal->setAlignment(MemOpSize); + GlobalVal->setDSOLocal(true); + GlobalVariableValue = GlobalVal; + } + } else { + GlobalVariableValue = + const_cast(getOrCreateGlobalRODataValueAtAt(mi, Offset)); + } + assert((GlobalVariableValue != nullptr) && "Failed to global variable value"); + return GlobalVariableValue; +} + +// Construct and return a Value* corresponding to PC-relative memory address +// access. Insert any intermediate values created in the process into +// curBlock. +// Construct and return a Value* corresponding to non-stack memory address +// expression in MachineInstr mi. Insert any intermediate values created in +// the process into curBlock. NOTE: This returns a value that may need to be +// loaded from if the expression does not involve global variable or +// dereferencing the global variable if expression involves global variable. +Value * +X86MachineInstructionRaiser::getMemoryAddressExprValue(const MachineInstr &mi, + BasicBlock *curBlock) { + Value *memrefValue = nullptr; + // Get index of memory reference in the instruction. + int memoryRefOpIndex = getMemoryRefOpIndex(mi); + // Should have found the index of the memory reference operand + assert(memoryRefOpIndex != -1 && + "Unable to find memory reference operand of a load/store instruction"); + X86AddressMode memRef = llvm::getAddressFromInstr(&mi, memoryRefOpIndex); + + // LLVM represents memory operands using 5 operands + // viz., BaseReg, ScaleAmt, IndexReg, Disp, Segment, ... + // The disassembly in AT&T syntax is shown as + // Segment:Disp(BaseReg, IndexReg, ScaleAmt). + // or as + // Segment:[BaseReg + Disp + IndexReg * ScaleAmt] + // in Intel syntax. + // effective address is calculated to be Segment:[BaseReg + IndexReg * + // ScaleAmt + Disp] Segment is typically X86::NoRegister. + + assert(mi.getOperand(memoryRefOpIndex + X86::AddrSegmentReg).getReg() == + X86::NoRegister && + "Expect no segment register"); + // Construct non-stack memory referencing value + unsigned BaseReg = memRef.Base.Reg; + unsigned IndexReg = memRef.IndexReg; + unsigned ScaleAmt = memRef.Scale; + int Disp = memRef.Disp; + const MachineOperand &SegRegOperand = + mi.getOperand(memoryRefOpIndex + X86::AddrSegmentReg); + // For now, we assume default segment DS (and hence no specification of + // Segment register. + assert(SegRegOperand.isReg() && (SegRegOperand.getReg() == X86::NoRegister) && + "Unhandled memory reference instruction with non-zero segment " + "register"); + + // Non-stack memory address is supported by this function. + uint64_t BaseSupReg = find64BitSuperReg(BaseReg); + assert((BaseSupReg != x86RegisterInfo->getStackRegister()) && + (BaseSupReg != x86RegisterInfo->getFramePtr()) && + "Not yet supported: Abstraction of value representing stack-based " + "address expression"); + // IndexReg * ScaleAmt + // Generate mul scaleAmt, IndexRegVal, if IndexReg is not 0. + if (IndexReg != X86::NoRegister) { + Value *IndexRegVal = getRegValue(IndexReg); + switch (ScaleAmt) { + case 0: + break; + case 1: + memrefValue = IndexRegVal; + break; + default: { + Type *MulValTy = IndexRegVal->getType(); + Value *ScaleAmtValue = ConstantInt::get(MulValTy, ScaleAmt); + Instruction *MulInst = + BinaryOperator::CreateMul(ScaleAmtValue, IndexRegVal); + curBlock->getInstList().push_back(MulInst); + memrefValue = MulInst; + } break; + } + } + + // BaseReg + IndexReg*ScaleAmt + // Generate add BaseRegVal, memrefVal (if IndexReg*ScaleAmt was computed) + + if (BaseReg != X86::NoRegister) { + Value *BaseRegVal = getRegValue(BaseReg); + if (memrefValue != nullptr) { + Instruction *AddInst = BinaryOperator::CreateAdd(BaseRegVal, memrefValue); + curBlock->getInstList().push_back(AddInst); + memrefValue = AddInst; + } else { + memrefValue = BaseRegVal; + } + } + + // BaseReg + Index*ScaleAmt + Disp + // + if (Disp != 0) { + if (memrefValue != nullptr) { + // Generate add memrefVal, Disp + Type *DispTy = memrefValue->getType(); + Value *DispValue = ConstantInt::get(DispTy, Disp); + Instruction *AddInst = BinaryOperator::CreateAdd(memrefValue, DispValue); + curBlock->getInstList().push_back(AddInst); + memrefValue = AddInst; + } else { + // Check that this is an instruction of the kind + // mov %rax, 0x605798 which in reality is + // mov %rax, 0x605798(X86::NoRegister, X86::NoRegister, 1) + assert(((BaseReg == X86::NoRegister) && (IndexReg == X86::NoRegister) && + (ScaleAmt == 1)) && + "Unhandled addressing mode in memory addr expression calculation"); + memrefValue = getGlobalVariableValueAt(mi, Disp); + } + } + assert((memrefValue != nullptr) && "Failed to get memory reference value"); + return memrefValue; +} + +// Find the (SSA) Value currently mapped to to PhyRes. +// Return nullptr if none exists. +// NOTE : DO NOT call this directly unless you wish to check to +// see if this is an argument register. +// Use getRegValue(unsigned PReg) instead. + +// Find SSA value associated with physical register PReg. +// If the PReg is an argument register and hence does not have a +// previous definition, function prototype is consulted to return +// the corresponding value. In that case, return argument value +// associated with physical register PReg according to C calling +// convention. +// NOTE : This is the preferred API to get the SSA value associated +// with PReg. Do not use findPhysRegSSAValue(unsigned) as you +// do not need to. See comment of that function for more details. + +Value *X86MachineInstructionRaiser::getRegValue(unsigned PReg) { + Value *PRegValue = findPhysRegSSAValue(PReg); + + // Just return the value associated with PReg, if one exists. + if (PRegValue == nullptr) { + int pos = getArgumentNumber(PReg); + + // If PReg is an argument register, get its value from function + // argument list. + if (pos > 0) { + // Get the value only if the function has an argument at + // pos. + if (pos <= (int)raisedFunction->arg_size()) { + Function::arg_iterator argIter = raisedFunction->arg_begin() + pos - 1; + PRegValue = argIter; + } + } + } + return PRegValue; +} + +// Get the 64-bit super register of PhysReg. Return PhysReg is it is +// a 64-bit register. +// Add a new PhysReg-Val pair if no mapping for PhysReg exists +// Replace the mapping to PhysReg-Val if one already exists. +Type * +X86MachineInstructionRaiser::getReturnTypeFromMBB(MachineBasicBlock &MBB) { + Type *returnType = nullptr; + + // Check liveness of EAX in the return block. We assume that EAX (or + // RAX) would have to be defined in the return block. + // TODO : We may have to revisit this assumption, if needed. + + MachineBasicBlock::const_iterator I(MBB.back()); + if (I != MBB.begin()) { + do { + --I; + // Check if any of RAX, EAX, AX or AL are defined + if (I->getDesc().getNumDefs() != 0) { + const MachineOperand &MO = I->getOperand(0); + if (!MO.isReg()) { + continue; + } + unsigned PReg = MO.getReg(); + if (!TargetRegisterInfo::isPhysicalRegister(PReg)) { + continue; + } + if (PReg == X86::RAX) { + if (returnType == nullptr) { + returnType = Type::getInt64Ty(MF.getFunction().getContext()); + break; + } else { + assert(returnType->isIntegerTy() && + returnType->getScalarSizeInBits() == 64 && + "Inconsistency while discovering return type"); + } + } else if (PReg == X86::EAX) { + if (returnType == nullptr) { + returnType = Type::getInt32Ty(MF.getFunction().getContext()); + break; + } else { + assert(returnType->isIntegerTy() && + returnType->getScalarSizeInBits() == 32 && + "Inconsistency while discovering return type"); + } + } else if (PReg == X86::AX) { + if (returnType == nullptr) { + returnType = Type::getInt16Ty(MF.getFunction().getContext()); + break; + } else { + assert(returnType->isIntegerTy() && + returnType->getScalarSizeInBits() == 16 && + "Inconsistency while discovering return type"); + } + } else if (PReg == X86::AL) { + if (returnType == nullptr) { + returnType = Type::getInt8Ty(MF.getFunction().getContext()); + break; + } else { + assert(returnType->isIntegerTy() && + returnType->getScalarSizeInBits() == 8 && + "Inconsistency while discovering return type"); + } + } + } + } while (I != MBB.begin()); + } + return returnType; +} + +Type *X86MachineInstructionRaiser::getFunctionReturnType() { + Type *returnType = nullptr; + SmallVector WorkList; + BitVector BlockVisited(MF.getNumBlockIDs(), false); + + assert(x86TargetInfo.is64Bit() && "Only x86_64 binaries supported for now"); + + // Find a return block. It is sufficient to get the dominator tree path + // whose leaf is one of the return blocks to find the return type. This + // type should be the same on any of the dominator paths from entry to + // return block. + MachineBasicBlock *RetBlock = nullptr; + for (MachineBasicBlock &MBB : MF) { + if (MBB.isReturnBlock()) { + RetBlock = &MBB; + break; + } + } + + WorkList.push_back(RetBlock); + + while (!WorkList.empty()) { + MachineBasicBlock *N = WorkList.pop_back_val(); + assert(!BlockVisited[N->getNumber()] && + "Encountered previously visited block"); + // Mark block as visited + BlockVisited.set(N->getNumber()); + returnType = getReturnTypeFromMBB(*N); + if (returnType != nullptr) { + return returnType; + } + for (auto P : N->predecessors()) { + WorkList.push_back(P); + } + } + return nullptr; +} + +// Construct prototype of the Function for the MachineFunction being raised. +FunctionType *X86MachineInstructionRaiser::getRaisedFunctionPrototype() { + + if (raisedFunction == nullptr) { + // Cleanup NOOP instructions from all MachineBasicBlocks + deleteNOOPInstrMF(); + + MF.getRegInfo().freezeReservedRegs(MF); + Type *returnType = nullptr; + std::vector argTypeVector; + + // 1. Discover function arguments. + // Build live-ins for all blocks + LivePhysRegs liveInPhysRegs; + for (MachineBasicBlock &MBB : MF) { + computeAndAddLiveIns(liveInPhysRegs, MBB); + } + + // Get the live-in values of the entry block. These should be the + // arguments. + MachineBasicBlock &MBB = MF.front(); + MBB.sortUniqueLiveIns(); + + std::set LiveInRegs; + + for (const auto &LI : MBB.liveins()) { + LiveInRegs.emplace(LI.PhysReg); + } + buildFuncArgTypeVector(LiveInRegs, argTypeVector); + // 2. Discover function return type + returnType = getFunctionReturnType(); + // If we are unable to discover the return type assume that the return + // type is void. + // TODO : Refine this once support is added to discover arguments passed + // on the stack?? + if (returnType == nullptr) { + returnType = Type::getVoidTy(MF.getFunction().getContext()); + } + + // The Function object associated with current MachineFunction object + // is only a place holder. It was created to facilitate creation of + // MachineFunction object with a prototype void functionName(void). + // The Module object contains this place-holder Function object in its + // FunctionList. Since the return type and arguments are now discovered, + // we need to replace this place holder Function object in module with the + // correct Function object being created now. + // 1. Get the current function name + StringRef functionName = MF.getFunction().getName(); + Module &module = MR->getModule(); + // 2. Get the corresponding Function* registered in module + Function *tempFunctionPtr = module.getFunction(functionName); + assert(tempFunctionPtr != nullptr && "Function not found in module list"); + // 4. Delete the tempFunc from module list to allow for the creation of + // the real function to add the correct one to FunctionList of the + // module. + module.getFunctionList().remove(tempFunctionPtr); + // 3. Now create a function type using the discovered argument + // types and return value. + FunctionType *FT = + FunctionType::get(returnType, argTypeVector, false /* isVarArg*/); + // 4. Create the real Function now that we have discovered the arguments. + raisedFunction = Function::Create(FT, GlobalValue::ExternalLinkage, + functionName, &module); + + // Set global linkage + raisedFunction->setLinkage(GlobalValue::ExternalLinkage); + // Set C calling convention + raisedFunction->setCallingConv(CallingConv::C); + // TODO : Set other function attributes as needed. + // Add argument names to the function. + // Note: Call to arg_begin() calls Function::BuildLazyArguments() + // to build the arguments. + Function::arg_iterator ArgIt = raisedFunction->arg_begin(); + unsigned numFuncArgs = raisedFunction->arg_size(); + StringRef prefix("arg"); + for (unsigned i = 0; i < numFuncArgs; ++i, ++ArgIt) { + // Set the name. + ArgIt->setName(prefix + std::to_string(i + 1)); + } + + // Insert the map of raised function to tempFunctionPointer. + const_cast(MR)->insertPlaceholderRaisedFunctionMap( + raisedFunction, tempFunctionPtr); + } + + return raisedFunction->getFunctionType(); +} + +// Find the index of the first memory reference operand. +int X86MachineInstructionRaiser::getMemoryRefOpIndex(const MachineInstr &mi) { + const MCInstrDesc &Desc = mi.getDesc(); + int memOperandNo = X86II::getMemoryOperandNo(Desc.TSFlags); + if (memOperandNo >= 0) { + memOperandNo += X86II::getOperandBias(Desc); + } + return memOperandNo; +} + +// Check the sizes of the operand register at SrcOpindex and that of the +// corresponding SSA value. Return a value that is either truncated or +// sign-extended version of the SSA Value if their sizes do not match. +// Return the SSA value of the operand register at SrcOpindex, if they match. +// This is handles the situation following pattern of instructions +// rax <- ... +// edx <- opcode eax, ... +bool X86MachineInstructionRaiser::insertAllocaInEntryBlock( + Instruction *alloca) { + + // Avoid using BasicBlock InstrList iterators so that the tool can + // use LLVM built with LLVM_ABI_BREAKING_CHECKS ON or OFF. + BasicBlock &EntryBlock = getRaisedFunction()->getEntryBlock(); + + BasicBlock::InstListType &InstList = EntryBlock.getInstList(); + if (InstList.size() == 0) { + InstList.push_back(alloca); + } else { + Instruction *Inst = &EntryBlock.back(); + while (Inst != nullptr) { + if (Inst->getOpcode() == Instruction::Alloca) { + InstList.insert(Inst->getNextNode()->getIterator(), alloca); + break; + } + Inst = Inst->getPrevNode(); + } + // If there is no alloca instruction yet, push to front + if (Inst == nullptr) { + InstList.push_front(alloca); + } + } + return true; +} + +Value *X86MachineInstructionRaiser::matchSSAValueToSrcRegSize( + const MachineInstr &mi, unsigned SrcOpIndex, BasicBlock *curBlock) { + unsigned SrcOpSize = getPhysRegOperandSize(mi, SrcOpIndex); + Value *SrcOpValue = getRegValue(mi.getOperand(SrcOpIndex).getReg()); + const DataLayout &dataLayout = MR->getModule().getDataLayout(); + + // Generate the appropriate cast instruction if the sizes of the current + // source value and that of the source register do not match. + uint64_t SrcValueSize = + dataLayout.getTypeSizeInBits(SrcOpValue->getType()) / sizeof(uint64_t); + + assert(SrcValueSize <= sizeof(uint64_t) && SrcOpSize <= sizeof(uint64_t) && + "Unexpected source Value size in move instruction"); + + if (SrcOpSize != SrcValueSize) { + Type *CastTy = getPhysRegOperandType(mi, SrcOpIndex); + CastInst *CInst = CastInst::Create( + CastInst::getCastOpcode(SrcOpValue, false, CastTy, false), SrcOpValue, + CastTy); + curBlock->getInstList().push_back(CInst); + SrcOpValue = CInst; + } + return SrcOpValue; +} + +// Record information to raise a terminator instruction in a later pass. +bool X86MachineInstructionRaiser::recordMachineInstrInfo(const MachineInstr &mi, + BasicBlock *curBlock) { + // Return instruction is a Terminator. There is nothing to record. + // Its raising is handled as a normal instruction. This function should not + // be called when mi is a call instruction. + assert(mi.isTerminator() && "Not a terminator instruction - can not record " + "control transfer information"); + assert(!mi.isReturn() && + "Unexpected attempt to record info for a return instruction"); + + // Set common info of the record + ControlTransferInfo *CurCTInfo = new ControlTransferInfo; + CurCTInfo->CandidateMachineInstr = &mi; + CurCTInfo->CandidateBlock = curBlock; + + const MCInstrDesc &MCID = mi.getDesc(); + // Save all values of implicitly used operands + unsigned ImplUsesCount = MCID.getNumImplicitUses(); + if (ImplUsesCount > 0) { + const MCPhysReg *ImplUses = MCID.getImplicitUses(); + for (unsigned i = 0; i < ImplUsesCount; i++) { + Value *val = getRegValue(ImplUses[i]); + CurCTInfo->RegValues.push_back(val); + } + } + CurCTInfo->Raised = false; + CTInfo.push_back(CurCTInfo); + + return true; +} + +std::pair::iterator, bool> +X86MachineInstructionRaiser::updatePhysRegSSAValue(unsigned int PhysReg, + Value *Val) { + // Always convert PhysReg to the 64-bit version. + unsigned int SuperReg = find64BitSuperReg(PhysReg); + + if (findPhysRegSSAValue(SuperReg)) { + physToValueMap.erase(SuperReg); + } + return physToValueMap.emplace(SuperReg, Val); +} + +bool X86MachineInstructionRaiser::raisePushInstruction(const MachineInstr &mi) { + // TODO : Need to handle push instructions other than those that push bp to + // stack. + const MCInstrDesc &MCIDesc = mi.getDesc(); + uint64_t MCIDTSFlags = MCIDesc.TSFlags; + + if ((MCIDTSFlags & X86II::FormMask) == X86II::AddRegFrm) { + // This is a register PUSH. If the source is base pointer, + // not need to raise the instruction. + if (find64BitSuperReg(mi.getOperand(0).getReg()) == X86::RBP) { + return true; + } else { + assert(false && "Unhandled PUSH instruction that stores a register " + "other than frame pointer"); + } + } else { + assert(false && "Unhandled PUSH instruction with source operand other " + "than AddrRegFrm"); + } + return false; +} + +bool X86MachineInstructionRaiser::raisePopInstruction(const MachineInstr &mi) { + // TODO : Need to handle pop instructions other than those that restore bp + // from stack. + const MCInstrDesc &MCIDesc = mi.getDesc(); + uint64_t MCIDTSFlags = MCIDesc.TSFlags; + + if ((MCIDTSFlags & X86II::FormMask) == X86II::AddRegFrm) { + // This is a register POP. If the source is base pointer, + // not need to raise the instruction. + if (mi.definesRegister(X86::RBP) || mi.definesRegister(X86::EBP)) { + return true; + } else { + assert(false && "Unhandled POP instruction that restores a register " + "other than frame pointer"); + } + } else { + if (getInstructionKind(mi.getOpcode()) == InstructionKind::LEAVE_OP) { + return true; + } + assert(false && "Unhandled POP instruction with source operand other " + "than AddrRegFrm"); + } + return false; +} + +bool X86MachineInstructionRaiser::raiseConvertBWWDDQMachineInstr( + const MachineInstr &mi, BasicBlock *curBlock) { + const MCInstrDesc &MIDesc = mi.getDesc(); + unsigned int opcode = mi.getOpcode(); + LLVMContext &llvmContext(MF.getFunction().getContext()); + + assert(MIDesc.getNumImplicitUses() == 1 && MIDesc.getNumImplicitDefs() == 1 && + "Unexpected number of implicit uses and defs in cbw/cwde/cdqe " + "instruction"); + MCPhysReg UseReg = MIDesc.ImplicitUses[0]; + MCPhysReg DefReg = MIDesc.ImplicitDefs[0]; + Type *TargetTy = nullptr; + + if (opcode == X86::CDQE) { + assert(is32BitPhysReg(UseReg) && + "Unexpected non-32-bit register in cdqe instruction"); + assert(is64BitPhysReg(DefReg) && + "Unexpected non-64-bit register in cdqe instruction"); + TargetTy = Type::getInt64Ty(llvmContext); + } else if (opcode == X86::CBW) { + assert(is8BitPhysReg(UseReg) && + "Unexpected non-32-bit register in cbw instruction"); + assert(is16BitPhysReg(DefReg) && + "Unexpected non-64-bit register in cbw instruction"); + TargetTy = Type::getInt16Ty(llvmContext); + } else if (opcode == X86::CWDE) { + assert(is16BitPhysReg(UseReg) && + "Unexpected non-32-bit register in cwde instruction"); + assert(is32BitPhysReg(DefReg) && + "Unexpected non-64-bit register in cwde instruction"); + TargetTy = Type::getInt32Ty(llvmContext); + } + assert(TargetTy != nullptr && + "Target type not set for cbw/cwde/cdqe instruction"); + Value *UseValue = getRegValue(UseReg); + + // Generate sign-extend instruction + SExtInst *SextInst = new SExtInst(UseValue, TargetTy); + curBlock->getInstList().push_back(SextInst); + + // Update the value mapping of DefReg + updatePhysRegSSAValue(DefReg, SextInst); + return true; +} + +bool X86MachineInstructionRaiser::raiseConvertWDDQQOMachineInstr( + const MachineInstr &mi, BasicBlock *curBlock) { + const MCInstrDesc &MIDesc = mi.getDesc(); + unsigned int opcode = mi.getOpcode(); + LLVMContext &llvmContext(MF.getFunction().getContext()); + + assert(MIDesc.getNumImplicitUses() == 1 && MIDesc.getNumImplicitDefs() == 2 && + "Unexpected number of implicit uses and defs in cwd/cdq/cqo " + "instruction"); + MCPhysReg UseReg = MIDesc.ImplicitUses[0]; + MCPhysReg DefReg_0 = MIDesc.ImplicitDefs[0]; + MCPhysReg DefReg_1 = MIDesc.ImplicitDefs[1]; + Type *TargetTy = nullptr; + Type *UseRegTy = nullptr; + + if (opcode == X86::CWD) { + assert( + is16BitPhysReg(UseReg) && is16BitPhysReg(DefReg_0) && + is16BitPhysReg(DefReg_1) && (UseReg == DefReg_0) && + "Unexpected characteristics of use/def registers in cwd instruction"); + TargetTy = Type::getInt32Ty(llvmContext); + UseRegTy = Type::getInt16Ty(llvmContext); + } else if (opcode == X86::CDQ) { + assert( + is32BitPhysReg(UseReg) && is32BitPhysReg(DefReg_0) && + is32BitPhysReg(DefReg_1) && (UseReg == DefReg_0) && + "Unexpected characteristics of use/def registers in cdq instruction"); + TargetTy = Type::getInt64Ty(llvmContext); + UseRegTy = Type::getInt32Ty(llvmContext); + } else if (opcode == X86::CQO) { + assert( + is64BitPhysReg(UseReg) && is16BitPhysReg(DefReg_0) && + is64BitPhysReg(DefReg_1) && (UseReg == DefReg_0) && + "Unexpected characteristics of use/def registers in cdo instruction"); + TargetTy = Type::getInt128Ty(llvmContext); + UseRegTy = Type::getInt64Ty(llvmContext); + } + + assert((TargetTy != nullptr) && (UseRegTy != nullptr) && + "Target type not set for cwd/cdq/cqo instruction"); + Value *UseValue = getRegValue(UseReg); + + // Generate sign-extend instruction + SExtInst *TargetSextInst = new SExtInst(UseValue, TargetTy); + assert(UseValue->getType()->getScalarSizeInBits() == + UseRegTy->getScalarSizeInBits() && + "Mismatched types in cwd/cdq/cqo instruction"); + curBlock->getInstList().push_back(TargetSextInst); + + // Logical Shift TargetSextInst by n-bits (where n is the size of UserRegTy) + // to get the high bytes and set DefReg_1 to the resulting value. + Value *ShiftAmount = ConstantInt::get( + TargetTy, UseRegTy->getScalarSizeInBits(), false /* isSigned */); + Instruction *LShrInst = + BinaryOperator::CreateLShr(TargetSextInst, ShiftAmount); + curBlock->getInstList().push_back(LShrInst); + // Truncate LShrInst to get the high bytes + Instruction *HighBytesInst = + CastInst::Create(Instruction::Trunc, LShrInst, UseRegTy); + curBlock->getInstList().push_back(HighBytesInst); + // Update the value mapping of DefReg_1 + updatePhysRegSSAValue(DefReg_1, HighBytesInst); + + return true; +} + +bool X86MachineInstructionRaiser::raiseMoveImmToRegMachineInstr( + const MachineInstr &mi, BasicBlock *curBlock) { + unsigned int opcode = mi.getOpcode(); + // LLVMContext &llvmContext(MF.getFunction().getContext()); + bool success = false; + + switch (opcode) { + case X86::MOV8ri: + case X86::MOV16ri: + case X86::MOV32ri: + case X86::MOV64ri: { + unsigned DestOpIndex = 0, SrcOpIndex = 1; + const MachineOperand &DestOp = mi.getOperand(DestOpIndex); + const MachineOperand &SrcOp = mi.getOperand(SrcOpIndex); + assert(mi.getNumExplicitOperands() == 2 && DestOp.isReg() && + SrcOp.isImm() && + "Expecting exactly two operands for move imm-to-reg instructions"); + + unsigned int DstPReg = DestOp.getReg(); + int64_t SrcImm = SrcOp.getImm(); + + unsigned int DstPRegSize = getPhysRegOperandSize(mi, DestOpIndex); + + Type *ImmTy = getImmOperandType(mi, 1); + Value *srcValue = nullptr; + + assert(DstPRegSize == + (ImmTy->getPrimitiveSizeInBits() / sizeof(uint64_t)) && + "Mismatched imm and dest sizes in move imm to reg instruction."); + if (opcode == X86::MOV64ri) { + srcValue = + const_cast(getOrCreateGlobalRODataValueAtAt(mi, SrcImm)); + } else { + srcValue = ConstantInt::get(ImmTy, SrcImm); + } + // Update the value mapping of dstReg + updatePhysRegSSAValue(DstPReg, srcValue); + success = true; + } break; + default: + assert(false && "Unhandled move imm-to-reg instruction"); + break; + } + return success; +} + +bool X86MachineInstructionRaiser::raiseMoveRegToRegMachineInstr( + const MachineInstr &mi, BasicBlock *curBlock) { + unsigned int opcode = mi.getOpcode(); + LLVMContext &llvmContext(MF.getFunction().getContext()); + bool success = false; + unsigned DstIndex = 0; + unsigned SrcIndex = 1; + assert(mi.getNumExplicitOperands() == 2 && mi.getOperand(DstIndex).isReg() && + mi.getOperand(SrcIndex).isReg() && + "Expecting exactly two operands for move reg-to-reg instructions"); + + unsigned int DstPReg = mi.getOperand(DstIndex).getReg(); + unsigned int SrcPReg = mi.getOperand(SrcIndex).getReg(); + + // Get source value + Value *srcValue = getRegValue(SrcPReg); + + switch (opcode) { + case X86::MOVSX16rr8: + case X86::MOVSX32rr8: + case X86::MOVSX32rr16: + case X86::MOVSX64rr8: + case X86::MOVSX64rr16: + case X86::MOVSX64rr32: + case X86::MOVZX16rr8: + case X86::MOVZX32rr8: + case X86::MOVZX32rr16: + case X86::MOVZX64rr8: + case X86::MOVZX64rr16: { + Type *Ty = nullptr; + Instruction::CastOps Cast; + // Check for sanity of source value + assert(srcValue && + "Encountered instruction with undefined source register"); + + switch (opcode) { + case X86::MOVSX16rr8: { + assert(is16BitPhysReg(DstPReg) && + "Not found expected 16-bit destination register - movsx " + "instruction"); + Ty = Type::getInt16Ty(llvmContext); + Cast = Instruction::SExt; + } break; + case X86::MOVSX32rr8: + case X86::MOVSX32rr16: { + assert(is32BitPhysReg(DstPReg) && + "Not found expected 32-bit destination register - movsx " + "instruction"); + Ty = Type::getInt32Ty(llvmContext); + Cast = Instruction::SExt; + } break; + case X86::MOVSX64rr8: + case X86::MOVSX64rr16: + case X86::MOVSX64rr32: { + assert(is64BitPhysReg(DstPReg) && + "Not found expected 64-bit destination register - movsx " + "instruction"); + Ty = Type::getInt64Ty(llvmContext); + Cast = Instruction::SExt; + } break; + case X86::MOVZX16rr8: { + assert(is16BitPhysReg(DstPReg) && + "Not found expected 16-bit destination register - movsx " + "instruction"); + Ty = Type::getInt16Ty(llvmContext); + Cast = Instruction::ZExt; + } break; + case X86::MOVZX32rr8: + case X86::MOVZX32rr16: { + assert(is32BitPhysReg(DstPReg) && + "Not found expected 32-bit destination register - movsx " + "instruction"); + Ty = Type::getInt32Ty(llvmContext); + Cast = Instruction::ZExt; + } break; + case X86::MOVZX64rr8: + case X86::MOVZX64rr16: { + assert(is64BitPhysReg(DstPReg) && + "Not found expected 64-bit destination register - movsx " + "instruction"); + Ty = Type::getInt64Ty(llvmContext); + Cast = Instruction::ZExt; + } break; + default: + assert(false && "Should not reach here! - movsx instruction"); + } + + assert(Ty != nullptr && "Failed to set type - movsx instruction"); + CastInst *CInst = CastInst::Create(Cast, srcValue, Ty); + curBlock->getInstList().push_back(CInst); + + // Update the value mapping of dstReg + updatePhysRegSSAValue(DstPReg, CInst); + success = true; + + } break; + + case X86::MOV64rr: + case X86::MOV32rr: + case X86::MOV16rr: + case X86::MOV8rr: { + + unsigned int DstPRegSize = getPhysRegOperandSize(mi, DstIndex); + unsigned int SrcPRegSize = getPhysRegOperandSize(mi, SrcIndex); + + // Verify sanity of the instruction. + assert(DstPRegSize != 0 && DstPRegSize == SrcPRegSize && + "Unexpected sizes of source and destination registers size differ " + "in mov instruction"); + + // Source register is either stack pointer or base pointer and destination + // register is correspondingly not base pointer or stack pointer. + if (((find64BitSuperReg(SrcPReg) == X86::RSP) && + !(find64BitSuperReg(DstPReg) == X86::RBP)) || + ((find64BitSuperReg(SrcPReg) == X86::RBP) && + !(find64BitSuperReg(DstPReg) == X86::RSP))) { + // This is a mov (e|r)sp to reg or mov (e|r)bp to reg. This is treated + // as a load effective address instruction lea (%rsp), reg or lea + // (%rbp), reg + X86AddressMode stackAddr; + stackAddr.Base.Reg = SrcPReg; + unsigned int stackFrameIndex; + // If this is a new stack reference + MemRefToFrameIndexMapType::iterator mapIter = + memRefToFrameIndexMap.find(stackAddr); + if (mapIter == memRefToFrameIndexMap.end()) { + // Create an alloca instruction since this memory reference is + // encountered for the first time. + Type *Ty = nullptr; + // Uninitialized stack object size + uint64_t stackObjectSize = 0; + unsigned int typeAlignment; + const DataLayout &dataLayout = MR->getModule().getDataLayout(); + unsigned allocaAddrSpace = dataLayout.getAllocaAddrSpace(); + + switch (SrcPReg) { + case X86::RSP: { + Ty = Type::getInt64Ty(llvmContext); + stackObjectSize = 8; + } break; + case X86::ESP: { + Ty = Type::getInt32Ty(llvmContext); + stackObjectSize = 4; + } break; + case X86::SP: { + Ty = Type::getInt16Ty(llvmContext); + stackObjectSize = 2; + } break; + default: + assert(false && "Encountered stack register of unexpected size"); + break; + } + + assert(stackObjectSize != 0 && Ty != nullptr && + "Unknown type of operand in memory referencing instruction"); + typeAlignment = dataLayout.getPrefTypeAlignment(Ty); + + // Create alloca instruction to allocate stack slot + AllocaInst *alloca = + new AllocaInst(Ty, allocaAddrSpace, 0, typeAlignment); + + // Create a stack slot associated with the alloca instruction + stackFrameIndex = MF.getFrameInfo().CreateStackObject( + stackObjectSize, dataLayout.getPrefTypeAlignment(Ty), + false /* isSpillSlot */, alloca); + + MF.getFrameInfo().setObjectOffset(stackFrameIndex, stackAddr.Disp); + + // Book-keeping: Add memory reference to the map + memRefToFrameIndexMap.emplace(stackAddr, stackFrameIndex); + // Add the alloca instruction to entry block + insertAllocaInEntryBlock(alloca); + } + // Stack frame slot already allocated for this memRef + else { + stackFrameIndex = (*mapIter).second; + } + srcValue = const_cast( + MF.getFrameInfo().getObjectAllocation(stackFrameIndex)); + // Update the value mapping of dstReg + updatePhysRegSSAValue(DstPReg, srcValue); + } + // Neither of the source nor the destination registers is stack pointer or + // base pointer. Note that there is no need to raise move (e|r)sp to (e|r)bp + else if (!((find64BitSuperReg(SrcPReg) == X86::RSP) && + (find64BitSuperReg(DstPReg) == X86::RBP))) { + assert(srcValue && + "Encountered mov instruction with undefined source register"); + assert(srcValue->getType()->isSized() && + "Unsized source value in move instruction"); + srcValue = matchSSAValueToSrcRegSize(mi, SrcIndex, curBlock); + // Update the value mapping of dstReg + updatePhysRegSSAValue(DstPReg, srcValue); + } else { + // Make sure this is mov (r|e)sp, (r|e)bp or mov (r|e)bp, (r|e)sp + assert((((find64BitSuperReg(SrcPReg) == X86::RSP) && + (find64BitSuperReg(DstPReg) == X86::RBP)) || + ((find64BitSuperReg(SrcPReg) == X86::RBP) && + (find64BitSuperReg(DstPReg) == X86::RSP))) && + "Unhandled reg-to-reg mov instruction"); + } + + success = true; + } break; + default: + assert(false && "Unhandled move reg-to-reg instruction"); + break; + } + return success; +} + +bool X86MachineInstructionRaiser::raiseLEAMachineInstr(const MachineInstr &mi, + BasicBlock *curBlock) { + unsigned int opcode = mi.getOpcode(); + + assert(mi.getNumExplicitOperands() == 6 && + "Unexpected number of arguments of lea instruction"); + // Get dest operand + MachineOperand DestOp = mi.getOperand(0); + assert(DestOp.isReg() && + "Unhandled non-register destination operand in lea instruction"); + unsigned int DestReg = DestOp.getReg(); + + int OpIndex = X86II::getMemoryOperandNo(mi.getDesc().TSFlags); + assert(OpIndex >= 0 && "Failed to get first operand of addressing-mode " + "expression in lea instruction"); + + MachineOperand BaseRegOp = mi.getOperand(OpIndex + X86::AddrBaseReg); + assert(BaseRegOp.isReg() && + "Unhandled non-register BaseReg operand in lea instruction"); + unsigned int BaseReg = BaseRegOp.getReg(); + Value *EffectiveAddrValue = nullptr; + + // If the basereg refers stack, get the stack allocated object value + uint64_t BaseSupReg = find64BitSuperReg(BaseReg); + if ((BaseSupReg == x86RegisterInfo->getStackRegister()) || + (BaseSupReg == x86RegisterInfo->getFramePtr())) { + EffectiveAddrValue = getStackAllocatedValue(mi, curBlock, OpIndex); + } else { + MachineOperand ScaleAmtOp = mi.getOperand(OpIndex + X86::AddrScaleAmt); + assert(ScaleAmtOp.isImm() && + "Unhandled non-immediate ScaleAmt operand in lea instruction"); + + MachineOperand IndexRegOp = mi.getOperand(OpIndex + X86::AddrIndexReg); + assert(IndexRegOp.isReg() && + "Unhandled non-register IndexReg operand in lea instruction"); + + unsigned int IndexReg = IndexRegOp.getReg(); + + MachineOperand SegmentRegOp = mi.getOperand(OpIndex + X86::AddrSegmentReg); + assert(SegmentRegOp.getReg() == X86::NoRegister && + "Unhandled vaule of SegmentReg operand in lea instruction"); + + MachineOperand Disp = mi.getOperand(OpIndex + X86::AddrDisp); + assert(Disp.isImm() && + "Unhandled non-immediate Disp operand in lea instruction"); + + // Check the sanity of register sizes + if ((opcode == X86::LEA64r) || (opcode == X86::LEA64_32r)) { + // lea64mem (see LEA64 and LEA64_32r description in + // X86InstrArithmetic.td) + assert((is64BitPhysReg(BaseReg) || BaseReg == X86::NoRegister) && + "Unexpected non-64 bit base register in lea instruction"); + assert(((IndexReg == X86::NoRegister) || is64BitPhysReg(IndexReg)) && + "Unexpected index register type in lea instruction"); + assert(IndexReg != x86RegisterInfo->getStackRegister() && + "Unexpected stack pointer register as indexReg operand of lea " + "instruction"); + if (opcode == X86::LEA64_32r) { + assert(is32BitPhysReg(DestReg) && + "Unexpected non-32 bit destination register in lea instruction"); + } else { + assert(is64BitPhysReg(DestReg) && + "Unexpected non-32 bit dest register in lea instruction"); + } + } else if (opcode == X86::LEA32r) { + assert((is32BitPhysReg(BaseReg) || BaseReg == X86::NoRegister) && + "Unexpected non-32 bit base register in lea instruction"); + assert(((IndexReg == X86::NoRegister) || is32BitPhysReg(IndexReg)) && + "Unexpected indext register type in lea instruction"); + assert(is32BitPhysReg(DestReg) && + "Unexpected non-32 bit dest register in lea instruction"); + } else if (opcode == X86::LEA16r) { + assert((is16BitPhysReg(BaseReg) || BaseReg == X86::NoRegister) && + "Unexpected non-16 bit source register in lea instruction"); + assert(((IndexReg == X86::NoRegister) || is16BitPhysReg(IndexReg)) && + "Unexpected indext register type in lea instruction"); + assert(is16BitPhysReg(DestReg) && + "Unexpected non-16 bit dest register in lea instruction"); + } + + EffectiveAddrValue = getMemoryAddressExprValue(mi, curBlock); + } + + assert((EffectiveAddrValue != nullptr) && + "Failed to get effective address value"); + + // Update the value mapping of DestReg + updatePhysRegSSAValue(DestReg, EffectiveAddrValue); + return true; +} + +bool X86MachineInstructionRaiser::raiseBinaryOpRegToRegMachineInstr( + const MachineInstr &mi, BasicBlock *curBlock) { + + auto MCID = mi.getDesc(); + std::vector Uses; + for (const MachineOperand &MO : mi.explicit_uses()) { + assert(MO.isReg() && + "Unexpected non-register operand in binary op instruction"); + unsigned int SrcReg = MO.getReg(); + Value *srcValue = getRegValue(SrcReg); + Uses.push_back(srcValue); + } + // Verify there are exactly 2 use operands. + assert(Uses.size() == 2 && + "Expecting exactly two operands for register binary op instruction"); + + // Figure out the destination register, corresponding value and the + // binary operator. + unsigned int dstReg = X86::NoRegister; + Value *dstValue = nullptr; + + // Construct the appropriate binary operation instruction + switch (mi.getOpcode()) { + case X86::ADD64rr: + case X86::ADD32rr: + // Verify the def operand is a register. + assert(mi.getOperand(0).isReg() && + "Expecting destination of add instruction to be a register operand"); + assert((MCID.getNumDefs() == 1) && + "Unexpected number of defines in an add instruction"); + assert((Uses.at(0) != nullptr) && (Uses.at(1) != nullptr) && + "Unhandled situation: register is used before initialization in " + "add"); + dstReg = mi.getOperand(0).getReg(); + dstValue = BinaryOperator::CreateNSWAdd(Uses.at(0), Uses.at(1)); + break; + case X86::IMUL32rr: + case X86::IMUL64rr: + // Verify the def operand is a register. + assert(mi.getOperand(0).isReg() && + "Expecting destination of mul instruction to be a register operand"); + assert((MCID.getNumDefs() == 1) && + "Unexpected number of defines in a mul instruction"); + assert( + (Uses.at(0) != nullptr) && (Uses.at(1) != nullptr) && + "Unhandled situation: register is used before initialization in mul"); + dstReg = mi.getOperand(0).getReg(); + dstValue = BinaryOperator::CreateNSWMul(Uses.at(0), Uses.at(1)); + break; + case X86::XOR32rr: + case X86::XOR64rr: { + // Verify the def operand is a register. + const MachineOperand &DestOp = mi.getOperand(0); + // const MachineOperand &Use1Op = mi.getOperand(1); + const MachineOperand &Use2Op = mi.getOperand(2); + assert(DestOp.isReg() && + "Expecting destination of xor instruction to be a register operand"); + assert((MCID.getNumDefs() == 1) && + MCID.hasImplicitDefOfPhysReg(X86::EFLAGS) && + "Unexpected defines in a xor instruction"); + dstReg = DestOp.getReg(); + // Generate an or instruction to set the zero flag if the + // operands are the same. An instruction such as 'xor $ecx, ecx' is + // generated to set the register value to 0. + if ((mi.findTiedOperandIdx(1) == 0) && (dstReg == Use2Op.getReg())) { + // No instruction to generate. Just set destReg value to 0. + Type *DestTy = getPhysRegOperandType(mi, 0); + Value *Val = ConstantInt::get(DestTy, 0, false /* isSigned */); + dstValue = Val; + } else { + assert((Uses.at(0) != nullptr) && (Uses.at(1) != nullptr) && + "Unhandled situation: register used before initialization in xor"); + dstValue = BinaryOperator::CreateXor(Uses.at(0), Uses.at(1)); + } + } break; + case X86::TEST32rr: + case X86::TEST64rr: + assert((MCID.getNumDefs() == 0) && + MCID.hasImplicitDefOfPhysReg(X86::EFLAGS) && + "Unexpected defines in a test instruction"); + assert((Uses.at(0) != nullptr) && (Uses.at(1) != nullptr) && + "Unhandled situation: register is used before initialization in " + "test"); + dstReg = X86::EFLAGS; + dstValue = BinaryOperator::CreateAnd(Uses.at(0), Uses.at(1)); + break; + default: + assert(false && "Unhandled binary instruction"); + } + assert(dstValue != nullptr && (dstReg != X86::NoRegister) && + "Raising of instruction unimplemented"); + if (isa(dstValue)) { + curBlock->getInstList().push_back(dyn_cast(dstValue)); + } + updatePhysRegSSAValue(dstReg, dstValue); + return true; +} + +bool X86MachineInstructionRaiser::raiseBinaryOpMemToRegInstr( + const MachineInstr &mi, BasicBlock *curBlock, Value *memRefValue) { + unsigned int opcode = mi.getOpcode(); + const MCInstrDesc &MIDesc = mi.getDesc(); + + assert((MIDesc.getNumDefs() == 1) && + "Encountered memory load instruction with more than 1 defs"); + unsigned int DestIndex = 0; + const MachineOperand &DestOp = mi.getOperand(DestIndex); + assert(DestOp.isReg() && + "Expect destination register operand in binary reg/mem instruction"); + unsigned int DestPReg = DestOp.getReg(); + unsigned int memAlignment = getInstructionMemOpSize(opcode); + Type *DestopTy = getPhysRegOperandType(mi, DestIndex); + Value *DestValue = getRegValue(DestPReg); + assert(DestValue != nullptr && + "Encountered instruction with undefined register"); + + // Verify sanity of the instruction. + assert((DestValue->getType()->getPrimitiveSizeInBits() / sizeof(uint64_t)) == + memAlignment && + "Mismatched value type size and instruction size of binary op " + "instruction"); + // Load the value from memory location of memRefValue. + // memRefVal is either an AllocaInst (stack access) or GlobalValue (global + // data access) or an LoadInst that loads an address in memory.. + assert((isa(memRefValue) || isa(memRefValue) || + isa(memRefValue)) && + "Unexpected type of memory reference in binary mem op instruction"); + bool isMemRefGlobalVal = false; + // If it is a load instruction, convert it to a pointer. + if (isa(memRefValue)) { + LoadInst *ldInst = dyn_cast(memRefValue); + if (isa(ldInst->getPointerOperand())) { + isMemRefGlobalVal = true; + } else { + // Cast it to a pointer of type of destination operand. + PointerType *PtrTy = PointerType::get(DestopTy, 0); + IntToPtrInst *convIntToPtr = new IntToPtrInst(memRefValue, PtrTy); + curBlock->getInstList().push_back(convIntToPtr); + memRefValue = convIntToPtr; + } + } + LoadInst *loadInst = nullptr; + if (isMemRefGlobalVal) { + // Load the global value. + loadInst = + new LoadInst(dyn_cast(memRefValue)->getPointerOperand()); + } else { + loadInst = new LoadInst(memRefValue); + } + // Insert the instruction that loads memory reference + loadInst->setAlignment(memAlignment); + curBlock->getInstList().push_back(loadInst); + Instruction *BinOpInst = nullptr; + + switch (opcode) { + case X86::ADD64rm: + case X86::ADD32rm: + case X86::ADD16rm: + case X86::ADD8rm: { + // Create add instruction + BinOpInst = BinaryOperator::CreateAdd(DestValue, loadInst); + } break; + case X86::OR32rm: { + // Create add instruction + BinOpInst = BinaryOperator::CreateOr(DestValue, loadInst); + } break; + case X86::IMUL32rm: + case X86::IMUL32rmi8: { + // Create mul instruction + BinOpInst = BinaryOperator::CreateMul(DestValue, loadInst); + } break; + default: + assert(false && "Unhandled binary op mem to reg instruction "); + } + // Add instruction to block + curBlock->getInstList().push_back(BinOpInst); + + // Update PhysReg to Value map + updatePhysRegSSAValue(DestPReg, BinOpInst); + return true; +} + +bool X86MachineInstructionRaiser::raiseLoadIntToFloatRegInstr( + const MachineInstr &mi, BasicBlock *curBlock, Value *memRefValue) { + + const unsigned int opcode = mi.getOpcode(); + const MCInstrDesc &MIDesc = mi.getDesc(); + // Get index of memory reference in the instruction. + int memoryRefOpIndex = getMemoryRefOpIndex(mi); + assert(memoryRefOpIndex == 0 && + "Expect memory operand of floating-point load instruction at index 0"); + assert(MIDesc.getNumDefs() == 0 && + "Expect no defs in floating-point load instruction"); + X86AddressMode memRef = llvm::getAddressFromInstr(&mi, memoryRefOpIndex); + uint64_t BaseSupReg = find64BitSuperReg(memRef.Base.Reg); + bool isPCRelMemRef = (BaseSupReg == X86::RIP); + + // Load the value from memory location of memRefValue. + // memRefVal is either an AllocaInst (stack access) or GlobalValue (global + // data access) or an effective address value. + assert((isa(memRefValue) || isEffectiveAddrValue(memRefValue) || + isa(memRefValue)) && + "Unexpected type of memory reference in FPU load op instruction"); + + LLVMContext &llvmContext(MF.getFunction().getContext()); + if (isPCRelMemRef) { + // If it is a PC-relative mem ref, memRefValue is a + // global value loaded from PC-relative memory location. If it is a + // derived type value, get its element pointer. + Type *memRefValueTy = memRefValue->getType(); + if (!memRefValueTy->isFloatingPointTy()) { + assert(memRefValueTy->isPointerTy() && + "Unhandled non-pointer type found while attempting to push value " + "to FPU register stack."); + Type *memRefValPtrElementTy = memRefValueTy->getPointerElementType(); + switch (memRefValPtrElementTy->getTypeID()) { + case Type::ArrayTyID: { + assert(memRefValPtrElementTy->getArrayNumElements() == 1 && + "Unexpected number of array elements in value being cast to " + "float"); + // Make sure the array element type is integer or floating point type. + Type *arrElemTy = memRefValPtrElementTy->getArrayElementType(); + assert((arrElemTy->isIntegerTy() || arrElemTy->isFloatingPointTy()) && + "Unexpected type of data referenced in FPU register stack " + "load instruction"); + // Get the element + Value *IndexOne = ConstantInt::get(llvmContext, APInt(32, 1)); + Instruction *GetElem = GetElementPtrInst::CreateInBounds( + memRefValPtrElementTy, memRefValue, {IndexOne, IndexOne}, "", + curBlock); + memRefValue = GetElem; + } break; + // Primitive types that need not be reached into. + case Type::IntegerTyID: + break; + default: { + assert(false && "Encountered value with type whose cast to float is " + "not yet handled"); + } break; + } + } + } + // If it is an effective address value, convert it to a pointer to + // the type of load reg. + if (isEffectiveAddrValue(memRefValue)) { + assert(false && + "*** Unhandled situation. Need to implement support correctly"); + Type *PtrTy = memRefValue->getType(); + IntToPtrInst *convIntToPtr = new IntToPtrInst(memRefValue, PtrTy); + curBlock->getInstList().push_back(convIntToPtr); + memRefValue = convIntToPtr; + } + assert(memRefValue->getType()->isPointerTy() && + "Pointer type expected in load instruction"); + // Load the value from memory location + LoadInst *loadInst = new LoadInst(memRefValue); + unsigned int memAlignment = memRefValue->getType() + ->getPointerElementType() + ->getPrimitiveSizeInBits() / + 8; + loadInst->setAlignment(memAlignment); + curBlock->getInstList().push_back(loadInst); + + switch (opcode) { + default: { + assert(false && "Unhandled load floating-point register instruction"); + } break; + case X86::ILD_F32m: + case X86::ILD_F64m: { + Type *floatTy = Type::getFloatTy(llvmContext); + assert(loadInst->getType()->isIntegerTy() && + "Unexpected non-integter type of source in fild instruction"); + // Cast source to float + Instruction *CInst = + CastInst::Create(CastInst::getCastOpcode(loadInst, true, floatTy, true), + loadInst, floatTy); + curBlock->getInstList().push_back(CInst); + // Push value to top of FPU register stack + FPURegisterStackPush(CInst); + } break; + case X86::LD_F32m: { + Type *floatTy = Type::getFloatTy(llvmContext); + // Cast source to float + Instruction *CInst = + CastInst::Create(CastInst::getCastOpcode(loadInst, true, floatTy, true), + loadInst, floatTy); + curBlock->getInstList().push_back(CInst); + // Push value to top of FPU register stack + FPURegisterStackPush(CInst); + } + } + return true; +} + +bool X86MachineInstructionRaiser::raiseStoreIntToFloatRegInstr( + const MachineInstr &mi, BasicBlock *curBlock, Value *memRefValue) { + + const unsigned int opcode = mi.getOpcode(); + const MCInstrDesc &MIDesc = mi.getDesc(); + // Get index of memory reference in the instruction. + int memoryRefOpIndex = getMemoryRefOpIndex(mi); + assert(memoryRefOpIndex == 0 && + "Expect memory operand of floating-point load instruction at index 0"); + assert(MIDesc.getNumDefs() == 0 && + "Expect no defs in floating-point load instruction"); + X86AddressMode memRef = llvm::getAddressFromInstr(&mi, memoryRefOpIndex); + uint64_t BaseSupReg = find64BitSuperReg(memRef.Base.Reg); + bool isPCRelMemRef = (BaseSupReg == X86::RIP); + + // Load the value from memory location of memRefValue. + // memRefVal is either an AllocaInst (stack access) or GlobalValue (global + // data access) or an effective address value. + assert((isa(memRefValue) || isEffectiveAddrValue(memRefValue) || + isa(memRefValue)) && + "Unexpected type of memory reference in FPU store op instruction"); + + LLVMContext &llvmContext(MF.getFunction().getContext()); + if (isPCRelMemRef) { + // If it is a PC-relative mem ref, memRefValue is a global value loaded + // from PC-relative memory location. If it is a derived type value, get + // its element pointer. + Type *memRefValueTy = memRefValue->getType(); + if (!memRefValueTy->isFloatingPointTy()) { + assert(memRefValueTy->isPointerTy() && + "Unhandled non-pointer type found while attempting to load value " + "from FPU register stack."); + Type *memRefValPtrElementTy = memRefValueTy->getPointerElementType(); + switch (memRefValPtrElementTy->getTypeID()) { + case Type::ArrayTyID: { + assert(memRefValPtrElementTy->getArrayNumElements() == 1 && + "Unexpected number of array elements in value being cast to " + "float"); + // Make sure the array element type is integer or floating point type. + Type *arrElemTy = memRefValPtrElementTy->getArrayElementType(); + assert((arrElemTy->isIntegerTy() || arrElemTy->isFloatingPointTy()) && + "Unexpected type of data referenced in FPU register stack " + "store instruction"); + // Get the element + Value *IndexOne = ConstantInt::get(llvmContext, APInt(32, 1)); + Instruction *GetElem = GetElementPtrInst::CreateInBounds( + memRefValPtrElementTy, memRefValue, {IndexOne, IndexOne}, "", + curBlock); + memRefValue = GetElem; + } break; + // Primitive types that need not be reached into. + case Type::IntegerTyID: + break; + default: { + assert(false && "Encountered value with type whose cast to float is " + "not yet handled"); + } break; + } + } + } + // If it is an effective address value, convert it to a pointer to + // the type of load reg. + if (isEffectiveAddrValue(memRefValue)) { + assert(false && + "*** Unhandled situation. Need to implement support correctly"); + Type *PtrTy = memRefValue->getType(); + IntToPtrInst *convIntToPtr = new IntToPtrInst(memRefValue, PtrTy); + curBlock->getInstList().push_back(convIntToPtr); + memRefValue = convIntToPtr; + } + assert(memRefValue->getType()->isPointerTy() && + "Pointer type expected in store instruction"); + + switch (opcode) { + default: { + assert(false && "Unhandled store floating-point register instruction"); + } break; + case X86::ST_FP32m: + case X86::ST_FP64m: { + Value *ST0Val = FPURegisterStackTop(); + Type *SrcTy = ST0Val->getType(); + // The value in ST0 is converted to single-precision or double precision + // floating-point format. So, cast the memRefValue to the PointerType of + // SrcTy. + Type *DestElemTy = memRefValue->getType()->getPointerElementType(); + if (DestElemTy != SrcTy) { + PointerType *SrcPtrTy = SrcTy->getPointerTo(0); + Instruction *CInst = CastInst::Create( + CastInst::getCastOpcode(memRefValue, true, SrcPtrTy, true), + memRefValue, SrcPtrTy); + curBlock->getInstList().push_back(CInst); + memRefValue = CInst; + } + // Create the store + StoreInst *StInst = new StoreInst(ST0Val, memRefValue); + curBlock->getInstList().push_back(StInst); + + // Pop value to top of FPU register stack + FPURegisterStackPop(); + } + } + return true; +} + +bool X86MachineInstructionRaiser::raiseMoveFromMemInstr(const MachineInstr &mi, + BasicBlock *curBlock, + Value *memRefValue) { + const unsigned int opcode = mi.getOpcode(); + const MCInstrDesc &MIDesc = mi.getDesc(); + unsigned LoadOpIndex = 0; + // Get index of memory reference in the instruction. + int memoryRefOpIndex = getMemoryRefOpIndex(mi); + assert(memoryRefOpIndex == 1 && + "Expect memory operand of a mem move instruction at index 1"); + assert(MIDesc.getNumDefs() == 1 && mi.getOperand(LoadOpIndex).isReg() && + "Expect store operand register target"); + X86AddressMode memRef = llvm::getAddressFromInstr(&mi, memoryRefOpIndex); + uint64_t BaseSupReg = find64BitSuperReg(memRef.Base.Reg); + bool isPCRelMemRef = (BaseSupReg == X86::RIP); + const MachineOperand &LoadOp = mi.getOperand(LoadOpIndex); + unsigned int LoadPReg = LoadOp.getReg(); + assert(TargetRegisterInfo::isPhysicalRegister(LoadPReg) && + "Expect destination to be a physical register in move from mem " + "instruction"); + + // Load the value from memory location of memRefValue. + // memRefVal is either an AllocaInst (stack access) or GlobalValue (global + // data access) or an effective address value. + assert((isa(memRefValue) || isEffectiveAddrValue(memRefValue) || + isa(memRefValue)) && + "Unexpected type of memory reference in binary mem op instruction"); + + if (isPCRelMemRef) { + // memRefValue already represents the global value loaded from PC-relative + // memory location. It is incorrect to generate an additional load of this + // value. It should be directly used. + updatePhysRegSSAValue(LoadPReg, memRefValue); + } else { + // If it is an effective address value, convert it to a pointer to the + // type of load reg. + if (isEffectiveAddrValue(memRefValue)) { + PointerType *PtrTy = + PointerType::get(getPhysRegOperandType(mi, LoadOpIndex), 0); + IntToPtrInst *convIntToPtr = new IntToPtrInst(memRefValue, PtrTy); + curBlock->getInstList().push_back(convIntToPtr); + memRefValue = convIntToPtr; + } + assert(memRefValue->getType()->isPointerTy() && + "Pointer type expected in load instruction"); + // Load the value from memory location + LoadInst *loadInst = new LoadInst(memRefValue); + unsigned int memAlignment = memRefValue->getType() + ->getPointerElementType() + ->getPrimitiveSizeInBits() / + 8; + loadInst->setAlignment(memAlignment); + curBlock->getInstList().push_back(loadInst); + + LLVMContext &llvmContext(MF.getFunction().getContext()); + Type *memTy = nullptr; + Type *extTy = nullptr; + switch (opcode) { + default: { + updatePhysRegSSAValue(LoadPReg, loadInst); + } break; + case X86::MOVSX64rm32: { + extTy = Type::getInt64Ty(llvmContext); + memTy = Type::getInt32Ty(llvmContext); + } break; + case X86::MOVZX64rm16: { + case X86::MOVSX64rm16: + extTy = Type::getInt64Ty(llvmContext); + memTy = Type::getInt16Ty(llvmContext); + } break; + case X86::MOVZX64rm8: + case X86::MOVSX64rm8: { + extTy = Type::getInt64Ty(llvmContext); + memTy = Type::getInt8Ty(llvmContext); + } break; + + case X86::MOVZX32rm8: + case X86::MOVZX32rm8_NOREX: + case X86::MOVSX32rm8: { + extTy = Type::getInt32Ty(llvmContext); + memTy = Type::getInt8Ty(llvmContext); + } break; + case X86::MOVZX32rm16: + case X86::MOVSX32rm16: { + extTy = Type::getInt32Ty(llvmContext); + memTy = Type::getInt16Ty(llvmContext); + } break; + + case X86::MOVZX16rm8: + case X86::MOVSX16rm8: { + extTy = Type::getInt16Ty(llvmContext); + memTy = Type::getInt8Ty(llvmContext); + } break; + case X86::MOVZX16rm16: + case X86::MOVSX16rm16: { + extTy = Type::getInt16Ty(llvmContext); + memTy = Type::getInt16Ty(llvmContext); + } break; + } + // Decide based on opcode value and not opcode name?? + bool isSextInst = + x86InstrInfo->getName(MIDesc.getOpcode()).startswith("MOVSX"); + bool isZextInst = + x86InstrInfo->getName(MIDesc.getOpcode()).startswith("MOVZX"); + + if (isSextInst || isZextInst) { + assert(((extTy != nullptr) && (memTy != nullptr)) && + "Unhandled move from memory instruction"); + + // Load value of type memTy + Instruction *CInst = loadInst; + if (loadInst->getType() != memTy) { + CInst = CastInst::Create( + CastInst::getCastOpcode(loadInst, false, memTy, false), loadInst, + memTy); + curBlock->getInstList().push_back(CInst); + } + Instruction *extInst; + + // Now extend the value accordingly + if (isSextInst) { + // Sign extend + extInst = new SExtInst(CInst, extTy); + } else { + // Zero extend + extInst = new ZExtInst(CInst, extTy); + } + curBlock->getInstList().push_back(extInst); + // Update PhysReg to Value map + updatePhysRegSSAValue(LoadPReg, extInst); + } else { + // This is a normal mov instruction + // Update PhysReg to Value map + updatePhysRegSSAValue(LoadPReg, loadInst); + } + } + + return true; +} + +bool X86MachineInstructionRaiser::raiseMoveToMemInstr(const MachineInstr &mi, + BasicBlock *curBlock, + Value *memRefVal) { + unsigned int SrcOpIndex = getMemoryRefOpIndex(mi) + X86::AddrNumOperands; + + const MachineOperand &SrcOp = mi.getOperand(SrcOpIndex); + + assert((SrcOp.isImm() || SrcOp.isReg()) && + "Register or immediate value source expected in a move to mem " + "instruction"); + + unsigned int memAlignment = getInstructionMemOpSize(mi.getOpcode()); + Value *SrcValue = nullptr; + Type *SrcOpTy = nullptr; + + // If Source op is immediate, create a constant int value + // of type memory location. + if (SrcOp.isImm()) { + SrcOpTy = getImmOperandType(mi, SrcOpIndex); + SrcValue = ConstantInt::get(SrcOpTy, SrcOp.getImm()); + } else { + // If it is not an immediate value, get source value + unsigned int PReg = SrcOp.getReg(); + assert( + TargetRegisterInfo::isPhysicalRegister(PReg) && + "Expect source to be a physical register in move to mem instruction"); + SrcValue = getRegValue(PReg); + SrcOpTy = getPhysRegOperandType(mi, SrcOpIndex); + } + assert(SrcValue != nullptr && + "Unable to get source value while raising move to mem instruction"); + // Load the value from memory location of memRefValue. + // memRefVal is either an AllocaInst (stack access) or GlobalValue (global + // data access) or an effective address value. + assert((isa(memRefVal) || isEffectiveAddrValue(memRefVal) || + isa(memRefVal)) && + "Unexpected type of memory reference in mem-to-reg instruction"); + if (isEffectiveAddrValue(memRefVal)) { + // If it is a load of global value use the global value + // directly, else convert it to a pointer. + if (isa(memRefVal)) { + LoadInst *ldInst = dyn_cast(memRefVal); + // If it is a load of global variable, use it directly. + if (isa(ldInst->getPointerOperand())) { + memRefVal = dyn_cast(ldInst->getPointerOperand()); + } + } + } + + // If memory reference is not a pointer type, cast it to a pointer + Type *DstMemTy = memRefVal->getType(); + if (!DstMemTy->isPointerTy()) { + // Cast it as pointer to SrcOpTy + PointerType *PtrTy = PointerType::get(SrcOpTy, 0); + IntToPtrInst *convIntToPtr = new IntToPtrInst(memRefVal, PtrTy); + curBlock->getInstList().push_back(convIntToPtr); + memRefVal = convIntToPtr; + } + + // This instruction moves a source value to memory. So, if the types of the + // source value and that of the memory pointer content are not the same, it + // is the source value that needs to be cast to match the type of + // destination (i.e., memory). It needs to be sign extended as needed. + Type *MatchTy = memRefVal->getType()->getPointerElementType(); + if (SrcValue->getType() != MatchTy) { + Type *CastTy = MatchTy; + CastInst *CInst = CastInst::Create( + CastInst::getCastOpcode(SrcValue, false, CastTy, false), SrcValue, + CastTy); + curBlock->getInstList().push_back(CInst); + SrcValue = CInst; + } + + StoreInst *storeInst = new StoreInst(SrcValue, memRefVal); + + storeInst->setAlignment(memAlignment); + curBlock->getInstList().push_back(storeInst); + return true; +} + +// Raise idiv instruction. +// TODO: Need to add support for div. +bool X86MachineInstructionRaiser::raiseDivideInstr(const MachineInstr &mi, + BasicBlock *curBlock, + Value *memRefValue) { + const MCInstrDesc &MIDesc = mi.getDesc(); + unsigned int opcode = mi.getOpcode(); + LLVMContext &llvmContext(MF.getFunction().getContext()); + + // idiv uses AX(AH:AL or DX:AX or EDX:EAX or RDX:RAX pairs as dividend and + // stores the result in the same pair. Additionally, EFLAGS is an implicit + // def. + assert(MIDesc.getNumImplicitUses() == 2 && MIDesc.getNumImplicitDefs() == 3 && + MIDesc.hasImplicitDefOfPhysReg(X86::EFLAGS) && + "Unexpected number of implicit uses and defs in div instruction"); + MCPhysReg UseDefReg_0 = MIDesc.ImplicitUses[0]; + MCPhysReg UseDefReg_1 = MIDesc.ImplicitUses[1]; + assert((UseDefReg_0 == MIDesc.ImplicitDefs[0]) && + (UseDefReg_1 == MIDesc.ImplicitDefs[1]) && + "Unexpected use/def registers in div instruction"); + + Value *DividendLowBytes = getRegValue(UseDefReg_0); + Value *DividendHighBytes = getRegValue(UseDefReg_1); + assert((DividendLowBytes != nullptr) && (DividendHighBytes != nullptr) && + "Unexpected use before definition in div instruction"); + // Divisor is memRefValue. + // Create a Value representing the dividend. + // TODO: Not sure how the implicit use registers of IDIV8m are encode. Does + // the instruction have AX as a single use/def register or does it have 2 + // use/def registers, viz., AH:AL pair similar to the other IDIV + // instructions? Handle it when it is encountered. + assert((opcode != X86::IDIV8m) && "*** Need to handle IDIV8m"); + assert((DividendLowBytes->getType() == DividendHighBytes->getType()) && + "Unexpected types of dividend registers in idiv instruction"); + unsigned int UseDefRegSize = + DividendLowBytes->getType()->getScalarSizeInBits(); + // Generate the following code + // %h = lshl DividendHighBytes, UseDefRegSize + // %f = or %h, DividendLowBytes + // %quo = idiv %f, memRefValue + // %rem = irem %f, memRefValue + // UseDef_0 = %quo + // UseDef_1 = %rem + + // Logical Shift left DividendHighBytes by n-bits (where n is the size of + // UseDefRegSize) to get the high bytes and set DefReg_1 to the resulting + // value. + // DoubleTy type is of type twice the use reg size + Type *DoubleTy = Type::getIntNTy(llvmContext, UseDefRegSize * 2); + Value *ShiftAmountVal = + ConstantInt::get(DoubleTy, UseDefRegSize, false /* isSigned */); + // Cast DividendHighBytes and DividendLowBytes to types with double the + // size. + CastInst *DividendLowBytesDT = CastInst::Create( + CastInst::getCastOpcode(DividendLowBytes, true, DoubleTy, true), + DividendLowBytes, DoubleTy); + curBlock->getInstList().push_back(DividendLowBytesDT); + + CastInst *DividendHighBytesDT = CastInst::Create( + CastInst::getCastOpcode(DividendHighBytes, true, DoubleTy, true), + DividendHighBytes, DoubleTy); + curBlock->getInstList().push_back(DividendHighBytesDT); + + Instruction *LShlInst = + BinaryOperator::CreateNUWShl(DividendHighBytesDT, ShiftAmountVal); + curBlock->getInstList().push_back(LShlInst); + + // Combine the dividend values to get full dividend. + // or instruction + Instruction *FullDividend = + BinaryOperator::CreateOr(LShlInst, DividendLowBytesDT); + curBlock->getInstList().push_back(FullDividend); + + // Cast divisor (memRefValue) to double type + CastInst *memRefValueDT = CastInst::Create( + CastInst::getCastOpcode(memRefValue, true, DoubleTy, true), memRefValue, + DoubleTy); + curBlock->getInstList().push_back(memRefValueDT); + + // quotient + Instruction *QuotientDT = + BinaryOperator::CreateSDiv(FullDividend, memRefValueDT); + curBlock->getInstList().push_back(QuotientDT); + + // Cast Quotient back to UseDef reg value type + CastInst *Quotient = + CastInst::Create(CastInst::getCastOpcode( + QuotientDT, true, DividendLowBytes->getType(), true), + QuotientDT, DividendLowBytes->getType()); + + curBlock->getInstList().push_back(Quotient); + // Update ssa val of UseDefReg_0 + updatePhysRegSSAValue(UseDefReg_0, Quotient); + + // remainder + Instruction *RemainderDT = + BinaryOperator::CreateSRem(FullDividend, memRefValueDT); + curBlock->getInstList().push_back(RemainderDT); + + // Cast RemainderDT back to UseDef reg value type + CastInst *Remainder = CastInst::Create( + CastInst::getCastOpcode(RemainderDT, true, DividendHighBytes->getType(), + true), + RemainderDT, DividendHighBytes->getType()); + + curBlock->getInstList().push_back(Remainder); + // Update ssa val of UseDefReg_1 + updatePhysRegSSAValue(UseDefReg_1, Remainder); + + return true; +} +// Raise compare instruction. If the the instruction is a memory compare, it +// is expected that this function is called from raiseMemRefMachineInstr after +// verifying the accessibility of memory location and with isMemCompare set +// true.If isMemCompare is true, memRefValue needs to be the non-null memory +// reference value representing the memory reference the instruction uses. + +bool X86MachineInstructionRaiser::raiseCompareMachineInstr( + const MachineInstr &mi, BasicBlock *curBlock, bool isMemCompare, + Value *memRefValue) { + // Get index of memory reference in the instruction. + int memoryRefOpIndex = getMemoryRefOpIndex(mi); + assert((((memoryRefOpIndex != -1) && isMemCompare) || + ((memoryRefOpIndex == -1) && !isMemCompare)) && + "Inconsistent memory reference operand information specified for " + "compare instruction"); + MCInstrDesc MCIDesc = mi.getDesc(); + // Is this a cmp instruction? + bool isCMPInst = x86InstrInfo->getName(MCIDesc.getOpcode()).startswith("CMP"); + + SmallVector OpValues = {nullptr, nullptr}; + + // Get operand indices + if (isMemCompare) { + // This is a memory referencing instruction. + Type *NonMemRefOpTy; + const MachineOperand *NonMemRefOp; + assert(memoryRefOpIndex >= 0 && + "Unexpected memory operand index in compare instruction"); + unsigned nonMemRefOpIndex = + (memoryRefOpIndex == 0) ? X86::AddrNumOperands : 0; + NonMemRefOp = &(mi.getOperand(nonMemRefOpIndex)); + if (NonMemRefOp->isReg()) { + NonMemRefOpTy = getPhysRegOperandType(mi, nonMemRefOpIndex); + } else if (NonMemRefOp->isImm()) { + NonMemRefOpTy = getImmOperandType(mi, nonMemRefOpIndex); + } else { + mi.dump(); + assert(false && "Unhandled second operand type in compare instruction"); + } + + assert(memRefValue != nullptr && "Null memory reference value encountered " + "while raising compare instruction"); + // Convert it to a pointer of type of non-memory operand + if (isEffectiveAddrValue(memRefValue)) { + PointerType *PtrTy = PointerType::get(NonMemRefOpTy, 0); + IntToPtrInst *convIntToPtr = new IntToPtrInst(memRefValue, PtrTy); + curBlock->getInstList().push_back(convIntToPtr); + memRefValue = convIntToPtr; + } + // Load the value from memory location + LoadInst *loadInst = new LoadInst(memRefValue); + loadInst->setAlignment( + memRefValue->getPointerAlignment(MR->getModule().getDataLayout())); + curBlock->getInstList().push_back(loadInst); + // save it at the appropriate index of operand value array + if (memoryRefOpIndex == 0) { + OpValues[0] = loadInst; + } else { + OpValues[1] = loadInst; + } + + // Get value for non-memory operand of compare. + Value *NonMemRefVal = nullptr; + if (NonMemRefOp->isReg()) { + NonMemRefVal = getRegValue(NonMemRefOp->getReg()); + } else if (NonMemRefOp->isImm()) { + NonMemRefVal = + ConstantInt::get(memRefValue->getType()->getPointerElementType(), + NonMemRefOp->getImm()); + } else { + mi.dump(); + assert(false && "Unhandled first operand type in compare instruction"); + } + // save non-memory reference value at the appropriate index of operand + // value array + if (memoryRefOpIndex == 0) { + OpValues[1] = NonMemRefVal; + } else { + OpValues[0] = NonMemRefVal; + } + } else { + // The instruction operands do not reference memory + unsigned Op1Index = MCIDesc.getNumDefs() == 0 ? 0 : 1; + + MachineOperand CmpOp1 = mi.getOperand(Op1Index); + MachineOperand CmpOp2 = mi.getOperand(Op1Index + 1); + + assert((CmpOp1.isReg() || CmpOp1.isImm()) && + "Unhandled first operand type in compare instruction"); + + assert((CmpOp2.isReg() || CmpOp2.isImm()) && + "Unhandled second operand type in compare instruction"); + + if (CmpOp1.isReg()) { + OpValues[0] = getRegValue(CmpOp1.getReg()); + } + + if (CmpOp2.isReg()) { + OpValues[1] = getRegValue(CmpOp2.getReg()); + } + + // Construct value if either of the operands is an immediate + if (CmpOp1.isImm()) { + assert((OpValues[1] != nullptr) && + "At least one value expected while raising compare instruction"); + OpValues[0] = ConstantInt::get(OpValues[1]->getType(), CmpOp1.getImm()); + } + + if (CmpOp2.isImm()) { + assert((OpValues[0] != nullptr) && + "At least one value expected while raising compare instruction"); + OpValues[1] = ConstantInt::get(OpValues[0]->getType(), CmpOp2.getImm()); + } + } + assert(OpValues[0] != nullptr && OpValues[1] != nullptr && + "Unable to materialize compare operand values"); + + Instruction *CmpInst = nullptr; + // Sub instruction is marked as a compare instruction (MCID::Compare) + switch (mi.getOpcode()) { + case X86::SUB8mi: + case X86::SUB8mr: + case X86::SUB8rm: + case X86::SUB16mi: + case X86::SUB16mr: + case X86::SUB16rm: + case X86::SUB32mi: + case X86::SUB32mr: + case X86::SUB32rm: + case X86::SUB64mi8: + case X86::SUB64mi32: + case X86::SUB64mr: + case X86::SUB64rm: + case X86::SUB32rr: { + assert(MCIDesc.getNumDefs() == 1 && + "Unexpected number of def operands of sub memref instruction"); + const MachineOperand &MO = mi.getOperand(0); + assert(mi.getOperand(0).isReg() && "Unexpected non-register def operand"); + // Make sure the source operand value types are the same as destination + // register type. + Type *DestTy = getPhysRegOperandType(mi, 0); + for (int i = 0; i < 2; i++) { + if (OpValues[i]->getType() != DestTy) { + CastInst *CInst = CastInst::Create( + CastInst::getCastOpcode(OpValues[i], false, DestTy, false), + OpValues[i], DestTy); + curBlock->getInstList().push_back(CInst); + OpValues[i] = CInst; + } + } + + CmpInst = BinaryOperator::CreateSub(OpValues[0], OpValues[1]); + updatePhysRegSSAValue(MO.getReg(), CmpInst); + } break; + default: { + assert(isCMPInst && + "Expect compare instruction. Possibly an unhandled compare " + "instruction?"); + if (OpValues[0]->getType()->isIntegerTy() && + OpValues[1]->getType()->isIntegerTy()) { + // The predicate value used ICMP_EQ is temporary. This will be fixed + // based on the condition of the branch using the effects of this + // comparison. + CmpInst = + new ICmpInst(CmpInst::Predicate::ICMP_EQ, OpValues[0], OpValues[1]); + } else if (OpValues[0]->getType()->isFloatTy() && + OpValues[1]->getType()->isFloatTy()) { + // The predicate value used FCMP_OEQ is temporary. This will be fixed + // based on the condition of the branch using the effects of this + // comparison. + CmpInst = + new FCmpInst(CmpInst::Predicate::FCMP_OEQ, OpValues[0], OpValues[1]); + } else { + assert(false && "Incompatible types of comparison operands found"); + } + assert(MCIDesc.getNumImplicitDefs() == 1 && + "Compare instruction does not have exactly one implicit def"); + MCPhysReg ImpDefReg = MCIDesc.ImplicitDefs[0]; + assert(ImpDefReg == X86::EFLAGS && + "Expected implicit EFLAGS def in compare instruction"); + updatePhysRegSSAValue(ImpDefReg, CmpInst); + } + } + // Add the compare instruction + curBlock->getInstList().push_back(CmpInst); + return true; +} + +// Raise a load/store instruction. +// Current implementation only raises instructions that load and store to +// stack. +bool X86MachineInstructionRaiser::raiseMemRefMachineInstr( + const MachineInstr &mi, BasicBlock *curBlock) { + + // Handle the push instruction that is marked as a memory store instruction + if (isPushToStack(mi)) { + return raisePushInstruction(mi); + } + + if (isPopFromStack(mi)) { + return raisePopInstruction(mi); + } + + const MCInstrDesc &MIDesc = mi.getDesc(); + unsigned int opcode = mi.getOpcode(); + + int loadOrStoreOpIndex = -1; + + // Get index of memory reference in the instruction. + int memoryRefOpIndex = getMemoryRefOpIndex(mi); + // Should have found the index of the memory reference operand + assert(memoryRefOpIndex != -1 && + "Unable to find memory reference operand of a load/store instruction"); + X86AddressMode memRef = llvm::getAddressFromInstr(&mi, memoryRefOpIndex); + + // Get the operand whose value is stored to memory or that is loaded from + // memory. + + if (MIDesc.mayStore()) { + // If the instruction stores to stack, find the register whose value is + // being stored. It would be the operand at offset memRefOperandStartIndex + // + X86::AddrNumOperands + loadOrStoreOpIndex = memoryRefOpIndex + X86::AddrNumOperands; + } else if (MIDesc.mayLoad()) { + // If the instruction loads to memory to a register, it has 1 def. + // Operand 0 is the loadOrStoreOp. + assert(((MIDesc.getNumDefs() == 0) || (MIDesc.getNumDefs() == 1)) && + "Instruction that loads from memory expected to have only " + "one target"); + if (MIDesc.getNumDefs() == 1) { + loadOrStoreOpIndex = 0; + assert(mi.getOperand(loadOrStoreOpIndex).isReg() && + "Target of instruction that loads from " + "memory expected to be a register"); + } else if (!MIDesc.isCompare()) { + switch (getInstructionKind(opcode)) { + case InstructionKind::DIVIDE_OP: + case InstructionKind::LOAD_FPU_REG: + break; + default: + mi.print(errs()); + assert(false && "Encountered unhandled memory load instruction"); + } + } + } else { + mi.print(errs()); + assert(false && "Encountered unhandled instruction that is not load/store"); + } + + Value *memoryRefValue = nullptr; + + if (memRef.BaseType == X86AddressMode::RegBase) { + // If it is a stack reference, allocate a stack slot in case the current + // memory reference is new. Else get the stack reference using the + // stackslot index of the previously known stack ref. + + uint64_t BaseSupReg = find64BitSuperReg(memRef.Base.Reg); + if (BaseSupReg == x86RegisterInfo->getStackRegister() || + BaseSupReg == x86RegisterInfo->getFramePtr()) { + memoryRefValue = getStackAllocatedValue(mi, curBlock, loadOrStoreOpIndex); + } + // Handle PC-relative addressing. + + // NOTE: This tool now raises only shared libraries and executables - NOT + // object files. So, instructions with 0 register (which typically are + // seen in a relocatable object file for the linker to patch) are not + // expected to be encountered. + else if (BaseSupReg == X86::RIP) { + memoryRefValue = createPCRelativeAccesssValue(mi, curBlock); + } else { + // Get load/store operand + Value *memrefValue = getMemoryAddressExprValue(mi, curBlock); + memoryRefValue = memrefValue; + } + } else { + // TODO : Memory references with BaseType FrameIndexBase + // (i.e., not RegBase type) + outs() << "****** Unhandled memory reference in instruction\n\t"; + mi.dump(); + outs() << "****** reference of type FrameIndexBase"; + return false; + } + + assert(memoryRefValue != nullptr && + "Unable to construct memory referencing value"); + + // Raise a memory compare instruction + if (mi.isCompare()) { + return raiseCompareMachineInstr(mi, curBlock, true /* isMemRef */, + memoryRefValue); + } + + // Now that we have all necessary information about memory reference and the + // load/store operand, we can raise the memory referencing instruction + // according to the opcode. + bool success = false; + switch (getInstructionKind(opcode)) { + // Move register or immediate to memory + case InstructionKind::MOV_TO_MEM: { + success = raiseMoveToMemInstr(mi, curBlock, memoryRefValue); + } break; + // Move register from memory + case InstructionKind::MOV_FROM_MEM: { + success = raiseMoveFromMemInstr(mi, curBlock, memoryRefValue); + } break; + case InstructionKind::BINARY_OP_RM: { + success = raiseBinaryOpMemToRegInstr(mi, curBlock, memoryRefValue); + } break; + case InstructionKind::DIVIDE_OP: { + success = raiseDivideInstr(mi, curBlock, memoryRefValue); + } break; + case InstructionKind::LOAD_FPU_REG: + success = raiseLoadIntToFloatRegInstr(mi, curBlock, memoryRefValue); + break; + case InstructionKind::STORE_FPU_REG: + success = raiseStoreIntToFloatRegInstr(mi, curBlock, memoryRefValue); + break; + default: + outs() << "Unhandled memory referencing instruction.\n"; + mi.dump(); + } + return success; +} + +bool X86MachineInstructionRaiser::raiseSetCCMachineInstr(const MachineInstr &mi, + BasicBlock *curBlock) { + const MCInstrDesc &MIDesc = mi.getDesc(); + LLVMContext &llvmContext(MF.getFunction().getContext()); + bool success = false; + + assert(MIDesc.getNumDefs() == 1 && + "Not found expected one destination operand of set instruction"); + assert(MIDesc.getNumImplicitUses() == 1 && + MIDesc.hasImplicitUseOfPhysReg(X86::EFLAGS) && + "Not found expected implicit use of eflags in set instruction."); + + const MachineOperand &DestOp = mi.getOperand(0); + CmpInst::Predicate pred = CmpInst::Predicate::BAD_ICMP_PREDICATE; + uint64_t EflagsCond = EFLAGS_UNDEFINED; + + switch (mi.getOpcode()) { + case X86::SETNEm: + case X86::SETNEr: + pred = CmpInst::Predicate::ICMP_NE; + EflagsCond = EFLAGS_ZF; + break; + case X86::SETEm: + case X86::SETEr: + pred = CmpInst::Predicate::ICMP_EQ; + EflagsCond = EFLAGS_ZF; + break; + default: + break; + } + + assert(EflagsCond != EFLAGS_UNDEFINED && "Undefined EFLAGS"); + + if (pred == CmpInst::Predicate::BAD_ICMP_PREDICATE) { + mi.dump(); + assert(false && "Unhandled set instruction"); + } + + if (DestOp.isReg()) { + // TODO : Using the eflags value seems very coarse. May be I should model + // the constituent flags as seperate values ??? + Value *EflagsVal = getRegValue(X86::EFLAGS); + Value *OneConstVal = + ConstantInt::get(Type::getInt1Ty(llvmContext), 1, false /* isSigned */); + CmpInst *cmp = new ICmpInst(pred, EflagsVal, OneConstVal); + curBlock->getInstList().push_back(cmp); + updatePhysRegSSAValue(DestOp.getReg(), cmp); + success = true; + } else { + outs() << "Unhandled set instruction with memory destination\n"; + success = false; + } + return success; +} +// Raise a binary operation instruction with operand encoding I or RI +bool X86MachineInstructionRaiser::raiseBinaryOpImmToRegMachineInstr( + const MachineInstr &mi, BasicBlock *curBlock) { + unsigned int DstIndex = 0, SrcOp1Index = 1, SrcOp2Index = 2; + const MCInstrDesc &MIDesc = mi.getDesc(); + // A binary operation instruction with encoding I specifies one operand - + // using AL/AX/EAX/RAX as implicit register operand. + // A binary operation instruction with encoding RI specifies two operands - + // the first operand is a register and the second the immediate value + // + // The first operand is also as the destination operand. + // X86::EFLAGS is the implicit def operand. + unsigned NumOperands = mi.getNumExplicitOperands() + + MIDesc.getNumImplicitUses() + + MIDesc.getNumImplicitDefs(); + + if (NumOperands == 4) { + // No need to raise an instruction that adjusts stack pointer. + if ((MIDesc.getNumDefs() == 1) && + (find64BitSuperReg(mi.getOperand(DstIndex).getReg()) == X86::RSP) && + (find64BitSuperReg(mi.getOperand(SrcOp1Index).getReg()) == X86::RSP) && + mi.getOperand(SrcOp2Index).isImm() && + MIDesc.hasImplicitDefOfPhysReg(X86::EFLAGS)) { + return true; + } else { + Value *SrcOp1Value = nullptr; + Value *SrcOp2Value = nullptr; + unsigned int DstPReg = X86::NoRegister; + + assert(MIDesc.hasImplicitDefOfPhysReg(X86::EFLAGS) && + "Expected implicit def operand EFLAGS not found"); + + if (MIDesc.getNumDefs() == 1) { + const MachineOperand &DstOp = mi.getOperand(DstIndex); + const MachineOperand &SrcOp1 = mi.getOperand(SrcOp1Index); + const MachineOperand &SrcOp2 = mi.getOperand(SrcOp2Index); + assert(DstOp.isReg() && "Not found expected register to be the " + "destination operand of BinOp instruction with " + "RI/I operand format"); + assert(SrcOp1.isReg() && + "Not found expected register to be the first " + "operand of BinOp instruction with RI/I operand format"); + + // Get value of SrcOp1 + unsigned int SrcOp1PReg = SrcOp1.getReg(); + SrcOp1Value = getRegValue(SrcOp1PReg); + + // Get value of SrcOp2 + assert(SrcOp2.isImm() && "Expect immediate operand in a BinOp " + "instruction with RI/I operand format"); + // Create constant of type that matches that of the dest operand + Type *Ty = getPhysRegOperandType(mi, DstIndex); + SrcOp2Value = ConstantInt::get(Ty, SrcOp2.getImm()); + assert(SrcOp1Value != nullptr && SrcOp2Value != nullptr && + "Undefined source values encountered in BinOp instruction with " + "RI/I operand format"); + + // Get destination reg + DstPReg = DstOp.getReg(); + + // Generate any necessary trunc or sext instrs to match the sizes + // of source and dest operands, as needed. + SrcOp1Value = matchSSAValueToSrcRegSize(mi, SrcOp1Index, curBlock); + } else if (MIDesc.getNumDefs() == 0) { + SrcOp1Index = 0; + // Uses implicit register AL/AX/EAX/RAX as source and dest + assert(MIDesc.getNumImplicitUses() == 1 && + "Expected one implicit use operand of BinOp instruction with " + "RI/I operand format"); + assert(MIDesc.getNumImplicitDefs() == 2 && + "Expected one implicit use operand of BinOp instruction with " + "RI/I operand format"); + + // Get the first (and only) operand + const MachineOperand &SrcOp = mi.getOperand(SrcOp1Index); + + // Get dest reg + DstPReg = MIDesc.ImplicitDefs[0]; + + assert(((DstPReg == X86::AL) || (DstPReg == X86::AX) || + (DstPReg == X86::EAX) || (DstPReg == X86::RAX)) && + "Expected implicit use of operand AL/AX/EAX/RAX not found"); + + assert(MIDesc.hasImplicitUseOfPhysReg(DstPReg) && + "Expected implicit use of operand AL/AX/EAX/RAX not found"); + + // Get value of SrcOp1 + SrcOp1Value = getRegValue(DstPReg); + + // Get value of SrcOp2 + assert(SrcOp.isImm() && "Expect immediate operand in a BinOp " + "instruction with RI/I operand format"); + // Create constant of type that matches that of the dest operand + Type *Ty = getImmOperandType(mi, SrcOp1Index); + SrcOp2Value = ConstantInt::get(Ty, SrcOp.getImm()); + } else { + mi.dump(); + assert(false && "Unhandled binary operation instruction with RI/I " + "operand format"); + } + + assert(DstPReg != X86::NoRegister && + "Failed to determine destination register of BinOp instruction " + "with RI/I operand format"); + + assert(SrcOp1Value != nullptr && SrcOp2Value != nullptr && + "Undefined source values encountered in BinOp instruction with " + "RI/I operand format"); + + Instruction *BinOpInstr = nullptr; + switch (mi.getOpcode()) { + case X86::ADD8i8: + case X86::ADD32ri: + case X86::ADD32ri8: + case X86::ADD64ri8: + case X86::ADD64ri32: + // Generate add instruction + BinOpInstr = BinaryOperator::CreateAdd(SrcOp1Value, SrcOp2Value); + break; + case X86::SUB32ri: + case X86::SUB32ri8: + case X86::SUB64ri8: + case X86::SUB64ri32: + // Generate sub instruction + BinOpInstr = BinaryOperator::CreateSub(SrcOp1Value, SrcOp2Value); + break; + case X86::AND8i8: + case X86::AND8ri: + case X86::AND16ri: + case X86::AND32ri: + case X86::AND64ri8: + case X86::AND64ri32: + // Generate and instruction + BinOpInstr = BinaryOperator::CreateAnd(SrcOp1Value, SrcOp2Value); + break; + case X86::XOR8ri: + // Generate xor instruction + BinOpInstr = BinaryOperator::CreateXor(SrcOp1Value, SrcOp2Value); + break; + case X86::IMUL32rri8: + case X86::IMUL64rri32: + BinOpInstr = BinaryOperator::CreateMul(SrcOp1Value, SrcOp2Value); + break; + default: + assert(false && "Unhandled reg to imm binary operator instruction"); + break; + } + + curBlock->getInstList().push_back(BinOpInstr); + // Update PhysReg to Value map + updatePhysRegSSAValue(DstPReg, BinOpInstr); + } + } else { + mi.dump(); + assert(false && "Unhandled add imeediate instruction"); + } + return true; +} + +// Raise indirect branch instruction. +// TODO : NYI +bool X86MachineInstructionRaiser::raiseIndirectBranchMachineInstr( + ControlTransferInfo *CTRec) { + const MachineInstr *MI = CTRec->CandidateMachineInstr; + // BasicBlock *CandBB = CTRec->CandidateBlock; + + const MCInstrDesc &MCID = MI->getDesc(); + + // Make sure this function was called on a direct branch instruction. + assert((MCID.TSFlags & X86II::ImmMask) == 0 && + "PC-Relative control transfer not expected"); + + // TODO: Change this once implementation is complete + return false; +} + +// Raise direct branch instruction. +bool X86MachineInstructionRaiser::raiseDirectBranchMachineInstr( + ControlTransferInfo *CTRec) { + const MachineInstr *MI = CTRec->CandidateMachineInstr; + BasicBlock *CandBB = CTRec->CandidateBlock; + + const MCInstrDesc &MCID = MI->getDesc(); + + // Make sure this function was called on a direct branch instruction. + assert(X86II::isImmPCRel(MCID.TSFlags) && + "PC-Relative control transfer expected"); + + // Get branch offset of the branch instruction + const MachineOperand &MO = MI->getOperand(0); + assert(MO.isImm() && "Expected immediate operand not found"); + int64_t BranchOffset = MO.getImm(); + MCInstRaiser *MCIR = getMCInstRaiser(); + // Get MCInst offset - the offset of machine instruction in the binary + uint64_t MCInstOffset = MCIR->getMCInstIndex(*MI); + + assert(MCIR != nullptr && "MCInstRaiser not initialized"); + int64_t BranchTargetOffset = + MCInstOffset + MCIR->getMCInstSize(MCInstOffset) + BranchOffset; + const uint64_t TgtMBBNo = + MCIR->getMBBNumberOfMCInstOffset(BranchTargetOffset); + auto iter = mbbToBBMap.find(TgtMBBNo); + assert(iter != mbbToBBMap.end() && + "BasicBlock corresponding to MachineInstr branch not found"); + BasicBlock *TgtBB = (*iter).second; + if (MI->isUnconditionalBranch()) { + // Just create a branch instruction targeting TgtBB + BranchInst *UncondBr = BranchInst::Create(TgtBB); + CandBB->getInstList().push_back(UncondBr); + CTRec->Raised = true; + } else if (MI->isConditionalBranch()) { + // Find the fall through basic block + MCInstRaiser::const_mcinst_iter MCIter = MCIR->getMCInstAt(MCInstOffset); + // Go to next instruction + MCIter++; + assert(MCIter != MCIR->const_mcinstr_end() && + "Attempt to go past MCInstr stream"); + // Get MBB number whose lead instruction is at the offset of next + // instruction. This is the fall-through MBB. + uint64_t FTMBBNum = MCIR->getMBBNumberOfMCInstOffset((*MCIter).first); + // Find raised BasicBlock corresponding to fall-through MBB + auto mapIter = mbbToBBMap.find(FTMBBNum); + assert(mapIter != mbbToBBMap.end() && + "Fall-through BasicBlock corresponding to MachineInstr branch not " + "found"); + BasicBlock *FTBB = (*mapIter).second; + // Get the condition value + assert(CTRec->RegValues.size() == 1 && + "Multiple implicit uses in conditional branch not handled"); + + // If the Cond value is a compare, change the predicate of the compare + // instruction based on condition of the branch. + + Value *Cond = CTRec->RegValues[0]; + Instruction *Inst = dyn_cast(Cond); + if (isa(Inst)) { + if (ICmpInst *IntCmpInst = dyn_cast(Inst)) { + // Detect the appropriate predicate + switch (MI->getOpcode()) { + case X86::JE_1: + case X86::JE_4: + IntCmpInst->setPredicate(CmpInst::Predicate::ICMP_EQ); + break; + case X86::JNE_1: + case X86::JNE_4: + IntCmpInst->setPredicate(CmpInst::Predicate::ICMP_NE); + break; + case X86::JA_4: + IntCmpInst->setPredicate(CmpInst::Predicate::ICMP_UGT); + break; + case X86::JAE_4: + IntCmpInst->setPredicate(CmpInst::Predicate::ICMP_UGE); + break; + case X86::JB_4: + IntCmpInst->setPredicate(CmpInst::Predicate::ICMP_ULT); + break; + case X86::JBE_4: + IntCmpInst->setPredicate(CmpInst::Predicate::ICMP_ULE); + break; + case X86::JG_4: + IntCmpInst->setPredicate(CmpInst::Predicate::ICMP_SGT); + break; + case X86::JGE_4: + IntCmpInst->setPredicate(CmpInst::Predicate::ICMP_SGE); + break; + case X86::JL_4: + IntCmpInst->setPredicate(CmpInst::Predicate::ICMP_SLT); + break; + case X86::JLE_1: + case X86::JLE_4: + IntCmpInst->setPredicate(CmpInst::Predicate::ICMP_SLE); + break; + default: + MI->dump(); + assert(false && "Unhandled conditional branch"); + } + } else if (FCmpInst *FC = dyn_cast(Inst)) { + assert(false && "Unhandled FCMP based branch raising"); + } + } + // If Cond is not a conditional instruction, construct one + else { + Value *CmpVal1 = Cond; + Type *CmpType = Cond->getType(); + Value *CmpVal2 = ConstantInt::get(CmpType, 0); + + if (CmpType->isIntegerTy()) { + CmpInst *IntCmpInst = new ICmpInst( + CmpInst::Predicate::FIRST_ICMP_PREDICATE, CmpVal1, CmpVal2); + CandBB->getInstList().push_back(IntCmpInst); + // Set this value to be used as branch condition + Cond = IntCmpInst; + // Detect the appropriate predicate + switch (MI->getOpcode()) { + case X86::JE_1: + case X86::JE_4: + IntCmpInst->setPredicate(CmpInst::Predicate::ICMP_EQ); + break; + case X86::JNE_1: + case X86::JNE_4: + IntCmpInst->setPredicate(CmpInst::Predicate::ICMP_NE); + break; + case X86::JA_4: + IntCmpInst->setPredicate(CmpInst::Predicate::ICMP_UGT); + break; + case X86::JAE_4: + IntCmpInst->setPredicate(CmpInst::Predicate::ICMP_UGE); + break; + case X86::JB_4: + IntCmpInst->setPredicate(CmpInst::Predicate::ICMP_ULT); + break; + case X86::JBE_4: + IntCmpInst->setPredicate(CmpInst::Predicate::ICMP_ULE); + break; + case X86::JG_4: + IntCmpInst->setPredicate(CmpInst::Predicate::ICMP_SGT); + break; + case X86::JGE_4: + IntCmpInst->setPredicate(CmpInst::Predicate::ICMP_SGE); + break; + case X86::JL_4: + IntCmpInst->setPredicate(CmpInst::Predicate::ICMP_SLT); + break; + case X86::JLE_4: + IntCmpInst->setPredicate(CmpInst::Predicate::ICMP_SLE); + break; + default: + MI->dump(); + assert(false && "Unhandled conditional branch"); + } + } else if (CmpType->isFloatTy()) { + assert(false && + "NYI - Generation of floating point compare instructions."); + } else { + assert(false && "Incompatible types of comparison operands found"); + } + } + // Set the predicate of the compare instruction according to the + // branch condition + + // Create branch instruction + BranchInst *CondBr = BranchInst::Create(TgtBB, FTBB, Cond); + CandBB->getInstList().push_back(CondBr); + CTRec->Raised = true; + } else { + assert(false && "Unhandled type of branch instruction"); + } + return true; +} + +// Raise a generic instruction. This is the catch all MachineInstr raiser +bool X86MachineInstructionRaiser::raiseGenericMachineInstr( + const MachineInstr &mi, BasicBlock *curBlock) { + unsigned int opcode = mi.getOpcode(); + bool success = false; + + // Now raise the instruction according to the opcode kind + switch (getInstructionKind(opcode)) { + case InstructionKind::BINARY_OP_WITH_IMM: + success = raiseBinaryOpImmToRegMachineInstr(mi, curBlock); + break; + case InstructionKind::CONVERT_BWWDDQ: + success = raiseConvertBWWDDQMachineInstr(mi, curBlock); + break; + case InstructionKind::CONVERT_WDDQQO: + success = raiseConvertWDDQQOMachineInstr(mi, curBlock); + break; + case InstructionKind::LEA_OP: + success = raiseLEAMachineInstr(mi, curBlock); + break; + case InstructionKind::MOV_RR: + success = raiseMoveRegToRegMachineInstr(mi, curBlock); + break; + case InstructionKind::MOV_RI: + success = raiseMoveImmToRegMachineInstr(mi, curBlock); + break; + case InstructionKind::BINARY_OP_RR: + success = raiseBinaryOpRegToRegMachineInstr(mi, curBlock); + break; + case InstructionKind::SETCC: + success = raiseSetCCMachineInstr(mi, curBlock); + break; + case InstructionKind::COMPARE: + success = raiseCompareMachineInstr(mi, curBlock, false, nullptr); + break; + case InstructionKind::FPU_REG_OP: + success = raiseFPURegisterOpInstr(mi, curBlock); + break; + default: { + outs() << "*** Generic instruction not raised : "; + mi.dump(); + success = false; + } + } + return success; +} + +// Raise a return instruction. +bool X86MachineInstructionRaiser::raiseReturnMachineInstr( + const MachineInstr &mi, BasicBlock *curBlock) { + Type *retType = raisedFunction->getReturnType(); + Value *retValue = nullptr; + + if (!retType->isVoidTy()) { + unsigned int retReg = + (retType->getPrimitiveSizeInBits() == 64) ? X86::RAX : X86::EAX; + retValue = findPhysRegSSAValue(retReg); + } + // Create return instruction + Instruction *retInstr = + ReturnInst::Create(MF.getFunction().getContext(), retValue); + curBlock->getInstList().push_back(retInstr); + + return true; +} + +bool X86MachineInstructionRaiser::raiseBranchMachineInstrs() { + // Raise branch instructions with control transfer records + bool success = true; + for (ControlTransferInfo *CTRec : CTInfo) { + if (CTRec->CandidateMachineInstr->isBranch()) { + const MachineInstr *MI = CTRec->CandidateMachineInstr; + const MCInstrDesc &MCID = MI->getDesc(); + uint64_t imm = MCID.TSFlags & X86II::ImmMask; + + if ((imm == X86II::Imm8PCRel) || (imm == X86II::Imm16PCRel) || + (imm == X86II::Imm32PCRel)) { + success &= raiseDirectBranchMachineInstr(CTRec); + assert(success && "Failed to raise direct branch instruction"); + } else { + success &= raiseIndirectBranchMachineInstr(CTRec); + assert(success && "Failed to raise indirect branch instruction"); + } + } + } + + // Delete all ControlTransferInfo records of branch instructions + // that were raised. + if (!CTInfo.empty()) { + CTInfo.erase( + std::remove_if(CTInfo.begin(), CTInfo.end(), + [](const ControlTransferInfo *r) { return r->Raised; }), + CTInfo.end()); + } + assert(CTInfo.empty() && "Unhandled branch instructions exist"); + + // Note that for basic blocks that fall-through and have no terminator, + // no control transfer record is created. Insert branch instructions + // at the end of all such blocks. + + // Walk basic blocks of the MachineFunction. + for (MachineFunction::iterator mfIter = MF.begin(), mfEnd = MF.end(); + mfIter != mfEnd; mfIter++) { + MachineBasicBlock &MBB = *mfIter; + // Get the number of MachineBasicBlock being looked at. + // If MBB has no terminators, insert a branch to the fall through edge. + if (MBB.getFirstTerminator() == MBB.end()) { + assert(MBB.succ_size() == 1 && "Expect MachineBasicBlock with no " + "terminators to have successors 1"); + // Find the BasicBlock corresponding to MBB + auto iter = mbbToBBMap.find(MBB.getNumber()); + assert(iter != mbbToBBMap.end() && + "Unable to find BasicBlock to insert unconditional branch"); + BasicBlock *BB = iter->second; + + // Find the BasicBlock corresponding to the successor of MBB + MachineBasicBlock *SuccMBB = *(MBB.succ_begin()); + iter = mbbToBBMap.find(SuccMBB->getNumber()); + assert(iter != mbbToBBMap.end() && "Unable to find successor BasicBlock"); + BasicBlock *SuccBB = iter->second; + + // Create a branch instruction targeting SuccBB + BranchInst *UncondBr = BranchInst::Create(SuccBB); + BB->getInstList().push_back(UncondBr); + } + } + return true; +} + +// Raise FPU instructions +bool X86MachineInstructionRaiser::raiseFPURegisterOpInstr( + const MachineInstr &mi, BasicBlock *curBlock) { + + // Construct the appropriate instruction + unsigned opcode = mi.getOpcode(); + switch (opcode) { + case X86::MUL_FPrST0: + case X86::DIV_FPrST0: { + Value *st0Val = FPURegisterStackGetValueAt(0); + assert((st0Val != nullptr) && "Failed to get ST(0) value"); + Type *st0ValTy = st0Val->getType(); + assert(st0ValTy->isFloatingPointTy() && + "Unexpected non-FP value on FPU register stack"); + assert((mi.getNumDefs() == 0) && + "Unexpected number of defs in FP register op instruction format"); + assert( + (mi.getNumExplicitOperands() == 1) && + "Unexpected number of operands in FP register op instruction format"); + const MachineOperand &stRegOp = mi.getOperand(0); + assert(stRegOp.isReg() && + "Unexpected non-register operand of FP register op instruction"); + int8_t FPRegIndex = stRegOp.getReg() - X86::ST0; + assert((FPRegIndex >= 0) && (FPRegIndex < FPUSTACK_SZ) && + "Unexpected FPU register stack index computed"); + Value *stVal = FPURegisterStackGetValueAt(FPRegIndex); + assert((stVal != nullptr) && "Failed to get value of FPU register"); + if (stVal->getType() != st0ValTy) { + CastInst *CInst = CastInst::Create( + CastInst::getCastOpcode(stVal, false, st0ValTy, false), stVal, + st0ValTy); + curBlock->getInstList().push_back(CInst); + stVal = CInst; + } + // Create fmul + Instruction *FPRegOpInstr = nullptr; + if (opcode == X86::MUL_FPrST0) { + FPRegOpInstr = BinaryOperator::CreateFMul(stVal, st0Val); + } else if (opcode == X86::DIV_FPrST0) { + FPRegOpInstr = BinaryOperator::CreateFDiv(stVal, st0Val); + } + curBlock->getInstList().push_back(FPRegOpInstr); + // Update the FP register FPRegIndex with FPRegOpInstr + FPURegisterStackSetValueAt(FPRegIndex, FPRegOpInstr); + // Pop FPU register stack + FPURegisterStackPop(); + } break; + default: { + assert(false && "Unhandled FPU instruction"); + } break; + } + + return true; +} + +// Raise Call instruction +bool X86MachineInstructionRaiser::raiseCallMachineInstr( + const MachineInstr &CallMI, BasicBlock *curBlock) { + unsigned int opcode = CallMI.getOpcode(); + switch (opcode) { + // case X86::CALLpcrel16 : + // case X86::CALLpcrel32 : + case X86::CALL64pcrel32: { + const MCInstrDesc &MCID = CallMI.getDesc(); + assert(X86II::isImmPCRel(MCID.TSFlags) && + "PC-Relative control transfer expected"); + + // Get target offset of the call instruction + const MachineOperand &MO = CallMI.getOperand(0); + assert(MO.isImm() && "Expected immediate operand not found"); + int64_t RelCallTargetOffset = MO.getImm(); + + // Compute the MCInst index of the call target + MCInstRaiser *MCIR = getMCInstRaiser(); + // Get MCInst offset of the corresponding call instruction in the binary. + uint64_t MCInstOffset = MCIR->getMCInstIndex(CallMI); + assert(MCIR != nullptr && "MCInstRaiser not initialized"); + Function *CalledFunc = nullptr; + uint64_t MCInstSize = MCIR->getMCInstSize(MCInstOffset); + // First check if PC-relative call target embedded in the call instruction + // can be used to get called function. + int64_t CallTargetIndex = MCInstOffset + MR->getTextSectionAddress() + + MCInstSize + RelCallTargetOffset; + // Get the function at index CalltargetIndex + CalledFunc = MR->getFunctionAt(CallTargetIndex); + // If not, use text section relocations to get the + // call target function. + if (CalledFunc == nullptr) { + CalledFunc = + MR->getCalledFunctionUsingTextReloc(MCInstOffset, MCInstSize); + } + // Look up the PLT to find called function + if (CalledFunc == nullptr) { + CalledFunc = getTargetFunctionAtPLTOffset(CallMI, CallTargetIndex); + } + + std::vector CallInstFuncArgs; + unsigned NumArgs = CalledFunc->arg_size(); + Argument *CalledFuncArgs = CalledFunc->arg_begin(); + + if (CalledFunc->isVarArg()) { + // Discover argument registers that are live just before the CallMI. + const MachineBasicBlock *CurMBB = CallMI.getParent(); + // Liveness of the blocks is already computed in + // getRaisedFunctionPrototype(). So no need to run it again since no MBB + // would be modified. + MachineBasicBlock::const_reverse_iterator CallInstIter(CallMI); + // Find the highest argument register that is defined in the block + // before the CallMI. NOTE : We assume that all arguments are setup + // prior to the call. This argument setup manifests as defines in the + // block or a combination of argument registers that are live-in and + // defines in the block. Additionally, if the block has more than one + // calls, it is assumed that call setup for all calls other than the + // first is done entirely in the block after the preceding call. In such + // a situation, there is no need to look for argument registers in the + // live-ins of the block. bool UseLiveIns = true; + + std::set RegsLiveAtCall; + // Bit mask to keep track of argument register positions already + // discovered. + uint8_t PositionMask = 0; + + // Find out the types of arguments set up before call instruction + for (const MachineInstr &MI : + make_range(++CallInstIter, CurMBB->rend())) { + // Stop walking past the most recent call instruction in the block. + if (MI.isCall()) { + // UseLiveIns = false; + break; + } + // If the instruction has a define + if (MI.getNumDefs() > 0) { + for (auto MO : MI.defs()) { + // If the define is a register + if (MO.isReg()) { + unsigned Reg = MO.getReg(); + if (TargetRegisterInfo::isPhysicalRegister(Reg)) { + int ArgNo = getArgumentNumber(Reg); + if (ArgNo > 0) { + uint8_t ArgNoMask = (1 << ArgNo); + // Consider only the most recent definition + if ((PositionMask & ArgNoMask) == 0) { + RegsLiveAtCall.emplace(Reg); + PositionMask |= ArgNoMask; + } + } + } + } + } + } + } +#if 0 + // May be incorrect?? + // TODO : Do we need to look to see if any of the liveins are argument registers + if (UseLiveIns) { + for (auto LI : CurMBB->liveins()) { + MCPhysReg Reg = LI.PhysReg; + if (TargetRegisterInfo::isPhysicalRegister(Reg)) { + int ArgNo = MIR.getArgumentNumber(Reg); + if (ArgNo > 0) { + uint8_t ArgNoMask = (1 << ArgNo); + if ((PositionMask & ArgNoMask) == 0) { + RegsLiveAtCall.emplace(Reg); + PositionMask |= ArgNoMask; + } + } + } + } + } +#endif + // Find the number of arguments + // NOTE: Handling register arguments - 6 in number. Need to handle + // arguments passed on stack make sure bit 8 and bit 0 are not set + assert(!(PositionMask & 1) && !(PositionMask & (1 << 7)) && + "Invalid argument numbers discovered"); + uint8_t ShftPositionMask = PositionMask >> 1; + uint8_t NumArgsDiscovered = 0; + // Consider only consecutive argument registers. + while (ShftPositionMask & 1) { + ShftPositionMask = ShftPositionMask >> 1; + NumArgsDiscovered++; + } + // If number of arguments discovered is greater than CalledFunc + // arguments use that as the number of arguments of the called function. + if (NumArgsDiscovered > NumArgs) { + NumArgs = NumArgsDiscovered; + } + } + // Construct the argument list with values to be used to construct a new + // CallInst. These values are those of the physical registers as defined + // in C calling convention (the calling convention currently supported). + for (unsigned i = 0; i < NumArgs; i++) { + // Get the values of argument registers + Value *ArgVal = getRegValue(GPR64ArgRegs64Bit[i]); + if (i < CalledFunc->arg_size()) { + // This condition will not be true for variadic functions. + // In that case just add the value. + if (ArgVal->getType() != CalledFuncArgs[i].getType()) { + CastInst *CInst = CastInst::Create( + CastInst::getCastOpcode(ArgVal, false, + CalledFuncArgs[i].getType(), false), + ArgVal, CalledFuncArgs[i].getType()); + curBlock->getInstList().push_back(CInst); + ArgVal = CInst; + } + } + CallInstFuncArgs.push_back(ArgVal); + } + // Construct call inst. + CallInst *callInst = + CallInst::Create(CalledFunc, ArrayRef(CallInstFuncArgs)); + curBlock->getInstList().push_back(callInst); + // A function call with a non-void return will modify + // RAX. + Type *RetType = CalledFunc->getReturnType(); + if (!RetType->isVoidTy()) { + updatePhysRegSSAValue(X86::RAX, callInst); + } + } break; + default: { + assert(false && "Unhandled call instruction"); + } break; + } + + return true; +} + +// Top-level function that calls appropriate function that raises +// a MachineInstruction. +// Returns true upon success. + +bool X86MachineInstructionRaiser::raiseMachineInstr(MachineInstr &mi, + BasicBlock *curBlock) { + const MCInstrDesc &MIDesc = mi.getDesc(); + + if (MIDesc.mayLoad() || MIDesc.mayStore()) { + return raiseMemRefMachineInstr(mi, curBlock); + } else if (MIDesc.isReturn()) { + return raiseReturnMachineInstr(mi, curBlock); + } else { + return raiseGenericMachineInstr(mi, curBlock); + } + return false; +} + +// Raise MachineInstr in MachineFunction to MachineInstruction + +bool X86MachineInstructionRaiser::raiseMachineFunction() { + Function *curFunction = getRaisedFunction(); + LLVMContext &llvmContext(curFunction->getContext()); + // Start with an assumption that values of EFLAGS and RSP are 0 at the entry + // of each function. + Value *Zero32BitValue = + ConstantInt::get(Type::getInt32Ty(llvmContext), 0, false /* isSigned */); + Value *Zero64BitValue = + ConstantInt::get(Type::getInt64Ty(llvmContext), 0, false /* isSigned */); + updatePhysRegSSAValue(X86::EFLAGS, Zero32BitValue); + // Set values of some registers that appear to be used in main function to + // 0. + if (curFunction->getName().equals("main")) { + updatePhysRegSSAValue(X86::RCX, Zero64BitValue); + } + + // Walk basic blocks of the MachineFunction. Raise all non control + // transfer MachineInstrs of each MachineBasicBlocks of MachineFunction, + // except branch instructions. + for (MachineFunction::iterator mfIter = MF.begin(), mfEnd = MF.end(); + mfIter != mfEnd; mfIter++) { + MachineBasicBlock &MBB = *mfIter; + // Get the number of MachineBasicBlock being looked at. + int MBBNo = MBB.getNumber(); + // Name of the corresponding BasicBlock to be created + StringRef BBName = MBBNo == 0 ? "entry" : "bb." + std::to_string(MBBNo); + // Create a BasicBlock instance corresponding to MBB being looked at. + // The raised form of MachineInstr of MBB will be added to curBlock. + BasicBlock *CurIBB = BasicBlock::Create(llvmContext, BBName, curFunction); + // Record the mapping of the number of MBB to corresponding BasicBlock. + // This information is used to raise branch instructions, if any, of the + // MBB in a later walk of MachineBasicBlocks of MF. + mbbToBBMap.insert(std::make_pair(MBBNo, CurIBB)); + // Walk MachineInsts of the MachineBasicBlock + for (MachineBasicBlock::iterator mbbIter = mfIter->instr_begin(), + mbbEnd = mfIter->instr_end(); + mbbIter != mbbEnd; mbbIter++) { + MachineInstr &mi = *mbbIter; + // Ignore noop instructions. + if (isNoop(mi.getOpcode())) { + continue; + } + // If this is a terminator instruction, record + // necessary information to raise it in a later pass. + if (mi.isTerminator() && !mi.isReturn()) { + recordMachineInstrInfo(mi, CurIBB); + continue; + } + if (mi.isCall()) { + if (!raiseCallMachineInstr(mi, CurIBB)) { + return false; + } + } else if (!raiseMachineInstr(mi, CurIBB)) { + return false; + } + } + } + return raiseBranchMachineInstrs(); +} + +bool X86MachineInstructionRaiser::raise() { return raiseMachineFunction(); } + +#ifdef __cplusplus +extern "C" { +#endif +MachineInstructionRaiser * +InitializeX86MachineInstructionRaiser(MachineFunction &machFunc, Module &m, + const ModuleRaiser *mr, + MCInstRaiser *mcir) { + return new X86MachineInstructionRaiser(machFunc, m, mr, mcir); +} +#ifdef __cplusplus +} +#endif Index: tools/llvm-mctoll/llvm-mctoll.h =================================================================== --- /dev/null +++ tools/llvm-mctoll/llvm-mctoll.h @@ -0,0 +1,108 @@ +//===---- llvm-mctoll.h - Binary raiser utility llvm-mctoll ---------------===// +// +// The LLVM Compiler Infrastructure +// +// This file is distributed under the University of Illinois Open Source +// License. See LICENSE.TXT for details. +// +//===----------------------------------------------------------------------===// + +#ifndef LLVM_TOOLS_LLVM_MCTOLL_LLVM_MCTOLL_H +#define LLVM_TOOLS_LLVM_MCTOLL_LLVM_MCTOLL_H + +#include "llvm/DebugInfo/DIContext.h" +#include "llvm/Object/Archive.h" +#include "llvm/Support/CommandLine.h" +#include "llvm/Support/Compiler.h" +#include "llvm/Support/DataTypes.h" + +namespace llvm { +class StringRef; + +namespace object { +class COFFObjectFile; +class COFFImportFile; +class MachOObjectFile; +class ObjectFile; +class Archive; +class RelocationRef; +} // namespace object + +extern cl::opt TripleName; +extern cl::opt ArchName; +extern cl::list FilterSections; +extern cl::list FilterFunctions; +extern cl::opt Disassemble; +// extern cl::opt DisassembleAll; +extern cl::opt NoShowRawInsn; +extern cl::opt NoLeadingAddr; +extern cl::opt PrivateHeaders; +extern cl::opt FirstPrivateHeader; +extern cl::opt ExportsTrie; +extern cl::opt Rebase; +extern cl::opt Bind; +extern cl::opt LazyBind; +extern cl::opt WeakBind; +extern cl::opt RawClangAST; +extern cl::opt UniversalHeaders; +extern cl::opt ArchiveHeaders; +extern cl::opt IndirectSymbols; +extern cl::opt DataInCode; +extern cl::opt LinkOptHints; +extern cl::opt InfoPlist; +extern cl::opt DylibsUsed; +extern cl::opt DylibId; +extern cl::opt ObjcMetaData; +extern cl::opt DisSymName; +extern cl::opt NonVerbose; +extern cl::opt Relocations; +extern cl::opt SectionHeaders; +extern cl::opt SectionContents; +extern cl::opt SymbolTable; +extern cl::opt UnwindInfo; +extern cl::opt PrintImmHex; +extern cl::opt DwarfDumpType; + +// Various helper functions. +void error(std::error_code ec); +bool RelocAddressLess(object::RelocationRef a, object::RelocationRef b); +void ParseInputMachO(StringRef Filename); +void printCOFFUnwindInfo(const object::COFFObjectFile *o); +void printMachOUnwindInfo(const object::MachOObjectFile *o); +void printMachOExportsTrie(const object::MachOObjectFile *o); +void printMachORebaseTable(object::MachOObjectFile *o); +void printMachOBindTable(object::MachOObjectFile *o); +void printMachOLazyBindTable(object::MachOObjectFile *o); +void printMachOWeakBindTable(object::MachOObjectFile *o); +void printELFFileHeader(const object::ObjectFile *o); +void printCOFFFileHeader(const object::ObjectFile *o); +void printCOFFSymbolTable(const object::COFFImportFile *i); +void printCOFFSymbolTable(const object::COFFObjectFile *o); +void printMachOFileHeader(const object::ObjectFile *o); +void printMachOLoadCommands(const object::ObjectFile *o); +void printWasmFileHeader(const object::ObjectFile *o); +void printExportsTrie(const object::ObjectFile *o); +void printRebaseTable(object::ObjectFile *o); +void printBindTable(object::ObjectFile *o); +void printLazyBindTable(object::ObjectFile *o); +void printWeakBindTable(object::ObjectFile *o); +void printRawClangAST(const object::ObjectFile *o); +void PrintRelocations(const object::ObjectFile *o); +void PrintSectionHeaders(const object::ObjectFile *o); +void PrintSectionContents(const object::ObjectFile *o); +void PrintSymbolTable(const object::ObjectFile *o, StringRef ArchiveName, + StringRef ArchitectureName = StringRef()); +LLVM_ATTRIBUTE_NORETURN void error(Twine Message); +LLVM_ATTRIBUTE_NORETURN void report_error(StringRef File, Twine Message); +LLVM_ATTRIBUTE_NORETURN void report_error(StringRef File, std::error_code EC); +LLVM_ATTRIBUTE_NORETURN void report_error(StringRef File, llvm::Error E); +LLVM_ATTRIBUTE_NORETURN void +report_error(StringRef FileName, StringRef ArchiveName, llvm::Error E, + StringRef ArchitectureName = StringRef()); +LLVM_ATTRIBUTE_NORETURN void +report_error(StringRef ArchiveName, const object::Archive::Child &C, + llvm::Error E, StringRef ArchitectureName = StringRef()); + +} // end namespace llvm + +#endif // LLVM_TOOLS_LLVM_MCTOLL_LLVM_MCTOLL_H Index: tools/llvm-mctoll/llvm-mctoll.cpp =================================================================== --- /dev/null +++ tools/llvm-mctoll/llvm-mctoll.cpp @@ -0,0 +1,2137 @@ +//===-- llvm-mctoll.cpp - Object file dumping utility for llvm -----------===// +// +// The LLVM Compiler Infrastructure +// +//===----------------------------------------------------------------------===// +// +// This program is a utility that converts a binary to LLVM IR (.ll file) +// +//===----------------------------------------------------------------------===// + +#include "llvm-mctoll.h" +#include "EmitRaisedOutputPass.h" +#include "MCInstOrData.h" +#include "MachineFunctionRaiser.h" +#include "ModuleRaiser.h" +#include "llvm/ADT/Optional.h" +#include "llvm/ADT/STLExtras.h" +#include "llvm/ADT/StringExtras.h" +#include "llvm/ADT/Triple.h" +#include "llvm/Bitcode/BitcodeWriter.h" +#include "llvm/Bitcode/BitcodeWriterPass.h" +#include "llvm/CodeGen/FaultMaps.h" +#include "llvm/CodeGen/MachineFunctionPass.h" +#include "llvm/CodeGen/MachineInstrBuilder.h" +#include "llvm/CodeGen/MachineModuleInfo.h" +#include "llvm/CodeGen/Passes.h" +#include "llvm/CodeGen/TargetPassConfig.h" +#include "llvm/DebugInfo/DWARF/DWARFContext.h" +#include "llvm/DebugInfo/Symbolize/Symbolize.h" +#include "llvm/IR/Function.h" +#include "llvm/IR/IRPrintingPasses.h" +#include "llvm/IR/LLVMContext.h" +#include "llvm/IR/LegacyPassManager.h" +#include "llvm/IR/Module.h" +#include "llvm/IR/Type.h" +#include "llvm/MC/MCAsmInfo.h" +#include "llvm/MC/MCContext.h" +#include "llvm/MC/MCDisassembler/MCDisassembler.h" +#include "llvm/MC/MCDisassembler/MCRelocationInfo.h" +#include "llvm/MC/MCInstPrinter.h" +#include "llvm/MC/MCInstrAnalysis.h" +#include "llvm/MC/MCInstrInfo.h" +#include "llvm/MC/MCObjectFileInfo.h" +#include "llvm/MC/MCRegisterInfo.h" +#include "llvm/MC/MCSubtargetInfo.h" +#include "llvm/Object/Archive.h" +#include "llvm/Object/COFF.h" +#include "llvm/Object/COFFImportFile.h" +#include "llvm/Object/ELFObjectFile.h" +#include "llvm/Object/MachO.h" +#include "llvm/Object/ObjectFile.h" +#include "llvm/Object/Wasm.h" +#include "llvm/Support/Casting.h" +#include "llvm/Support/CommandLine.h" +#include "llvm/Support/Debug.h" +#include "llvm/Support/Errc.h" +#include "llvm/Support/FileSystem.h" +#include "llvm/Support/Format.h" +#include "llvm/Support/GraphWriter.h" +#include "llvm/Support/Host.h" +#include "llvm/Support/ManagedStatic.h" +#include "llvm/Support/MemoryBuffer.h" +#include "llvm/Support/PrettyStackTrace.h" +#include "llvm/Support/Signals.h" +#include "llvm/Support/SourceMgr.h" +#include "llvm/Support/TargetRegistry.h" +#include "llvm/Support/TargetSelect.h" +#include "llvm/Support/ToolOutputFile.h" +#include "llvm/Support/raw_ostream.h" +#include "llvm/Target/TargetMachine.h" +#include "llvm/Target/TargetOptions.h" +#include +#include +#include +#include +#include +#include +#include +#include + +using namespace llvm; +using namespace object; + +static cl::OptionCategory LLVMMCToLLCategory("llvm-mctoll options"); + +static cl::list InputFilenames(cl::Positional, + cl::desc(""), + cl::ZeroOrMore); +static cl::opt OutputFilename("o", cl::desc("Output filename"), + cl::value_desc("filename"), + cl::cat(LLVMMCToLLCategory), + cl::NotHidden); + +cl::opt + MCPU("mcpu", + cl::desc("Target a specific cpu type (-mcpu=help for details)"), + cl::value_desc("cpu-name"), cl::init("")); + +cl::list + MAttrs("mattr", cl::CommaSeparated, + cl::desc("Target specific attributes (-mattr=help for details)"), + cl::value_desc("a1,+a2,-a3,...")); + +// Output file type. Default is binary bitcode. +cl::opt OutputFormat( + "output-format", cl::init(TargetMachine::CGFT_AssemblyFile), + cl::desc("Output format (default: binary bitcode):"), + cl::values(clEnumValN(TargetMachine::CGFT_AssemblyFile, "ll", + "Emit llvm text bitcode ('.ll') file"), + clEnumValN(TargetMachine::CGFT_ObjectFile, "bc", + "Emit llvm binary bitcode ('.bc') file"), + clEnumValN(TargetMachine::CGFT_Null, "null", + "Emit nothing, for performance testing")), + cl::cat(LLVMMCToLLCategory), cl::NotHidden); + +cl::opt llvm::Disassemble("raise", cl::desc("Raise machine instruction"), + cl::cat(LLVMMCToLLCategory), cl::NotHidden); + +cl::alias Disassembled("d", cl::desc("Alias for -raise"), + cl::aliasopt(Disassemble), cl::cat(LLVMMCToLLCategory), + cl::NotHidden); + +cl::opt + llvm::Relocations("r", + cl::desc("Display the relocation entries in the file")); + +cl::opt llvm::SymbolTable("t", cl::desc("Display the symbol table")); + +cl::opt llvm::ExportsTrie("exports-trie", + cl::desc("Display mach-o exported symbols")); + +cl::opt llvm::Rebase("rebase", cl::desc("Display mach-o rebasing info")); + +cl::opt llvm::Bind("bind", cl::desc("Display mach-o binding info")); + +cl::opt llvm::LazyBind("lazy-bind", + cl::desc("Display mach-o lazy binding info")); + +cl::opt llvm::WeakBind("weak-bind", + cl::desc("Display mach-o weak binding info")); + +cl::opt llvm::RawClangAST( + "raw-clang-ast", + cl::desc("Dump the raw binary contents of the clang AST section")); + +static cl::opt + MachOOpt("macho", cl::desc("Use MachO specific object file parser")); +static cl::alias MachOm("m", cl::desc("Alias for --macho"), + cl::aliasopt(MachOOpt)); + +static cl::opt NoVerify("disable-verify", cl::Hidden, + cl::desc("Do not verify input module")); + +cl::opt + llvm::TripleName("triple", cl::desc("Target triple to disassemble for, " + "see -version for available targets")); + +cl::opt + llvm::ArchName("arch-name", cl::desc("Target arch to disassemble for, " + "see -version for available targets")); + +cl::opt llvm::SectionHeaders("section-headers", + cl::desc("Display summaries of the " + "headers for each section.")); +static cl::alias SectionHeadersShort("headers", + cl::desc("Alias for --section-headers"), + cl::aliasopt(SectionHeaders)); +static cl::alias SectionHeadersShorter("h", + cl::desc("Alias for --section-headers"), + cl::aliasopt(SectionHeaders)); + +cl::list + llvm::FilterSections("section", + cl::desc("Operate on the specified sections only. " + "With -macho dump segment,section")); +cl::list + llvm::FilterFunctions("function", + cl::desc("Operate on the specified functions only. "), + cl::cat(LLVMMCToLLCategory), cl::NotHidden); + +cl::alias static FilterSectionsj("j", cl::desc("Alias for --section"), + cl::aliasopt(llvm::FilterSections)); + +cl::opt llvm::NoShowRawInsn("no-show-raw-insn", + cl::desc("When disassembling " + "instructions, do not print " + "the instruction bytes.")); +cl::opt llvm::NoLeadingAddr("no-leading-addr", + cl::desc("Print no leading address")); + +cl::opt llvm::UnwindInfo("unwind-info", + cl::desc("Display unwind information")); + +static cl::alias UnwindInfoShort("u", cl::desc("Alias for --unwind-info"), + cl::aliasopt(UnwindInfo)); + +cl::opt + llvm::PrivateHeaders("private-headers", + cl::desc("Display format specific file headers")); + +cl::opt llvm::FirstPrivateHeader( + "private-header", cl::desc("Display only the first format specific file " + "header")); + +static cl::alias PrivateHeadersShort("p", + cl::desc("Alias for --private-headers"), + cl::aliasopt(PrivateHeaders)); + +cl::opt + llvm::PrintImmHex("print-imm-hex", + cl::desc("Use hex format for immediate values")); + +cl::opt PrintFaultMaps("fault-map-section", + cl::desc("Display contents of faultmap section")); + +cl::opt PrintSource( + "source", + cl::desc( + "Display source inlined with disassembly. Implies disassmble object")); + +cl::alias PrintSourceShort("S", cl::desc("Alias for -source"), + cl::aliasopt(PrintSource)); + +cl::opt PrintLines("line-numbers", + cl::desc("Display source line numbers with " + "disassembly. Implies disassemble object")); + +cl::alias PrintLinesShort("l", cl::desc("Alias for -line-numbers"), + cl::aliasopt(PrintLines)); + +cl::opt + StartAddress("start-address", cl::desc("Disassemble beginning at address"), + cl::value_desc("address"), cl::init(0)); +cl::opt StopAddress("stop-address", + cl::desc("Stop disassembly at address"), + cl::value_desc("address"), + cl::init(UINT64_MAX)); + +namespace { +static ManagedStatic> RunPassNames; + +struct RunPassOption { + void operator=(const std::string &Val) const { + if (Val.empty()) + return; + SmallVector PassNames; + StringRef(Val).split(PassNames, ',', -1, false); + for (auto PassName : PassNames) + RunPassNames->push_back(PassName); + } +}; +} // namespace + +static RunPassOption RunPassOpt; + +static cl::opt> RunPass( + "run-pass", + cl::desc("Run compiler only for specified passes (comma separated list)"), + cl::value_desc("pass-name"), cl::ZeroOrMore, cl::location(RunPassOpt)); + +static StringRef ToolName; + +typedef std::tuple SectionSymbolInfo; +typedef std::vector SectionSymbolsTy; + +namespace { +typedef std::function FilterPredicate; + +class SectionFilterIterator { +public: + SectionFilterIterator(FilterPredicate P, + llvm::object::section_iterator const &I, + llvm::object::section_iterator const &E) + : Predicate(std::move(P)), Iterator(I), End(E) { + ScanPredicate(); + } + const llvm::object::SectionRef &operator*() const { return *Iterator; } + SectionFilterIterator &operator++() { + ++Iterator; + ScanPredicate(); + return *this; + } + bool operator!=(SectionFilterIterator const &Other) const { + return Iterator != Other.Iterator; + } + +private: + void ScanPredicate() { + while (Iterator != End && !Predicate(*Iterator)) { + ++Iterator; + } + } + FilterPredicate Predicate; + llvm::object::section_iterator Iterator; + llvm::object::section_iterator End; +}; + +class SectionFilter { +public: + SectionFilter(FilterPredicate P, llvm::object::ObjectFile const &O) + : Predicate(std::move(P)), Object(O) {} + SectionFilterIterator begin() { + return SectionFilterIterator(Predicate, Object.section_begin(), + Object.section_end()); + } + SectionFilterIterator end() { + return SectionFilterIterator(Predicate, Object.section_end(), + Object.section_end()); + } + +private: + FilterPredicate Predicate; + llvm::object::ObjectFile const &Object; +}; +SectionFilter ToolSectionFilter(llvm::object::ObjectFile const &O) { + return SectionFilter( + [](llvm::object::SectionRef const &S) { + if (FilterSections.empty()) + return true; + llvm::StringRef String; + std::error_code error = S.getName(String); + if (error) + return false; + return is_contained(FilterSections, String); + }, + O); +} +} // namespace + +void llvm::error(std::error_code EC) { + if (!EC) + return; + + errs() << ToolName << ": error reading file: " << EC.message() << ".\n"; + errs().flush(); + exit(1); +} + +LLVM_ATTRIBUTE_NORETURN void llvm::error(Twine Message) { + errs() << ToolName << ": " << Message << ".\n"; + errs().flush(); + exit(1); +} + +LLVM_ATTRIBUTE_NORETURN void llvm::report_error(StringRef File, Twine Message) { + errs() << ToolName << ": '" << File << "': " << Message << ".\n"; + exit(1); +} + +LLVM_ATTRIBUTE_NORETURN void llvm::report_error(StringRef File, + std::error_code EC) { + assert(EC); + errs() << ToolName << ": '" << File << "': " << EC.message() << ".\n"; + exit(1); +} + +LLVM_ATTRIBUTE_NORETURN void llvm::report_error(StringRef File, llvm::Error E) { + assert(E); + std::string Buf; + raw_string_ostream OS(Buf); + logAllUnhandledErrors(std::move(E), OS, ""); + OS.flush(); + errs() << ToolName << ": '" << File << "': " << Buf; + exit(1); +} + +LLVM_ATTRIBUTE_NORETURN void llvm::report_error(StringRef ArchiveName, + StringRef FileName, + llvm::Error E, + StringRef ArchitectureName) { + assert(E); + errs() << ToolName << ": "; + if (ArchiveName != "") + errs() << ArchiveName << "(" << FileName << ")"; + else + errs() << "'" << FileName << "'"; + if (!ArchitectureName.empty()) + errs() << " (for architecture " << ArchitectureName << ")"; + std::string Buf; + raw_string_ostream OS(Buf); + logAllUnhandledErrors(std::move(E), OS, ""); + OS.flush(); + errs() << ": " << Buf; + exit(1); +} + +LLVM_ATTRIBUTE_NORETURN void llvm::report_error(StringRef ArchiveName, + const object::Archive::Child &C, + llvm::Error E, + StringRef ArchitectureName) { + Expected NameOrErr = C.getName(); + // TODO: if we have a error getting the name then it would be nice to print + // the index of which archive member this is and or its offset in the + // archive instead of "???" as the name. + if (!NameOrErr) { + consumeError(NameOrErr.takeError()); + llvm::report_error(ArchiveName, "???", std::move(E), ArchitectureName); + } else + llvm::report_error(ArchiveName, NameOrErr.get(), std::move(E), + ArchitectureName); +} + +static const Target *getTarget(const ObjectFile *Obj = nullptr) { + // Figure out the target triple. + llvm::Triple TheTriple("unknown-unknown-unknown"); + if (TripleName.empty()) { + if (Obj) { + auto Arch = Obj->getArch(); + TheTriple.setArch(Triple::ArchType(Arch)); + + // For ARM targets, try to use the build attributes to build determine + // the build target. Target features are also added, but later during + // disassembly. + if (Arch == Triple::arm || Arch == Triple::armeb) { + Obj->setARMSubArch(TheTriple); + } + + // TheTriple defaults to ELF, and COFF doesn't have an environment: + // the best we can do here is indicate that it is mach-o. + if (Obj->isMachO()) + TheTriple.setObjectFormat(Triple::MachO); + + if (Obj->isCOFF()) { + const auto COFFObj = dyn_cast(Obj); + if (COFFObj->getArch() == Triple::thumb) + TheTriple.setTriple("thumbv7-windows"); + } + } + } else { + TheTriple.setTriple(Triple::normalize(TripleName)); + // Use the triple, but also try to combine with ARM build attributes. + if (Obj) { + auto Arch = Obj->getArch(); + if (Arch == Triple::arm || Arch == Triple::armeb) { + Obj->setARMSubArch(TheTriple); + } + } + } + + // Get the target specific parser. + std::string Error; + const Target *TheTarget = + TargetRegistry::lookupTarget(ArchName, TheTriple, Error); + if (!TheTarget) { + if (Obj) + report_error(Obj->getFileName(), "can't find target: " + Error); + else + error("can't find target: " + Error); + } + + // Update the triple name and return the found target. + TripleName = TheTriple.getTriple(); + return TheTarget; +} + +static std::unique_ptr GetOutputStream(const char *TargetName, + Triple::OSType OS, + const char *ProgName) { + // If we don't yet have an output filename, make one. + if (OutputFilename.empty()) { + // If InputFilename ends in .o, remove it. + StringRef IFN = InputFilenames[0]; + if (IFN.endswith(".o")) + OutputFilename = IFN.drop_back(2); + else if (IFN.endswith(".so")) + OutputFilename = IFN.drop_back(3); + else + OutputFilename = IFN; + + switch (OutputFormat) { + case TargetMachine::CGFT_AssemblyFile: + OutputFilename += "-dis.ll"; + break; + // Just uses enum CGFT_ObjectFile represent llvm bitcode file type + // provisionally. + case TargetMachine::CGFT_ObjectFile: + OutputFilename += "-dis.bc"; + break; + case TargetMachine::CGFT_Null: + OutputFilename += ".null"; + break; + } + } + + // Decide if we need "binary" output. + bool Binary = false; + switch (OutputFormat) { + case TargetMachine::CGFT_AssemblyFile: + break; + case TargetMachine::CGFT_ObjectFile: + case TargetMachine::CGFT_Null: + Binary = true; + break; + } + + // Open the file. + std::error_code EC; + sys::fs::OpenFlags OpenFlags = sys::fs::F_None; + if (!Binary) + OpenFlags |= sys::fs::F_Text; + auto FDOut = llvm::make_unique(OutputFilename, EC, OpenFlags); + if (EC) { + errs() << EC.message() << '\n'; + return nullptr; + } + + return FDOut; +} + +static bool addPass(PassManagerBase &PM, StringRef toolname, StringRef PassName, + TargetPassConfig &TPC) { + if (PassName == "none") + return false; + + const PassRegistry *PR = PassRegistry::getPassRegistry(); + const PassInfo *PI = PR->getPassInfo(PassName); + if (!PI) { + errs() << toolname << ": run-pass " << PassName << " is not registered.\n"; + return true; + } + + Pass *P; + if (PI->getNormalCtor()) + P = PI->getNormalCtor()(); + else { + errs() << toolname << ": cannot create pass: " << PI->getPassName() << "\n"; + return true; + } + std::string Banner = std::string("After ") + std::string(P->getPassName()); + PM.add(P); + TPC.printAndVerify(Banner); + + return false; +} + +bool llvm::RelocAddressLess(RelocationRef a, RelocationRef b) { + return a.getOffset() < b.getOffset(); +} + +namespace { +class SourcePrinter { +protected: + DILineInfo OldLineInfo; + const ObjectFile *Obj; + std::unique_ptr Symbolizer; + // File name to file contents of source + std::unordered_map> SourceCache; + // Mark the line endings of the cached source + std::unordered_map> LineCache; + +private: + bool cacheSource(std::string File); + +public: + virtual ~SourcePrinter() {} + SourcePrinter() : Obj(nullptr), Symbolizer(nullptr) {} + SourcePrinter(const ObjectFile *Obj, StringRef DefaultArch) : Obj(Obj) { + symbolize::LLVMSymbolizer::Options SymbolizerOpts( + DILineInfoSpecifier::FunctionNameKind::None, true, false, false, + DefaultArch); + Symbolizer.reset(new symbolize::LLVMSymbolizer(SymbolizerOpts)); + } + virtual void printSourceLine(raw_ostream &OS, uint64_t Address, + StringRef Delimiter = "; "); +}; + +bool SourcePrinter::cacheSource(std::string File) { + auto BufferOrError = MemoryBuffer::getFile(File); + if (!BufferOrError) + return false; + // Chomp the file to get lines + size_t BufferSize = (*BufferOrError)->getBufferSize(); + const char *BufferStart = (*BufferOrError)->getBufferStart(); + for (const char *Start = BufferStart, *End = BufferStart; + End < BufferStart + BufferSize; End++) + if (*End == '\n' || End == BufferStart + BufferSize - 1 || + (*End == '\r' && *(End + 1) == '\n')) { + LineCache[File].push_back(StringRef(Start, End - Start)); + if (*End == '\r') + End++; + Start = End + 1; + } + SourceCache[File] = std::move(*BufferOrError); + return true; +} + +void SourcePrinter::printSourceLine(raw_ostream &OS, uint64_t Address, + StringRef Delimiter) { + if (!Symbolizer) + return; + DILineInfo LineInfo = DILineInfo(); + auto ExpectecLineInfo = + Symbolizer->symbolizeCode(Obj->getFileName(), Address); + if (!ExpectecLineInfo) + consumeError(ExpectecLineInfo.takeError()); + else + LineInfo = *ExpectecLineInfo; + + if ((LineInfo.FileName == "") || OldLineInfo.Line == LineInfo.Line || + LineInfo.Line == 0) + return; + + if (PrintLines) + OS << Delimiter << LineInfo.FileName << ":" << LineInfo.Line << "\n"; + if (PrintSource) { + if (SourceCache.find(LineInfo.FileName) == SourceCache.end()) + if (!cacheSource(LineInfo.FileName)) + return; + auto FileBuffer = SourceCache.find(LineInfo.FileName); + if (FileBuffer != SourceCache.end()) { + auto LineBuffer = LineCache.find(LineInfo.FileName); + if (LineBuffer != LineCache.end()) { + if (LineInfo.Line > LineBuffer->second.size()) + return; + // Vector begins at 0, line numbers are non-zero + OS << Delimiter << LineBuffer->second[LineInfo.Line - 1].ltrim() + << "\n"; + } + } + } + OldLineInfo = LineInfo; +} + +static bool isArmElf(const ObjectFile *Obj) { + return (Obj->isELF() && + (Obj->getArch() == Triple::aarch64 || + Obj->getArch() == Triple::aarch64_be || + Obj->getArch() == Triple::arm || Obj->getArch() == Triple::armeb || + Obj->getArch() == Triple::thumb || + Obj->getArch() == Triple::thumbeb)); +} + +class PrettyPrinter { +public: + virtual ~PrettyPrinter() {} + virtual void printInst(MCInstPrinter &IP, const MCInst *MI, + ArrayRef Bytes, uint64_t Address, + raw_ostream &OS, StringRef Annot, + MCSubtargetInfo const &STI, SourcePrinter *SP) { + if (SP && (PrintSource || PrintLines)) + SP->printSourceLine(OS, Address); + if (!NoLeadingAddr) + OS << format("%8" PRIx64 ":", Address); + if (!NoShowRawInsn) { + OS << "\t"; + dumpBytes(Bytes, OS); + } + if (MI) + IP.printInst(MI, OS, "", STI); + else + OS << " "; + } +}; +PrettyPrinter PrettyPrinterInst; +class HexagonPrettyPrinter : public PrettyPrinter { +public: + void printLead(ArrayRef Bytes, uint64_t Address, raw_ostream &OS) { + uint32_t opcode = + (Bytes[3] << 24) | (Bytes[2] << 16) | (Bytes[1] << 8) | Bytes[0]; + if (!NoLeadingAddr) + OS << format("%8" PRIx64 ":", Address); + if (!NoShowRawInsn) { + OS << "\t"; + dumpBytes(Bytes.slice(0, 4), OS); + OS << format("%08" PRIx32, opcode); + } + } + void printInst(MCInstPrinter &IP, const MCInst *MI, ArrayRef Bytes, + uint64_t Address, raw_ostream &OS, StringRef Annot, + MCSubtargetInfo const &STI, SourcePrinter *SP) override { + if (SP && (PrintSource || PrintLines)) + SP->printSourceLine(OS, Address, ""); + if (!MI) { + printLead(Bytes, Address, OS); + OS << " "; + return; + } + std::string Buffer; + { + raw_string_ostream TempStream(Buffer); + IP.printInst(MI, TempStream, "", STI); + } + StringRef Contents(Buffer); + // Split off bundle attributes + auto PacketBundle = Contents.rsplit('\n'); + // Split off first instruction from the rest + auto HeadTail = PacketBundle.first.split('\n'); + auto Preamble = " { "; + auto Separator = ""; + while (!HeadTail.first.empty()) { + OS << Separator; + Separator = "\n"; + if (SP && (PrintSource || PrintLines)) + SP->printSourceLine(OS, Address, ""); + printLead(Bytes, Address, OS); + OS << Preamble; + Preamble = " "; + StringRef Inst; + auto Duplex = HeadTail.first.split('\v'); + if (!Duplex.second.empty()) { + OS << Duplex.first; + OS << "; "; + Inst = Duplex.second; + } else + Inst = HeadTail.first; + OS << Inst; + Bytes = Bytes.slice(4); + Address += 4; + HeadTail = HeadTail.second.split('\n'); + } + OS << " } " << PacketBundle.second; + } +}; +HexagonPrettyPrinter HexagonPrettyPrinterInst; + +class AMDGCNPrettyPrinter : public PrettyPrinter { +public: + void printInst(MCInstPrinter &IP, const MCInst *MI, ArrayRef Bytes, + uint64_t Address, raw_ostream &OS, StringRef Annot, + MCSubtargetInfo const &STI, SourcePrinter *SP) override { + if (SP && (PrintSource || PrintLines)) + SP->printSourceLine(OS, Address); + + if (!MI) { + OS << " "; + return; + } + + SmallString<40> InstStr; + raw_svector_ostream IS(InstStr); + + IP.printInst(MI, IS, "", STI); + + OS << left_justify(IS.str(), 60) << format("// %012" PRIX64 ": ", Address); + typedef support::ulittle32_t U32; + for (auto D : makeArrayRef(reinterpret_cast(Bytes.data()), + Bytes.size() / sizeof(U32))) + // D should be explicitly casted to uint32_t here as it is passed + // by format to snprintf as vararg. + OS << format("%08" PRIX32 " ", static_cast(D)); + + if (!Annot.empty()) + OS << "// " << Annot; + } +}; +AMDGCNPrettyPrinter AMDGCNPrettyPrinterInst; + +class BPFPrettyPrinter : public PrettyPrinter { +public: + void printInst(MCInstPrinter &IP, const MCInst *MI, ArrayRef Bytes, + uint64_t Address, raw_ostream &OS, StringRef Annot, + MCSubtargetInfo const &STI, SourcePrinter *SP) override { + if (SP && (PrintSource || PrintLines)) + SP->printSourceLine(OS, Address); + if (!NoLeadingAddr) + OS << format("%8" PRId64 ":", Address / 8); + if (!NoShowRawInsn) { + OS << "\t"; + dumpBytes(Bytes, OS); + } + if (MI) + IP.printInst(MI, OS, "", STI); + else + OS << " "; + } +}; +BPFPrettyPrinter BPFPrettyPrinterInst; + +PrettyPrinter &selectPrettyPrinter(Triple const &Triple) { + switch (Triple.getArch()) { + default: + return PrettyPrinterInst; + case Triple::hexagon: + return HexagonPrettyPrinterInst; + case Triple::amdgcn: + return AMDGCNPrettyPrinterInst; + case Triple::bpfel: + case Triple::bpfeb: + return BPFPrettyPrinterInst; + } +} +} // namespace + +template +static std::error_code getRelocationValueString(const ELFObjectFile *Obj, + const RelocationRef &RelRef, + SmallVectorImpl &Result) { + DataRefImpl Rel = RelRef.getRawDataRefImpl(); + + typedef typename ELFObjectFile::Elf_Sym Elf_Sym; + typedef typename ELFObjectFile::Elf_Shdr Elf_Shdr; + typedef typename ELFObjectFile::Elf_Rela Elf_Rela; + + const ELFFile &EF = *Obj->getELFFile(); + + auto SecOrErr = EF.getSection(Rel.d.a); + if (!SecOrErr) + return errorToErrorCode(SecOrErr.takeError()); + const Elf_Shdr *Sec = *SecOrErr; + auto SymTabOrErr = EF.getSection(Sec->sh_link); + if (!SymTabOrErr) + return errorToErrorCode(SymTabOrErr.takeError()); + const Elf_Shdr *SymTab = *SymTabOrErr; + assert(SymTab->sh_type == ELF::SHT_SYMTAB || + SymTab->sh_type == ELF::SHT_DYNSYM); + auto StrTabSec = EF.getSection(SymTab->sh_link); + if (!StrTabSec) + return errorToErrorCode(StrTabSec.takeError()); + auto StrTabOrErr = EF.getStringTable(*StrTabSec); + if (!StrTabOrErr) + return errorToErrorCode(StrTabOrErr.takeError()); + StringRef StrTab = *StrTabOrErr; + uint8_t type = RelRef.getType(); + StringRef res; + int64_t addend = 0; + switch (Sec->sh_type) { + default: + return object_error::parse_failed; + case ELF::SHT_REL: { + // TODO: Read implicit addend from section data. + break; + } + case ELF::SHT_RELA: { + const Elf_Rela *ERela = Obj->getRela(Rel); + addend = ERela->r_addend; + break; + } + } + symbol_iterator SI = RelRef.getSymbol(); + const Elf_Sym *symb = Obj->getSymbol(SI->getRawDataRefImpl()); + StringRef Target; + if (symb->getType() == ELF::STT_SECTION) { + Expected SymSI = SI->getSection(); + if (!SymSI) + return errorToErrorCode(SymSI.takeError()); + const Elf_Shdr *SymSec = Obj->getSection((*SymSI)->getRawDataRefImpl()); + auto SecName = EF.getSectionName(SymSec); + if (!SecName) + return errorToErrorCode(SecName.takeError()); + Target = *SecName; + } else { + Expected SymName = symb->getName(StrTab); + if (!SymName) + return errorToErrorCode(SymName.takeError()); + Target = *SymName; + } + switch (EF.getHeader()->e_machine) { + case ELF::EM_X86_64: + switch (type) { + case ELF::R_X86_64_PC8: + case ELF::R_X86_64_PC16: + case ELF::R_X86_64_PC32: { + std::string fmtbuf; + raw_string_ostream fmt(fmtbuf); + fmt << Target << (addend < 0 ? "" : "+") << addend << "-P"; + fmt.flush(); + Result.append(fmtbuf.begin(), fmtbuf.end()); + } break; + case ELF::R_X86_64_8: + case ELF::R_X86_64_16: + case ELF::R_X86_64_32: + case ELF::R_X86_64_32S: + case ELF::R_X86_64_64: { + std::string fmtbuf; + raw_string_ostream fmt(fmtbuf); + fmt << Target << (addend < 0 ? "" : "+") << addend; + fmt.flush(); + Result.append(fmtbuf.begin(), fmtbuf.end()); + } break; + default: + res = "Unknown"; + } + break; + case ELF::EM_LANAI: + case ELF::EM_AVR: + case ELF::EM_AARCH64: { + std::string fmtbuf; + raw_string_ostream fmt(fmtbuf); + fmt << Target; + if (addend != 0) + fmt << (addend < 0 ? "" : "+") << addend; + fmt.flush(); + Result.append(fmtbuf.begin(), fmtbuf.end()); + break; + } + case ELF::EM_386: + case ELF::EM_IAMCU: + case ELF::EM_ARM: + case ELF::EM_HEXAGON: + case ELF::EM_MIPS: + case ELF::EM_BPF: + case ELF::EM_RISCV: + res = Target; + break; + default: + res = "Unknown"; + } + if (Result.empty()) + Result.append(res.begin(), res.end()); + return std::error_code(); +} + +static uint8_t getElfSymbolType(const ObjectFile *Obj, const SymbolRef &Sym) { + assert(Obj->isELF()); + if (auto *Elf32LEObj = dyn_cast(Obj)) + return Elf32LEObj->getSymbol(Sym.getRawDataRefImpl())->getType(); + if (auto *Elf64LEObj = dyn_cast(Obj)) + return Elf64LEObj->getSymbol(Sym.getRawDataRefImpl())->getType(); + if (auto *Elf32BEObj = dyn_cast(Obj)) + return Elf32BEObj->getSymbol(Sym.getRawDataRefImpl())->getType(); + if (auto *Elf64BEObj = cast(Obj)) + return Elf64BEObj->getSymbol(Sym.getRawDataRefImpl())->getType(); + llvm_unreachable("Unsupported binary format"); + // Keep the code analyzer happy + return ELF::STT_NOTYPE; +} + +template +static void +addDynamicElfSymbols(const ELFObjectFile *Obj, + std::map &AllSymbols) { + for (auto Symbol : Obj->getDynamicSymbolIterators()) { + uint8_t SymbolType = Symbol.getELFType(); + if (SymbolType != ELF::STT_FUNC || Symbol.getSize() == 0) + continue; + + Expected AddressOrErr = Symbol.getAddress(); + if (!AddressOrErr) + report_error(Obj->getFileName(), AddressOrErr.takeError()); + uint64_t Address = *AddressOrErr; + + Expected Name = Symbol.getName(); + if (!Name) + report_error(Obj->getFileName(), Name.takeError()); + if (Name->empty()) + continue; + + Expected SectionOrErr = Symbol.getSection(); + if (!SectionOrErr) + report_error(Obj->getFileName(), SectionOrErr.takeError()); + section_iterator SecI = *SectionOrErr; + if (SecI == Obj->section_end()) + continue; + + AllSymbols[*SecI].emplace_back(Address, *Name, SymbolType); + } +} + +static void +addDynamicElfSymbols(const ObjectFile *Obj, + std::map &AllSymbols) { + assert(Obj->isELF()); + if (auto *Elf32LEObj = dyn_cast(Obj)) + addDynamicElfSymbols(Elf32LEObj, AllSymbols); + else if (auto *Elf64LEObj = dyn_cast(Obj)) + addDynamicElfSymbols(Elf64LEObj, AllSymbols); + else if (auto *Elf32BEObj = dyn_cast(Obj)) + addDynamicElfSymbols(Elf32BEObj, AllSymbols); + else if (auto *Elf64BEObj = cast(Obj)) + addDynamicElfSymbols(Elf64BEObj, AllSymbols); + else + llvm_unreachable("Unsupported binary format"); +} + +/* + A list of symbol entries corresponding to CRT functions added by + the linker while creating an ELF executable. It is not necessary to + disassemble and translate these functions. +*/ + +static std::set ELFCRTSymbols = { + "deregister_tm_clones", + "__do_global_dtors_aux", + "__do_global_dtors_aux_fini_array_entry", + "_fini", + "frame_dummy", + "__frame_dummy_init_array_entry", + "_init", + "__init_array_end", + "__init_array_start", + "__libc_csu_fini", + "__libc_csu_init", + "register_tm_clones", + "_start"}; + +/* + A list of symbol entries corresponding to CRT functions added by + the linker while creating an MachO executable. It is not necessary + to disassemble and translate these functions. +*/ + +static std::set MachOCRTSymbols = {"__mh_execute_header", + "dyld_stub_binder", "__text", + "__stubs", "__stub_helper"}; + +/* + A list of sections whose contents are to be disassembled as code +*/ + +static std::set ELFSectionsToDisassemble = {".text"}; +static std::set MachOSectionsToDisassemble = {}; + +/* TODO : If it is a C++ binary object symbol, look at the + signature of the symbol to deduce the return value and return + type. If the symbol does not include the function signature, + just create a function that takes no arguments */ +/* A non vararg function type with no arguments */ +/* TODO: Figure out the symbol linkage type from the symbol + table. For now assuming global linkage +*/ + +static bool isAFunctionSymbol(const ObjectFile *Obj, + SectionSymbolInfo &Symbol) { + if (Obj->isELF()) { + return (std::get<2>(Symbol) == ELF::STT_FUNC); + } + if (Obj->isMachO()) { + // If Symbol is not in the MachOCRTSymbol list return true indicating that + // this is a symbol of a function we are interested in disassembling and + // raising. + return (MachOCRTSymbols.find(std::get<1>(Symbol)) == MachOCRTSymbols.end()); + } + return false; +} + +static bool disasmSection(const ObjectFile *Obj, StringRef §ionName) { + if (Obj->isELF()) { + return (ELFSectionsToDisassemble.find(sectionName) != + ELFSectionsToDisassemble.end()); + } + if (Obj->isMachO()) { + // Already picking up the text section + return true; + } + return false; +} + +static void DisassembleObject(const ObjectFile *Obj, bool InlineRelocs) { + if (StartAddress > StopAddress) + error("Start address should be less than stop address"); + + const Target *TheTarget = getTarget(Obj); + + // Package up features to be passed to target/subtarget + SubtargetFeatures Features = Obj->getFeatures(); + if (MAttrs.size()) { + for (unsigned i = 0; i != MAttrs.size(); ++i) + Features.AddFeature(MAttrs[i]); + } + + std::unique_ptr MRI( + TheTarget->createMCRegInfo(TripleName)); + if (!MRI) + report_error(Obj->getFileName(), + "no register info for target " + TripleName); + + // Set up disassembler. + std::unique_ptr AsmInfo( + TheTarget->createMCAsmInfo(*MRI, TripleName)); + if (!AsmInfo) + report_error(Obj->getFileName(), + "no assembly info for target " + TripleName); + std::unique_ptr STI( + TheTarget->createMCSubtargetInfo(TripleName, MCPU, Features.getString())); + if (!STI) + report_error(Obj->getFileName(), + "no subtarget info for target " + TripleName); + std::unique_ptr MII(TheTarget->createMCInstrInfo()); + if (!MII) + report_error(Obj->getFileName(), + "no instruction info for target " + TripleName); + MCObjectFileInfo MOFI; + MCContext Ctx(AsmInfo.get(), MRI.get(), &MOFI); + // FIXME: for now initialize MCObjectFileInfo with default values + MOFI.InitMCObjectFileInfo(Triple(TripleName), false, Ctx); + + std::unique_ptr DisAsm( + TheTarget->createMCDisassembler(*STI, Ctx)); + if (!DisAsm) + report_error(Obj->getFileName(), + "no disassembler for target " + TripleName); + + std::unique_ptr MIA( + TheTarget->createMCInstrAnalysis(MII.get())); + + int AsmPrinterVariant = AsmInfo->getAssemblerDialect(); + std::unique_ptr IP(TheTarget->createMCInstPrinter( + Triple(TripleName), AsmPrinterVariant, *AsmInfo, *MII, *MRI)); + if (!IP) + report_error(Obj->getFileName(), + "no instruction printer for target " + TripleName); + IP->setPrintImmHex(PrintImmHex); + PrettyPrinter &PIP = selectPrettyPrinter(Triple(TripleName)); + + SourcePrinter SP(Obj, TheTarget->getName()); + + LLVMContext llvmCtx; + std::unique_ptr Target( + TheTarget->createTargetMachine(TripleName, MCPU, Features.getString(), + TargetOptions(), /* RelocModel */ None)); + assert(Target && "Could not allocate target machine!"); + + // LLVMTargetMachine &llvmTgtMach = static_cast(*Target); + MachineModuleInfo *machineModuleInfo = new MachineModuleInfo(Target.get()); + /* New Module instance with file name */ + Module module(Obj->getFileName(), llvmCtx); + /* Set datalayout of the module to be the same as LLVMTargetMachine */ + module.setDataLayout(Target->createDataLayout()); + machineModuleInfo->doInitialization(module); + ModuleRaiser *moduleRaiser = + new ModuleRaiser(module, Target.get(), machineModuleInfo, MIA.get(), + MII.get(), Obj, DisAsm.get()); + + if (!moduleRaiser->isSupportedArch()) + return; + + // Create a mapping, RelocSecs = SectionRelocMap[S], where sections + // in RelocSecs contain the relocations for section S. + std::error_code EC; + std::map> SectionRelocMap; + for (const SectionRef &Section : ToolSectionFilter(*Obj)) { + section_iterator Sec2 = Section.getRelocatedSection(); + if (Sec2 != Obj->section_end()) + SectionRelocMap[*Sec2].push_back(Section); + } + + // Create a mapping from virtual address to symbol name. This is used to + // pretty print the symbols while disassembling. + std::map AllSymbols; + for (const SymbolRef &Symbol : Obj->symbols()) { + Expected AddressOrErr = Symbol.getAddress(); + if (!AddressOrErr) + report_error(Obj->getFileName(), AddressOrErr.takeError()); + uint64_t Address = *AddressOrErr; + + Expected Name = Symbol.getName(); + if (!Name) + report_error(Obj->getFileName(), Name.takeError()); + if (Name->empty()) + continue; + + Expected SectionOrErr = Symbol.getSection(); + if (!SectionOrErr) + report_error(Obj->getFileName(), SectionOrErr.takeError()); + section_iterator SecI = *SectionOrErr; + if (SecI == Obj->section_end()) + continue; + + uint8_t SymbolType = ELF::STT_NOTYPE; + if (Obj->isELF()) + SymbolType = getElfSymbolType(Obj, Symbol); + + AllSymbols[*SecI].emplace_back(Address, *Name, SymbolType); + } + if (AllSymbols.empty() && Obj->isELF()) + addDynamicElfSymbols(Obj, AllSymbols); + + // Create a mapping from virtual address to section. + std::vector> SectionAddresses; + for (SectionRef Sec : Obj->sections()) + SectionAddresses.emplace_back(Sec.getAddress(), Sec); + array_pod_sort(SectionAddresses.begin(), SectionAddresses.end()); + + // Linked executables (.exe and .dll files) typically don't include a real + // symbol table but they might contain an export table. + if (const auto *COFFObj = dyn_cast(Obj)) { + for (const auto &ExportEntry : COFFObj->export_directories()) { + StringRef Name; + error(ExportEntry.getSymbolName(Name)); + if (Name.empty()) + continue; + + uint32_t RVA; + error(ExportEntry.getExportRVA(RVA)); + + uint64_t VA = COFFObj->getImageBase() + RVA; + auto Sec = std::upper_bound( + SectionAddresses.begin(), SectionAddresses.end(), VA, + [](uint64_t LHS, const std::pair &RHS) { + return LHS < RHS.first; + }); + if (Sec != SectionAddresses.begin()) + --Sec; + else + Sec = SectionAddresses.end(); + + if (Sec != SectionAddresses.end()) + AllSymbols[Sec->second].emplace_back(VA, Name, ELF::STT_NOTYPE); + } + } + + // Sort all the symbols, this allows us to use a simple binary search to find + // a symbol near an address. + for (std::pair &SecSyms : AllSymbols) + array_pod_sort(SecSyms.second.begin(), SecSyms.second.end()); + + for (const SectionRef &Section : ToolSectionFilter(*Obj)) { + if ((!Section.isText() || Section.isVirtual())) + continue; + + StringRef SectionName; + Section.getName(SectionName); + + if (SectionName.compare(".text") != 0) { + continue; + } + uint64_t SectionAddr = Section.getAddress(); + uint64_t SectSize = Section.getSize(); + if (!SectSize) + continue; + + // Get the list of all the symbols in this section. + SectionSymbolsTy &Symbols = AllSymbols[Section]; + std::vector DataMappingSymsAddr; + std::vector TextMappingSymsAddr; + if (isArmElf(Obj)) { + for (const auto &Symb : Symbols) { + uint64_t Address = std::get<0>(Symb); + StringRef Name = std::get<1>(Symb); + if (Name.startswith("$d")) + DataMappingSymsAddr.push_back(Address - SectionAddr); + if (Name.startswith("$x")) + TextMappingSymsAddr.push_back(Address - SectionAddr); + if (Name.startswith("$a")) + TextMappingSymsAddr.push_back(Address - SectionAddr); + if (Name.startswith("$t")) + TextMappingSymsAddr.push_back(Address - SectionAddr); + } + } + + std::sort(DataMappingSymsAddr.begin(), DataMappingSymsAddr.end()); + std::sort(TextMappingSymsAddr.begin(), TextMappingSymsAddr.end()); + + if (Obj->isELF() && Obj->getArch() == Triple::amdgcn) { + // AMDGPU disassembler uses symbolizer for printing labels + std::unique_ptr RelInfo( + TheTarget->createMCRelocationInfo(TripleName, Ctx)); + if (RelInfo) { + std::unique_ptr Symbolizer(TheTarget->createMCSymbolizer( + TripleName, nullptr, nullptr, &Symbols, &Ctx, std::move(RelInfo))); + DisAsm->setSymbolizer(std::move(Symbolizer)); + } + } + + // Make a list of all the relocations for this section. + std::vector Rels; + if (InlineRelocs) { + for (const SectionRef &RelocSec : SectionRelocMap[Section]) { + for (const RelocationRef &Reloc : RelocSec.relocations()) { + Rels.push_back(Reloc); + } + } + } + + // Sort relocations by address. + std::sort(Rels.begin(), Rels.end(), RelocAddressLess); + + StringRef SegmentName = ""; + if (const MachOObjectFile *MachO = dyn_cast(Obj)) { + DataRefImpl DR = Section.getRawDataRefImpl(); + SegmentName = MachO->getSectionFinalSegmentName(DR); + } + StringRef name; + error(Section.getName(name)); + if (!disasmSection(Obj, name)) { + continue; + } + + bool PrintAll = + (cl::getRegisteredOptions()["print-after-all"]->getNumOccurrences() > + 0); + + if (PrintAll) { + if ((SectionAddr <= StopAddress) && + (SectionAddr + SectSize) >= StartAddress) { + outs() << "Disassembling section "; + if (!SegmentName.empty()) + outs() << SegmentName << ","; + outs() << name << "\n"; + } + } + + // If the section has no symbol at the start, just insert a dummy one. + if (Symbols.empty() || std::get<0>(Symbols[0]) != 0) { + Symbols.insert( + Symbols.begin(), + std::make_tuple(SectionAddr, name, + Section.isText() ? ELF::STT_FUNC : ELF::STT_OBJECT)); + } + + SmallString<40> Comments; + raw_svector_ostream CommentStream(Comments); + + StringRef BytesStr; + error(Section.getContents(BytesStr)); + ArrayRef Bytes(reinterpret_cast(BytesStr.data()), + BytesStr.size()); + + uint64_t Size; + uint64_t Index; + + // Build a set of function symbol names to operate on, + // if specified on the command-line. + std::set filterFunctionSet; + for (unsigned i = 0; i < FilterFunctions.size(); ++i) { + filterFunctionSet.insert(FilterFunctions[i]); + } + + // Build a map of relocations (if they exist in the binary) of text + // section whose instructions are being raised. + moduleRaiser->collectTextSectionRelocs(Section); + + // Set used to record all branch targets of a function. + std::set branchTargetSet; + MachineFunctionRaiser *curMFRaiser = nullptr; + + // Disassemble symbol by symbol. + for (unsigned si = 0, se = Symbols.size(); si != se; ++si) { + uint64_t Start = std::get<0>(Symbols[si]) - SectionAddr; + // The end is either the section end or the beginning of the next + // symbol. + uint64_t End = (si == se - 1) + ? SectSize + : std::get<0>(Symbols[si + 1]) - SectionAddr; + // Don't try to disassemble beyond the end of section contents. + if (End > SectSize) + End = SectSize; + // If this symbol has the same address as the next symbol, then skip it. + if (Start >= End) + continue; + + // Check if we need to skip symbol + // Skip if the symbol's data is not between StartAddress and StopAddress + if (End + SectionAddr < StartAddress || + Start + SectionAddr > StopAddress) { + continue; + } + + // Stop disassembly at the stop address specified + if (End + SectionAddr > StopAddress) + End = StopAddress - SectionAddr; + + if (Obj->isELF() && Obj->getArch() == Triple::amdgcn) { + // make size 4 bytes folded + End = Start + ((End - Start) & ~0x3ull); + if (std::get<2>(Symbols[si]) == ELF::STT_AMDGPU_HSA_KERNEL) { + // skip amd_kernel_code_t at the begining of kernel symbol (256 bytes) + Start += 256; + } + if (si == se - 1 || + std::get<2>(Symbols[si + 1]) == ELF::STT_AMDGPU_HSA_KERNEL) { + // cut trailing zeroes at the end of kernel + // cut up to 256 bytes + const uint64_t EndAlign = 256; + const auto Limit = End - (std::min)(EndAlign, End - Start); + while (End > Limit && *reinterpret_cast( + &Bytes[End - 4]) == 0) + End -= 4; + } + } + +#ifndef NDEBUG + raw_ostream &DebugOut = DebugFlag ? dbgs() : nulls(); +#else + raw_ostream &DebugOut = nulls(); +#endif + + if (isAFunctionSymbol(Obj, Symbols[si])) { + if (!((FilterFunctions.getNumOccurrences() == 0) || + (filterFunctionSet.find(std::get<1>(Symbols[si])) != + filterFunctionSet.end()))) { + // This symbol is part of the filter symbols specified. + continue; + } + // If Symbol is in the ELFCRTSymbol list return this is a symbol of a + // function we are not interested in disassembling and raising. + if (ELFCRTSymbols.find(std::get<1>(Symbols[si])) != + ELFCRTSymbols.end()) { + continue; + } + + // Note that since LLVM infrastructure was built to be used to build a + // conventional compiler pipeline, MachineFunction is built well after + // Function object was created and populated fully. Hence, creation of + // a Function object is necessary to build MachineFunction. + // However, in a raiser, we are conceptually walking the traditional + // compiler pipeline backwards. So we build MachineFunction from + // the binary before building Function object. Given the dependency, + // build a place holder Function object to allow for building the + // MachineFunction object. + // This Function object is NOT populated when raising MachineFunction + // abstraction of the binary function. Instead, a new Function is + // created using the LLVMContext and name of this Function object. + FunctionType *FTy = FunctionType::get(Type::getVoidTy(llvmCtx), false); + StringRef FunctionName(std::get<1>(Symbols[si])); + // Strip leading underscore if the binary is MachO + if (Obj->isMachO()) { + FunctionName.consume_front("_"); + } + Function *Func = Function::Create(FTy, GlobalValue::ExternalLinkage, + FunctionName, &module); + // While PassManager is running FunctionPasses, it will check if current + // Function is empty or not. If the Function is empty, it will be + // skipped. So add an empty BasicBlock to Functions at here to guarantee + // the corresponding MachineFunction can be run. + // TODO: This BasicBlock should be removed when add real BasicBlocks. + BasicBlock::Create(Func->getContext(), "Useless", Func); + + // New function symbol encountered. Record all targets collected to + // current MachineFunctionRaiser before we start parsing the new + // function bytes. + curMFRaiser = moduleRaiser->getCurrentMachineFunctionRaiser(); + for (auto target : branchTargetSet) { + assert(curMFRaiser != nullptr && + "Encountered unintialized MachineFunction raiser object"); + curMFRaiser->getMCInstRaiser()->addTarget(target); + } + + // Clear the set used to record all branch targets of this function. + branchTargetSet.clear(); + // Create a new MachineFunction raiser + curMFRaiser = moduleRaiser->CreateAndAddMachineFunctionRaiser( + Func, moduleRaiser, Start, End); + // Flag to indicate all instructions of the current function were + // successfully decoded. + // TODO: As of now, we will only raise functions with all instructions + // decoded. + // bool allInstructionsDecoded = true; + if (PrintAll) + outs() << "\nFunction " << std::get<1>(Symbols[si]) << ":\n"; + } else { + // Continue using to the most recent MachineFunctionRaiser + // Get current MachineFunctionRaiser + curMFRaiser = moduleRaiser->getCurrentMachineFunctionRaiser(); + // assert(curMFRaiser != nullptr && "Current Machine Function Raiser not + // initialized"); + if (curMFRaiser == nullptr) { + // At this point in the instruction stream, we do not have a function + // symbol to which the bytes being parsed can be made part of. So skip + // parsing the bytes of this symbol. + continue; + } + + // Adjust function end to represent the addition of the content of the + // current symbol. This represents a situation where we have discovered + // bytes (most likely data bytes) that belong to the most recent + // function being parsed. + MCInstRaiser *mcInstRaiser = curMFRaiser->getMCInstRaiser(); + if (mcInstRaiser->getFuncEnd() < End) { + assert(mcInstRaiser->adjustFuncEnd(End) && + "Unable to adjust function end value"); + } + } + + // Get the associated MCInstRaiser + MCInstRaiser *mcInstRaiser = curMFRaiser->getMCInstRaiser(); + + // Start new basic block at the symbol. + branchTargetSet.insert(Start); + + for (Index = Start; Index < End; Index += Size) { + MCInst Inst; + + if (Index + SectionAddr < StartAddress || + Index + SectionAddr > StopAddress) { + // skip byte by byte till StartAddress is reached + Size = 1; + continue; + } + + // AArch64 ELF binaries can interleave data and text in the + // same section. We rely on the markers introduced to + // understand what we need to dump. If the data marker is within a + // function, it is denoted as a word/short etc + if (isArmElf(Obj) && std::get<2>(Symbols[si]) != ELF::STT_OBJECT) { + uint64_t Stride = 0; + + auto DAI = std::lower_bound(DataMappingSymsAddr.begin(), + DataMappingSymsAddr.end(), Index); + if (DAI != DataMappingSymsAddr.end() && *DAI == Index) { + // Switch to data. + while (Index < End) { + if (Index + 4 <= End) { + Stride = 4; + uint32_t Data = 0; + if (Obj->isLittleEndian()) { + const auto Word = + reinterpret_cast( + Bytes.data() + Index); + Data = *Word; + } else { + const auto Word = reinterpret_cast( + Bytes.data() + Index); + Data = *Word; + } + mcInstRaiser->addMCInstOrData(Index, Data); + } else if (Index + 2 <= End) { + Stride = 2; + uint16_t Data = 0; + if (Obj->isLittleEndian()) { + const auto Short = + reinterpret_cast( + Bytes.data() + Index); + Data = *Short; + } else { + const auto Short = + reinterpret_cast(Bytes.data() + + Index); + Data = *Short; + } + mcInstRaiser->addMCInstOrData(Index, Data); + } else { + Stride = 1; + mcInstRaiser->addMCInstOrData(Index, Bytes.slice(Index, 1)[0]); + } + Index += Stride; + + auto TAI = std::lower_bound(TextMappingSymsAddr.begin(), + TextMappingSymsAddr.end(), Index); + if (TAI != TextMappingSymsAddr.end() && *TAI == Index) + break; + } + } + } + + // If there is a data symbol inside an ELF text section and we are + // only disassembling text, we are in a situation where we must print + // the data and not disassemble it. + // TODO : Get rid of the following code in the if-block. + if (Obj->isELF() && std::get<2>(Symbols[si]) == ELF::STT_OBJECT && + Section.isText()) { + // parse data up to 8 bytes at a time + uint8_t AsciiData[9] = {'\0'}; + uint8_t Byte; + int NumBytes = 0; + + for (Index = Start; Index < End; Index += 1) { + if (((SectionAddr + Index) < StartAddress) || + ((SectionAddr + Index) > StopAddress)) + continue; + if (NumBytes == 0) { + outs() << format("%8" PRIx64 ":", SectionAddr + Index); + outs() << "\t"; + } + Byte = Bytes.slice(Index)[0]; + outs() << format(" %02x", Byte); + AsciiData[NumBytes] = isprint(Byte) ? Byte : '.'; + + uint8_t IndentOffset = 0; + NumBytes++; + if (Index == End - 1 || NumBytes > 8) { + // Indent the space for less than 8 bytes data. + // 2 spaces for byte and one for space between bytes + IndentOffset = 3 * (8 - NumBytes); + for (int Excess = 8 - NumBytes; Excess < 8; Excess++) + AsciiData[Excess] = '\0'; + NumBytes = 8; + } + if (NumBytes == 8) { + AsciiData[8] = '\0'; + outs() << std::string(IndentOffset, ' ') << " "; + outs() << reinterpret_cast(AsciiData); + outs() << '\n'; + NumBytes = 0; + } + } + } + + if (Index >= End) + break; + + // Disassemble a real instruction or a data + bool Disassembled = DisAsm->getInstruction( + Inst, Size, Bytes.slice(Index), SectionAddr + Index, DebugOut, + CommentStream); + if (Size == 0) + Size = 1; + + if (!Disassembled) { + errs() << "**** Warning: Failed to decode instruction\n"; + PIP.printInst(*IP, Disassembled ? &Inst : nullptr, + Bytes.slice(Index, Size), SectionAddr + Index, outs(), + "", *STI, &SP); + outs() << CommentStream.str(); + Comments.clear(); + errs() << "\n"; + } + + // allInstructionsDecoded &= Disassembled; + // Add MCInst to the list if all instructions were decoded + // successfully till now. Else, do not bother adding since no attemt + // will be made to raise this function. + if (Disassembled) { + mcInstRaiser->addMCInstOrData(Index, Inst); + + // Find branch target and record it. Call targets are not + // recorded as they are not needed to build per-function CFG. + if (MIA && MIA->isBranch(Inst)) { + uint64_t Target; + if (MIA->evaluateBranch(Inst, Index, Size, Target)) { + // In a relocatable object, the target's section must reside in + // the same section as the call instruction or it is accessed + // through a relocation. + // + // In a non-relocatable object, the target may be in any + // section. + // + // N.B. We don't walk the relocations in the relocatable case + // yet. + if (!Obj->isRelocatableObject()) { + auto SectionAddress = std::upper_bound( + SectionAddresses.begin(), SectionAddresses.end(), Target, + [](uint64_t LHS, + const std::pair &RHS) { + return LHS < RHS.first; + }); + if (SectionAddress != SectionAddresses.begin()) { + --SectionAddress; + } + } + // Add the index Target to target indices set. + branchTargetSet.insert(Target); + } + + // Mark the next instruction as a target. + uint64_t fallThruIndex = Index + Size; + branchTargetSet.insert(fallThruIndex); + } + } + } + filterFunctionSet.erase(std::get<1>(Symbols[si])); + } + + // Record all targets of the last function parsed + curMFRaiser = moduleRaiser->getCurrentMachineFunctionRaiser(); + for (auto target : branchTargetSet) + curMFRaiser->getMCInstRaiser()->addTarget(target); + + moduleRaiser->runMachineFunctionPasses(); + + if (filterFunctionSet.size() > 0) { + errs() << "***** WARNING: The following specified symbol(s) are not " + "found :\n\t"; + for (std::set::iterator it = filterFunctionSet.begin(); + it != filterFunctionSet.end(); it++) { + errs() << *it << " "; + } + errs() << "\n"; + } + } + + // Add the pass manager + Triple TheTriple = Triple(TripleName); + + // Decide where to send the output. + std::unique_ptr Out = + GetOutputStream(TheTarget->getName(), TheTriple.getOS(), ToolName.data()); + + if (!Out) + return; + + // Keep the file created. + Out->keep(); + + raw_pwrite_stream *OS = &Out->os(); + + legacy::PassManager PM; + + LLVMTargetMachine &LLVMTM = static_cast(*Target); + + if (RunPassNames->empty()) { + TargetPassConfig &TPC = *LLVMTM.createPassConfig(PM); + if (TPC.hasLimitedCodeGenPipeline()) { + errs() << ToolName << ": run-pass cannot be used with " + << TPC.getLimitedCodeGenPipelineReason(" and ") << ".\n"; + return; + } + + TPC.setDisableVerify(NoVerify); + PM.add(&TPC); + PM.add(machineModuleInfo); + + // Add print pass to emit ouptut file. + PM.add(new EmitRaisedOutputPass(*OS, OutputFormat)); + + TPC.printAndVerify(""); + for (const std::string &RunPassName : *RunPassNames) { + if (addPass(PM, ToolName, RunPassName, TPC)) + return; + } + + TPC.setInitialized(); + } else if (Target->addPassesToEmitFile( + PM, *OS, nullptr, /* no dwarf output file stream*/ + OutputFormat, NoVerify, machineModuleInfo)) { + outs() << ToolName << "run system pass!\n"; + } + + cl::PrintOptionValues(); + PM.run(module); +} + +void llvm::PrintSectionHeaders(const ObjectFile *Obj) { + outs() << "Sections:\n" + "Idx Name Size Address Type\n"; + unsigned i = 0; + for (const SectionRef &Section : ToolSectionFilter(*Obj)) { + StringRef Name; + error(Section.getName(Name)); + uint64_t Address = Section.getAddress(); + uint64_t Size = Section.getSize(); + bool Text = Section.isText(); + bool Data = Section.isData(); + bool BSS = Section.isBSS(); + std::string Type = (std::string(Text ? "TEXT " : "") + + (Data ? "DATA " : "") + (BSS ? "BSS" : "")); + outs() << format("%3d %-13s %08" PRIx64 " %016" PRIx64 " %s\n", i, + Name.str().c_str(), Size, Address, Type.c_str()); + ++i; + } +} + +void llvm::PrintSymbolTable(const ObjectFile *o, StringRef ArchiveName, + StringRef ArchitectureName) { + outs() << "SYMBOL TABLE:\n"; + + if (const COFFObjectFile *coff = dyn_cast(o)) { + printCOFFSymbolTable(coff); + return; + } + + for (const SymbolRef &Symbol : o->symbols()) { + Expected AddressOrError = Symbol.getAddress(); + if (!AddressOrError) + report_error(ArchiveName, o->getFileName(), AddressOrError.takeError(), + ArchitectureName); + uint64_t Address = *AddressOrError; + if ((Address < StartAddress) || (Address > StopAddress)) + continue; + + Expected TypeOrError = Symbol.getType(); + if (!TypeOrError) + report_error(ArchiveName, o->getFileName(), TypeOrError.takeError(), + ArchitectureName); + + SymbolRef::Type Type = *TypeOrError; + uint32_t Flags = Symbol.getFlags(); + Expected SectionOrErr = Symbol.getSection(); + if (!SectionOrErr) + report_error(ArchiveName, o->getFileName(), SectionOrErr.takeError(), + ArchitectureName); + + section_iterator Section = *SectionOrErr; + StringRef Name; + if (Type == SymbolRef::ST_Debug && Section != o->section_end()) { + Section->getName(Name); + } else { + Expected NameOrErr = Symbol.getName(); + if (!NameOrErr) + report_error(ArchiveName, o->getFileName(), NameOrErr.takeError(), + ArchitectureName); + Name = *NameOrErr; + } + + bool Global = Flags & SymbolRef::SF_Global; + bool Weak = Flags & SymbolRef::SF_Weak; + bool Absolute = Flags & SymbolRef::SF_Absolute; + bool Common = Flags & SymbolRef::SF_Common; + bool Hidden = Flags & SymbolRef::SF_Hidden; + + char GlobLoc = ' '; + if (Type != SymbolRef::ST_Unknown) + GlobLoc = Global ? 'g' : 'l'; + char Debug = + (Type == SymbolRef::ST_Debug || Type == SymbolRef::ST_File) ? 'd' : ' '; + char FileFunc = ' '; + if (Type == SymbolRef::ST_File) + FileFunc = 'f'; + else if (Type == SymbolRef::ST_Function) + FileFunc = 'F'; + + const char *Fmt = o->getBytesInAddress() > 4 ? "%016" PRIx64 : "%08" PRIx64; + + outs() << format(Fmt, Address) << " " + << GlobLoc // Local -> 'l', Global -> 'g', Neither -> ' ' + << (Weak ? 'w' : ' ') // Weak? + << ' ' // Constructor. Not supported yet. + << ' ' // Warning. Not supported yet. + << ' ' // Indirect reference to another symbol. + << Debug // Debugging (d) or dynamic (D) symbol. + << FileFunc // Name of function (F), file (f) or object (O). + << ' '; + if (Absolute) { + outs() << "*ABS*"; + } else if (Common) { + outs() << "*COM*"; + } else if (Section == o->section_end()) { + outs() << "*UND*"; + } else { + if (const MachOObjectFile *MachO = dyn_cast(o)) { + DataRefImpl DR = Section->getRawDataRefImpl(); + StringRef SegmentName = MachO->getSectionFinalSegmentName(DR); + outs() << SegmentName << ","; + } + StringRef SectionName; + error(Section->getName(SectionName)); + outs() << SectionName; + } + + outs() << '\t'; + if (Common || isa(o)) { + uint64_t Val = + Common ? Symbol.getAlignment() : ELFSymbolRef(Symbol).getSize(); + outs() << format("\t %08" PRIx64 " ", Val); + } + + if (Hidden) { + outs() << ".hidden "; + } + outs() << Name << '\n'; + } +} + +static void PrintUnwindInfo(const ObjectFile *o) { + outs() << "Unwind info:\n\n"; + + if (const COFFObjectFile *coff = dyn_cast(o)) { + printCOFFUnwindInfo(coff); + } else if (const MachOObjectFile *MachO = dyn_cast(o)) + printMachOUnwindInfo(MachO); + else { + // TODO: Extract DWARF dump tool to objdump. + errs() << "This operation is only currently supported " + "for COFF and MachO object files.\n"; + return; + } +} + +void llvm::printExportsTrie(const ObjectFile *o) { + outs() << "Exports trie:\n"; + if (const MachOObjectFile *MachO = dyn_cast(o)) + printMachOExportsTrie(MachO); + else { + errs() << "This operation is only currently supported " + "for Mach-O executable files.\n"; + return; + } +} + +void llvm::printRebaseTable(ObjectFile *o) { + outs() << "Rebase table:\n"; + if (MachOObjectFile *MachO = dyn_cast(o)) + printMachORebaseTable(MachO); + else { + errs() << "This operation is only currently supported " + "for Mach-O executable files.\n"; + return; + } +} + +void llvm::printBindTable(ObjectFile *o) { + outs() << "Bind table:\n"; + if (MachOObjectFile *MachO = dyn_cast(o)) + printMachOBindTable(MachO); + else { + errs() << "This operation is only currently supported " + "for Mach-O executable files.\n"; + return; + } +} + +void llvm::printLazyBindTable(ObjectFile *o) { + outs() << "Lazy bind table:\n"; + if (MachOObjectFile *MachO = dyn_cast(o)) + printMachOLazyBindTable(MachO); + else { + errs() << "This operation is only currently supported " + "for Mach-O executable files.\n"; + return; + } +} + +void llvm::printWeakBindTable(ObjectFile *o) { + outs() << "Weak bind table:\n"; + if (MachOObjectFile *MachO = dyn_cast(o)) + printMachOWeakBindTable(MachO); + else { + errs() << "This operation is only currently supported " + "for Mach-O executable files.\n"; + return; + } +} + +/// Dump the raw contents of the __clangast section so the output can be piped +/// into llvm-bcanalyzer. +void llvm::printRawClangAST(const ObjectFile *Obj) { + if (outs().is_displayed()) { + errs() << "The -raw-clang-ast option will dump the raw binary contents of " + "the clang ast section.\n" + "Please redirect the output to a file or another program such as " + "llvm-bcanalyzer.\n"; + return; + } + + StringRef ClangASTSectionName("__clangast"); + if (isa(Obj)) { + ClangASTSectionName = "clangast"; + } + + Optional ClangASTSection; + for (auto Sec : ToolSectionFilter(*Obj)) { + StringRef Name; + Sec.getName(Name); + if (Name == ClangASTSectionName) { + ClangASTSection = Sec; + break; + } + } + if (!ClangASTSection) + return; + + StringRef ClangASTContents; + error(ClangASTSection.getValue().getContents(ClangASTContents)); + outs().write(ClangASTContents.data(), ClangASTContents.size()); +} + +static void printFaultMaps(const ObjectFile *Obj) { + const char *FaultMapSectionName = nullptr; + + if (isa(Obj)) { + FaultMapSectionName = ".llvm_faultmaps"; + } else if (isa(Obj)) { + FaultMapSectionName = "__llvm_faultmaps"; + } else { + errs() << "This operation is only currently supported " + "for ELF and Mach-O executable files.\n"; + return; + } + + Optional FaultMapSection; + + for (auto Sec : ToolSectionFilter(*Obj)) { + StringRef Name; + Sec.getName(Name); + if (Name == FaultMapSectionName) { + FaultMapSection = Sec; + break; + } + } + + outs() << "FaultMap table:\n"; + + if (!FaultMapSection.hasValue()) { + outs() << "\n"; + return; + } + + StringRef FaultMapContents; + error(FaultMapSection.getValue().getContents(FaultMapContents)); + + FaultMapParser FMP(FaultMapContents.bytes_begin(), + FaultMapContents.bytes_end()); + + outs() << FMP; +} + +static void printPrivateFileHeaders(const ObjectFile *o, bool onlyFirst) { + if (o->isELF()) + return printELFFileHeader(o); + if (o->isCOFF()) + return printCOFFFileHeader(o); + if (o->isWasm()) + return printWasmFileHeader(o); + if (o->isMachO()) { + printMachOFileHeader(o); + if (!onlyFirst) + printMachOLoadCommands(o); + return; + } + report_error(o->getFileName(), "Invalid/Unsupported object file format"); +} + +static void DumpObject(ObjectFile *o, const Archive *a = nullptr) { + StringRef ArchiveName = a != nullptr ? a->getFileName() : ""; + bool PrintAll = + (cl::getRegisteredOptions()["print-after-all"]->getNumOccurrences() > 0); + // Avoid other output when using a raw option. + if (!RawClangAST && PrintAll) { + outs() << '\n'; + if (a) + outs() << a->getFileName() << "(" << o->getFileName() << ")"; + else + outs() << "; " << o->getFileName(); + outs() << ":\tfile format " << o->getFileFormatName() << "\n\n"; + } + + if (Disassemble) + DisassembleObject(o, Relocations); + if (SectionHeaders) + PrintSectionHeaders(o); + if (SymbolTable) + PrintSymbolTable(o, ArchiveName); + if (UnwindInfo) + PrintUnwindInfo(o); + if (PrivateHeaders || FirstPrivateHeader) + printPrivateFileHeaders(o, FirstPrivateHeader); + if (ExportsTrie) + printExportsTrie(o); + if (Rebase) + printRebaseTable(o); + if (Bind) + printBindTable(o); + if (LazyBind) + printLazyBindTable(o); + if (WeakBind) + printWeakBindTable(o); + if (RawClangAST) + printRawClangAST(o); + if (PrintFaultMaps) + printFaultMaps(o); +} + +static void DumpObject(const COFFImportFile *I, const Archive *A) { + StringRef ArchiveName = A ? A->getFileName() : ""; + + // Avoid other output when using a raw option. + if (!RawClangAST) + outs() << '\n' + << ArchiveName << "(" << I->getFileName() << ")" + << ":\tfile format COFF-import-file" + << "\n\n"; + + if (SymbolTable) + printCOFFSymbolTable(I); +} + +/// @brief Dump each object file in \a a; +static void DumpArchive(const Archive *a) { + Error Err = Error::success(); + for (auto &C : a->children(Err)) { + Expected> ChildOrErr = C.getAsBinary(); + if (!ChildOrErr) { + if (auto E = isNotObjectErrorInvalidFileType(ChildOrErr.takeError())) + report_error(a->getFileName(), C, std::move(E)); + continue; + } + if (ObjectFile *o = dyn_cast(&*ChildOrErr.get())) + DumpObject(o, a); + else if (COFFImportFile *I = dyn_cast(&*ChildOrErr.get())) + DumpObject(I, a); + else + report_error(a->getFileName(), object_error::invalid_file_type); + } + if (Err) + report_error(a->getFileName(), std::move(Err)); +} + +/// @brief Open file and figure out how to dump it. +static void DumpInput(StringRef file) { + + // If we are using the Mach-O specific object file parser, then let it parse + // the file and process the command line options. So the -arch flags can + // be used to select specific slices, etc. + if (MachOOpt) { + ParseInputMachO(file); + return; + } + + // Attempt to open the binary. + Expected> BinaryOrErr = createBinary(file); + if (!BinaryOrErr) + report_error(file, BinaryOrErr.takeError()); + Binary &Binary = *BinaryOrErr.get().getBinary(); + + if (Archive *a = dyn_cast(&Binary)) + DumpArchive(a); + else if (ObjectFile *o = dyn_cast(&Binary)) + DumpObject(o); + else + report_error(file, object_error::invalid_file_type); +} + +int main(int argc, char **argv) { + // Print a stack trace if we signal out. + sys::PrintStackTraceOnErrorSignal(argv[0]); + PrettyStackTraceProgram X(argc, argv); + llvm_shutdown_obj Y; // Call llvm_shutdown() on exit. + + // Initialize targets and assembly printers/parsers. + llvm::InitializeAllTargets(); + llvm::InitializeAllTargetInfos(); + llvm::InitializeAllTargetMCs(); + llvm::InitializeAllDisassemblers(); + + // Register the target printer for --version. + cl::AddExtraVersionPrinter(TargetRegistry::printRegisteredTargetsForVersion); + + cl::HideUnrelatedOptions(LLVMMCToLLCategory); + + StringMap &Map = cl::getRegisteredOptions(); + + // Unhide print-after-all option and place it in LLVMMCToLLCategory + // Change its help string value appropriately + assert(Map.count("print-after-all") > 0); + Map["print-after-all"]->setHiddenFlag(cl::NotHidden); + Map["print-after-all"]->setCategory(LLVMMCToLLCategory); + Map["print-after-all"]->setDescription("Print IR after each raiser pass"); + + cl::ParseCommandLineOptions(argc, argv, "MC to LLVM IR dumper\n"); + + ToolName = argv[0]; + + // Defaults to a.out if no filenames specified. + if (InputFilenames.size() == 0) + InputFilenames.push_back("a.out"); + + if (/* DisassembleAll || */ PrintSource || PrintLines) + Disassemble = true; + if (!Disassemble && !Relocations && + !SectionHeaders + //&& !SectionContents + && !SymbolTable && !UnwindInfo && !PrivateHeaders && + !FirstPrivateHeader && !ExportsTrie && !Rebase && !Bind && !LazyBind && + !WeakBind && !RawClangAST && !(UniversalHeaders && MachOOpt) && + !(ArchiveHeaders && MachOOpt) && !(IndirectSymbols && MachOOpt) && + !(DataInCode && MachOOpt) && !(LinkOptHints && MachOOpt) && + !(InfoPlist && MachOOpt) && !(DylibsUsed && MachOOpt) && + !(DylibId && MachOOpt) && !(ObjcMetaData && MachOOpt) && + !(FilterSections.size() != 0 && MachOOpt) && !PrintFaultMaps) { + cl::PrintHelpMessage(); + return 2; + } + + std::for_each(InputFilenames.begin(), InputFilenames.end(), DumpInput); + + return EXIT_SUCCESS; +} Index: tools/llvm-mctoll/test/CMakeLists.txt =================================================================== --- /dev/null +++ tools/llvm-mctoll/test/CMakeLists.txt @@ -0,0 +1,31 @@ +# Test runner infrastructure for LLVM-mctoll. This configures the LLVM-mctoll +# test trees for use by Lit, and delegates to LLVM's lit test handlers. + +if (CMAKE_CFG_INTDIR STREQUAL ".") + set(LLVM_BUILD_MODE ".") +else () + set(LLVM_BUILD_MODE "%(build_mode)s") +endif () + +string(REPLACE ${CMAKE_CFG_INTDIR} ${LLVM_BUILD_MODE} LLVM_MCTOLL_TOOLS_DIR ${LLVM_RUNTIME_OUTPUT_INTDIR}) + +set(LLVM_MCTEST_DEPENDS llvm-mctoll) +if (NOT LLVM_MCTOLL_BUILT_STANDALONE) + list(APPEND + LLVM_MCTEST_DEPENDS + clang count FileCheck llc lli llvm-as llvm-cat llvm-dis llvm-mc not opt) +endif() + +configure_lit_site_cfg( + ${CMAKE_CURRENT_SOURCE_DIR}/lit.site.cfg.in + ${CMAKE_CURRENT_BINARY_DIR}/lit.site.cfg +) + +add_lit_testsuite(check-mctoll "Running the llvm-mctoll tests" + ${CMAKE_CURRENT_BINARY_DIR} + PARAMS llvm_site_config=${CMAKE_CURRENT_BINARY_DIR}/lit.site.cfg + llvm_unit_site_config=${CMAKE_CURRENT_BINARY_DIR}/Unit/lit.site.cfg + DEPENDS ${LLVM_MCTEST_DEPENDS} +) + +set_target_properties(check-mctoll PROPERTIES FOLDER "llvm-mctoll tests") Index: tools/llvm-mctoll/test/dhrystone/README =================================================================== --- /dev/null +++ tools/llvm-mctoll/test/dhrystone/README @@ -0,0 +1,9 @@ +Dhrystone sources and test script +1. dhry_funcs_mod.c - contains functions that can be successfully +raised and tested for execution correctness. +2. dhry_main.c - contains main function and other functions whose +raised results need to be tested for execution correctness. +3. dhry.h - Unmodified header file. +4. README - for notes about the test + +NOTE: switch statement in Proc_6 has been temporarily changed to if-then-else \ No newline at end of file Index: tools/llvm-mctoll/test/dhrystone/dhry.h =================================================================== --- /dev/null +++ tools/llvm-mctoll/test/dhrystone/dhry.h @@ -0,0 +1,431 @@ +/* + **************************************************************************** + * + * "DHRYSTONE" Benchmark Program + * ----------------------------- + * + * Version: C, Version 2.1 + * + * File: dhry.h (part 1 of 3) + * + * Date: May 25, 1988 + * + * Author: Reinhold P. Weicker + * Siemens AG, E STE 35 + * Postfach 3240 + * 8520 Erlangen + * Germany (West) + * Phone: [xxx-49]-9131-7-20330 + * (8-17 Central European Time) + * Usenet: ..!mcvax!unido!estevax!weicker + * + * Original Version (in Ada) published in + * "Communications of the ACM" vol. 27., no. 10 (Oct. 1984), + * pp. 1013 - 1030, together with the statistics + * on which the distribution of statements etc. is based. + * + * In this C version, the following C library functions are used: + * - strcpy, strcmp (inside the measurement loop) + * - printf, scanf (outside the measurement loop) + * In addition, Berkeley UNIX system calls "times ()" or "time ()" + * are used for execution time measurement. For measurements + * on other systems, these calls have to be changed. + * + * Collection of Results: + * Reinhold Weicker (address see above) and + * + * Rick Richardson + * PC Research. Inc. + * 94 Apple Orchard Drive + * Tinton Falls, NJ 07724 + * Phone: (201) 389-8963 (9-17 EST) + * Usenet: ...!uunet!pcrat!rick + * + * Please send results to Rick Richardson and/or Reinhold Weicker. + * Complete information should be given on hardware and software used. + * Hardware information includes: Machine type, CPU, type and size + * of caches; for microprocessors: clock frequency, memory speed + * (number of wait states). + * Software information includes: Compiler (and runtime library) + * manufacturer and version, compilation switches, OS version. + * The Operating System version may give an indication about the + * compiler; Dhrystone itself performs no OS calls in the measurement loop. + * + * The complete output generated by the program should be mailed + * such that at least some checks for correctness can be made. + * + *************************************************************************** + * + * History: This version C/2.1 has been made for two reasons: + * + * 1) There is an obvious need for a common C version of + * Dhrystone, since C is at present the most popular system + * programming language for the class of processors + * (microcomputers, minicomputers) where Dhrystone is used most. + * There should be, as far as possible, only one C version of + * Dhrystone such that results can be compared without + * restrictions. In the past, the C versions distributed + * by Rick Richardson (Version 1.1) and by Reinhold Weicker + * had small (though not significant) differences. + * + * 2) As far as it is possible without changes to the Dhrystone + * statistics, optimizing compilers should be prevented from + * removing significant statements. + * + * This C version has been developed in cooperation with + * Rick Richardson (Tinton Falls, NJ), it incorporates many + * ideas from the "Version 1.1" distributed previously by + * him over the UNIX network Usenet. + * I also thank Chaim Benedelac (National Semiconductor), + * David Ditzel (SUN), Earl Killian and John Mashey (MIPS), + * Alan Smith and Rafael Saavedra-Barrera (UC at Berkeley) + * for their help with comments on earlier versions of the + * benchmark. + * + * Changes: In the initialization part, this version follows mostly + * Rick Richardson's version distributed via Usenet, not the + * version distributed earlier via floppy disk by Reinhold Weicker. + * As a concession to older compilers, names have been made + * unique within the first 8 characters. + * Inside the measurement loop, this version follows the + * version previously distributed by Reinhold Weicker. + * + * At several places in the benchmark, code has been added, + * but within the measurement loop only in branches that + * are not executed. The intention is that optimizing compilers + * should be prevented from moving code out of the measurement + * loop, or from removing code altogether. Since the statements + * that are executed within the measurement loop have NOT been + * changed, the numbers defining the "Dhrystone distribution" + * (distribution of statements, operand types and locality) + * still hold. Except for sophisticated optimizing compilers, + * execution times for this version should be the same as + * for previous versions. + * + * Since it has proven difficult to subtract the time for the + * measurement loop overhead in a correct way, the loop check + * has been made a part of the benchmark. This does have + * an impact - though a very minor one - on the distribution + * statistics which have been updated for this version. + * + * All changes within the measurement loop are described + * and discussed in the companion paper "Rationale for + * Dhrystone version 2". + * + * Because of the self-imposed limitation that the order and + * distribution of the executed statements should not be + * changed, there are still cases where optimizing compilers + * may not generate code for some statements. To a certain + * degree, this is unavoidable for small synthetic benchmarks. + * Users of the benchmark are advised to check code listings + * whether code is generated for all statements of Dhrystone. + * + * Version 2.1 is identical to version 2.0 distributed via + * the UNIX network Usenet in March 1988 except that it corrects + * some minor deficiencies that were found by users of version 2.0. + * The only change within the measurement loop is that a + * non-executed "else" part was added to the "if" statement in + * Func_3, and a non-executed "else" part removed from Proc_3. + * + *************************************************************************** + * + * Defines: The following "Defines" are possible: + * -DREG=register (default: Not defined) + * As an approximation to what an average C programmer + * might do, the "register" storage class is applied + * (if enabled by -DREG=register) + * - for local variables, if they are used (dynamically) + * five or more times + * - for parameters if they are used (dynamically) + * six or more times + * Note that an optimal "register" strategy is + * compiler-dependent, and that "register" declarations + * do not necessarily lead to faster execution. + * -DNOSTRUCTASSIGN (default: Not defined) + * Define if the C compiler does not support + * assignment of structures. + * -DNOENUMS (default: Not defined) + * Define if the C compiler does not support + * enumeration types. + * -DTIMES (default) + * -DTIME + * The "times" function of UNIX (returning process times) + * or the "time" function (returning wallclock time) + * is used for measurement. + * For single user machines, "time ()" is adequate. For + * multi-user machines where you cannot get single-user + * access, use the "times ()" function. If you have + * neither, use a stopwatch in the dead of night. + * "printf"s are provided marking the points "Start Timer" + * and "Stop Timer". DO NOT use the UNIX "time(1)" + * command, as this will measure the total time to + * run this program, which will (erroneously) include + * the time to allocate storage (malloc) and to perform + * the initialization. + * -DHZ=nnn + * In Berkeley UNIX, the function "times" returns process + * time in 1/HZ seconds, with HZ = 60 for most systems. + * CHECK YOUR SYSTEM DESCRIPTION BEFORE YOU JUST APPLY + * A VALUE. + * + *************************************************************************** + * + * Compilation model and measurement (IMPORTANT): + * + * This C version of Dhrystone consists of three files: + * - dhry.h (this file, containing global definitions and comments) + * - dhry_1.c (containing the code corresponding to Ada package Pack_1) + * - dhry_2.c (containing the code corresponding to Ada package Pack_2) + * + * The following "ground rules" apply for measurements: + * - Separate compilation + * - No procedure merging + * - Otherwise, compiler optimizations are allowed but should be indicated + * - Default results are those without register declarations + * See the companion paper "Rationale for Dhrystone Version 2" for a more + * detailed discussion of these ground rules. + * + * For 16-Bit processors (e.g. 80186, 80286), times for all compilation + * models ("small", "medium", "large" etc.) should be given if possible, + * together with a definition of these models for the compiler system used. + * + ************************************************************************** + * + * Dhrystone (C version) statistics: + * + * [Comment from the first distribution, updated for version 2. + * Note that because of language differences, the numbers are slightly + * different from the Ada version.] + * + * The following program contains statements of a high level programming + * language (here: C) in a distribution considered representative: + * + * assignments 52 (51.0 %) + * control statements 33 (32.4 %) + * procedure, function calls 17 (16.7 %) + * + * 103 statements are dynamically executed. The program is balanced with + * respect to the three aspects: + * + * - statement type + * - operand type + * - operand locality + * operand global, local, parameter, or constant. + * + * The combination of these three aspects is balanced only approximately. + * + * 1. Statement Type: + * ----------------- number + * + * V1 = V2 9 + * (incl. V1 = F(..) + * V = Constant 12 + * Assignment, 7 + * with array element + * Assignment, 6 + * with record component + * -- + * 34 34 + * + * X = Y +|-|"&&"|"|" Z 5 + * X = Y +|-|"==" Constant 6 + * X = X +|- 1 3 + * X = Y *|/ Z 2 + * X = Expression, 1 + * two operators + * X = Expression, 1 + * three operators + * -- + * 18 18 + * + * if .... 14 + * with "else" 7 + * without "else" 7 + * executed 3 + * not executed 4 + * for ... 7 | counted every time + * while ... 4 | the loop condition + * do ... while 1 | is evaluated + * switch ... 1 + * break 1 + * declaration with 1 + * initialization + * -- + * 34 34 + * + * P (...) procedure call 11 + * user procedure 10 + * library procedure 1 + * X = F (...) + * function call 6 + * user function 5 + * library function 1 + * -- + * 17 17 + * --- + * 103 + * + * The average number of parameters in procedure or function calls + * is 1.82 (not counting the function values aX * + * + * 2. Operators + * ------------ + * number approximate + * percentage + * + * Arithmetic 32 50.8 + * + * + 21 33.3 + * - 7 11.1 + * * 3 4.8 + * / (int div) 1 1.6 + * + * Comparison 27 42.8 + * + * == 9 14.3 + * /= 4 6.3 + * > 1 1.6 + * < 3 4.8 + * >= 1 1.6 + * <= 9 14.3 + * + * Logic 4 6.3 + * + * && (AND-THEN) 1 1.6 + * | (OR) 1 1.6 + * ! (NOT) 2 3.2 + * + * -- ----- + * 63 100.1 + * + * + * 3. Operand Type (counted once per operand reference): + * --------------- + * number approximate + * percentage + * + * Integer 175 72.3 % + * Character 45 18.6 % + * Pointer 12 5.0 % + * String30 6 2.5 % + * Array 2 0.8 % + * Record 2 0.8 % + * --- ------- + * 242 100.0 % + * + * When there is an access path leading to the final operand (e.g. a record + * component), only the final data type on the access path is counted. + * + * + * 4. Operand Locality: + * ------------------- + * number approximate + * percentage + * + * local variable 114 47.1 % + * global variable 22 9.1 % + * parameter 45 18.6 % + * value 23 9.5 % + * reference 22 9.1 % + * function result 6 2.5 % + * constant 55 22.7 % + * --- ------- + * 242 100.0 % + * + * + * The program does not compute anything meaningful, but it is syntactically + * and semantically correct. All variables have a value assigned to them + * before they are used as a source operand. + * + * There has been no explicit effort to account for the effects of a + * cache, or to balance the use of long or short displacements for code or + * data. + * + *************************************************************************** + */ + +/* Compiler and system dependent definitions: */ + +#ifndef TIME +#undef TIMES +#define TIMES +#endif + /* Use times(2) time function unless */ + /* explicitly defined otherwise */ + +#ifdef MSC_CLOCK +#undef HZ +#undef TIMES +#include +#define HZ CLK_TCK +#endif + /* Use Microsoft C hi-res clock */ + +#ifdef TIMES +#include +#include + /* for "times" */ +#endif + +#define Mic_secs_Per_Second 1000000.0 + /* Berkeley UNIX C returns process times in seconds/HZ */ + +#ifdef NOSTRUCTASSIGN +#define structassign(d, s) libc_memcpy(&(d), &(s), sizeof(d)) +#else +#define structassign(d, s) d = s +#endif + +#ifdef NOENUM +#define Ident_1 0 +#define Ident_2 1 +#define Ident_3 2 +#define Ident_4 3 +#define Ident_5 4 + typedef int Enumeration; +#else + typedef enum {Ident_1, Ident_2, Ident_3, Ident_4, Ident_5} + Enumeration; +#endif + /* for boolean and enumeration types in Ada, Pascal */ + +/* General definitions: */ + +#include + /* for strcpy, strcmp */ + +#define Null 0 + /* Value of a Null pointer */ +#define true 1 +#define false 0 + +typedef int One_Thirty; +typedef int One_Fifty; +typedef char Capital_Letter; +typedef int Boolean; +typedef char Str_30 [31]; +typedef int Arr_1_Dim [50]; +typedef int Arr_2_Dim [50] [50]; + +typedef struct record + { + struct record *Ptr_Comp; + Enumeration Discr; + union { + struct { + Enumeration Enum_Comp; + int Int_Comp; + char Str_Comp [31]; + } var_1; + struct { + Enumeration E_Comp_2; + char Str_2_Comp [31]; + } var_2; + struct { + char Ch_1_Comp; + char Ch_2_Comp; + } var_3; + } variant; + } Rec_Type, *Rec_Pointer; + + Index: tools/llvm-mctoll/test/dhrystone/dhry.test =================================================================== --- /dev/null +++ tools/llvm-mctoll/test/dhrystone/dhry.test @@ -0,0 +1,40 @@ +// RUN: clang -o %t.so %S/dhry_funcs_mod.c -shared -fPIC -g -DTIME -DHZ=2133 -DNOSTRUCTASSIGN +// RUN: llvm-mctoll -d %t.so +// RUN: clang -o %t1 %S/dhry_main.c %t-dis.ll -DTIME -DHZ=2133 -DNOSTRUCTASSIGN +// RUN: %t1 2>&1| FileCheck %s + +// CHECK: Dhrystone Benchmark, Version 2.1 (Language: C) +// CHECK: Program compiled without 'register' attribute +// CHECK: Execution starts, 100000000 runs through Dhrystone +// CHECK: Execution ends + +// CHECK: Final values of the variables used in the benchmark: +// CHECK: Int_Glob: 5 +// CHECK: Bool_Glob: 1 +// CHECK: Ch_1_Glob: A +// CHECK: Ch_2_Glob: B +// CHECK: Arr_1_Glob[8]: 7 +// CHECK: Arr_2_Glob[8][7]: 100000010 + +// CHECK: Ptr_Glob-> +// CHECK: Ptr_Comp: {{[0-9]+}} +// CHECK: Discr: 0 +// CHECK: Enum_Comp: 2 +// CHECK: Int_Comp: 17 +// CHECK: Str_Comp: DHRYSTONE PROGRAM, SOME STRING + +// CHECK: Next_Ptr_Glob-> +// CHECK: Ptr_Comp: {{[0-9]+}} +// CHECK: Discr: 0 +// CHECK: Enum_Comp: 1 +// CHECK: Int_Comp: 18 +// CHECK: Str_Comp: DHRYSTONE PROGRAM, SOME STRING +// CHECK: Int_1_Loc: 5 +// CHECK: Int_2_Loc: 13 +// CHECK: Int_3_Loc: 7 +// CHECK: Enum_Loc: 1 +// CHECK: Str_1_Loc: DHRYSTONE PROGRAM, 1'ST STRING +// CHECK: Str_2_Loc: DHRYSTONE PROGRAM, 2'ND STRING + +// CHECK: Microseconds for one run through Dhrystone: {{[0-9]+}}.{{[0-9]+}} +// CHECK: Dhrystones per Second: {{[0-9]+}}.{{[0-9]+}} \ No newline at end of file Index: tools/llvm-mctoll/test/dhrystone/dhry_funcs_mod.c =================================================================== --- /dev/null +++ tools/llvm-mctoll/test/dhrystone/dhry_funcs_mod.c @@ -0,0 +1,337 @@ +/* + **************************************************************************** + * + * "DHRYSTONE" Benchmark Program + * ----------------------------- + * + * Version: C, Version 2.1 + * + * File: dhry_2.c (part 3 of 3) + * + * Date: May 25, 1988 + * + * Author: Reinhold P. Weicker + * + **************************************************************************** + */ + +#include "dhry.h" + +#ifndef REG +#define REG + /* REG becomes defined as empty */ + /* i.e. no register variables */ +#endif + +int Int_Glob; +char Ch_1_Glob; +char Ch_2_Glob; + +Boolean Bool_Glob; +Rec_Pointer Ptr_Glob; + + +Proc_4 () /* without parameters */ +/*******/ + /* executed once */ +{ + Boolean Bool_Loc; + + Bool_Loc = Ch_1_Glob == 'A'; + Bool_Glob = Bool_Loc | Bool_Glob; + Ch_2_Glob = 'B'; +} /* Proc_4 */ + +Proc_5 () /* without parameters */ +/*******/ + /* executed once */ +{ + Ch_1_Glob = 'A'; + Bool_Glob = false; +} /* Proc_5 */ + +Proc_3 (Ptr_Ref_Par) +/******************/ + /* executed once */ + /* Ptr_Ref_Par becomes Ptr_Glob */ + +Rec_Pointer *Ptr_Ref_Par; + +{ + if (Ptr_Glob != Null) + /* then, executed */ + *Ptr_Ref_Par = Ptr_Glob->Ptr_Comp; + Proc_7 (10, Int_Glob, &Ptr_Glob->variant.var_1.Int_Comp); +} /* Proc_3 */ + +Proc_7 (Int_1_Par_Val, Int_2_Par_Val, Int_Par_Ref) +/**********************************************/ + /* executed three times */ + /* first call: Int_1_Par_Val == 2, Int_2_Par_Val == 3, */ + /* Int_Par_Ref becomes 7 */ + /* second call: Int_1_Par_Val == 10, Int_2_Par_Val == 5, */ + /* Int_Par_Ref becomes 17 */ + /* third call: Int_1_Par_Val == 6, Int_2_Par_Val == 10, */ + /* Int_Par_Ref becomes 18 */ +One_Fifty Int_1_Par_Val; +One_Fifty Int_2_Par_Val; +One_Fifty *Int_Par_Ref; +{ + One_Fifty Int_Loc; + + Int_Loc = Int_1_Par_Val + 2; + *Int_Par_Ref = Int_2_Par_Val + Int_Loc; +} /* Proc_7 */ + + +Proc_2 (Int_Par_Ref) +/******************/ + /* executed once */ + /* *Int_Par_Ref == 1, becomes 4 */ + +One_Fifty *Int_Par_Ref; +{ + One_Fifty Int_Loc; + Enumeration Enum_Loc; + + Int_Loc = *Int_Par_Ref + 10; + do /* executed once */ + if (Ch_1_Glob == 'A') + /* then, executed */ + { + Int_Loc -= 1; + *Int_Par_Ref = Int_Loc - Int_Glob; + Enum_Loc = Ident_1; + } /* if */ + while (Enum_Loc != Ident_1); /* true */ +} /* Proc_2 */ + + + + +Proc_8 (Arr_1_Par_Ref, Arr_2_Par_Ref, Int_1_Par_Val, Int_2_Par_Val) +/*********************************************************************/ + /* executed once */ + /* Int_Par_Val_1 == 3 */ + /* Int_Par_Val_2 == 7 */ +Arr_1_Dim Arr_1_Par_Ref; +Arr_2_Dim Arr_2_Par_Ref; +int Int_1_Par_Val; +int Int_2_Par_Val; +{ + REG One_Fifty Int_Index; + REG One_Fifty Int_Loc; + + Int_Loc = Int_1_Par_Val + 5; + Arr_1_Par_Ref [Int_Loc] = Int_2_Par_Val; + Arr_1_Par_Ref [Int_Loc+1] = Arr_1_Par_Ref [Int_Loc]; + Arr_1_Par_Ref [Int_Loc+30] = Int_Loc; + for (Int_Index = Int_Loc; Int_Index <= Int_Loc+1; ++Int_Index) + Arr_2_Par_Ref [Int_Loc] [Int_Index] = Int_Loc; + Arr_2_Par_Ref [Int_Loc] [Int_Loc-1] += 1; + Arr_2_Par_Ref [Int_Loc+20] [Int_Loc] = Arr_1_Par_Ref [Int_Loc]; + Int_Glob = 5; +} /* Proc_8 */ + + /* Procedure for the assignment of structures, */ + /* if the C compiler doesn't support this feature */ +#ifdef NOSTRUCTASSIGN +libc_memcpy (d, s, l) +register char *d; +register char *s; +register int l; +{ + while (l--) *d++ = *s++; +} +#endif + +/* Compare S1 and S2, returning less than, equal to or + greater than zero if S1 is lexicographically less than, + equal to or greater than S2. */ +int +libc_strcmp (p1, p2) + const char *p1; + const char *p2; +{ + const unsigned char *s1 = (const unsigned char *) p1; + const unsigned char *s2 = (const unsigned char *) p2; + unsigned char c1, c2; + + do + { + c1 = (unsigned char) *s1++; + c2 = (unsigned char) *s2++; + if (c1 == '\0') + return c1 - c2; + } + while (c1 == c2); + + return c1 - c2; +} + +/*******************************/ +Proc_6 (Enum_Val_Par, Enum_Ref_Par) +/*********************************/ + /* executed once */ + /* Enum_Val_Par == Ident_3, Enum_Ref_Par becomes Ident_2 */ + +Enumeration Enum_Val_Par; +Enumeration *Enum_Ref_Par; +{ + *Enum_Ref_Par = Enum_Val_Par; + if (! Func_3 (Enum_Val_Par)) + /* then, not executed */ + *Enum_Ref_Par = Ident_4; + #if 0 + switch (Enum_Val_Par) + { + case Ident_1: + *Enum_Ref_Par = Ident_1; + break; + case Ident_2: + if (Int_Glob > 100) + /* then */ + *Enum_Ref_Par = Ident_1; + else *Enum_Ref_Par = Ident_4; + break; + case Ident_3: /* executed */ + *Enum_Ref_Par = Ident_2; + break; + case Ident_4: break; + case Ident_5: + *Enum_Ref_Par = Ident_3; + break; + } /* switch */ + #endif + if (Enum_Val_Par == Ident_1) { + *Enum_Ref_Par = Ident_1; + } else if (Enum_Val_Par == Ident_2) { + if (Int_Glob > 100) + /* then */ + *Enum_Ref_Par = Ident_1; + else *Enum_Ref_Par = Ident_4; + } else if (Enum_Val_Par == Ident_3) { /* executed */ + *Enum_Ref_Par = Ident_2; + } else if (Enum_Val_Par == Ident_4) { + } else if (Enum_Val_Par == Ident_5) { + *Enum_Ref_Par = Ident_3; + } +} /* Proc_6 */ + + + +Boolean Func_3 (Enum_Par_Val) +/***************************/ + /* executed once */ + /* Enum_Par_Val == Ident_3 */ +Enumeration Enum_Par_Val; +{ + Enumeration Enum_Loc; + + Enum_Loc = Enum_Par_Val; + if (Enum_Loc == Ident_3) + /* then, executed */ + return (true); + else /* not executed */ + return (false); +} /* Func_3 */ + +Enumeration Func_1 (Ch_1_Par_Val, Ch_2_Par_Val) +/*************************************************/ + /* executed three times */ + /* first call: Ch_1_Par_Val == 'H', Ch_2_Par_Val == 'R' */ + /* second call: Ch_1_Par_Val == 'A', Ch_2_Par_Val == 'C' */ + /* third call: Ch_1_Par_Val == 'B', Ch_2_Par_Val == 'C' */ + +Capital_Letter Ch_1_Par_Val; +Capital_Letter Ch_2_Par_Val; +{ + Capital_Letter Ch_1_Loc; + Capital_Letter Ch_2_Loc; + + Ch_1_Loc = Ch_1_Par_Val; + Ch_2_Loc = Ch_1_Loc; + if (Ch_2_Loc != Ch_2_Par_Val) + /* then, executed */ + return (Ident_1); + else /* not executed */ + { + Ch_1_Glob = Ch_1_Loc; + return (Ident_2); + } +} /* Func_1 */ + + +Boolean Func_2 (Str_1_Par_Ref, Str_2_Par_Ref) +/*************************************************/ + /* executed once */ + /* Str_1_Par_Ref == "DHRYSTONE PROGRAM, 1'ST STRING" */ + /* Str_2_Par_Ref == "DHRYSTONE PROGRAM, 2'ND STRING" */ + +Str_30 Str_1_Par_Ref; +Str_30 Str_2_Par_Ref; +{ + REG One_Thirty Int_Loc; + Capital_Letter Ch_Loc; + + Int_Loc = 2; + while (Int_Loc <= 2) /* loop body executed once */ + if (Func_1 (Str_1_Par_Ref[Int_Loc], + Str_2_Par_Ref[Int_Loc+1]) == Ident_1) + /* then, executed */ + { + Ch_Loc = 'A'; + Int_Loc += 1; + } /* if, while */ + if (Ch_Loc >= 'W' && Ch_Loc < 'Z') + /* then, not executed */ + Int_Loc = 7; + if (Ch_Loc == 'R') + /* then, not executed */ + return (true); + else /* executed */ + { + if (libc_strcmp (Str_1_Par_Ref, Str_2_Par_Ref) > 0) + /* then, not executed */ + { + Int_Loc += 7; + Int_Glob = Int_Loc; + return (true); + } + else /* executed */ + return (false); + } /* if Ch_Loc */ +} /* Func_2 */ + +Proc_1 (Ptr_Val_Par) +/******************/ + +REG Rec_Pointer Ptr_Val_Par; + /* executed once */ +{ + REG Rec_Pointer Next_Record = Ptr_Val_Par->Ptr_Comp; + /* == Ptr_Glob_Next */ + /* Local variable, initialized with Ptr_Val_Par->Ptr_Comp, */ + /* corresponds to "rename" in Ada, "with" in Pascal */ + + structassign (*Ptr_Val_Par->Ptr_Comp, *Ptr_Glob); + Ptr_Val_Par->variant.var_1.Int_Comp = 5; + Next_Record->variant.var_1.Int_Comp + = Ptr_Val_Par->variant.var_1.Int_Comp; + Next_Record->Ptr_Comp = Ptr_Val_Par->Ptr_Comp; + Proc_3 (&Next_Record->Ptr_Comp); + /* Ptr_Val_Par->Ptr_Comp->Ptr_Comp + == Ptr_Glob->Ptr_Comp */ + if (Next_Record->Discr == Ident_1) + /* then, executed */ + { + Next_Record->variant.var_1.Int_Comp = 6; + Proc_6 (Ptr_Val_Par->variant.var_1.Enum_Comp, + &Next_Record->variant.var_1.Enum_Comp); + Next_Record->Ptr_Comp = Ptr_Glob->Ptr_Comp; + Proc_7 (Next_Record->variant.var_1.Int_Comp, 10, + &Next_Record->variant.var_1.Int_Comp); + } + else /* not executed */ + structassign (*Ptr_Val_Par, *Ptr_Val_Par->Ptr_Comp); +} /* Proc_1 */ Index: tools/llvm-mctoll/test/dhrystone/dhry_main.c =================================================================== --- /dev/null +++ tools/llvm-mctoll/test/dhrystone/dhry_main.c @@ -0,0 +1,291 @@ +/* + **************************************************************************** + * + * "DHRYSTONE" Benchmark Program + * ----------------------------- + * + * Version: C, Version 2.1 + * + * File: dhry_1.c (part 2 of 3) + * + * Date: May 25, 1988 + * + * Author: Reinhold P. Weicker + * + **************************************************************************** + */ + +#include "dhry.h" + +/* Global Variables: */ +extern int Int_Glob; +extern char Ch_1_Glob; + +extern Rec_Pointer Ptr_Glob; +Rec_Pointer Next_Ptr_Glob; +extern Boolean Bool_Glob; +extern char Ch_2_Glob; +int Arr_1_Glob [50]; +int Arr_2_Glob [50] [50]; + +extern char *malloc (); +Enumeration Func_1 (); + /* forward declaration necessary since Enumeration may not simply be int */ + +#ifndef REG + Boolean Reg = false; +#define REG + /* REG becomes defined as empty */ + /* i.e. no register variables */ +#else + Boolean Reg = true; +#endif + +/* variables for time measurement: */ + +#ifdef TIMES +struct tms time_info; +extern int times (); + /* see library function "times" */ +#define Too_Small_Time (2*HZ) + /* Measurements should last at least about 2 seconds */ +#endif +#ifdef TIME +extern long time(); + /* see library function "time" */ +#define Too_Small_Time 2 + /* Measurements should last at least 2 seconds */ +#endif +#ifdef MSC_CLOCK +extern clock_t clock(); +#define Too_Small_Time (2*HZ) +#endif + +long Begin_Time, + End_Time, + User_Time; +float Microseconds, + Dhrystones_Per_Second; + +/* end of variables for time measurement */ + +main () +/*****/ + + /* main program, corresponds to procedures */ + /* Main and Proc_0 in the Ada version */ +{ + One_Fifty Int_1_Loc; + REG One_Fifty Int_2_Loc; + One_Fifty Int_3_Loc; + REG char Ch_Index; + Enumeration Enum_Loc; + Str_30 Str_1_Loc; + Str_30 Str_2_Loc; + REG int Run_Index; + // A value is specifed for testing purposes + REG int Number_Of_Runs = 100000000; + + /* Initializations */ + + Next_Ptr_Glob = (Rec_Pointer) malloc (sizeof (Rec_Type)); + Ptr_Glob = (Rec_Pointer) malloc (sizeof (Rec_Type)); + + Ptr_Glob->Ptr_Comp = Next_Ptr_Glob; + Ptr_Glob->Discr = Ident_1; + Ptr_Glob->variant.var_1.Enum_Comp = Ident_3; + Ptr_Glob->variant.var_1.Int_Comp = 40; + strcpy (Ptr_Glob->variant.var_1.Str_Comp, + "DHRYSTONE PROGRAM, SOME STRING"); + strcpy (Str_1_Loc, "DHRYSTONE PROGRAM, 1'ST STRING"); + + Arr_2_Glob [8][7] = 10; + /* Was missing in published program. Without this statement, */ + /* Arr_2_Glob [8][7] would have an undefined value. */ + /* Warning: With 16-Bit processors and Number_Of_Runs > 32000, */ + /* overflow may occur for this array element. */ + + printf ("\n"); + printf ("Dhrystone Benchmark, Version 2.1 (Language: C)\n"); + printf ("\n"); + if (Reg) + { + printf ("Program compiled with 'register' attribute\n"); + printf ("\n"); + } + else + { + printf ("Program compiled without 'register' attribute\n"); + printf ("\n"); + } + #if 0 + // This is commented out and the number of runs is specified as a constant + printf ("Please give the number of runs through the benchmark: "); + { + int n; + scanf ("%d", &n); + Number_Of_Runs = n; + } + #endif + + printf ("\n"); + + printf ("Execution starts, %d runs through Dhrystone\n", Number_Of_Runs); + + /***************/ + /* Start timer */ + /***************/ + +#ifdef TIMES + times (&time_info); + Begin_Time = (long) time_info.tms_utime; +#endif +#ifdef TIME + Begin_Time = time ( (long *) 0); +#endif +#ifdef MSC_CLOCK + Begin_Time = clock(); +#endif + + for (Run_Index = 1; Run_Index <= Number_Of_Runs; ++Run_Index) + { + + Proc_5(); + Proc_4(); + /* Ch_1_Glob == 'A', Ch_2_Glob == 'B', Bool_Glob == true */ + Int_1_Loc = 2; + Int_2_Loc = 3; + strcpy (Str_2_Loc, "DHRYSTONE PROGRAM, 2'ND STRING"); + Enum_Loc = Ident_2; + Bool_Glob = ! Func_2 (Str_1_Loc, Str_2_Loc); + /* Bool_Glob == 1 */ + while (Int_1_Loc < Int_2_Loc) /* loop body executed once */ + { + Int_3_Loc = 5 * Int_1_Loc - Int_2_Loc; + /* Int_3_Loc == 7 */ + Proc_7 (Int_1_Loc, Int_2_Loc, &Int_3_Loc); + /* Int_3_Loc == 7 */ + Int_1_Loc += 1; + } /* while */ + /* Int_1_Loc == 3, Int_2_Loc == 3, Int_3_Loc == 7 */ + Proc_8 (Arr_1_Glob, Arr_2_Glob, Int_1_Loc, Int_3_Loc); + /* Int_Glob == 5 */ + Proc_1 (Ptr_Glob); + for (Ch_Index = 'A'; Ch_Index <= Ch_2_Glob; ++Ch_Index) + /* loop body executed twice */ + { + if (Enum_Loc == Func_1 (Ch_Index, 'C')) + /* then, not executed */ + { + Proc_6 (Ident_1, &Enum_Loc); + strcpy (Str_2_Loc, "DHRYSTONE PROGRAM, 3'RD STRING"); + Int_2_Loc = Run_Index; + Int_Glob = Run_Index; + } + } + /* Int_1_Loc == 3, Int_2_Loc == 3, Int_3_Loc == 7 */ + Int_2_Loc = Int_2_Loc * Int_1_Loc; + Int_1_Loc = Int_2_Loc / Int_3_Loc; + Int_2_Loc = 7 * (Int_2_Loc - Int_3_Loc) - Int_1_Loc; + /* Int_1_Loc == 1, Int_2_Loc == 13, Int_3_Loc == 7 */ + Proc_2 (&Int_1_Loc); + /* Int_1_Loc == 5 */ + + } /* loop "for Run_Index" */ + + /**************/ + /* Stop timer */ + /**************/ + +#ifdef TIMES + times (&time_info); + End_Time = (long) time_info.tms_utime; +#endif +#ifdef TIME + End_Time = time ( (long *) 0); +#endif +#ifdef MSC_CLOCK + End_Time = clock(); +#endif + + printf ("Execution ends\n"); + printf ("\n"); + printf ("Final values of the variables used in the benchmark:\n"); + printf ("\n"); + printf ("Int_Glob: %d\n", Int_Glob); + printf (" should be: %d\n", 5); + printf ("Bool_Glob: %d\n", Bool_Glob); + printf (" should be: %d\n", 1); + printf ("Ch_1_Glob: %c\n", Ch_1_Glob); + printf (" should be: %c\n", 'A'); + printf ("Ch_2_Glob: %c\n", Ch_2_Glob); + printf (" should be: %c\n", 'B'); + printf ("Arr_1_Glob[8]: %d\n", Arr_1_Glob[8]); + printf (" should be: %d\n", 7); + printf ("Arr_2_Glob[8][7]: %d\n", Arr_2_Glob[8][7]); + printf (" should be: Number_Of_Runs + 10\n"); + printf ("Ptr_Glob->\n"); + printf (" Ptr_Comp: %d\n", (int) Ptr_Glob->Ptr_Comp); + printf (" should be: (implementation-dependent)\n"); + printf (" Discr: %d\n", Ptr_Glob->Discr); + printf (" should be: %d\n", 0); + printf (" Enum_Comp: %d\n", Ptr_Glob->variant.var_1.Enum_Comp); + printf (" should be: %d\n", 2); + printf (" Int_Comp: %d\n", Ptr_Glob->variant.var_1.Int_Comp); + printf (" should be: %d\n", 17); + printf (" Str_Comp: %s\n", Ptr_Glob->variant.var_1.Str_Comp); + printf (" should be: DHRYSTONE PROGRAM, SOME STRING\n"); + printf ("Next_Ptr_Glob->\n"); + printf (" Ptr_Comp: %d\n", (int) Next_Ptr_Glob->Ptr_Comp); + printf (" should be: (implementation-dependent), same as above\n"); + printf (" Discr: %d\n", Next_Ptr_Glob->Discr); + printf (" should be: %d\n", 0); + printf (" Enum_Comp: %d\n", Next_Ptr_Glob->variant.var_1.Enum_Comp); + printf (" should be: %d\n", 1); + printf (" Int_Comp: %d\n", Next_Ptr_Glob->variant.var_1.Int_Comp); + printf (" should be: %d\n", 18); + printf (" Str_Comp: %s\n", + Next_Ptr_Glob->variant.var_1.Str_Comp); + printf (" should be: DHRYSTONE PROGRAM, SOME STRING\n"); + printf ("Int_1_Loc: %d\n", Int_1_Loc); + printf (" should be: %d\n", 5); + printf ("Int_2_Loc: %d\n", Int_2_Loc); + printf (" should be: %d\n", 13); + printf ("Int_3_Loc: %d\n", Int_3_Loc); + printf (" should be: %d\n", 7); + printf ("Enum_Loc: %d\n", Enum_Loc); + printf (" should be: %d\n", 1); + printf ("Str_1_Loc: %s\n", Str_1_Loc); + printf (" should be: DHRYSTONE PROGRAM, 1'ST STRING\n"); + printf ("Str_2_Loc: %s\n", Str_2_Loc); + printf (" should be: DHRYSTONE PROGRAM, 2'ND STRING\n"); + printf ("\n"); + + User_Time = End_Time - Begin_Time; + + if (User_Time < Too_Small_Time) + { + printf ("Measured time too small to obtain meaningful results\n"); + printf ("Please increase number of runs\n"); + printf ("\n"); + } + else + { +#ifdef TIME + Microseconds = (float) User_Time * Mic_secs_Per_Second + / (float) Number_Of_Runs; + Dhrystones_Per_Second = (float) Number_Of_Runs / (float) User_Time; +#else + Microseconds = (float) User_Time * Mic_secs_Per_Second + / ((float) HZ * ((float) Number_Of_Runs)); + Dhrystones_Per_Second = ((float) HZ * (float) Number_Of_Runs) + / (float) User_Time; +#endif + printf ("Microseconds for one run through Dhrystone: "); + printf ("%6.1f \n", Microseconds); + printf ("Dhrystones per Second: "); + printf ("%6.1f \n", Dhrystones_Per_Second); + printf ("\n"); + } + +} Index: tools/llvm-mctoll/test/dhrystone/lit.local.cfg =================================================================== --- /dev/null +++ tools/llvm-mctoll/test/dhrystone/lit.local.cfg @@ -0,0 +1 @@ +config.suffixes = ['.test'] Index: tools/llvm-mctoll/test/lit.cfg =================================================================== --- /dev/null +++ tools/llvm-mctoll/test/lit.cfg @@ -0,0 +1,48 @@ +# -*- Python -*- + +# Configuration file for the 'lit' test runner. + +import os +import lit.formats + +from lit.llvm import llvm_config + +# Configuration file for the 'lit' test runner. + +# name: The name of this test suite. +config.name = 'mctoll' + +# testFormat: The test format to use to interpret tests. +config.test_format = lit.formats.ShTest(not llvm_config.use_lit_shell) + +# suffixes: A list of file extensions to treat as test files. This is overriden +# by individual lit.local.cfg files in the test subdirectories. +config.suffixes = [] + +# excludes: A list of directories or files to exclude from the testsuite even +# if they match the suffixes pattern. +config.excludes = ['Inputs'] + +# test_source_root: The root path where tests are located. +config.test_source_root = os.path.dirname(__file__) + +# test_exec_root: The root path where tests should be run. +config.test_exec_root = os.path.join(config.llvm_mctoll_obj_root, 'test') + +# Tweak the PATH to include the tools dir. +llvm_config.with_environment('PATH', config.llvm_tools_dir, append_path=True) + +# Propagate some variables from the host environment. +llvm_config.with_system_environment( + ['HOME', 'INCLUDE', 'LIB', 'TMP', 'TEMP']) + + +llvm_config.use_default_substitutions() + +# For each occurrence of a tool name, replace it with the full path to +# the build directory holding that tool. We explicitly specify the directories +# to search to ensure that we get the tools just built and not some random +# tools that might happen to be in the user's PATH. +tool_dirs = [config.llvm_mctoll_tools_dir, config.llvm_tools_dir] +tools = [ 'clang', 'llvm-mctoll' ] +llvm_config.add_tool_substitutions(tools, tool_dirs) Index: tools/llvm-mctoll/test/lit.site.cfg.in =================================================================== --- /dev/null +++ tools/llvm-mctoll/test/lit.site.cfg.in @@ -0,0 +1,23 @@ +@LIT_SITE_CFG_IN_HEADER@ + +config.llvm_tools_dir = "@LLVM_TOOLS_DIR@" +config.llvm_mctoll_obj_root = "@LLVM_MCTOLL_BINARY_DIR@" +config.llvm_mctoll_tools_dir = "@LLVM_MCTOLL_TOOLS_DIR@" +config.lit_tools_dir = "@LLVM_LIT_TOOLS_DIR@" +config.target_triple = "@TARGET_TRIPLE@" + +# Support substitution of the tools and build_mode with user parameters. +# This is used when we can't determine the tool dir at configuration time. +try: + config.llvm_tools_dir = config.llvm_tools_dir % lit_config.params + config.llvm_mctoll_tools_dir = config.llvm_mctoll_tools_dir % lit_config.params +except KeyError as e: + key, = e.args + lit_config.fatal("unable to find %r parameter, use '--param=%s=VALUE'" % (key,key)) + +import lit.llvm +lit.llvm.initialize(lit_config, config) + +# Let the main config do the real work. +lit_config.load_config(config, "@LLVM_MCTOLL_SOURCE_DIR@/test/lit.cfg") + Index: tools/llvm-mctoll/test/smoke_test/Inputs/factorial.c =================================================================== --- /dev/null +++ tools/llvm-mctoll/test/smoke_test/Inputs/factorial.c @@ -0,0 +1,6 @@ +int factorial(int n) { + if (n == 0) { + return 1; + } + return n * factorial(n - 1); +} Index: tools/llvm-mctoll/test/smoke_test/Inputs/fibfunc.c =================================================================== --- /dev/null +++ tools/llvm-mctoll/test/smoke_test/Inputs/fibfunc.c @@ -0,0 +1,7 @@ +long fib(long n) { + if (n <= 1) { + return 1; + } else { + return fib(n - 1) + fib(n - 2); + } +} Index: tools/llvm-mctoll/test/smoke_test/Inputs/globalvar.c =================================================================== --- /dev/null +++ tools/llvm-mctoll/test/smoke_test/Inputs/globalvar.c @@ -0,0 +1,7 @@ +int myglob = 42; + +int myglobal_func(int a, int b) +{ + myglob += a; + return b + myglob; +} Index: tools/llvm-mctoll/test/smoke_test/Inputs/simple-phi.c =================================================================== --- /dev/null +++ tools/llvm-mctoll/test/smoke_test/Inputs/simple-phi.c @@ -0,0 +1,3 @@ +typedef int bool; + +bool orvalues(bool r, bool y) { return (y || r); } Index: tools/llvm-mctoll/test/smoke_test/Inputs/strcmp.c =================================================================== --- /dev/null +++ tools/llvm-mctoll/test/smoke_test/Inputs/strcmp.c @@ -0,0 +1,16 @@ +int libc_strcmp(p1, p2) const char *p1; +const char *p2; +{ + const unsigned char *s1 = (const unsigned char *)p1; + const unsigned char *s2 = (const unsigned char *)p2; + unsigned char c1, c2; + + do { + c1 = (unsigned char)*s1++; + c2 = (unsigned char)*s2++; + if (c1 == '\0') + return c1 - c2; + } while (c1 == c2); + + return c1 - c2; +} Index: tools/llvm-mctoll/test/smoke_test/Inputs/test-1.c =================================================================== --- /dev/null +++ tools/llvm-mctoll/test/smoke_test/Inputs/test-1.c @@ -0,0 +1,5 @@ +/** + * Compile command : clang -c test-1.c + **/ + +long test_1_func(int a, long b) { return a + b; } Index: tools/llvm-mctoll/test/smoke_test/Inputs/test-2.c =================================================================== --- /dev/null +++ tools/llvm-mctoll/test/smoke_test/Inputs/test-2.c @@ -0,0 +1,8 @@ +/** + * Compile command : clang -c test-2.c + **/ + +long test_2_func(int a, long b) { + int c = a + b; + return a + c; +} Index: tools/llvm-mctoll/test/smoke_test/Inputs/test-3.c =================================================================== --- /dev/null +++ tools/llvm-mctoll/test/smoke_test/Inputs/test-3.c @@ -0,0 +1,5 @@ +int test_3_func(int a, int b) { + int c = 0; + c = b - a; + return c; +} Index: tools/llvm-mctoll/test/smoke_test/factorial-test.c =================================================================== --- /dev/null +++ tools/llvm-mctoll/test/smoke_test/factorial-test.c @@ -0,0 +1,14 @@ +// RUN: clang -o %t.so %S/Inputs/factorial.c -shared -fPIC +// RUN: llvm-mctoll -d %t.so +// RUN: clang -o %t1 %s %t-dis.ll +// RUN: %t1 2>&1 | FileCheck %s +// CHECK: Factorial of 10 3628800 + +#include + +extern int factorial(int n); + +int main() { + printf("Factorial of 10 %d\n", factorial(10)); + return 0; +} Index: tools/llvm-mctoll/test/smoke_test/fibfunc-test.c =================================================================== --- /dev/null +++ tools/llvm-mctoll/test/smoke_test/fibfunc-test.c @@ -0,0 +1,14 @@ +// RUN: clang -o %t.so %S/Inputs/fibfunc.c -shared -fPIC +// RUN: llvm-mctoll -d %t.so +// RUN: clang -o %t1 %s %t-dis.ll +// RUN: %t1 2>&1 | FileCheck %s +// CHECK: Fibonacci of 42 433494437 + +#include + +extern long fib(long n); + +int main() { + printf("Fibonacci of 42 %ld\n", fib(42)); + return 0; +} Index: tools/llvm-mctoll/test/smoke_test/globalvar-test.c =================================================================== --- /dev/null +++ tools/llvm-mctoll/test/smoke_test/globalvar-test.c @@ -0,0 +1,19 @@ +// RUN: clang -o %t.so %S/Inputs/globalvar.c -shared -fPIC +// RUN: llvm-mctoll -d %t.so +// RUN: clang -o %t1 %s %t-dis.ll +// RUN: %t1 2>&1 | FileCheck %s +// CHECK: GlobalVar Initial value = 42 +// CHECK-NEXT: myglobal_func returns 72 +// CHECK-NEXT: GlobalVar updated value = 52 + +#include + +extern int myglob; +extern int myglobal_func(int a, int b); + +int main() { + printf("GlobalVar Initial value = %d\n", myglob); + printf("myglobal_func returns %d\n", myglobal_func(10, 20)); + printf("GlobalVar updated value = %d\n", myglob); + return 0; +} Index: tools/llvm-mctoll/test/smoke_test/hello.c =================================================================== --- /dev/null +++ tools/llvm-mctoll/test/smoke_test/hello.c @@ -0,0 +1,11 @@ +// RUN: clang -o %t %s +// RUN: llvm-mctoll -d %t +// RUN: clang -o %t1 %t-dis.ll +// RUN: %t1 2>&1 | FileCheck %s +// CHECK: Hello world! + +#include +int main(int argc, char **argv) { + printf("Hello world!\n"); + return 0; +} Index: tools/llvm-mctoll/test/smoke_test/lit.local.cfg =================================================================== --- /dev/null +++ tools/llvm-mctoll/test/smoke_test/lit.local.cfg @@ -0,0 +1 @@ +config.suffixes = ['.c'] Index: tools/llvm-mctoll/test/smoke_test/simple-phi-test.c =================================================================== --- /dev/null +++ tools/llvm-mctoll/test/smoke_test/simple-phi-test.c @@ -0,0 +1,23 @@ +// RUN: clang -o %t.so %S/Inputs/simple-phi.c -shared -fPIC +// RUN: llvm-mctoll -d %t.so +// RUN: clang -o %t1 %s %t-dis.ll +// RUN: %t1 2>&1 | FileCheck %s +// CHECK: true or true = true +// CHECK-NEXT: true or false = true +// CHECK-NEXT: false or true = true +// CHECK-NEXT: false or false = false + +#include +typedef int bool; +#define true 1 +#define false 0 + +extern bool orvalues(bool r, bool y); + +int main() { + printf("true or true = %s\n", (orvalues(true, true) ? "true" : "false")); + printf("true or false = %s\n", (orvalues(true, false) ? "true" : "false")); + printf("false or true = %s\n", (orvalues(false, true) ? "true" : "false")); + printf("false or false = %s\n", (orvalues(false, false) ? "true" : "false")); + return 0; +} Index: tools/llvm-mctoll/test/smoke_test/strcmp-test.c =================================================================== --- /dev/null +++ tools/llvm-mctoll/test/smoke_test/strcmp-test.c @@ -0,0 +1,46 @@ +// RUN: clang -o %t.so %S/Inputs/strcmp.c -shared -fPIC +// RUN: llvm-mctoll -d %t.so +// RUN: clang -o %t1 %s %t-dis.ll +// RUN: %t1 2>&1 | FileCheck %s +// CHECK: Lesser +// CHECK-NEXT: Equal +// CHECK-NEXT: Greater + +#include + +extern int libc_strcmp(const char *p1, const char *p2); + +int main() { + const char s1[] = "This is a string with label AOne"; + const char s2[] = "This is a string with label ATwo"; + + int val = libc_strcmp(s1, s2); + + if (val > 0) { + printf("Greater\n"); + } else if (val == 0) { + printf("Equal\n"); + } else { + printf("Lesser\n"); + } + + val = libc_strcmp(s2, s2); + if (val > 0) { + printf("Greater\n"); + } else if (val == 0) { + printf("Equal\n"); + } else { + printf("Lesser\n"); + } + + val = libc_strcmp(s2, s1); + if (val > 0) { + printf("Greater\n"); + } else if (val == 0) { + printf("Equal\n"); + } else { + printf("Lesser\n"); + } + + return 0; +} Index: tools/llvm-mctoll/test/smoke_test/test-1-test.c =================================================================== --- /dev/null +++ tools/llvm-mctoll/test/smoke_test/test-1-test.c @@ -0,0 +1,14 @@ +// RUN: clang -o %t.so %S/Inputs/test-1.c -shared -fPIC +// RUN: llvm-mctoll -d %t.so +// RUN: clang -o %t1 %s %t-dis.ll +// RUN: %t1 2>&1 | FileCheck %s +// CHECK: test_1_func result 5 + +#include + +extern long test_1_func(int a, long b); + +int main() { + printf("test_1_func result %ld\n", test_1_func(2, 3)); + return 0; +} Index: tools/llvm-mctoll/test/smoke_test/test-2-test.c =================================================================== --- /dev/null +++ tools/llvm-mctoll/test/smoke_test/test-2-test.c @@ -0,0 +1,14 @@ +// RUN: clang -o %t.so %S/Inputs/test-2.c -shared -fPIC +// RUN: llvm-mctoll -d %t.so +// RUN: clang -o %t1 %s %t-dis.ll +// RUN: %t1 2>&1 | FileCheck %s +// CHECK: test_2_func result 7 + +#include + +extern long test_2_func(int a, long b); + +int main() { + printf("test_2_func result %ld\n", test_2_func(2, 3)); + return 0; +} Index: tools/llvm-mctoll/test/smoke_test/test-3-test.c =================================================================== --- /dev/null +++ tools/llvm-mctoll/test/smoke_test/test-3-test.c @@ -0,0 +1,14 @@ +// RUN: clang -o %t.so %S/Inputs/test-3.c -shared -fPIC +// RUN: llvm-mctoll -d %t.so +// RUN: clang -o %t1 %s %t-dis.ll +// RUN: %t1 2>&1 | FileCheck %s +// CHECK: test_3_func result 66 + +#include + +extern int test_3_func(int a, int b); + +int main() { + printf("test_3_func result %d\n", test_3_func(234, 300)); + return 0; +} Index: tools/llvm-mctoll/test/smoke_test/variadic-call-test.c =================================================================== --- /dev/null +++ tools/llvm-mctoll/test/smoke_test/variadic-call-test.c @@ -0,0 +1,18 @@ +// RUN: clang -o %t %s +// RUN: llvm-mctoll -d %t +// RUN: clang -o %t1 %t-dis.ll +// RUN: %t1 2>&1 | FileCheck %s +// CHECK: Hello, World! +// CHECK: Hello again, World! +// CHECK: Sum = 6912 +// CHECK: Sum of 1234 and 5678 = 6912 + +#include + +int main() { + int a = 1234, b = 5678; + printf("Hello, World!\n"); + printf("Hello again, World!\n"); + printf("Sum = %d\n", a + b); + printf("Sum of %d and %d = %d\n", a, b, a + b); +} Index: tools/llvm-mctoll/test/unittests/ARM/FunctionPrototype/lit.local.cfg =================================================================== --- /dev/null +++ tools/llvm-mctoll/test/unittests/ARM/FunctionPrototype/lit.local.cfg @@ -0,0 +1 @@ +config.suffixes = ['.c'] Index: tools/llvm-mctoll/test/unittests/ARM/FunctionPrototype/six_args.c =================================================================== --- /dev/null +++ tools/llvm-mctoll/test/unittests/ARM/FunctionPrototype/six_args.c @@ -0,0 +1,9 @@ +// RUN: clang -target arm -mfloat-abi=soft -c -o %t.o %s +// RUN: llvm-mctoll -d -print-after-all %t.o 2>&1 | FileCheck %s +// CHECK: ARMFunctionPrototype start +// CHECK: i32 @func(i32, i32, i32, i32, i32, i32) +// CHECK: ARMFunctionPrototype end + +long func(int a, long b, int c, long d, int e, long f) { + return a + b + c + d + e + f; +} Index: tools/llvm-mctoll/test/unittests/ARM/PrologEpilog/lit.local.cfg =================================================================== --- /dev/null +++ tools/llvm-mctoll/test/unittests/ARM/PrologEpilog/lit.local.cfg @@ -0,0 +1 @@ +config.suffixes = ['.s'] Index: tools/llvm-mctoll/test/unittests/ARM/PrologEpilog/push_pop.s =================================================================== --- /dev/null +++ tools/llvm-mctoll/test/unittests/ARM/PrologEpilog/push_pop.s @@ -0,0 +1,25 @@ +# RUN: clang -target arm -mfloat-abi=soft -c -o %t.o %s +# RUN: llvm-mctoll -d -print-after-all %t.o 2>&1 | FileCheck %s + +# CHECK: ARMEliminatePrologEpilog start +# CHECK: Frame Objects: +# CHECK-NOT: $sp = STMDB_UPD %SP +# CHECK-NOT: $sp = SUBri %SP +# CHECK-NOT: $r11 = ADDri $sp +# CHECK-NOT: $sp = LDMIA_UPD %SP +# CHECK: ARMEliminatePrologEpilog end + +# test push pop + .global test1 + .type test1, %function +test1: + push {r11,lr} + add r11, sp, #4 + sub sp, sp, #16 + + mov r0, #1 + mov r1, #2 + + sub sp, r11, #4 + pop {r11, pc} + .size test1, .-test1 Index: tools/llvm-mctoll/test/unittests/ARM/PrologEpilog/push_pop_branch.s =================================================================== --- /dev/null +++ tools/llvm-mctoll/test/unittests/ARM/PrologEpilog/push_pop_branch.s @@ -0,0 +1,32 @@ +# RUN: clang -target arm -mfloat-abi=soft -c -o %t.o %s +# RUN: llvm-mctoll -d -print-after-all %t.o 2>&1 | FileCheck %s + +# CHECK: ARMEliminatePrologEpilog start +# CHECK: Frame Objects: +# CHECK-NOT: $sp = STMDB_UPD %SP +# CHECK-NOT: $sp = ADDri $r11 +# CHECK-NOT: $r11, $sp = LDR_POST_IMM $sp +# CHECK: ARMEliminatePrologEpilog end + +# test push pop and branch + .global test2 + .type test2, %function +test2: + push {r11,lr} + add r11, sp, #4 + sub sp, sp, #16 + mov r0, #1 + mov r1, #2 + bl max + sub sp, r11, #4 + pop {r11, pc} +max: + push {r11} + add r11, sp, #0 + sub sp, sp, #12 + cmp r0, r1 + movlt r0, r1 + add sp, r11, #0 + pop {r11} + bx lr + .size test2, .-test2 Index: tools/llvm-mctoll/test/unittests/ARM/PrologEpilog/stm_ldm_no_frame.s =================================================================== --- /dev/null +++ tools/llvm-mctoll/test/unittests/ARM/PrologEpilog/stm_ldm_no_frame.s @@ -0,0 +1,21 @@ +# RUN: clang -target arm -mfloat-abi=soft -c -o %t.o %s +# RUN: llvm-mctoll -d -print-after-all %t.o 2>&1 | FileCheck %s + +# CHECK: ARMEliminatePrologEpilog start +# CHECK: Frame Objects: +# CHECK-NOT: $sp = STMDB_UPD %SP +# CHECK-NOT: LDMIA $sp, 14, $noreg, +# CHECK: ARMEliminatePrologEpilog end + +# test stm ldm with no frame + .global test3 + .type test3, %function +test3: + stmdb r13!, {r0-r3} + stmdb r13!, {r4-r12,r13,r14} + + mov r3, #0 + mov r0,r3 + + ldmia r13, {r4-r11, r13, r15} + .size test3, .-test3 Index: tools/llvm-mctoll/test/unittests/ARM/PrologEpilog/stm_ldm_with_frame.s =================================================================== --- /dev/null +++ tools/llvm-mctoll/test/unittests/ARM/PrologEpilog/stm_ldm_with_frame.s @@ -0,0 +1,25 @@ +# RUN: clang -target arm -mfloat-abi=soft -c -o %t.o %s +# RUN: llvm-mctoll -d -print-after-all %t.o 2>&1 | FileCheck %s + +# CHECK: ARMEliminatePrologEpilog start +# CHECK: Frame Objects: +# CHECK-NOT: $r12 = MOVr $sp +# CHECK-NOT: $sp = STMDB_UPD $sp, 14 +# CHECK-NOT: $r11 = SUBri $r12, 16, 14, +# CHECK-NOT: LDMDB $sp, 14, +# CHECK: ARMEliminatePrologEpilog end + +# test stm ldm with frame + .global test4 + .type test4, %function +test4: + mov r12, r13 + stmdb r13!, {r0-r3} + stmdb r13!, {r4-r12, r14} + sub r11, r12, #16 + + mov r3, #0 + mov r0,r3 + + ldmdb r13, {r4-r11, r13, r15} + .size test4, .-test4 Index: tools/llvm-mctoll/test/unittests/ARM/PrologEpilog/str_ldr.s =================================================================== --- /dev/null +++ tools/llvm-mctoll/test/unittests/ARM/PrologEpilog/str_ldr.s @@ -0,0 +1,30 @@ +# RUN: clang -target arm -mfloat-abi=soft -c -o %t.o %s +# RUN: llvm-mctoll -d -print-after-all %t.o 2>&1 | FileCheck %s + +# CHECK: ARMEliminatePrologEpilog start +# CHECK: Frame Objects: +# CHECK-NOT: early-clobber $sp = STR_PRE_IMM $r11 +# CHECK-NOT: $r11 = ADDri $sp, 0, 14, +# CHECK-NOT: $sp = SUBri $r11, 0, 14, +# CHECK-NOT: $r11, $sp = LDR_POST_IMM $sp, +# CHECK: ARMEliminatePrologEpilog end + +# test str ldr + .text + .align 4 + .code 32 + .global test + .type test, %function +test: + str fp, [sp, #-4]! + add fp, sp, #0 + + mov r3, #0 + mov r0,r3 + + sub sp, fp, #0 + ldr fp, [sp], #4 + + .size test, .-test + .global test + .type test, %function Index: tools/llvm-mctoll/test/unittests/ARMInstrs/add-dis.ll =================================================================== --- /dev/null +++ tools/llvm-mctoll/test/unittests/ARMInstrs/add-dis.ll @@ -0,0 +1,20 @@ +; ModuleID = 'add.o' +source_filename = "add.o" +target datalayout = "e-m:e-p:32:32-i64:64-v128:64:128-a:0:32-n32-S64" + +define i32 @funcAddReg(i32 %arg.1, i32 %arg.2) { + %stack.3 = alloca i32 + %stack.4 = alloca i32 + %stack.5 = alloca i32 + %stack.6 = alloca i32 + %1 = add i32 %arg.2, 0 + %2 = add i32 %arg.1, 0 + store i32 %1, i32* %stack.3 + store i32 %2, i32* %stack.4 + %3 = load i32, i32* %stack.3 + %4 = load i32, i32* %stack.4 + %5 = add i32 %3, %4 + store i32 %1, i32* %stack.5 + store i32 %2, i32* %stack.6 + ret i32 %5 +} Index: tools/llvm-mctoll/test/unittests/ARMInstrs/add.s =================================================================== --- /dev/null +++ tools/llvm-mctoll/test/unittests/ARMInstrs/add.s @@ -0,0 +1,19 @@ + .text + .align 4 + .code 32 + .global funcAddReg + .type funcAddReg, %function +funcAddReg: + sub sp, sp, #16 + mov r2, r1 + mov r3, r0 + str r0, [sp, #12] + str r1, [sp, #8] + ldr r0, [sp, #12] + ldr r1, [sp, #8] + add r0, r0, r1 + str r2, [sp, #4] + str r3, [sp] + add sp, sp, #16 + bx lr + .size funcAddReg, .-funcAddReg Index: tools/llvm-mctoll/test/unittests/ARMInstrs/harness.c =================================================================== --- /dev/null +++ tools/llvm-mctoll/test/unittests/ARMInstrs/harness.c @@ -0,0 +1,7 @@ +#include + +extern int funcAddReg(int a, int b); +int main() { + printf("funcAddReg result is %d\n", funcAddReg(2, 3)); + return 0; +} Index: tools/llvm-mctoll/test/unittests/ARMInstrs/inst-test.py =================================================================== --- /dev/null +++ tools/llvm-mctoll/test/unittests/ARMInstrs/inst-test.py @@ -0,0 +1,225 @@ +#!/usr/bin/env python +import os +import sys +import argparse +import subprocess +import filecmp +import difflib +import shutil +from distutils.spawn import find_executable + +test_src_harness = 'harness.c' +test_dir = os.path.dirname(os.path.realpath(__file__)) +test_sources = [] +for file in os.listdir(test_dir): + if os.path.splitext(file)[1] == '.s': + test_sources.append(file) +clang_bin='clang' +llc_bin='llc' +clang_executable=None +llc_executable=None +generated_files=[] +generated_results=[] + +def get_args(): + '''Get arguments''' + # Assign description to the help doc + parser = argparse.ArgumentParser( + description='Get script arguments') + # Add arguments + parser.add_argument( + '-b', '--binary', type=str, help='test specified llvm-mctoll binary', required=True) + parser.add_argument( + '-l', '--llvm', type=str, help='directory with LLVM binaries', default=None) + # Default is to not clean out artifacts created during the smoke-test + # So, if -c is specified, the action is to set it to true + parser.add_argument( + '-c', '--clean', help='Clean all artifacts', action='store_true') + # Array for all arguments passed to script + args = parser.parse_args() + # Assign args to variables + test_bin = args.binary + llvm_dir = args.llvm + clean = args.clean + print clean + # Return all variable values + return test_bin, llvm_dir, clean, parser + +def main(argv): + mctoll_binary, llvm_binary_dir, clean_after_run, argparser = get_args() + # Check sanity llvm_binary_dir, if specified + if llvm_binary_dir is None: + # Make sure clang is available + output = find_executable(clang_bin) + if output: + print "Using clang in command-line path" + else: + print "clang not found in path. Specify using -l option" + argparser.print_help() + sys.exit(-1) + # Make sure clang is available + output = find_executable(llc_bin) + if output: + print "Using llc in command-line path" + else: + print "llc not found in path. Specify using -l option" + argparser.print_help() + sys.exit(-1) + else: + if os.path.isdir(llvm_binary_dir): + # Make sure clang is available + clang_executable = os.path.join(llvm_binary_dir.rstrip(os.sep), clang_bin) + if os.path.exists(os.path.join(clang_executable)): + print "Using clang : " + clang_executable + else: + print "No clang found in " + llvm_binary_dir + sys.exit(2) + # Make sure llc is available + llc_executable = os.path.join(llvm_binary_dir.rstrip(os.sep), llc_bin) + if os.path.exists(os.path.join(llc_executable)): + print "Using llc : " + llc_executable + else: + print "No llc found in " + llvm_binary_dir + sys.exit(2) + else: + print "Directory " + llvm_binary_dir + " does not exist" + sys.exit(2) + + # Compile assemble file to object file + print "Looking in test directory " + test_dir + for test_src_name in test_sources : + test_src_full_path = os.path.join(test_dir.rstrip(os.sep), test_src_name) + print "Compiling " + test_src_full_path + subprocess.call([clang_executable, '-target', 'arm', '-c', test_src_full_path]) + # Add the .o to generated_files + generated_files.append(os.path.splitext(test_src_name)[0]+'.o') + + # Compile harness.c to ARM object file + harness_src_full_path = os.path.join(test_dir.rstrip(os.sep), test_src_harness) + print "Compiling ARM " + harness_src_full_path + subprocess.call([clang_executable, '-target', 'arm','-c', harness_src_full_path]) + os.rename(os.path.splitext(test_src_harness)[0]+'.o', os.path.splitext(test_src_harness)[0]+'_arm.o') + # Add the .o to generated_files + generated_files.append(os.path.splitext(test_src_harness)[0]+'_arm.o') + + # Link ARM object files with harness_arm.o to generate ARM executable file: + base_executable = os.path.splitext(test_src_harness)[0] + test_obj_list=[base_executable+'_arm.o'] + for test_src_name in test_sources : + test_obj_list.append(os.path.splitext(test_src_name)[0]+'.o') + + print "Linking ", + print test_obj_list + subprocess.call([clang_executable,"--target=arm-linux-gnueabi", "-static", "-o", base_executable] + test_obj_list) + # Add the base executable to generated_files + generated_results.append(base_executable) + + # Raise test objects to generate .ll files + for test_src_name in test_sources : + test_name = os.path.splitext(test_src_name)[0] + test_obj = test_name +'.o' + raised_test_ll = test_name+"-dis.ll" + #ll_output = open(raised_test_ll, "w") + #Run mctoll on test-name.o to result in test-name-dis.ll + #subprocess.call([mctoll_binary, '-d', test_obj], stdout=ll_output, stderr=ll_output) + #Close file + #ll_output.close() + #Add the ll file to generated_files + #generated_files.append(raised_test_ll) + + # Compile the ll files resulting from raising + print "Raising " + raised_test_ll + # Running llc -c test-name-dis.s + subprocess.call([llc_executable, raised_test_ll]) + # Add the .s file to generated_files + generated_files.append(test_name+'-dis.s') + + # Assemble the resulting .s to X86 object files using clang + # Running clang -c test-name-dis.s + subprocess.call([clang_executable, '-c', os.path.splitext(raised_test_ll)[0]+'.s']) + # Add the .o file to generated_files + generated_files.append(test_name+'-dis.o') + + # Compile harness.c to harness_x86.o + print "Compiling X86 " + harness_src_full_path + subprocess.call([clang_executable,'-c', harness_src_full_path]) + os.rename(os.path.splitext(test_src_harness)[0]+'.o', os.path.splitext(test_src_harness)[0]+'_x86.o') + # Add the .o to generated_files + generated_files.append(os.path.splitext(test_src_harness)[0]+'_x86.o') + + # Link harness_x86.o with X86 object files to generate harness-dis + base_executable_dis = os.path.splitext(test_src_harness)[0]+'-dis' + test_obj_list_dis=[base_executable+'_x86.o'] + for test_src_name in test_sources : + test_obj_list_dis.append(os.path.splitext(test_src_name)[0]+'-dis.o') + + print "Linking ", + print test_obj_list_dis + subprocess.call([clang_executable, "-o", base_executable_dis] + test_obj_list_dis) + # Add the generated executable file to generated_files + generated_results.append(base_executable_dis) + + # Now compare the execution of harness and harness-dis + gold_executable = './'+os.path.splitext(test_src_harness)[0] + raised_executable = gold_executable+'-dis' + gold_out_file_name = "gold_output" + gold_output = open(gold_out_file_name, "w") + print "Running " + gold_executable + + subprocess.call(['qemu-arm', gold_executable], stdout=gold_output) + # Close file + gold_output.close() + # Add the generated output file + generated_results.append(gold_out_file_name) + raised_out_file_name = "raised_output" + raised_output = open(raised_out_file_name, "w") + + print "Running " + raised_executable + subprocess.call([raised_executable], stdout=raised_output) + # Close file + raised_output.close() + # Add the generated output file + generated_results.append(raised_out_file_name) + + # Compare gold output with raised execution output + diff_file = "diff" + if filecmp.cmp(gold_out_file_name, raised_out_file_name) : + print "Tests PASSED" + else : + print "Tests FAILED" + a = open('gold_output').readlines() + b = open('raised_output').readlines() + diff_result = open(diff_file, 'w+') + stdout = diff_result + diff = difflib.ndiff(a, b) + stdout.writelines(diff) + diff_result.close() + + generated_results.append(diff_file) + + diff_result = open(diff_file, 'r+') + for line in diff_result: + if line[0]=='-': + print line.split(' ')[1]+' Failed!' + + # Move the generated files to corresponding folder + if os.path.exists("imm_files"): + shutil.rmtree("imm_files") + if os.path.exists("results"): + shutil.rmtree("results") + + os.mkdir("imm_files") + os.mkdir("results") + + for f in generated_files: + shutil.move(f, "imm_files") + for r in generated_results: + shutil.move(r, "results") + + if clean_after_run: + print "Deleting all created artifacts ..." + shutil.rmtree("imm_files") + shutil.rmtree("results") + +if __name__ == "__main__": + main(sys.argv[1:])