Index: lib/Target/WebAssembly/WebAssemblyInstrSIMD.td
===================================================================
--- lib/Target/WebAssembly/WebAssemblyInstrSIMD.td
+++ lib/Target/WebAssembly/WebAssemblyInstrSIMD.td
@@ -371,6 +371,9 @@
 defm "" : SIMDAbs<v4f32, "f32x4", 127>;
 defm "" : SIMDAbs<v2f64, "f64x2", 128>;
 
+defm MIN : SIMDBinaryFP<fminnan, "min", 129>;
+defm MAX : SIMDBinaryFP<fmaxnan, "max", 131>;
+
 } // Defs = [ARGUMENTS]
 
 // Def load and store patterns from WebAssemblyInstrMemory.td for vector types
Index: test/CodeGen/WebAssembly/simd-arith.ll
===================================================================
--- test/CodeGen/WebAssembly/simd-arith.ll
+++ test/CodeGen/WebAssembly/simd-arith.ll
@@ -679,6 +679,34 @@
   ret <4 x float> %a
 }
 
+; CHECK-LABEL: min_v4f32:
+; NO-SIMD128-NOT: f32x4
+; SIMD128-NEXT: .param v128{{$}}
+; SIMD128-NEXT: .result v128{{$}}
+; SIMD128-NEXT: f32.const $push[[L0:[0-9]+]]=, 0x0p0
+; SIMD128-NEXT: f32x4.splat $push[[L1:[0-9]+]]=, $pop[[L0]]
+; SIMD128-NEXT: f32x4.min $push[[R:[0-9]+]]=, $0, $pop[[L1]]{{$}}
+; SIMD128-NEXT: return $pop[[R]]{{$}}
+define <4 x float> @min_v4f32(<4 x float> %x) {
+  %cmps = fcmp ult <4 x float> %x, zeroinitializer
+  %a = select <4 x i1> %cmps, <4 x float> %x, <4 x float> zeroinitializer
+  ret <4 x float> %a
+}
+
+; CHECK-LABEL: max_v4f32:
+; NO-SIMD128-NOT: f32x4
+; SIMD128-NEXT: .param v128{{$}}
+; SIMD128-NEXT: .result v128{{$}}
+; SIMD128-NEXT: f32.const $push[[L0:[0-9]+]]=, 0x0p0
+; SIMD128-NEXT: f32x4.splat $push[[L1:[0-9]+]]=, $pop[[L0]]
+; SIMD128-NEXT: f32x4.max $push[[R:[0-9]+]]=, $0, $pop[[L1]]{{$}}
+; SIMD128-NEXT: return $pop[[R]]{{$}}
+define <4 x float> @max_v4f32(<4 x float> %x) {
+  %cmps = fcmp ugt <4 x float> %x, zeroinitializer
+  %a = select <4 x i1> %cmps, <4 x float> %x, <4 x float> zeroinitializer
+  ret <4 x float> %a
+}
+
 ; CHECK-LABEL: add_v4f32:
 ; NO-SIMD128-NOT: f32x4
 ; SIMD128-NEXT: .param v128, v128{{$}}
@@ -749,6 +777,33 @@
   ret <2 x double> %a
 }
 
+; CHECK-LABEL: min_v2f64:
+; NO-SIMD128-NOT: f64x2
+; SIMD128-NEXT: .param v128{{$}}
+; SIMD128-NEXT: .result v128{{$}}
+; SIMD128-NEXT: f64.const $push[[L0:[0-9]+]]=, 0x0p0
+; SIMD128-NEXT: f64x2.splat $push[[L1:[0-9]+]]=, $pop[[L0]]
+; SIMD128-NEXT: f64x2.min $push[[R:[0-9]+]]=, $0, $pop[[L1]]{{$}}
+; SIMD128-NEXT: return $pop[[R]]{{$}}
+define <2 x double> @min_v2f64(<2 x double> %x) {
+  %cmps = fcmp ult <2 x double> %x, zeroinitializer
+  %a = select <2 x i1> %cmps, <2 x double> %x, <2 x double> zeroinitializer
+  ret <2 x double> %a
+}
+
+; CHECK-LABEL: max_v2f64:
+; NO-SIMD128-NOT: f64x2
+; SIMD128-NEXT: .param v128{{$}}
+; SIMD128-NEXT: .result v128{{$}}
+; SIMD128-NEXT: f64.const $push[[L0:[0-9]+]]=, 0x0p0
+; SIMD128-NEXT: f64x2.splat $push[[L1:[0-9]+]]=, $pop[[L0]]
+; SIMD128-NEXT: f64x2.max $push[[R:[0-9]+]]=, $0, $pop[[L1]]{{$}}
+; SIMD128-NEXT: return $pop[[R]]{{$}}
+define <2 x double> @max_v2f64(<2 x double> %x) {
+  %cmps = fcmp ugt <2 x double> %x, zeroinitializer
+  %a = select <2 x i1> %cmps, <2 x double> %x,  <2 x double> zeroinitializer
+  ret <2 x double> %a
+}
 
 ; CHECK-LABEL: add_v2f64:
 ; NO-SIMD128-NOT: f64x2
Index: test/MC/WebAssembly/simd-encodings.s
===================================================================
--- test/MC/WebAssembly/simd-encodings.s
+++ test/MC/WebAssembly/simd-encodings.s
@@ -331,6 +331,18 @@
     # CHECK: f64x2.abs # encoding: [0xfd,0x80]
     f64x2.abs
 
+    # CHECK: f32x4.min # encoding: [0xfd,0x81]
+    f32x4.min
+
+    # CHECK: f64x2.min # encoding: [0xfd,0x82]
+    f64x2.min
+
+    # CHECK: f32x4.max # encoding: [0xfd,0x83]
+    f32x4.max
+
+    # CHECK: f64x2.max # encoding: [0xfd,0x84]
+    f64x2.max
+
     # CHECK: f32x4.add # encoding: [0xfd,0x85]
     f32x4.add