Index: include/llvm/CodeGen/TargetRegisterInfo.h =================================================================== --- include/llvm/CodeGen/TargetRegisterInfo.h +++ include/llvm/CodeGen/TargetRegisterInfo.h @@ -824,13 +824,6 @@ // Do nothing. } - /// The creation of multiple copy hints have been implemented in - /// weightCalcHelper(), but since this affects so many tests for many - /// targets, this is temporarily disabled per default. THIS SHOULD BE - /// "GENERAL GOODNESS" and hopefully all targets will update their tests - /// and enable this soon. This hook should then be removed. - virtual bool enableMultipleCopyHints() const { return false; } - /// Allow the target to reverse allocation order of local live ranges. This /// will generally allocate shorter local live ranges first. For targets with /// many registers, this could reduce regalloc compile time by a large Index: lib/CodeGen/CalcSpillWeights.cpp =================================================================== --- lib/CodeGen/CalcSpillWeights.cpp +++ lib/CodeGen/CalcSpillWeights.cpp @@ -70,15 +70,6 @@ return sub == hsub ? hreg : 0; const TargetRegisterClass *rc = mri.getRegClass(reg); - if (!tri.enableMultipleCopyHints()) { - // Only allow physreg hints in rc. - if (sub == 0) - return rc->contains(hreg) ? hreg : 0; - - // reg:sub should match the physreg hreg. - return tri.getMatchingSuperReg(hreg, sub, rc); - } - unsigned CopiedPReg = (hsub ? tri.getSubReg(hreg, hsub) : hreg); if (rc->contains(CopiedPReg)) return CopiedPReg; @@ -199,31 +190,19 @@ unsigned Reg; float Weight; bool IsPhys; - unsigned HintOrder; - CopyHint(unsigned R, float W, bool P, unsigned HR) : - Reg(R), Weight(W), IsPhys(P), HintOrder(HR) {} + CopyHint(unsigned R, float W, bool P) : + Reg(R), Weight(W), IsPhys(P) {} bool operator<(const CopyHint &rhs) const { // Always prefer any physreg hint. if (IsPhys != rhs.IsPhys) return (IsPhys && !rhs.IsPhys); if (Weight != rhs.Weight) return (Weight > rhs.Weight); - - // This is just a temporary way to achive NFC for targets that don't - // enable multiple copy hints. HintOrder should be removed when all - // targets return true in enableMultipleCopyHints(). - return (HintOrder < rhs.HintOrder); - -#if 0 // Should replace the HintOrder check, see above. - // (just for the purpose of maintaining the set) - return Reg < rhs.Reg; -#endif + return Reg < rhs.Reg; // Tie-breaker. } }; std::set CopyHints; - // Temporary: see comment for HintOrder above. - unsigned CopyHintOrder = 0; for (MachineRegisterInfo::reg_instr_iterator I = mri.reg_instr_begin(li.reg), E = mri.reg_instr_end(); I != E; ) { @@ -263,8 +242,7 @@ } // Get allocation hints from copies. - if (!mi->isCopy() || - (TargetHint.first != 0 && !tri.enableMultipleCopyHints())) + if (!mi->isCopy()) continue; unsigned hint = copyHint(mi, li.reg, tri, mri); if (!hint) @@ -275,8 +253,7 @@ // FIXME: we probably shouldn't use floats at all. volatile float hweight = Hint[hint] += weight; if (TargetRegisterInfo::isVirtualRegister(hint) || mri.isAllocatable(hint)) - CopyHints.insert(CopyHint(hint, hweight, tri.isPhysicalRegister(hint), - (tri.enableMultipleCopyHints() ? hint : CopyHintOrder++))); + CopyHints.insert(CopyHint(hint, hweight, tri.isPhysicalRegister(hint))); } Hint.clear(); @@ -294,8 +271,6 @@ // Don't add the same reg twice or the target-type hint again. continue; mri.addRegAllocationHint(li.reg, Hint.Reg); - if (!tri.enableMultipleCopyHints()) - break; } // Weakly boost the spill weight of hinted registers. Index: lib/Target/AArch64/AArch64RegisterInfo.h =================================================================== --- lib/Target/AArch64/AArch64RegisterInfo.h +++ lib/Target/AArch64/AArch64RegisterInfo.h @@ -84,8 +84,6 @@ const TargetRegisterClass * getCrossCopyRegClass(const TargetRegisterClass *RC) const override; - bool enableMultipleCopyHints() const override { return true; } - bool requiresRegisterScavenging(const MachineFunction &MF) const override; bool useFPForScavengingIndex(const MachineFunction &MF) const override; bool requiresFrameIndexScavenging(const MachineFunction &MF) const override; Index: lib/Target/AMDGPU/AMDGPURegisterInfo.h =================================================================== --- lib/Target/AMDGPU/AMDGPURegisterInfo.h +++ lib/Target/AMDGPU/AMDGPURegisterInfo.h @@ -27,8 +27,6 @@ struct AMDGPURegisterInfo : public AMDGPUGenRegisterInfo { AMDGPURegisterInfo(); - bool enableMultipleCopyHints() const override { return true; } - /// \returns the sub reg enum value for the given \p Channel /// (e.g. getSubRegFromChannel(0) -> AMDGPU::sub0) static unsigned getSubRegFromChannel(unsigned Channel); Index: lib/Target/ARM/ARMBaseRegisterInfo.h =================================================================== --- lib/Target/ARM/ARMBaseRegisterInfo.h +++ lib/Target/ARM/ARMBaseRegisterInfo.h @@ -156,7 +156,6 @@ void updateRegAllocHint(unsigned Reg, unsigned NewReg, MachineFunction &MF) const override; - bool enableMultipleCopyHints() const override { return true; } bool hasBasePointer(const MachineFunction &MF) const; Index: lib/Target/BPF/BPFRegisterInfo.h =================================================================== --- lib/Target/BPF/BPFRegisterInfo.h +++ lib/Target/BPF/BPFRegisterInfo.h @@ -29,8 +29,6 @@ BitVector getReservedRegs(const MachineFunction &MF) const override; - bool enableMultipleCopyHints() const override { return true; } - void eliminateFrameIndex(MachineBasicBlock::iterator MI, int SPAdj, unsigned FIOperandNum, RegScavenger *RS = nullptr) const override; Index: lib/Target/Hexagon/HexagonRegisterInfo.h =================================================================== --- lib/Target/Hexagon/HexagonRegisterInfo.h +++ lib/Target/Hexagon/HexagonRegisterInfo.h @@ -39,8 +39,6 @@ BitVector getReservedRegs(const MachineFunction &MF) const override; - bool enableMultipleCopyHints() const override { return true; } - void eliminateFrameIndex(MachineBasicBlock::iterator II, int SPAdj, unsigned FIOperandNum, RegScavenger *RS = nullptr) const override; Index: lib/Target/Mips/MipsRegisterInfo.h =================================================================== --- lib/Target/Mips/MipsRegisterInfo.h +++ lib/Target/Mips/MipsRegisterInfo.h @@ -57,8 +57,6 @@ BitVector getReservedRegs(const MachineFunction &MF) const override; - bool enableMultipleCopyHints() const override { return true; } - bool requiresRegisterScavenging(const MachineFunction &MF) const override; bool trackLivenessAfterRegAlloc(const MachineFunction &MF) const override; Index: lib/Target/PowerPC/PPCRegisterInfo.h =================================================================== --- lib/Target/PowerPC/PPCRegisterInfo.h +++ lib/Target/PowerPC/PPCRegisterInfo.h @@ -85,8 +85,6 @@ BitVector getReservedRegs(const MachineFunction &MF) const override; bool isCallerPreservedPhysReg(unsigned PhysReg, const MachineFunction &MF) const override; - bool enableMultipleCopyHints() const override { return true; } - /// We require the register scavenger. bool requiresRegisterScavenging(const MachineFunction &MF) const override { return true; Index: lib/Target/Sparc/SparcRegisterInfo.h =================================================================== --- lib/Target/Sparc/SparcRegisterInfo.h +++ lib/Target/Sparc/SparcRegisterInfo.h @@ -35,8 +35,6 @@ const TargetRegisterClass *getPointerRegClass(const MachineFunction &MF, unsigned Kind) const override; - bool enableMultipleCopyHints() const override { return true; } - void eliminateFrameIndex(MachineBasicBlock::iterator II, int SPAdj, unsigned FIOperandNum, RegScavenger *RS = nullptr) const override; Index: lib/Target/SystemZ/SystemZRegisterInfo.h =================================================================== --- lib/Target/SystemZ/SystemZRegisterInfo.h +++ lib/Target/SystemZ/SystemZRegisterInfo.h @@ -57,8 +57,6 @@ const VirtRegMap *VRM, const LiveRegMatrix *Matrix) const override; - bool enableMultipleCopyHints() const override { return true; } - // Override TargetRegisterInfo.h. bool requiresRegisterScavenging(const MachineFunction &MF) const override { return true; Index: lib/Target/X86/X86RegisterInfo.h =================================================================== --- lib/Target/X86/X86RegisterInfo.h +++ lib/Target/X86/X86RegisterInfo.h @@ -95,8 +95,6 @@ unsigned getRegPressureLimit(const TargetRegisterClass *RC, MachineFunction &MF) const override; - bool enableMultipleCopyHints() const override { return true; } - /// getCalleeSavedRegs - Return a null-terminated list of all of the /// callee-save registers on this target. const MCPhysReg * Index: lib/Target/XCore/XCoreRegisterInfo.h =================================================================== --- lib/Target/XCore/XCoreRegisterInfo.h +++ lib/Target/XCore/XCoreRegisterInfo.h @@ -33,8 +33,6 @@ BitVector getReservedRegs(const MachineFunction &MF) const override; - bool enableMultipleCopyHints() const override { return true; } - bool requiresRegisterScavenging(const MachineFunction &MF) const override; bool trackLivenessAfterRegAlloc(const MachineFunction &MF) const override;