Index: llvm/trunk/lib/Target/PowerPC/PPCAsmPrinter.cpp =================================================================== --- llvm/trunk/lib/Target/PowerPC/PPCAsmPrinter.cpp +++ llvm/trunk/lib/Target/PowerPC/PPCAsmPrinter.cpp @@ -279,6 +279,21 @@ if (MI->getOperand(OpNo).isImm()) O << "i"; return false; + case 'x': + if(!MI->getOperand(OpNo).isReg()) + return true; + // This operand uses VSX numbering. + // If the operand is a VMX register, convert it to a VSX register. + unsigned Reg = MI->getOperand(OpNo).getReg(); + if (PPCInstrInfo::isVRRegister(Reg)) + Reg = PPC::VSX32 + (Reg - PPC::V0); + else if (PPCInstrInfo::isVFRegister(Reg)) + Reg = PPC::VSX32 + (Reg - PPC::VF0); + const char *RegName; + RegName = PPCInstPrinter::getRegisterName(Reg); + RegName = stripRegisterPrefix(RegName); + O << RegName; + return false; } } Index: llvm/trunk/test/CodeGen/PowerPC/inlineasm-vsx-reg.ll =================================================================== --- llvm/trunk/test/CodeGen/PowerPC/inlineasm-vsx-reg.ll +++ llvm/trunk/test/CodeGen/PowerPC/inlineasm-vsx-reg.ll @@ -0,0 +1,22 @@ +; RUN: llc -verify-machineinstrs -ppc-vsr-nums-as-vr -ppc-asm-full-reg-names -mcpu=pwr9 -mtriple=powerpc64le-unknown-unknown < %s | FileCheck %s +define signext i32 @foo(<4 x float> %__A) { +entry: + %0 = tail call { i32, <4 x float> } asm "xxsldwi ${1:x},${2:x},${2:x},3;\0Axscvspdp ${1:x},${1:x};\0Afctiw $1,$1;\0Amfvsrd $0,${1:x};\0A", "=r,=&^wa,^wa"(<4 x float> %__A) + %asmresult = extractvalue { i32, <4 x float> } %0, 0 + ret i32 %asmresult +; CHECK: #APP +; CHECK: xxsldwi vs0, v2, v2, 3 +; CHECK: xscvspdp f0, f0 +; CHECK: fctiw f0, f0 +; CHECK: mffprd r3, f0 +; CHECK: #NO_APP +} + +define double @test() { + entry: + %0 = tail call double asm "mtvsrd ${0:x}, 1", "=^ws,~{f0},~{f1},~{f2},~{f3},~{f4},~{f5},~{f6},~{f7},~{f8},~{f9},~{f10},~{f11},~{f12},~{f13},~{f14}"() + ret double %0 +; CHECK: #APP +; CHECK: mtvsrd v2, r1 +; CHECK: #NO_APP +}