Index: lib/Target/Mips/MipsInstrInfo.h =================================================================== --- lib/Target/Mips/MipsInstrInfo.h +++ lib/Target/Mips/MipsInstrInfo.h @@ -122,6 +122,12 @@ MachineInstrBuilder genInstrWithNewOpc(unsigned NewOpc, MachineBasicBlock::iterator I) const; + DebugLoc + getDebugLoc(MachineBasicBlock::iterator I, MachineBasicBlock &MBB) const { + return (I != MBB.end() && !I->isDebugValue()) ? I->getDebugLoc() + : DebugLoc(); + } + protected: bool isZeroImm(const MachineOperand &op) const; Index: lib/Target/Mips/MipsSEFrameLowering.cpp =================================================================== --- lib/Target/Mips/MipsSEFrameLowering.cpp +++ lib/Target/Mips/MipsSEFrameLowering.cpp @@ -386,7 +386,7 @@ *static_cast(STI.getRegisterInfo()); MachineBasicBlock::iterator MBBI = MBB.begin(); - DebugLoc dl = MBBI != MBB.end() ? MBBI->getDebugLoc() : DebugLoc(); + DebugLoc dl = TII.getDebugLoc(MBBI, MBB); unsigned SP = STI.isABI_N64() ? Mips::SP_64 : Mips::SP; unsigned FP = STI.isABI_N64() ? Mips::FP_64 : Mips::FP; unsigned ZERO = STI.isABI_N64() ? Mips::ZERO_64 : Mips::ZERO; Index: lib/Target/Mips/MipsSEISelDAGToDAG.cpp =================================================================== --- lib/Target/Mips/MipsSEISelDAGToDAG.cpp +++ lib/Target/Mips/MipsSEISelDAGToDAG.cpp @@ -130,8 +130,8 @@ MachineBasicBlock &MBB = MF.front(); MachineBasicBlock::iterator I = MBB.begin(); MachineRegisterInfo &RegInfo = MF.getRegInfo(); - const TargetInstrInfo &TII = *Subtarget->getInstrInfo(); - DebugLoc DL = I != MBB.end() ? I->getDebugLoc() : DebugLoc(); + const MipsInstrInfo &TII = *Subtarget->getInstrInfo(); + DebugLoc DL = TII.getDebugLoc(I, MBB); unsigned V0, V1, GlobalBaseReg = MipsFI->getGlobalBaseReg(); const TargetRegisterClass *RC; const MipsABIInfo &ABI = static_cast(TM).getABI(); Index: lib/Target/Mips/MipsSEInstrInfo.cpp =================================================================== --- lib/Target/Mips/MipsSEInstrInfo.cpp +++ lib/Target/Mips/MipsSEInstrInfo.cpp @@ -181,8 +181,7 @@ unsigned SrcReg, bool isKill, int FI, const TargetRegisterClass *RC, const TargetRegisterInfo *TRI, int64_t Offset) const { - DebugLoc DL; - if (I != MBB.end()) DL = I->getDebugLoc(); + DebugLoc DL = getDebugLoc(I, MBB); MachineMemOperand *MMO = GetMemOperand(MBB, FI, MachineMemOperand::MOStore); unsigned Opc = 0; @@ -360,7 +359,7 @@ MachineBasicBlock &MBB, MachineBasicBlock::iterator I) const { const MipsSubtarget &STI = Subtarget; - DebugLoc DL = I != MBB.end() ? I->getDebugLoc() : DebugLoc(); + DebugLoc DL = getDebugLoc(I, MBB); unsigned ADDu = STI.isABI_N64() ? Mips::DADDu : Mips::ADDu; unsigned ADDiu = STI.isABI_N64() ? Mips::DADDiu : Mips::ADDiu; Index: test/DebugInfo/Mips/delay-slot.ll =================================================================== --- test/DebugInfo/Mips/delay-slot.ll +++ test/DebugInfo/Mips/delay-slot.ll @@ -13,8 +13,7 @@ ; CHECK: Address Line Column File ISA Discriminator Flags ; CHECK: ------------------ ------ ------ ------ --- ------------- ------------- ; CHECK: 0x0000000000000000 1 0 1 0 0 is_stmt -; CHECK: 0x0000000000000000 1 0 1 0 0 is_stmt prologue_end -; CHECK: 0x0000000000000008 2 0 1 0 0 is_stmt +; CHECK: 0x0000000000000008 2 0 1 0 0 is_stmt prologue_end ; CHECK: 0x0000000000000020 3 0 1 0 0 is_stmt ; CHECK: 0x0000000000000030 4 0 1 0 0 is_stmt ; CHECK: 0x0000000000000040 5 0 1 0 0 is_stmt Index: test/DebugInfo/Mips/prologue_end.ll =================================================================== --- /dev/null +++ test/DebugInfo/Mips/prologue_end.ll @@ -0,0 +1,88 @@ +; RUN: llc -mtriple=mips-linux-gnu -O0 -relocation-model=static < %s | FileCheck %s -check-prefix=STATIC +; RUN: llc -mtriple=mips-linux-gnu -O0 -relocation-model=static -disable-fp-elim < %s | FileCheck %s -check-prefix=STATIC-FP +; RUN: llc -mtriple=mips-linux-gnu -O0 -relocation-model=pic < %s | FileCheck %s -check-prefix=PIC +; RUN: llc -mtriple=mips-linux-gnu -O0 -relocation-model=pic -disable-fp-elim < %s | FileCheck %s -check-prefix=PIC-FP + + +; Generated using clang -target mipsel-linux-gnu -g -S test.c -emit-llvm -o test.ll +; test.c: +; 1: int g1 = 2; +; 2: +; 3: void test(int arg1) { +; 4: g1 = arg1; +; 5: } + + +@g1 = global i32 2, align 4 + +; Function Attrs: nounwind +define void @test(i32 signext %arg1) #0 { +entry: + %arg1.addr = alloca i32, align 4 + store i32 %arg1, i32* %arg1.addr, align 4 + call void @llvm.dbg.declare(metadata i32* %arg1.addr, metadata !14, metadata !15), !dbg !16 + %0 = load i32* %arg1.addr, align 4, !dbg !17 + store i32 %0, i32* @g1, align 4, !dbg !18 + ret void, !dbg !19 + +; STATIC: addiu $sp, $sp, -{{[0-9]+}} +; STATIC: sw $4, {{[0-9]+}}($sp) +; STATIC: .loc 1 4 3 prologue_end +; STATIC: lui ${{[0-9]+}}, %hi(g1) + +; STATIC-FP: addiu $sp, $sp, -{{[0-9]+}} +; STATIC-FP: sw $fp, {{[0-9]+}}($sp) +; STATIC-FP: move $fp, $sp +; STATIC-FP: sw $4, {{[0-9]+}}($fp) +; STATIC-FP: .loc 1 4 3 prologue_end +; STATIC-FP: lui ${{[0-9]+}}, %hi(g1) + +; PIC: lui $[[R0:[0-9]+]], %hi(_gp_disp) +; PIC: addiu $[[R0]], $[[R0]], %lo(_gp_disp) +; PIC: addiu $sp, $sp, -{{[0-9]+}} +; PIC: addu $[[R1:[0-9]+]], $[[R0]], $25 +; PIC: sw $4, {{[0-9]+}}($sp) +; PIC: .loc 1 4 3 prologue_end +; PIC: lw $[[R2:[0-9]+]], %got(g1)($[[R1]]) + +; PIC-FP: lui $[[R0:[0-9]+]], %hi(_gp_disp) +; PIC-FP: addiu $[[R0]], $[[R0]], %lo(_gp_disp) +; PIC-FP: addiu $sp, $sp, -{{[0-9]+}} +; PIC-FP: sw $fp, {{[0-9]+}}($sp) +; PIC-FP: move $fp, $sp +; PIC-FP: addu $[[R1:[0-9]+]], $[[R0]], $25 +; PIC-FP: sw $4, {{[0-9]+}}($fp) +; PIC-FP: .loc 1 4 3 prologue_end +; PIC-FP: lw $[[R2:[0-9]+]], %got(g1)($[[R1]]) +} + +; Function Attrs: nounwind readnone +declare void @llvm.dbg.declare(metadata, metadata, metadata) #1 + +attributes #0 = { nounwind "less-precise-fpmad"="false" "no-infs-fp-math"="false" "no-nans-fp-math"="false" "stack-protector-buffer-size"="8" "unsafe-fp-math"="false" "use-soft-float"="false" } +attributes #1 = { nounwind readnone } + +!llvm.dbg.cu = !{!0} +!llvm.module.flags = !{!11, !12} +!llvm.ident = !{!13} + +!0 = !{!"0x11\0012\00clang version 3.7.0 (trunk 226905)\000\00\000\00\001", !1, !2, !2, !3, !9, !2} ; [ DW_TAG_compile_unit ] [/tmp/test.c] [DW_LANG_C99] +!1 = !{!"test.c", !"/tmp"} +!2 = !{} +!3 = !{!4} +!4 = !{!"0x2e\00test\00test\00\003\000\001\000\000\00256\000\003", !1, !5, !6, null, void (i32)* @test, null, null, !2} ; [ DW_TAG_subprogram ] [line 3] [def] [test] +!5 = !{!"0x29", !1} ; [ DW_TAG_file_type ] [/tmp/test.c] +!6 = !{!"0x15\00\000\000\000\000\000\000", null, null, null, !7, null, null, null} ; [ DW_TAG_subroutine_type ] [line 0, size 0, align 0, offset 0] [from ] +!7 = !{null, !8} +!8 = !{!"0x24\00int\000\0032\0032\000\000\005", null, null} ; [ DW_TAG_base_type ] [int] [line 0, size 32, align 32, offset 0, enc DW_ATE_signed] +!9 = !{!10} +!10 = !{!"0x34\00g1\00g1\00\001\000\001", null, !5, !8, i32* @g1, null} ; [ DW_TAG_variable ] [g1] [line 1] [def] +!11 = !{i32 2, !"Dwarf Version", i32 4} +!12 = !{i32 2, !"Debug Info Version", i32 2} +!13 = !{!"clang version 3.7.0 (trunk 226905)"} +!14 = !{!"0x101\00arg1\0016777219\000", !4, !5, !8} ; [ DW_TAG_arg_variable ] [arg1] [line 3] +!15 = !{!"0x102"} ; [ DW_TAG_expression ] +!16 = !MDLocation(line: 3, column: 15, scope: !4) +!17 = !MDLocation(line: 4, column: 8, scope: !4) +!18 = !MDLocation(line: 4, column: 3, scope: !4) +!19 = !MDLocation(line: 5, column: 1, scope: !4)