Index: lib/Target/Mips/MipsSEFrameLowering.cpp
===================================================================
--- lib/Target/Mips/MipsSEFrameLowering.cpp
+++ lib/Target/Mips/MipsSEFrameLowering.cpp
@@ -417,7 +417,8 @@
                                         MF.getSubtarget().getRegisterInfo());
 
   MachineBasicBlock::iterator MBBI = MBB.begin();
-  DebugLoc dl = MBBI != MBB.end() ? MBBI->getDebugLoc() : DebugLoc();
+  DebugLoc dl = (MBBI != MBB.end() && !MBBI->isDebugValue())
+                ? MBBI->getDebugLoc() : DebugLoc();
   unsigned SP = STI.isABI_N64() ? Mips::SP_64 : Mips::SP;
   unsigned FP = STI.isABI_N64() ? Mips::FP_64 : Mips::FP;
   unsigned ZERO = STI.isABI_N64() ? Mips::ZERO_64 : Mips::ZERO;
Index: lib/Target/Mips/MipsSEISelDAGToDAG.cpp
===================================================================
--- lib/Target/Mips/MipsSEISelDAGToDAG.cpp
+++ lib/Target/Mips/MipsSEISelDAGToDAG.cpp
@@ -131,7 +131,8 @@
   MachineBasicBlock::iterator I = MBB.begin();
   MachineRegisterInfo &RegInfo = MF.getRegInfo();
   const TargetInstrInfo &TII = *MF.getSubtarget().getInstrInfo();
-  DebugLoc DL = I != MBB.end() ? I->getDebugLoc() : DebugLoc();
+  DebugLoc DL = (I != MBB.end() && !I->isDebugValue()) ? I->getDebugLoc()
+                                                       : DebugLoc();
   unsigned V0, V1, GlobalBaseReg = MipsFI->getGlobalBaseReg();
   const TargetRegisterClass *RC;
 
Index: lib/Target/Mips/MipsSEInstrInfo.cpp
===================================================================
--- lib/Target/Mips/MipsSEInstrInfo.cpp
+++ lib/Target/Mips/MipsSEInstrInfo.cpp
@@ -183,8 +183,8 @@
                 unsigned SrcReg, bool isKill, int FI,
                 const TargetRegisterClass *RC, const TargetRegisterInfo *TRI,
                 int64_t Offset) const {
-  DebugLoc DL;
-  if (I != MBB.end()) DL = I->getDebugLoc();
+  DebugLoc DL = (I != MBB.end() && !I->isDebugValue()) ? I->getDebugLoc()
+                                                       : DebugLoc();
   MachineMemOperand *MMO = GetMemOperand(MBB, FI, MachineMemOperand::MOStore);
 
   unsigned Opc = 0;
@@ -360,7 +360,8 @@
                                      MachineBasicBlock &MBB,
                                      MachineBasicBlock::iterator I) const {
   const MipsSubtarget &STI = Subtarget;
-  DebugLoc DL = I != MBB.end() ? I->getDebugLoc() : DebugLoc();
+  DebugLoc DL = (I != MBB.end() && !I->isDebugValue()) ? I->getDebugLoc()
+                                                       : DebugLoc();
   unsigned ADDu = STI.isABI_N64() ? Mips::DADDu : Mips::ADDu;
   unsigned ADDiu = STI.isABI_N64() ? Mips::DADDiu : Mips::ADDiu;
 
Index: test/DebugInfo/Mips/delay-slot.ll
===================================================================
--- test/DebugInfo/Mips/delay-slot.ll
+++ test/DebugInfo/Mips/delay-slot.ll
@@ -13,8 +13,7 @@
 ; CHECK: Address            Line   Column File   ISA Discriminator Flags
 ; CHECK: ------------------ ------ ------ ------ --- ------------- -------------
 ; CHECK: 0x0000000000000000      1      0      1   0             0  is_stmt
-; CHECK: 0x0000000000000000      1      0      1   0             0  is_stmt prologue_end
-; CHECK: 0x0000000000000008      2      0      1   0             0  is_stmt
+; CHECK: 0x0000000000000008      2      0      1   0             0  is_stmt prologue_end
 ; CHECK: 0x0000000000000020      3      0      1   0             0  is_stmt
 ; CHECK: 0x0000000000000030      4      0      1   0             0  is_stmt
 ; CHECK: 0x0000000000000040      5      0      1   0             0  is_stmt
Index: test/DebugInfo/Mips/prologue_end.ll
===================================================================
--- /dev/null
+++ test/DebugInfo/Mips/prologue_end.ll
@@ -0,0 +1,86 @@
+; RUN: llc -mtriple=mips-linux-gnu -O0 -relocation-model=static < %s | FileCheck %s -check-prefix=STATIC
+; RUN: llc -mtriple=mips-linux-gnu -O0 -relocation-model=static -disable-fp-elim < %s | FileCheck %s -check-prefix=STATIC-FP
+; RUN: llc -mtriple=mips-linux-gnu -O0 -relocation-model=pic < %s | FileCheck %s -check-prefix=PIC
+; RUN: llc -mtriple=mips-linux-gnu -O0 -relocation-model=pic -disable-fp-elim < %s | FileCheck %s -check-prefix=PIC-FP
+
+
+; Generated using clang -target mipsel-linux-gnu -g -S test.c -emit-llvm -o test.ll
+; test.c:
+; 1: int g1 = 2;
+; 2:
+; 3: void test(int arg1) {
+; 4:   g1 = arg1;
+; 5: }
+
+
+@g1 = global i32 2, align 4
+
+; Function Attrs: nounwind
+define void @test(i32 %arg1) #0 {
+entry:
+  %arg1.addr = alloca i32, align 4
+  store i32 %arg1, i32* %arg1.addr, align 4
+  call void @llvm.dbg.declare(metadata !{i32* %arg1.addr}, metadata !14), !dbg !15
+  %0 = load i32* %arg1.addr, align 4, !dbg !16
+  store i32 %0, i32* @g1, align 4, !dbg !16
+  ret void, !dbg !17
+
+; STATIC:       addiu   $sp, $sp, -{{[0-9]+}}
+; STATIC:       sw      $4, {{[0-9]+}}($sp)
+; STATIC:       .loc    1 4 3 prologue_end
+; STATIC:       lui     ${{[0-9]+}}, %hi(g1)
+
+; STATIC-FP:    addiu   $sp, $sp, -{{[0-9]+}}
+; STATIC-FP:    sw      $fp, {{[0-9]+}}($sp)
+; STATIC-FP:    move    $fp, $sp
+; STATIC-FP:    sw      $4, {{[0-9]+}}($fp)
+; STATIC-FP:    .loc    1 4 3 prologue_end
+; STATIC-FP:    lui     ${{[0-9]+}}, %hi(g1)
+
+; PIC:          lui     $[[R0:[0-9]+]], %hi(_gp_disp)
+; PIC:          addiu   $[[R0]], $[[R0]], %lo(_gp_disp)
+; PIC:          addiu   $sp, $sp, -{{[0-9]+}}
+; PIC:          addu    $[[R1:[0-9]+]], $[[R0]], $25
+; PIC:          sw      $4, {{[0-9]+}}($sp)
+; PIC:          .loc    1 4 3 prologue_end
+; PIC:          lw      $[[R2:[0-9]+]], %got(g1)($[[R1]])
+
+; PIC-FP:       lui     $[[R0:[0-9]+]], %hi(_gp_disp)
+; PIC-FP:       addiu   $[[R0]], $[[R0]], %lo(_gp_disp)
+; PIC-FP:       addiu   $sp, $sp, -{{[0-9]+}}
+; PIC-FP:       sw      $fp, {{[0-9]+}}($sp)
+; PIC-FP:       move    $fp, $sp
+; PIC-FP:       addu    $[[R1:[0-9]+]], $[[R0]], $25
+; PIC-FP:       sw      $4, {{[0-9]+}}($fp)
+; PIC-FP:       .loc    1 4 3 prologue_end
+; PIC-FP:       lw      $[[R2:[0-9]+]], %got(g1)($[[R1]])
+}
+
+; Function Attrs: nounwind readnone
+declare void @llvm.dbg.declare(metadata, metadata) #1
+
+attributes #0 = { nounwind }
+attributes #1 = { nounwind readnone }
+
+!llvm.dbg.cu = !{!0}
+!llvm.module.flags = !{!11, !12}
+!llvm.ident = !{!13}
+
+!0 = metadata !{i32 786449, metadata !1, i32 12, metadata !"clang version 3.6.0 (trunk 215696)", i1 false, metadata !"", i32 0, metadata !2, metadata !2, metadata !3, metadata !9, metadata !2, metadata !"", i32 1} ; [ DW_TAG_compile_unit ] [/tmp/test.c] [DW_LANG_C99]
+!1 = metadata !{metadata !"test.c", metadata !"/tmp"}
+!2 = metadata !{}
+!3 = metadata !{metadata !4}
+!4 = metadata !{i32 786478, metadata !1, metadata !5, metadata !"test", metadata !"test", metadata !"", i32 3, metadata !6, i1 false, i1 true, i32 0, i32 0, null, i32 256, i1 false, void (i32)* @test, null, null, metadata !2, i32 3} ; [ DW_TAG_subprogram ] [line 3] [def] [test]
+!5 = metadata !{i32 786473, metadata !1}          ; [ DW_TAG_file_type ] [/tmp/test.c]
+!6 = metadata !{i32 786453, i32 0, null, metadata !"", i32 0, i64 0, i64 0, i64 0, i32 0, null, metadata !7, i32 0, null, null, null} ; [ DW_TAG_subroutine_type ] [line 0, size 0, align 0, offset 0] [from ]
+!7 = metadata !{null, metadata !8}
+!8 = metadata !{i32 786468, null, null, metadata !"int", i32 0, i64 32, i64 32, i64 0, i32 0, i32 5} ; [ DW_TAG_base_type ] [int] [line 0, size 32, align 32, offset 0, enc DW_ATE_signed]
+!9 = metadata !{metadata !10}
+!10 = metadata !{i32 786484, i32 0, null, metadata !"g1", metadata !"g1", metadata !"", metadata !5, i32 1, metadata !8, i32 0, i32 1, i32* @g1, null} ; [ DW_TAG_variable ] [g1] [line 1] [def]
+!11 = metadata !{i32 2, metadata !"Dwarf Version", i32 4}
+!12 = metadata !{i32 2, metadata !"Debug Info Version", i32 1}
+!13 = metadata !{metadata !"clang version 3.6.0 (trunk 215696)"}
+!14 = metadata !{i32 786689, metadata !4, metadata !"arg1", metadata !5, i32 16777219, metadata !8, i32 0, i32 0} ; [ DW_TAG_arg_variable ] [arg1] [line 3]
+!15 = metadata !{i32 3, i32 15, metadata !4, null}
+!16 = metadata !{i32 4, i32 3, metadata !4, null}
+!17 = metadata !{i32 5, i32 1, metadata !4, null}