Index: lib/Target/AMDGPU/AMDGPU.td =================================================================== --- lib/Target/AMDGPU/AMDGPU.td +++ lib/Target/AMDGPU/AMDGPU.td @@ -402,6 +402,12 @@ "Generate code object version 3" >; +def FeatureTrigReducedRange : SubtargetFeature<"trig-reduced-range", + "HasTrigReducedRange", + "true", + "Requires use of fract on arguments to trig instructions" +>; + // Dummy feature used to disable assembler instructions. def FeatureDisable : SubtargetFeature<"", "FeatureDisable","true", @@ -421,13 +427,13 @@ def FeatureSouthernIslands : GCNSubtargetFeatureGeneration<"SOUTHERN_ISLANDS", [FeatureFP64, FeatureLocalMemorySize32768, FeatureMIMG_R128, FeatureWavefrontSize64, FeatureGCN, - FeatureLDSBankCount32, FeatureMovrel] + FeatureLDSBankCount32, FeatureMovrel, FeatureTrigReducedRange] >; def FeatureSeaIslands : GCNSubtargetFeatureGeneration<"SEA_ISLANDS", [FeatureFP64, FeatureLocalMemorySize65536, FeatureMIMG_R128, FeatureWavefrontSize64, FeatureGCN, FeatureFlatAddressSpace, - FeatureCIInsts, FeatureMovrel] + FeatureCIInsts, FeatureMovrel, FeatureTrigReducedRange] >; def FeatureVolcanicIslands : GCNSubtargetFeatureGeneration<"VOLCANIC_ISLANDS", @@ -437,7 +443,7 @@ FeatureSMemRealTime, FeatureVGPRIndexMode, FeatureMovrel, FeatureScalarStores, FeatureInv2PiInlineImm, FeatureSDWA, FeatureSDWAOutModsVOPC, FeatureSDWAMac, FeatureDPP, - FeatureIntClamp + FeatureIntClamp, FeatureTrigReducedRange ] >; Index: lib/Target/AMDGPU/AMDGPUSubtarget.h =================================================================== --- lib/Target/AMDGPU/AMDGPUSubtarget.h +++ lib/Target/AMDGPU/AMDGPUSubtarget.h @@ -75,6 +75,7 @@ bool HasInv2PiInlineImm; bool HasFminFmaxLegacy; bool EnablePromoteAlloca; + bool HasTrigReducedRange; int LocalMemorySize; unsigned WavefrontSize; @@ -179,6 +180,10 @@ return HasFminFmaxLegacy; } + bool hasTrigReducedRange() const { + return HasTrigReducedRange; + } + bool isPromoteAllocaEnabled() const { return EnablePromoteAlloca; } Index: lib/Target/AMDGPU/AMDGPUSubtarget.cpp =================================================================== --- lib/Target/AMDGPU/AMDGPUSubtarget.cpp +++ lib/Target/AMDGPU/AMDGPUSubtarget.cpp @@ -139,6 +139,7 @@ HasInv2PiInlineImm(false), HasFminFmaxLegacy(true), EnablePromoteAlloca(false), + HasTrigReducedRange(false), LocalMemorySize(0), WavefrontSize(0) { } Index: lib/Target/AMDGPU/SIISelLowering.cpp =================================================================== --- lib/Target/AMDGPU/SIISelLowering.cpp +++ lib/Target/AMDGPU/SIISelLowering.cpp @@ -6646,17 +6646,25 @@ SDLoc DL(Op); EVT VT = Op.getValueType(); SDValue Arg = Op.getOperand(0); + SDValue TrigVal; + // TODO: Should this propagate fast-math-flags? - SDValue FractPart = DAG.getNode(AMDGPUISD::FRACT, DL, VT, - DAG.getNode(ISD::FMUL, DL, VT, Arg, - DAG.getConstantFP(0.5/M_PI, DL, - VT))); + + if (Subtarget->hasTrigReducedRange()) { + TrigVal = DAG.getNode(AMDGPUISD::FRACT, DL, VT, + DAG.getNode(ISD::FMUL, DL, VT, Arg, + DAG.getConstantFP(0.5 / M_PI, DL, + VT))); + } else { + TrigVal = DAG.getNode(ISD::FMUL, DL, VT, Arg, + DAG.getConstantFP(0.5 / M_PI, DL, VT)); + } switch (Op.getOpcode()) { case ISD::FCOS: - return DAG.getNode(AMDGPUISD::COS_HW, SDLoc(Op), VT, FractPart); + return DAG.getNode(AMDGPUISD::COS_HW, SDLoc(Op), VT, TrigVal); case ISD::FSIN: - return DAG.getNode(AMDGPUISD::SIN_HW, SDLoc(Op), VT, FractPart); + return DAG.getNode(AMDGPUISD::SIN_HW, SDLoc(Op), VT, TrigVal); default: llvm_unreachable("Wrong trig opcode"); } Index: test/CodeGen/AMDGPU/llvm.cos.f16.ll =================================================================== --- test/CodeGen/AMDGPU/llvm.cos.f16.ll +++ test/CodeGen/AMDGPU/llvm.cos.f16.ll @@ -1,5 +1,6 @@ -; RUN: llc -amdgpu-scalarize-global-loads=false -march=amdgcn -mcpu=tahiti -verify-machineinstrs < %s | FileCheck -check-prefix=GCN -check-prefix=SI %s -; RUN: llc -amdgpu-scalarize-global-loads=false -march=amdgcn -mcpu=fiji -mattr=-flat-for-global -verify-machineinstrs < %s | FileCheck -check-prefix=GCN -check-prefix=VI %s +; RUN: llc -amdgpu-scalarize-global-loads=false -march=amdgcn -mcpu=tahiti -verify-machineinstrs < %s | FileCheck -check-prefixes=GCN,SI,SIVI %s +; RUN: llc -amdgpu-scalarize-global-loads=false -march=amdgcn -mcpu=fiji -mattr=-flat-for-global -verify-machineinstrs < %s | FileCheck -check-prefixes=GCN,SIVI,VI,VIGFX9 %s +; RUN: llc -amdgpu-scalarize-global-loads=false -march=amdgcn -mcpu=gfx900 -mattr=-flat-for-global -verify-machineinstrs < %s | FileCheck -check-prefixes=GCN,GFX9,VIGFX9 %s declare half @llvm.cos.f16(half %a) declare <2 x half> @llvm.cos.v2f16(<2 x half> %a) @@ -8,8 +9,10 @@ ; GCN: buffer_load_ushort v[[A_F16:[0-9]+]] ; GCN: v_cvt_f32_f16_e32 v[[A_F32:[0-9]+]], v[[A_F16]] ; GCN: v_mul_f32_e32 v[[M_F32:[0-9]+]], {{0.15915494|0x3e22f983}}, v[[A_F32]] -; GCN: v_fract_f32_e32 v[[F_F32:[0-9]+]], v[[M_F32]] -; GCN: v_cos_f32_e32 v[[R_F32:[0-9]+]], v[[F_F32]] +; SIVI: v_fract_f32_e32 v[[F_F32:[0-9]+]], v[[M_F32]] +; SIVI: v_cos_f32_e32 v[[R_F32:[0-9]+]], v[[F_F32]] +; GFX9-NOT: v_fract_f32 +; GFX9: v_cos_f32_e32 v[[R_F32:[0-9]+]], v[[M_F32]] ; GCN: v_cvt_f16_f32_e32 v[[R_F16:[0-9]+]], v[[R_F32]] ; GCN: buffer_store_short v[[R_F16]] ; GCN: s_endpgm @@ -23,38 +26,44 @@ ret void } -; GCN-LABEL: {{^}}cos_v2f16 -; GCN-DAG: buffer_load_dword v[[A_V2_F16:[0-9]+]] -; SI-DAG: v_mov_b32_e32 v[[HALF_PI:[0-9]+]], 0x3e22f983{{$}} +; GCN-LABEL: {{^}}cos_v2f16: +; GCN: buffer_load_dword v[[A_V2_F16:[0-9]+]] +; SI: v_mov_b32_e32 v[[HALF_PI:[0-9]+]], 0x3e22f983{{$}} ; SI: v_cvt_f32_f16_e32 v[[A_F32_0:[0-9]+]], v[[A_V2_F16]] ; SI: v_lshrrev_b32_e32 v[[A_F16_1:[0-9]+]], 16, v[[A_V2_F16]] -; SI-DAG: v_cvt_f32_f16_e32 v[[A_F32_1:[0-9]+]], v[[A_F16_1]] +; SI: v_cvt_f32_f16_e32 v[[A_F32_1:[0-9]+]], v[[A_F16_1]] ; SI: v_mul_f32_e32 v[[M_F32_0:[0-9]+]], v[[A_F32_0]], v[[HALF_PI]] ; SI: v_fract_f32_e32 v[[F_F32_0:[0-9]+]], v[[M_F32_0]] ; SI: v_mul_f32_e32 v[[M_F32_1:[0-9]+]], v[[A_F32_1]], v[[HALF_PI]] ; SI: v_fract_f32_e32 v[[F_F32_1:[0-9]+]], v[[M_F32_1]] +; SI: v_cos_f32_e32 v[[R_F32_1:[0-9]+]], v[[F_F32_1]] +; SI: v_cos_f32_e32 v[[R_F32_0:[0-9]+]], v[[F_F32_0]] +; SI: v_cvt_f16_f32_e32 v[[R_F16_1:[0-9]+]], v[[R_F32_1]] -; VI-DAG: v_cvt_f32_f16_e32 v[[A_F32_0:[0-9]+]], v[[A_V2_F16]] -; VI-DAG: v_cvt_f32_f16_sdwa v[[A_F32_1:[0-9]+]], v[[A_V2_F16]] dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1 -; VI-DAG: v_mul_f32_e32 v[[M_F32_0:[0-9]+]], 0.15915494, v[[A_F32_0]] -; VI-DAG: v_mul_f32_e32 v[[M_F32_1:[0-9]+]], 0.15915494, v[[A_F32_1]] +; VIGFX9-DAG: v_cvt_f32_f16_e32 v[[A_F32_0:[0-9]+]], v[[A_V2_F16]] +; VIGFX9-DAG: v_cvt_f32_f16_sdwa v[[A_F32_1:[0-9]+]], v[[A_V2_F16]] dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1 +; VIGFX9-DAG: v_mul_f32_e32 v[[M_F32_0:[0-9]+]], 0.15915494, v[[A_F32_0]] +; VIGFX9-DAG: v_mul_f32_e32 v[[M_F32_1:[0-9]+]], 0.15915494, v[[A_F32_1]] ; VI-DAG: v_fract_f32_e32 v[[F_F32_0:[0-9]+]], v[[M_F32_0]] ; VI-DAG: v_fract_f32_e32 v[[F_F32_1:[0-9]+]], v[[M_F32_1]] +; VI-DAG: v_cos_f32_e32 v[[R_F32_1:[0-9]+]], v[[F_F32_1]] +; VI-DAG: v_cos_f32_e32 v[[R_F32_0:[0-9]+]], v[[F_F32_0]] +; GFX9-DAG: v_cos_f32_e32 v[[R_F32_1:[0-9]+]], v[[M_F32_1]] +; GFX9-DAG: v_cos_f32_e32 v[[R_F32_0:[0-9]+]], v[[M_F32_0]] -; GCN: v_cos_f32_e32 v[[R_F32_1:[0-9]+]], v[[F_F32_1]] -; GCN: v_cos_f32_e32 v[[R_F32_0:[0-9]+]], v[[F_F32_0]] - -; SI-DAG: v_cvt_f16_f32_e32 v[[R_F16_1:[0-9]+]], v[[R_F32_1]] -; SI-DAG: v_cvt_f16_f32_e32 v[[R_F16_0:[0-9]+]], v[[R_F32_0]] - -; VI-DAG: v_cvt_f16_f32_e32 v[[R_F16_0:[0-9]+]], v[[R_F32_0]] -; VI-DAG: v_cvt_f16_f32_sdwa v[[R_F16_1:[0-9]+]], v[[R_F32_1]] dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD -; GCN-NOT: and +; GCN-DAG: v_cvt_f16_f32_e32 v[[R_F16_0:[0-9]+]], v[[R_F32_0]] ; SI: v_lshlrev_b32_e32 v[[R_F16_HI:[0-9]+]], 16, v[[R_F16_1]] ; SI: v_or_b32_e32 v[[R_V2_F16:[0-9]+]], v[[R_F16_0]], v[[R_F16_HI]] -; VI: v_or_b32_e32 v[[R_V2_F16:[0-9]+]], v[[R_F16_0]], v[[R_F16_1]] + +; VI-DAG: v_cvt_f16_f32_sdwa v[[R_F16_1:[0-9]+]], v[[R_F32_1]] dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD +; VI: v_or_b32_e32 v[[R_V2_F16:[0-9]+]], v[[R_F16_0]], v[[R_F16_1]] + +; GFX9-DAG: v_cvt_f16_f32_e32 v[[R_F16_1:[0-9]+]], v[[R_F32_1]] +; GFX9-DAG: v_and_b32_e32 v[[R2_F16_0:[0-9]+]], 0xffff, v[[R_F16_0]] +; GFX9-DAG: v_lshl_or_b32 v[[R_V2_F16:[0-9]+]], v[[R_F16_1]], 16, v[[R2_F16_0]] + ; GCN: buffer_store_dword v[[R_V2_F16]] ; GCN: s_endpgm define amdgpu_kernel void @cos_v2f16( Index: test/CodeGen/AMDGPU/llvm.sin.f16.ll =================================================================== --- test/CodeGen/AMDGPU/llvm.sin.f16.ll +++ test/CodeGen/AMDGPU/llvm.sin.f16.ll @@ -1,5 +1,6 @@ -; RUN: llc -amdgpu-scalarize-global-loads=false -march=amdgcn -mcpu=tahiti -verify-machineinstrs < %s | FileCheck -enable-var-scope -check-prefixes=GCN,SI %s -; RUN: llc -amdgpu-scalarize-global-loads=false -march=amdgcn -mcpu=fiji -mattr=-flat-for-global -verify-machineinstrs < %s | FileCheck -enable-var-scope -check-prefixes=GCN,VI %s +; RUN: llc -amdgpu-scalarize-global-loads=false -march=amdgcn -mcpu=tahiti -verify-machineinstrs < %s | FileCheck -enable-var-scope -check-prefixes=GCN,SIVI,SI %s +; RUN: llc -amdgpu-scalarize-global-loads=false -march=amdgcn -mcpu=fiji -mattr=-flat-for-global -verify-machineinstrs < %s | FileCheck -enable-var-scope -check-prefixes=GCN,SIVI,VI,VIGFX9 %s +; RUN: llc -amdgpu-scalarize-global-loads=false -march=amdgcn -mcpu=gfx900 -mattr=-flat-for-global -verify-machineinstrs < %s | FileCheck -enable-var-scope -check-prefixes=GCN,GFX9,VIGFX9 %s declare half @llvm.sin.f16(half %a) declare <2 x half> @llvm.sin.v2f16(<2 x half> %a) @@ -8,8 +9,10 @@ ; GCN: buffer_load_ushort v[[A_F16:[0-9]+]] ; GCN: v_cvt_f32_f16_e32 v[[A_F32:[0-9]+]], v[[A_F16]] ; GCN: v_mul_f32_e32 v[[M_F32:[0-9]+]], {{0.15915494|0x3e22f983}}, v[[A_F32]] -; GCN: v_fract_f32_e32 v[[F_F32:[0-9]+]], v[[M_F32]] -; GCN: v_sin_f32_e32 v[[R_F32:[0-9]+]], v[[F_F32]] +; SIVI: v_fract_f32_e32 v[[F_F32:[0-9]+]], v[[M_F32]] +; SIVI: v_sin_f32_e32 v[[R_F32:[0-9]+]], v[[F_F32]] +; GFX9-NOT: v_fract_f32_e32 +; GFX9: v_sin_f32_e32 v[[R_F32:[0-9]+]], v[[M_F32]] ; GCN: v_cvt_f16_f32_e32 v[[R_F16:[0-9]+]], v[[R_F32]] ; GCN: buffer_store_short v[[R_F16]] ; GCN: s_endpgm @@ -38,14 +41,16 @@ ; SI: v_sin_f32_e32 v[[R_F32_0:[0-9]+]], v[[F_F32_0]] ; SI: v_cvt_f16_f32_e32 v[[R_F16_1:[0-9]+]], v[[R_F32_1]] -; VI-DAG: v_cvt_f32_f16_e32 v[[A_F32_0:[0-9]+]], v[[A_V2_F16]] -; VI-DAG: v_cvt_f32_f16_sdwa v[[A_F32_1:[0-9]+]], v[[A_V2_F16]] dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1 -; VI-DAG: v_mul_f32_e32 v[[M_F32_0:[0-9]+]], 0.15915494, v[[A_F32_0]] -; VI-DAG: v_mul_f32_e32 v[[M_F32_1:[0-9]+]], 0.15915494, v[[A_F32_1]] +; VIGFX9-DAG: v_cvt_f32_f16_e32 v[[A_F32_0:[0-9]+]], v[[A_V2_F16]] +; VIGFX9-DAG: v_cvt_f32_f16_sdwa v[[A_F32_1:[0-9]+]], v[[A_V2_F16]] dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1 +; VIGFX9-DAG: v_mul_f32_e32 v[[M_F32_0:[0-9]+]], 0.15915494, v[[A_F32_0]] +; VIGFX9-DAG: v_mul_f32_e32 v[[M_F32_1:[0-9]+]], 0.15915494, v[[A_F32_1]] ; VI-DAG: v_fract_f32_e32 v[[F_F32_0:[0-9]+]], v[[M_F32_0]] ; VI-DAG: v_fract_f32_e32 v[[F_F32_1:[0-9]+]], v[[M_F32_1]] -; VI: v_sin_f32_e32 v[[R_F32_1:[0-9]+]], v[[F_F32_1]] -; VI: v_sin_f32_e32 v[[R_F32_0:[0-9]+]], v[[F_F32_0]] +; VI-DAG: v_sin_f32_e32 v[[R_F32_1:[0-9]+]], v[[F_F32_1]] +; VI-DAG: v_sin_f32_e32 v[[R_F32_0:[0-9]+]], v[[F_F32_0]] +; GFX9-DAG: v_sin_f32_e32 v[[R_F32_1:[0-9]+]], v[[M_F32_1]] +; GFX9-DAG: v_sin_f32_e32 v[[R_F32_0:[0-9]+]], v[[M_F32_0]] ; GCN-DAG: v_cvt_f16_f32_e32 v[[R_F16_0:[0-9]+]], v[[R_F32_0]] @@ -55,6 +60,10 @@ ; VI-DAG: v_cvt_f16_f32_sdwa v[[R_F16_1:[0-9]+]], v[[R_F32_1]] dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD ; VI: v_or_b32_e32 v[[R_V2_F16:[0-9]+]], v[[R_F16_0]], v[[R_F16_1]] +; GFX9-DAG: v_cvt_f16_f32_e32 v[[R_F16_1:[0-9]+]], v[[R_F32_1]] +; GFX9-DAG: v_and_b32_e32 v[[R2_F16_0:[0-9]+]], 0xffff, v[[R_F16_0]] +; GFX9-DAG: v_lshl_or_b32 v[[R_V2_F16:[0-9]+]], v[[R_F16_1]], 16, v[[R2_F16_0]] + ; GCN: buffer_store_dword v[[R_V2_F16]] ; GCN: s_endpgm define amdgpu_kernel void @sin_v2f16( Index: test/CodeGen/AMDGPU/llvm.sin.ll =================================================================== --- test/CodeGen/AMDGPU/llvm.sin.ll +++ test/CodeGen/AMDGPU/llvm.sin.ll @@ -1,5 +1,8 @@ ; RUN: llc -march=r600 -mcpu=redwood < %s | FileCheck -check-prefix=EG -check-prefix=FUNC %s -; RUN: llc -march=amdgcn -verify-machineinstrs < %s | FileCheck -check-prefix=SI -check-prefix=FUNC %s +; RUN: llc -march=amdgcn -mcpu=kaveri -verify-machineinstrs < %s | FileCheck -check-prefixes=GCN,SICIVI,FUNC %s +; RUN: llc -march=amdgcn -mcpu=tahiti -verify-machineinstrs < %s | FileCheck -check-prefixes=GCN,SICIVI,FUNC %s +; RUN: llc -march=amdgcn -mcpu=fiji -verify-machineinstrs < %s | FileCheck -check-prefixes=GCN,SICIVI,FUNC %s +; RUN: llc -march=amdgcn -mcpu=gfx900 -verify-machineinstrs < %s | FileCheck -check-prefixes=GCN,GFX9,FUNC %s ; FUNC-LABEL: sin_f32 ; EG: MULADD_IEEE * @@ -8,10 +11,11 @@ ; EG: SIN * T{{[0-9]+\.[XYZW], PV\.[XYZW]}} ; EG-NOT: SIN -; SI: v_mul_f32 -; SI: v_fract_f32 -; SI: v_sin_f32 -; SI-NOT: v_sin_f32 +; GCN: v_mul_f32 +; SICIVI: v_fract_f32 +; GFX9-NOT: v_fract_f32 +; GCN: v_sin_f32 +; GCN-NOT: v_sin_f32 define amdgpu_kernel void @sin_f32(float addrspace(1)* %out, float %x) #1 { %sin = call float @llvm.sin.f32(float %x) store float %sin, float addrspace(1)* %out @@ -19,11 +23,12 @@ } ; FUNC-LABEL: {{^}}safe_sin_3x_f32: -; SI: v_mul_f32 -; SI: v_mul_f32 -; SI: v_fract_f32 -; SI: v_sin_f32 -; SI-NOT: v_sin_f32 +; GCN: v_mul_f32 +; GCN: v_mul_f32 +; SICIVI: v_fract_f32 +; GFX9-NOT: v_fract_f32 +; GCN: v_sin_f32 +; GCN-NOT: v_sin_f32 define amdgpu_kernel void @safe_sin_3x_f32(float addrspace(1)* %out, float %x) #1 { %y = fmul float 3.0, %x %sin = call float @llvm.sin.f32(float %y) @@ -32,12 +37,13 @@ } ; FUNC-LABEL: {{^}}unsafe_sin_3x_f32: -; SI-NOT: v_add_f32 -; SI: 0x3ef47644 -; SI: v_mul_f32 -; SI: v_fract_f32 -; SI: v_sin_f32 -; SI-NOT: v_sin_f32 +; GCN-NOT: v_add_f32 +; GCN: 0x3ef47644 +; GCN: v_mul_f32 +; SICIVI: v_fract_f32 +; GFX9-NOT: v_fract_f32 +; GCN: v_sin_f32 +; GCN-NOT: v_sin_f32 define amdgpu_kernel void @unsafe_sin_3x_f32(float addrspace(1)* %out, float %x) #2 { %y = fmul float 3.0, %x %sin = call float @llvm.sin.f32(float %y) @@ -46,11 +52,12 @@ } ; FUNC-LABEL: {{^}}safe_sin_2x_f32: -; SI: v_add_f32 -; SI: v_mul_f32 -; SI: v_fract_f32 -; SI: v_sin_f32 -; SI-NOT: v_sin_f32 +; GCN: v_add_f32 +; GCN: v_mul_f32 +; SICIVI: v_fract_f32 +; GFX9-NOT: v_fract_f32 +; GCN: v_sin_f32 +; GCN-NOT: v_sin_f32 define amdgpu_kernel void @safe_sin_2x_f32(float addrspace(1)* %out, float %x) #1 { %y = fmul float 2.0, %x %sin = call float @llvm.sin.f32(float %y) @@ -59,12 +66,13 @@ } ; FUNC-LABEL: {{^}}unsafe_sin_2x_f32: -; SI-NOT: v_add_f32 -; SI: 0x3ea2f983 -; SI: v_mul_f32 -; SI: v_fract_f32 -; SI: v_sin_f32 -; SI-NOT: v_sin_f32 +; GCN-NOT: v_add_f32 +; GCN: 0x3ea2f983 +; GCN: v_mul_f32 +; SICIVI: v_fract_f32 +; GFX9-NOT: v_fract_f32 +; GCN: v_sin_f32 +; GCN-NOT: v_sin_f32 define amdgpu_kernel void @unsafe_sin_2x_f32(float addrspace(1)* %out, float %x) #2 { %y = fmul float 2.0, %x %sin = call float @llvm.sin.f32(float %y) @@ -73,11 +81,12 @@ } ; FUNC-LABEL: {{^}}test_safe_2sin_f32: -; SI: v_add_f32 -; SI: v_mul_f32 -; SI: v_fract_f32 -; SI: v_sin_f32 -; SI-NOT: v_sin_f32 +; GCN: v_add_f32 +; GCN: v_mul_f32 +; SICIVI: v_fract_f32 +; GFX9-NOT: v_fract_f32 +; GCN: v_sin_f32 +; GCN-NOT: v_sin_f32 define amdgpu_kernel void @test_safe_2sin_f32(float addrspace(1)* %out, float %x) #1 { %y = fmul float 2.0, %x %sin = call float @llvm.sin.f32(float %y) @@ -86,11 +95,12 @@ } ; FUNC-LABEL: {{^}}test_unsafe_2sin_f32: -; SI: 0x3ea2f983 -; SI: v_mul_f32 -; SI: v_fract_f32 -; SI: v_sin_f32 -; SI-NOT: v_sin_f32 +; GCN: 0x3ea2f983 +; GCN: v_mul_f32 +; SICIVI: v_fract_f32 +; GFX9-NOT: v_fract_f32 +; GCN: v_sin_f32 +; GCN-NOT: v_sin_f32 define amdgpu_kernel void @test_unsafe_2sin_f32(float addrspace(1)* %out, float %x) #2 { %y = fmul float 2.0, %x %sin = call float @llvm.sin.f32(float %y) @@ -105,11 +115,11 @@ ; EG: SIN * T{{[0-9]+\.[XYZW], PV\.[XYZW]}} ; EG-NOT: SIN -; SI: v_sin_f32 -; SI: v_sin_f32 -; SI: v_sin_f32 -; SI: v_sin_f32 -; SI-NOT: v_sin_f32 +; GCN: v_sin_f32 +; GCN: v_sin_f32 +; GCN: v_sin_f32 +; GCN: v_sin_f32 +; GCN-NOT: v_sin_f32 define amdgpu_kernel void @sin_v4f32(<4 x float> addrspace(1)* %out, <4 x float> %vx) #1 { %sin = call <4 x float> @llvm.sin.v4f32( <4 x float> %vx) store <4 x float> %sin, <4 x float> addrspace(1)* %out