Index: lib/Target/Mips/MipsInstrInfo.td
===================================================================
--- lib/Target/Mips/MipsInstrInfo.td
+++ lib/Target/Mips/MipsInstrInfo.td
@@ -1148,12 +1148,13 @@
 }
 
 def SYNC : MMRel, SYNC_FT<"sync">, SYNC_FM, ISA_MIPS32;
-def TEQ : MMRel, TEQ_FT<"teq", GPR32Opnd>, TEQ_FM<0x34>;
-def TGE : MMRel, TEQ_FT<"tge", GPR32Opnd>, TEQ_FM<0x30>;
-def TGEU : MMRel, TEQ_FT<"tgeu", GPR32Opnd>, TEQ_FM<0x31>;
-def TLT : MMRel, TEQ_FT<"tlt", GPR32Opnd>, TEQ_FM<0x32>;
-def TLTU : MMRel, TEQ_FT<"tltu", GPR32Opnd>, TEQ_FM<0x33>;
-def TNE : MMRel, TEQ_FT<"tne", GPR32Opnd>, TEQ_FM<0x36>;
+
+def TEQ : MMRel, TEQ_FT<"teq", GPR32Opnd>, TEQ_FM<0x34>, ISA_MIPS2;
+def TGE : MMRel, TEQ_FT<"tge", GPR32Opnd>, TEQ_FM<0x30>, ISA_MIPS2;
+def TGEU : MMRel, TEQ_FT<"tgeu", GPR32Opnd>, TEQ_FM<0x31>, ISA_MIPS2;
+def TLT : MMRel, TEQ_FT<"tlt", GPR32Opnd>, TEQ_FM<0x32>, ISA_MIPS2;
+def TLTU : MMRel, TEQ_FT<"tltu", GPR32Opnd>, TEQ_FM<0x33>, ISA_MIPS2;
+def TNE : MMRel, TEQ_FT<"tne", GPR32Opnd>, TEQ_FM<0x36>, ISA_MIPS2;
 
 def TEQI : MMRel, TEQI_FT<"teqi", GPR32Opnd>, TEQI_FM<0xc>,
            ISA_MIPS2_NOT_32R6_64R6;
@@ -1483,14 +1484,19 @@
 def : MipsInstAlias<"ei", (EI ZERO), 1>;
 def : MipsInstAlias<"di", (DI ZERO), 1>;
 
-def  : MipsInstAlias<"teq $rs, $rt", (TEQ GPR32Opnd:$rs, GPR32Opnd:$rt, 0), 1>;
-def  : MipsInstAlias<"tge $rs, $rt", (TGE GPR32Opnd:$rs, GPR32Opnd:$rt, 0), 1>;
-def  : MipsInstAlias<"tgeu $rs, $rt", (TGEU GPR32Opnd:$rs, GPR32Opnd:$rt, 0),
-                     1>;
-def  : MipsInstAlias<"tlt $rs, $rt", (TLT GPR32Opnd:$rs, GPR32Opnd:$rt, 0), 1>;
-def  : MipsInstAlias<"tltu $rs, $rt", (TLTU GPR32Opnd:$rs, GPR32Opnd:$rt, 0),
-                     1>;
-def  : MipsInstAlias<"tne $rs, $rt", (TNE GPR32Opnd:$rs, GPR32Opnd:$rt, 0), 1>;
+def : MipsInstAlias<"teq $rs, $rt",
+                    (TEQ GPR32Opnd:$rs, GPR32Opnd:$rt, 0), 1>, ISA_MIPS2;
+def : MipsInstAlias<"tge $rs, $rt",
+                    (TGE GPR32Opnd:$rs, GPR32Opnd:$rt, 0), 1>, ISA_MIPS2;
+def : MipsInstAlias<"tgeu $rs, $rt",
+                    (TGEU GPR32Opnd:$rs, GPR32Opnd:$rt, 0), 1>, ISA_MIPS2;
+def : MipsInstAlias<"tlt $rs, $rt",
+                    (TLT GPR32Opnd:$rs, GPR32Opnd:$rt, 0), 1>, ISA_MIPS2;
+def : MipsInstAlias<"tltu $rs, $rt",
+                    (TLTU GPR32Opnd:$rs, GPR32Opnd:$rt, 0), 1>, ISA_MIPS2;
+def : MipsInstAlias<"tne $rs, $rt",
+                    (TNE GPR32Opnd:$rs, GPR32Opnd:$rt, 0), 1>, ISA_MIPS2;
+
 def  : MipsInstAlias<"sll $rd, $rt, $rs",
                      (SLLV GPR32Opnd:$rd, GPR32Opnd:$rt, GPR32Opnd:$rs), 0>;
 def : MipsInstAlias<"sub, $rd, $rs, $imm",
Index: test/MC/Mips/mips1/invalid-mips2.s
===================================================================
--- test/MC/Mips/mips1/invalid-mips2.s
+++ test/MC/Mips/mips1/invalid-mips2.s
@@ -13,11 +13,17 @@
         round.w.s $f27,$f28       # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled
         sqrt.d    $f17,$f22       # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled
         sqrt.s    $f0,$f1         # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled
+        teq       $0,$3           # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled
         teqi      $s5,-17504      # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled
+        tge       $0,$3           # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled
         tgei      $s1,5025        # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled
         tgeiu     $sp,-28621      # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled
+        tgeu      $0,$3           # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled
+        tlt       $0,$3           # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled
         tlti      $t6,-21059      # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled
         tltiu     $ra,-5076       # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled
+        tltu      $0,$3           # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled
+        tne       $0,$3           # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled
         tnei      $t4,-29647      # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled
         trunc.w.d $f22,$f15       # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled
         trunc.w.s $f28,$f30       # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled
Index: test/MC/Mips/mips2/valid.s
===================================================================
--- test/MC/Mips/mips2/valid.s
+++ test/MC/Mips/mips2/valid.s
@@ -123,15 +123,21 @@
         swl       $15,13694($s3)
         swr       $s1,-26590($14)
         sync                           # CHECK: sync                   # encoding: [0x00,0x00,0x00,0x0f]
+        teq       $0,$3                # CHECK: teq $zero, $3          # encoding: [0x00,0x03,0x00,0x34]
         teqi      $s5,-17504
+        tge       $0,$3                # CHECK: tge $zero, $3          # encoding: [0x00,0x03,0x00,0x30]
         tgei      $s1,5025
         tgeiu     $sp,-28621
+        tgeu      $0,$3                # CHECK: tgeu $zero, $3         # encoding: [0x00,0x03,0x00,0x31]
         tlbp                           # CHECK: tlbp                   # encoding: [0x42,0x00,0x00,0x08]
         tlbr                           # CHECK: tlbr                   # encoding: [0x42,0x00,0x00,0x01]
         tlbwi                          # CHECK: tlbwi                  # encoding: [0x42,0x00,0x00,0x02]
         tlbwr                          # CHECK: tlbwr                  # encoding: [0x42,0x00,0x00,0x06]
+        tlt       $0,$3                # CHECK: tlt $zero, $3          # encoding: [0x00,0x03,0x00,0x32]
         tlti      $14,-21059
         tltiu     $ra,-5076
+        tltu      $0,$3                # CHECK: tltu $zero, $3         # encoding: [0x00,0x03,0x00,0x33]
+        tne       $0,$3                # CHECK: tne $zero, $3          # encoding: [0x00,0x03,0x00,0x36]
         tnei      $12,-29647
         trunc.w.d $f22,$f15
         trunc.w.s $f28,$f30
Index: test/MC/Mips/mips3/valid.s
===================================================================
--- test/MC/Mips/mips3/valid.s
+++ test/MC/Mips/mips3/valid.s
@@ -180,15 +180,21 @@
         swl       $15,13694($s3)
         swr       $s1,-26590($14)
         sync                           # CHECK: sync                   # encoding: [0x00,0x00,0x00,0x0f]
+        teq       $0,$3                # CHECK: teq $zero, $3          # encoding: [0x00,0x03,0x00,0x34]
         teqi      $s5,-17504
+        tge       $0,$3                # CHECK: tge $zero, $3          # encoding: [0x00,0x03,0x00,0x30]
         tgei      $s1,5025
         tgeiu     $sp,-28621
+        tgeu      $0,$3                # CHECK: tgeu $zero, $3         # encoding: [0x00,0x03,0x00,0x31]
         tlbp                           # CHECK: tlbp                   # encoding: [0x42,0x00,0x00,0x08]
         tlbr                           # CHECK: tlbr                   # encoding: [0x42,0x00,0x00,0x01]
         tlbwi                          # CHECK: tlbwi                  # encoding: [0x42,0x00,0x00,0x02]
         tlbwr                          # CHECK: tlbwr                  # encoding: [0x42,0x00,0x00,0x06]
+        tlt       $0,$3                # CHECK: tlt $zero, $3          # encoding: [0x00,0x03,0x00,0x32]
         tlti      $14,-21059
         tltiu     $ra,-5076
+        tltu      $0,$3                # CHECK: tltu $zero, $3         # encoding: [0x00,0x03,0x00,0x33]
+        tne       $0,$3                # CHECK: tne $zero, $3          # encoding: [0x00,0x03,0x00,0x36]
         tnei      $12,-29647
         trunc.l.d $f23,$f23
         trunc.l.s $f28,$f31
Index: test/MC/Mips/mips32/valid.s
===================================================================
--- test/MC/Mips/mips32/valid.s
+++ test/MC/Mips/mips32/valid.s
@@ -151,15 +151,21 @@
         swr       $s1,-26590($14)
         sync                           # CHECK: sync                   # encoding: [0x00,0x00,0x00,0x0f]
         sync      1                    # CHECK: sync 1                 # encoding: [0x00,0x00,0x00,0x4f]
+        teq       $0,$3                # CHECK: teq $zero, $3          # encoding: [0x00,0x03,0x00,0x34]
         teqi      $s5,-17504
+        tge       $0,$3                # CHECK: tge $zero, $3          # encoding: [0x00,0x03,0x00,0x30]
         tgei      $s1,5025
         tgeiu     $sp,-28621
+        tgeu      $0,$3                # CHECK: tgeu $zero, $3         # encoding: [0x00,0x03,0x00,0x31]
         tlbp                           # CHECK: tlbp                   # encoding: [0x42,0x00,0x00,0x08]
         tlbr                           # CHECK: tlbr                   # encoding: [0x42,0x00,0x00,0x01]
         tlbwi                          # CHECK: tlbwi                  # encoding: [0x42,0x00,0x00,0x02]
         tlbwr                          # CHECK: tlbwr                  # encoding: [0x42,0x00,0x00,0x06]
+        tlt       $0,$3                # CHECK: tlt $zero, $3          # encoding: [0x00,0x03,0x00,0x32]
         tlti      $14,-21059
         tltiu     $ra,-5076
+        tltu      $0,$3                # CHECK: tltu $zero, $3         # encoding: [0x00,0x03,0x00,0x33]
+        tne       $0,$3                # CHECK: tne $zero, $3          # encoding: [0x00,0x03,0x00,0x36]
         tnei      $12,-29647
         trunc.w.d $f22,$f15
         trunc.w.s $f28,$f30
Index: test/MC/Mips/mips32r2/valid.s
===================================================================
--- test/MC/Mips/mips32r2/valid.s
+++ test/MC/Mips/mips32r2/valid.s
@@ -181,15 +181,21 @@
         swxc1     $f19,$12($k0)
         sync                           # CHECK: sync                   # encoding: [0x00,0x00,0x00,0x0f]
         sync      1                    # CHECK: sync 1                 # encoding: [0x00,0x00,0x00,0x4f]
+        teq       $0,$3                # CHECK: teq $zero, $3          # encoding: [0x00,0x03,0x00,0x34]
         teqi      $s5,-17504
+        tge       $0,$3                # CHECK: tge $zero, $3          # encoding: [0x00,0x03,0x00,0x30]
         tgei      $s1,5025
         tgeiu     $sp,-28621
+        tgeu      $0,$3                # CHECK: tgeu $zero, $3         # encoding: [0x00,0x03,0x00,0x31]
         tlbp                           # CHECK: tlbp                   # encoding: [0x42,0x00,0x00,0x08]
         tlbr                           # CHECK: tlbr                   # encoding: [0x42,0x00,0x00,0x01]
         tlbwi                          # CHECK: tlbwi                  # encoding: [0x42,0x00,0x00,0x02]
         tlbwr                          # CHECK: tlbwr                  # encoding: [0x42,0x00,0x00,0x06]
+        tlt       $0,$3                # CHECK: tlt $zero, $3          # encoding: [0x00,0x03,0x00,0x32]
         tlti      $14,-21059
         tltiu     $ra,-5076
+        tltu      $0,$3                # CHECK: tltu $zero, $3         # encoding: [0x00,0x03,0x00,0x33]
+        tne       $0,$3                # CHECK: tne $zero, $3          # encoding: [0x00,0x03,0x00,0x36]
         tnei      $12,-29647
         trunc.w.d $f22,$f15
         trunc.w.s $f28,$f30
Index: test/MC/Mips/mips32r6/valid.s
===================================================================
--- test/MC/Mips/mips32r6/valid.s
+++ test/MC/Mips/mips32r6/valid.s
@@ -152,3 +152,9 @@
         sdbbp     34             # CHECK: sdbbp 34               # encoding: [0x00,0x00,0x08,0x8e]
         sync                     # CHECK: sync                   # encoding: [0x00,0x00,0x00,0x0f]
         sync    1                # CHECK: sync 1                 # encoding: [0x00,0x00,0x00,0x4f]
+        teq     $0,$3            # CHECK: teq $zero, $3          # encoding: [0x00,0x03,0x00,0x34]
+        tge     $0,$3            # CHECK: tge $zero, $3          # encoding: [0x00,0x03,0x00,0x30]
+        tgeu    $0,$3            # CHECK: tgeu $zero, $3         # encoding: [0x00,0x03,0x00,0x31]
+        tlt     $0,$3            # CHECK: tlt $zero, $3          # encoding: [0x00,0x03,0x00,0x32]
+        tltu    $0,$3            # CHECK: tltu $zero, $3         # encoding: [0x00,0x03,0x00,0x33]
+        tne     $0,$3            # CHECK: tne $zero, $3          # encoding: [0x00,0x03,0x00,0x36]
Index: test/MC/Mips/mips4/valid.s
===================================================================
--- test/MC/Mips/mips4/valid.s
+++ test/MC/Mips/mips4/valid.s
@@ -199,15 +199,21 @@
         swr       $s1,-26590($14)
         swxc1     $f19,$12($k0)
         sync                           # CHECK: sync                   # encoding: [0x00,0x00,0x00,0x0f]
+        teq       $0,$3                # CHECK: teq $zero, $3          # encoding: [0x00,0x03,0x00,0x34]
         teqi      $s5,-17504
+        tge       $0,$3                # CHECK: tge $zero, $3          # encoding: [0x00,0x03,0x00,0x30]
         tgei      $s1,5025
         tgeiu     $sp,-28621
+        tgeu      $0,$3                # CHECK: tgeu $zero, $3         # encoding: [0x00,0x03,0x00,0x31]
         tlbp                           # CHECK: tlbp                   # encoding: [0x42,0x00,0x00,0x08]
         tlbr                           # CHECK: tlbr                   # encoding: [0x42,0x00,0x00,0x01]
         tlbwi                          # CHECK: tlbwi                  # encoding: [0x42,0x00,0x00,0x02]
         tlbwr                          # CHECK: tlbwr                  # encoding: [0x42,0x00,0x00,0x06]
+        tlt       $0,$3                # CHECK: tlt $zero, $3          # encoding: [0x00,0x03,0x00,0x32]
         tlti      $14,-21059
         tltiu     $ra,-5076
+        tltu      $0,$3                # CHECK: tltu $zero, $3         # encoding: [0x00,0x03,0x00,0x33]
+        tne       $0,$3                # CHECK: tne $zero, $3          # encoding: [0x00,0x03,0x00,0x36]
         tnei      $12,-29647
         trunc.l.d $f23,$f23
         trunc.l.s $f28,$f31
Index: test/MC/Mips/mips5/valid.s
===================================================================
--- test/MC/Mips/mips5/valid.s
+++ test/MC/Mips/mips5/valid.s
@@ -201,15 +201,21 @@
         swr       $s1,-26590($14)
         swxc1     $f19,$12($k0)
         sync                           # CHECK: sync                   # encoding: [0x00,0x00,0x00,0x0f]
+        teq       $0,$3                # CHECK: teq $zero, $3          # encoding: [0x00,0x03,0x00,0x34]
         teqi      $s5,-17504
+        tge       $0,$3                # CHECK: tge $zero, $3          # encoding: [0x00,0x03,0x00,0x30]
         tgei      $s1,5025
         tgeiu     $sp,-28621
+        tgeu      $0,$3                # CHECK: tgeu $zero, $3         # encoding: [0x00,0x03,0x00,0x31]
         tlbp                           # CHECK: tlbp                   # encoding: [0x42,0x00,0x00,0x08]
         tlbr                           # CHECK: tlbr                   # encoding: [0x42,0x00,0x00,0x01]
         tlbwi                          # CHECK: tlbwi                  # encoding: [0x42,0x00,0x00,0x02]
         tlbwr                          # CHECK: tlbwr                  # encoding: [0x42,0x00,0x00,0x06]
+        tlt       $0,$3                # CHECK: tlt $zero, $3          # encoding: [0x00,0x03,0x00,0x32]
         tlti      $14,-21059
         tltiu     $ra,-5076
+        tltu      $0,$3                # CHECK: tltu $zero, $3         # encoding: [0x00,0x03,0x00,0x33]
+        tne       $0,$3                # CHECK: tne $zero, $3          # encoding: [0x00,0x03,0x00,0x36]
         tnei      $12,-29647
         trunc.l.d $f23,$f23
         trunc.l.s $f28,$f31
Index: test/MC/Mips/mips64/valid.s
===================================================================
--- test/MC/Mips/mips64/valid.s
+++ test/MC/Mips/mips64/valid.s
@@ -218,15 +218,21 @@
         swxc1     $f19,$12($k0)
         sync                           # CHECK: sync                   # encoding: [0x00,0x00,0x00,0x0f]
         sync      1                    # CHECK: sync 1                 # encoding: [0x00,0x00,0x00,0x4f]
+        teq       $0,$3                # CHECK: teq $zero, $3          # encoding: [0x00,0x03,0x00,0x34]
         teqi      $s5,-17504
+        tge       $0,$3                # CHECK: tge $zero, $3          # encoding: [0x00,0x03,0x00,0x30]
         tgei      $s1,5025
         tgeiu     $sp,-28621
+        tgeu      $0,$3                # CHECK: tgeu $zero, $3         # encoding: [0x00,0x03,0x00,0x31]
         tlbp                           # CHECK: tlbp                   # encoding: [0x42,0x00,0x00,0x08]
         tlbr                           # CHECK: tlbr                   # encoding: [0x42,0x00,0x00,0x01]
         tlbwi                          # CHECK: tlbwi                  # encoding: [0x42,0x00,0x00,0x02]
         tlbwr                          # CHECK: tlbwr                  # encoding: [0x42,0x00,0x00,0x06]
+        tlt       $0,$3                # CHECK: tlt $zero, $3          # encoding: [0x00,0x03,0x00,0x32]
         tlti      $14,-21059
         tltiu     $ra,-5076
+        tltu      $0,$3                # CHECK: tltu $zero, $3         # encoding: [0x00,0x03,0x00,0x33]
+        tne       $0,$3                # CHECK: tne $zero, $3          # encoding: [0x00,0x03,0x00,0x36]
         tnei      $12,-29647
         trunc.l.d $f23,$f23
         trunc.l.s $f28,$f31
Index: test/MC/Mips/mips64r2/valid.s
===================================================================
--- test/MC/Mips/mips64r2/valid.s
+++ test/MC/Mips/mips64r2/valid.s
@@ -245,15 +245,21 @@
         swxc1     $f19,$12($k0)
         sync                           # CHECK: sync                   # encoding: [0x00,0x00,0x00,0x0f]
         sync      1                    # CHECK: sync 1                 # encoding: [0x00,0x00,0x00,0x4f]
+        teq       $0,$3                # CHECK: teq $zero, $3          # encoding: [0x00,0x03,0x00,0x34]
         teqi      $s5,-17504
+        tge       $0,$3                # CHECK: tge $zero, $3          # encoding: [0x00,0x03,0x00,0x30]
         tgei      $s1,5025
         tgeiu     $sp,-28621
+        tgeu      $0,$3                # CHECK: tgeu $zero, $3         # encoding: [0x00,0x03,0x00,0x31]
         tlbp                           # CHECK: tlbp                   # encoding: [0x42,0x00,0x00,0x08]
         tlbr                           # CHECK: tlbr                   # encoding: [0x42,0x00,0x00,0x01]
         tlbwi                          # CHECK: tlbwi                  # encoding: [0x42,0x00,0x00,0x02]
         tlbwr                          # CHECK: tlbwr                  # encoding: [0x42,0x00,0x00,0x06]
+        tlt       $0,$3                # CHECK: tlt $zero, $3          # encoding: [0x00,0x03,0x00,0x32]
         tlti      $14,-21059
         tltiu     $ra,-5076
+        tltu      $0,$3                # CHECK: tltu $zero, $3         # encoding: [0x00,0x03,0x00,0x33]
+        tne       $0,$3                # CHECK: tne $zero, $3          # encoding: [0x00,0x03,0x00,0x36]
         tnei      $12,-29647
         trunc.l.d $f23,$f23
         trunc.l.s $f28,$f31
Index: test/MC/Mips/mips64r6/valid.s
===================================================================
--- test/MC/Mips/mips64r6/valid.s
+++ test/MC/Mips/mips64r6/valid.s
@@ -171,3 +171,9 @@
         sdbbp     34             # CHECK: sdbbp 34               # encoding: [0x00,0x00,0x08,0x8e]
         sync                     # CHECK: sync                   # encoding: [0x00,0x00,0x00,0x0f]
         sync    1                # CHECK: sync 1                 # encoding: [0x00,0x00,0x00,0x4f]
+        teq     $0,$3            # CHECK: teq $zero, $3          # encoding: [0x00,0x03,0x00,0x34]
+        tge     $0,$3            # CHECK: tge $zero, $3          # encoding: [0x00,0x03,0x00,0x30]
+        tgeu    $0,$3            # CHECK: tgeu $zero, $3         # encoding: [0x00,0x03,0x00,0x31]
+        tlt     $0,$3            # CHECK: tlt $zero, $3          # encoding: [0x00,0x03,0x00,0x32]
+        tltu    $0,$3            # CHECK: tltu $zero, $3         # encoding: [0x00,0x03,0x00,0x33]
+        tne     $0,$3            # CHECK: tne $zero, $3          # encoding: [0x00,0x03,0x00,0x36]