Index: llvm/trunk/lib/Target/Mips/MicroMipsInstrFPU.td =================================================================== --- llvm/trunk/lib/Target/Mips/MicroMipsInstrFPU.td +++ llvm/trunk/lib/Target/Mips/MicroMipsInstrFPU.td @@ -243,6 +243,8 @@ MFC1_FM_MM<0xe0>, ISA_MICROMIPS, FGR_64; def MFHC1_D64_MM : MFC1_FT<"mfhc1", GPR32Opnd, FGR64Opnd, II_MFHC1>, MFC1_FM_MM<0xc0>, ISA_MICROMIPS, FGR_64; + def MTC1_D64_MM : MTC1_FT<"mtc1", FGR64Opnd, GPR32Opnd, II_MTC1>, + MFC1_FM_MM<0xa0>, ISA_MICROMIPS, FGR_64; } let DecoderNamespace = "MicroMips" in { @@ -405,6 +407,9 @@ def : StoreRegImmPat, ISA_MICROMIPS; } +def : MipsPat<(MipsMTC1_D64 GPR32Opnd:$src), + (MTC1_D64_MM GPR32Opnd:$src)>, ISA_MICROMIPS, FGR_64; + def : MipsPat<(f32 fpimm0), (MTC1_MM ZERO)>, ISA_MICROMIPS32_NOT_MIPS32R6; def : MipsPat<(f32 fpimm0neg), (FNEG_S_MM (MTC1_MM ZERO))>, ISA_MICROMIPS32_NOT_MIPS32R6; Index: llvm/trunk/lib/Target/Mips/MicroMipsInstrInfo.td =================================================================== --- llvm/trunk/lib/Target/Mips/MicroMipsInstrInfo.td +++ llvm/trunk/lib/Target/Mips/MicroMipsInstrInfo.td @@ -1116,6 +1116,27 @@ ISA_MICROMIPS32_NOT_MIPS32R6; } +let AdditionalPredicates = [NotDSP] in { + def PseudoMULT_MM : MultDivPseudo, + ISA_MICROMIPS32_NOT_MIPS32R6; + def PseudoMULTu_MM : MultDivPseudo, + ISA_MICROMIPS32_NOT_MIPS32R6; + def PseudoMFHI_MM : PseudoMFLOHI, + ISA_MICROMIPS32_NOT_MIPS32R6; + def PseudoMFLO_MM : PseudoMFLOHI, + ISA_MICROMIPS32_NOT_MIPS32R6; + def PseudoMTLOHI_MM : PseudoMTLOHI, + ISA_MICROMIPS32_NOT_MIPS32R6; + def PseudoMADD_MM : MAddSubPseudo, + ISA_MICROMIPS32_NOT_MIPS32R6; + def PseudoMADDU_MM : MAddSubPseudo, + ISA_MICROMIPS32_NOT_MIPS32R6; + def PseudoMSUB_MM : MAddSubPseudo, + ISA_MICROMIPS32_NOT_MIPS32R6; + def PseudoMSUBU_MM : MAddSubPseudo, + ISA_MICROMIPS32_NOT_MIPS32R6; +} + def TAILCALL_MM : TailCall, ISA_MIPS1_NOT_32R6_64R6; def TAILCALLREG_MM : TailCallReg, Index: llvm/trunk/lib/Target/Mips/MipsSEInstrInfo.cpp =================================================================== --- llvm/trunk/lib/Target/Mips/MipsSEInstrInfo.cpp +++ llvm/trunk/lib/Target/Mips/MipsSEInstrInfo.cpp @@ -421,12 +421,16 @@ expandERet(MBB, MI); break; case Mips::PseudoMFHI: - Opc = isMicroMips ? Mips::MFHI16_MM : Mips::MFHI; - expandPseudoMFHiLo(MBB, MI, Opc); + expandPseudoMFHiLo(MBB, MI, Mips::MFHI); + break; + case Mips::PseudoMFHI_MM: + expandPseudoMFHiLo(MBB, MI, Mips::MFHI16_MM); break; case Mips::PseudoMFLO: - Opc = isMicroMips ? Mips::MFLO16_MM : Mips::MFLO; - expandPseudoMFHiLo(MBB, MI, Opc); + expandPseudoMFHiLo(MBB, MI, Mips::MFLO); + break; + case Mips::PseudoMFLO_MM: + expandPseudoMFHiLo(MBB, MI, Mips::MFLO16_MM); break; case Mips::PseudoMFHI64: expandPseudoMFHiLo(MBB, MI, Mips::MFHI64); Index: llvm/trunk/lib/Target/Mips/MipsSubtarget.h =================================================================== --- llvm/trunk/lib/Target/Mips/MipsSubtarget.h +++ llvm/trunk/lib/Target/Mips/MipsSubtarget.h @@ -295,8 +295,10 @@ bool inMips16HardFloat() const { return inMips16Mode() && InMips16HardFloat; } - bool inMicroMipsMode() const { return InMicroMipsMode; } - bool inMicroMips32r6Mode() const { return InMicroMipsMode && hasMips32r6(); } + bool inMicroMipsMode() const { return InMicroMipsMode && !InMips16Mode; } + bool inMicroMips32r6Mode() const { + return inMicroMipsMode() && hasMips32r6(); + } bool hasDSP() const { return HasDSP; } bool hasDSPR2() const { return HasDSPR2; } bool hasDSPR3() const { return HasDSPR3; } @@ -312,14 +314,14 @@ } bool useSmallSection() const { return UseSmallSection; } - bool hasStandardEncoding() const { return !inMips16Mode(); } + bool hasStandardEncoding() const { return !InMips16Mode && !InMicroMipsMode; } bool useSoftFloat() const { return IsSoftFloat; } bool useLongCalls() const { return UseLongCalls; } bool enableLongBranchPass() const { - return hasStandardEncoding() || allowMixed16_32(); + return hasStandardEncoding() || inMicroMipsMode() || allowMixed16_32(); } /// Features related to the presence of specific instructions. Index: llvm/trunk/test/CodeGen/Mips/micromips-mtc-mfc.ll =================================================================== --- llvm/trunk/test/CodeGen/Mips/micromips-mtc-mfc.ll +++ llvm/trunk/test/CodeGen/Mips/micromips-mtc-mfc.ll @@ -57,10 +57,9 @@ ; MM6: # %bb.0: # %entry ; MM6-NEXT: cmp.lt.d $f0, $f12, $f14 # encoding: [0x55,0xcc,0x01,0x15] ; MM6-NEXT: mfc1 $1, $f0 # encoding: [0x54,0x20,0x20,0x3b] -; MM6-NEXT: mtc1 $1, $f0 # encoding: [0x44,0x81,0x00,0x00] +; MM6-NEXT: mtc1 $1, $f0 # encoding: [0x54,0x20,0x28,0x3b] ; MM6-NEXT: sel.d $f0, $f14, $f12 # encoding: [0x55,0x8e,0x02,0xb8] ; MM6-NEXT: jrc $ra # encoding: [0x45,0xbf] -; FIXME: mtc1 is encoded as a regular non-microMIPS instruction entry: %z = fcmp olt double %x, %y %r = select i1 %z, double %x, double %y