Index: lib/CodeGen/MachineBasicBlock.cpp =================================================================== --- lib/CodeGen/MachineBasicBlock.cpp +++ lib/CodeGen/MachineBasicBlock.cpp @@ -1379,7 +1379,12 @@ const_iterator I(Before); // If this is the last insn in the block, don't search forwards. if (I != end()) { - for (++I; I != end() && N > 0; ++I, --N) { + for (++I; I != end() && N > 0; ++I) { + if (I->isDebugInstr()) + continue; + + --N; + MachineOperandIteratorBase::PhysRegInfo Info = ConstMIOperands(*I).analyzePhysReg(Reg, TRI); @@ -1416,6 +1421,11 @@ do { --I; + if (I->isDebugInstr()) + continue; + + --N; + MachineOperandIteratorBase::PhysRegInfo Info = ConstMIOperands(*I).analyzePhysReg(Reg, TRI); @@ -1440,7 +1450,8 @@ // Register must be live if we read it. if (Info.Read) return LQR_Live; - } while (I != begin() && --N > 0); + + } while (I != begin() && N > 0); } // Did we get to the start of the block? @@ -1454,7 +1465,6 @@ return LQR_Dead; } - // At this point we have no idea of the liveness of the register. return LQR_Unknown; } Index: test/CodeGen/AMDGPU/fold-immediate-operand-shrink.mir =================================================================== --- test/CodeGen/AMDGPU/fold-immediate-operand-shrink.mir +++ test/CodeGen/AMDGPU/fold-immediate-operand-shrink.mir @@ -407,3 +407,186 @@ S_ENDPGM implicit %2 ... +--- + +# This requires searching through many DBG_VALUE instructions before the insert poitn, which +# should not count against the search limit. + +name: vcc_liveness_dbg_value_search_before +tracksRegLiveness: true + +body: | + bb.0: + ; GCN-LABEL: name: vcc_liveness_dbg_value_search_before + ; GCN: [[S_MOV_B32_:%[0-9]+]]:sreg_32_xm0 = S_MOV_B32 12345 + ; GCN: [[DEF:%[0-9]+]]:vgpr_32 = IMPLICIT_DEF + ; GCN: DBG_VALUE $noreg, 0 + ; GCN: DBG_VALUE $noreg, 0 + ; GCN: DBG_VALUE $noreg, 0 + ; GCN: DBG_VALUE $noreg, 0 + ; GCN: DBG_VALUE $noreg, 0 + ; GCN: DBG_VALUE $noreg, 0 + ; GCN: DBG_VALUE $noreg, 0 + ; GCN: DBG_VALUE $noreg, 0 + ; GCN: DBG_VALUE $noreg, 0 + ; GCN: DBG_VALUE $noreg, 0 + ; GCN: DBG_VALUE $noreg, 0 + ; GCN: DBG_VALUE $noreg, 0 + ; GCN: DBG_VALUE $noreg, 0 + ; GCN: DBG_VALUE $noreg, 0 + ; GCN: DBG_VALUE $noreg, 0 + ; GCN: DBG_VALUE $noreg, 0 + ; GCN: DBG_VALUE $noreg, 0 + ; GCN: DBG_VALUE $noreg, 0 + ; GCN: DBG_VALUE $noreg, 0 + ; GCN: DBG_VALUE $noreg, 0 + ; GCN: DBG_VALUE $noreg, 0 + ; GCN: DBG_VALUE $noreg, 0 + ; GCN: DBG_VALUE $noreg, 0 + ; GCN: DBG_VALUE $noreg, 0 + ; GCN: DBG_VALUE $noreg, 0 + ; GCN: DBG_VALUE $noreg, 0 + ; GCN: DBG_VALUE $noreg, 0 + ; GCN: DBG_VALUE $noreg, 0 + ; GCN: [[V_ADD_I32_e32_:%[0-9]+]]:vgpr_32 = V_ADD_I32_e32 [[S_MOV_B32_]], [[DEF]], implicit-def $vcc, implicit $exec + ; GCN: S_ENDPGM implicit [[V_ADD_I32_e32_]] + %0:sreg_32_xm0 = S_MOV_B32 12345 + %1:vgpr_32 = IMPLICIT_DEF + DBG_VALUE $noreg, 0 + DBG_VALUE $noreg, 0 + DBG_VALUE $noreg, 0 + DBG_VALUE $noreg, 0 + DBG_VALUE $noreg, 0 + DBG_VALUE $noreg, 0 + DBG_VALUE $noreg, 0 + DBG_VALUE $noreg, 0 + DBG_VALUE $noreg, 0 + DBG_VALUE $noreg, 0 + DBG_VALUE $noreg, 0 + DBG_VALUE $noreg, 0 + DBG_VALUE $noreg, 0 + DBG_VALUE $noreg, 0 + DBG_VALUE $noreg, 0 + DBG_VALUE $noreg, 0 + DBG_VALUE $noreg, 0 + DBG_VALUE $noreg, 0 + DBG_VALUE $noreg, 0 + DBG_VALUE $noreg, 0 + DBG_VALUE $noreg, 0 + DBG_VALUE $noreg, 0 + DBG_VALUE $noreg, 0 + DBG_VALUE $noreg, 0 + DBG_VALUE $noreg, 0 + DBG_VALUE $noreg, 0 + DBG_VALUE $noreg, 0 + DBG_VALUE $noreg, 0 + %2:vgpr_32, %3:sreg_64 = V_ADD_I32_e64 %0, %1, implicit $exec + S_ENDPGM implicit %2 + +... +--- + +# This requires searching through many DBG_VALUE instructions after the insert point, which +# should not count against the search limit. + +name: vcc_liveness_dbg_value_search_after +tracksRegLiveness: true + +body: | + bb.0: + ; GCN-LABEL: name: vcc_liveness_dbg_value_search_after + ; GCN: [[S_MOV_B32_:%[0-9]+]]:sreg_32_xm0 = S_MOV_B32 12345 + ; GCN: [[DEF:%[0-9]+]]:vgpr_32 = IMPLICIT_DEF + ; GCN: [[V_ADD_I32_e32_:%[0-9]+]]:vgpr_32 = V_ADD_I32_e32 [[S_MOV_B32_]], [[DEF]], implicit-def $vcc, implicit $exec + ; GCN: DBG_VALUE $noreg, 0 + ; GCN: DBG_VALUE $noreg, 0 + ; GCN: DBG_VALUE $noreg, 0 + ; GCN: DBG_VALUE $noreg, 0 + ; GCN: DBG_VALUE $noreg, 0 + ; GCN: DBG_VALUE $noreg, 0 + ; GCN: DBG_VALUE $noreg, 0 + ; GCN: DBG_VALUE $noreg, 0 + ; GCN: DBG_VALUE $noreg, 0 + ; GCN: DBG_VALUE $noreg, 0 + ; GCN: DBG_VALUE $noreg, 0 + ; GCN: DBG_VALUE $noreg, 0 + ; GCN: DBG_VALUE $noreg, 0 + ; GCN: DBG_VALUE $noreg, 0 + ; GCN: DBG_VALUE $noreg, 0 + ; GCN: DBG_VALUE $noreg, 0 + ; GCN: DBG_VALUE $noreg, 0 + ; GCN: DBG_VALUE $noreg, 0 + ; GCN: DBG_VALUE $noreg, 0 + ; GCN: DBG_VALUE $noreg, 0 + ; GCN: DBG_VALUE $noreg, 0 + ; GCN: DBG_VALUE $noreg, 0 + ; GCN: DBG_VALUE $noreg, 0 + ; GCN: DBG_VALUE $noreg, 0 + ; GCN: DBG_VALUE $noreg, 0 + ; GCN: DBG_VALUE $noreg, 0 + ; GCN: DBG_VALUE $noreg, 0 + ; GCN: DBG_VALUE $noreg, 0 + ; GCN: S_ENDPGM implicit [[V_ADD_I32_e32_]] + %0:sreg_32_xm0 = S_MOV_B32 12345 + %1:vgpr_32 = IMPLICIT_DEF + S_NOP 0 + S_NOP 0 + S_NOP 0 + S_NOP 0 + S_NOP 0 + S_NOP 0 + S_NOP 0 + S_NOP 0 + S_NOP 0 + S_NOP 0 + S_NOP 0 + S_NOP 0 + S_NOP 0 + S_NOP 0 + S_NOP 0 + S_NOP 0 + S_NOP 0 + S_NOP 0 + S_NOP 0 + S_NOP 0 + S_NOP 0 + S_NOP 0 + S_NOP 0 + S_NOP 0 + S_NOP 0 + S_NOP 0 + S_NOP 0 + S_NOP 0 + %2:vgpr_32, %3:sreg_64 = V_ADD_I32_e64 %0, %1, implicit $exec + DBG_VALUE $noreg, 0 + DBG_VALUE $noreg, 0 + DBG_VALUE $noreg, 0 + DBG_VALUE $noreg, 0 + DBG_VALUE $noreg, 0 + DBG_VALUE $noreg, 0 + DBG_VALUE $noreg, 0 + DBG_VALUE $noreg, 0 + DBG_VALUE $noreg, 0 + DBG_VALUE $noreg, 0 + DBG_VALUE $noreg, 0 + DBG_VALUE $noreg, 0 + DBG_VALUE $noreg, 0 + DBG_VALUE $noreg, 0 + DBG_VALUE $noreg, 0 + DBG_VALUE $noreg, 0 + DBG_VALUE $noreg, 0 + DBG_VALUE $noreg, 0 + DBG_VALUE $noreg, 0 + DBG_VALUE $noreg, 0 + DBG_VALUE $noreg, 0 + DBG_VALUE $noreg, 0 + DBG_VALUE $noreg, 0 + DBG_VALUE $noreg, 0 + DBG_VALUE $noreg, 0 + DBG_VALUE $noreg, 0 + DBG_VALUE $noreg, 0 + DBG_VALUE $noreg, 0 + $vcc = S_MOV_B64 0 + S_ENDPGM implicit %2 + +...