Index: lib/Target/WebAssembly/WebAssemblyMCInstLower.cpp =================================================================== --- lib/Target/WebAssembly/WebAssemblyMCInstLower.cpp +++ lib/Target/WebAssembly/WebAssemblyMCInstLower.cpp @@ -285,8 +285,13 @@ static unsigned regInstructionToStackInstruction(unsigned OpCode) { // For most opcodes, this function could have been implemented as "return // OpCode + 1", but since table-gen alphabetically sorts them, this cannot be - // guaranteed (see e.g. BR and BR_IF), so we table-gen a giant switch - // statement instead. + // guaranteed (see e.g. BR and BR_IF). Instead we use a giant switch statement + // generated by a custom TableGen backend (WebAssemblyStackifierEmitter.cpp) + // that emits switch cases of the form + // + // case WebAssembly::RegisterInstr: return WebAssembly::StackInstr; + // + // for every pair of equivalent register and stack instructions. switch (OpCode) { default: llvm_unreachable( Index: utils/TableGen/WebAssemblyStackifierEmitter.cpp =================================================================== --- utils/TableGen/WebAssemblyStackifierEmitter.cpp +++ utils/TableGen/WebAssemblyStackifierEmitter.cpp @@ -17,6 +17,13 @@ namespace llvm { +// Find all register WebAssembly instructions and their corresponding stack +// instructions. For each pair, emit a switch case of the form +// +// case WebAssembly::RegisterInstr: return WebAssembly::StackInstr; +// +// This is useful for converting instructions from their register form to their +// equivalent stack form. void EmitWebAssemblyStackifier(RecordKeeper &RK, raw_ostream &OS) { Record *InstrClass = RK.getClass("WebAssemblyInst"); for (auto &RecordPair : RK.getDefs()) { @@ -24,7 +31,7 @@ bool IsStackBased = RecordPair.second->getValueAsBit("StackBased"); if (IsStackBased) continue; OS << " case WebAssembly::" << RecordPair.first << ": return " - << "WebAssembly::" << RecordPair.first << "_S; break;\n"; + << "WebAssembly::" << RecordPair.first << "_S;\n"; } }