Index: llvm/trunk/lib/Target/Hexagon/HexagonISelLowering.h =================================================================== --- llvm/trunk/lib/Target/Hexagon/HexagonISelLowering.h +++ llvm/trunk/lib/Target/Hexagon/HexagonISelLowering.h @@ -223,6 +223,9 @@ bool mayBeEmittedAsTailCall(const CallInst *CI) const override; + unsigned getRegisterByName(const char* RegName, EVT VT, + SelectionDAG &DAG) const override; + /// If a physical register, this returns the register that receives the /// exception address on entry to an EH pad. unsigned Index: llvm/trunk/lib/Target/Hexagon/HexagonISelLowering.cpp =================================================================== --- llvm/trunk/lib/Target/Hexagon/HexagonISelLowering.cpp +++ llvm/trunk/lib/Target/Hexagon/HexagonISelLowering.cpp @@ -22,6 +22,7 @@ #include "llvm/ADT/APInt.h" #include "llvm/ADT/ArrayRef.h" #include "llvm/ADT/SmallVector.h" +#include "llvm/ADT/StringSwitch.h" #include "llvm/CodeGen/CallingConvLower.h" #include "llvm/CodeGen/MachineFrameInfo.h" #include "llvm/CodeGen/MachineFunction.h" @@ -240,6 +241,18 @@ return true; } +unsigned HexagonTargetLowering::getRegisterByName(const char* RegName, EVT VT, + SelectionDAG &DAG) const { + // Just support r19, the linux kernel uses it. + unsigned Reg = StringSwitch(RegName) + .Case("r19", Hexagon::R19) + .Default(0); + if (Reg) + return Reg; + + report_fatal_error("Invalid register name global variable"); +} + /// LowerCallResult - Lower the result values of an ISD::CALL into the /// appropriate copies out of appropriate physical registers. This assumes that /// Chain/Glue are the input chain/glue to use, and that TheCall is the call Index: llvm/trunk/test/CodeGen/Hexagon/namedreg.ll =================================================================== --- llvm/trunk/test/CodeGen/Hexagon/namedreg.ll +++ llvm/trunk/test/CodeGen/Hexagon/namedreg.ll @@ -0,0 +1,13 @@ +; RUN: llc -mattr=+reserved-r19 -march=hexagon < %s | FileCheck %s +define dso_local i32 @r19f() #0 { +entry: + %0 = call i32 @llvm.read_register.i32(metadata !0) + ret i32 %0 +} + +declare i32 @llvm.read_register.i32(metadata) #1 + +!llvm.named.register.r19 = !{!0} + +!0 = !{!"r19"} +; CHECK: r0 = r19