[AMDGPU] Preliminary patch for divergence driven instruction selection. Operands Folding 1.

[alex-t]

Summary

This patch contains changes that are necessary to handle new patterns that will appear when the main patch for divergence driven ISel will be applied. We need this change before to avoid breaking tests.

Testing: lit tests Codegen/AMDGPU passed.

[arsenm]

Needs tests and comments.

I think I know what cases you are trying to solve, and there's usually a better way. Do you have a specific example?

lib/Target/AMDGPU/SIFoldOperands.cpp

387

Commented out code

[rampitec]

lib/Target/AMDGPU/SIFoldOperands.cpp

385

80 chars per line please.

[rampitec]

These are 3 different changes. You can also write mir tests for these even if it does not appear in current codegen.

[alex-t]

Change has been split to several separate.
MIR test added

[alex-t]

In D51316#1214831, @arsenm wrote:

Needs tests and comments.

I think I know what cases you are trying to solve, and there's usually a better way. Do you have a specific example?

This is NFC. It does nothing until the TD files are not changed.

My change in the TD files contain re-worked isVGPRImm predicate function.
It extends the set of the immediate operands selected to S_MOV. The goal is to save VGPRs.
If it detects that scalar operand is not valid in current position it asks SIInstrInfo if the user is commutable and if the scalar operand will be valid when commuted.
If so it selects to S_MOV.

The aim of the change is to workaround the COPY inserted by the generic ISel code.
It inserts the COPY SGPR to VGPR because it does not aware that we will commute further.

[rampitec]

It is not really an NFC. It changes codegen even if you cannot forge such an IR right now. You cannot write a test for an NFC. NFC is something like changing comment or formatting, or changing a vector with list. Also NFC does not usually need a review. Please change subject.

Also fix formatting.

test/CodeGen/AMDGPU/fold-imm-copy.mir

6

I do not see this copy even with current trunk, so the test needs to be different, at least test checks.

[alex-t]

test/CodeGen/AMDGPU/fold-imm-copy.mir

6

That is correct. You cannot see the COPY since it is created by general ISel code with new isVGPRImm predicate function. Current trunk contains old one. So no COPY so far.
The test checks that the SREG is folded. When I submit the rest of the changes it won't need to be updated.

[rampitec]

test/CodeGen/AMDGPU/fold-imm-copy.mir

6

This does not sound relevant. This is a mir test and ISel is not involved, you can create any artificial MIR you want to handle.

[alex-t]

test/CodeGen/AMDGPU/fold-imm-copy.mir

6

MIR test was generated by the new ISel and contains COPY:

line 32: %9:vgpr_32 = COPY %8

Thus, the aim of the check is that SIFoldOperands with the change is able to fold the SGPR with the COPY in between.

[rampitec]

test/CodeGen/AMDGPU/fold-imm-copy.mir

6

The problem is there is no copy even without the optimization. There is v_mov_b32 instruction though. Did you mean to check that mov was eliminated?

[alex-t]

Formatting. Test corrected.

test/CodeGen/AMDGPU/fold-imm-copy.mir

6

Oh... Yes. I understand :) No COPY after folding but V_MOV instead.
V_MOV will be cleared by DCE further if no uses that require VGPR exist.
The GCN-NOT COPY is odd.

[rampitec]

LGTM

[arsenm]

test/CodeGen/AMDGPU/fold-imm-copy.mir

10–19

You should be able to drop the registers section

[alex-t]

'registers' section dropped in test

[alex-t]

[alex-t]

comitted: r341068
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@341068 91177308-0d34-0410-b5e6-96231b3b80d8

lib/Target/AMDGPU/SIFoldOperands.cpp

 
   bool FoldingImm = OpToFold.isImm();
 
-  // In order to fold immediates into copies, we need to change the
-  // copy to a MOV.
   if (FoldingImm && UseMI->isCopy()) {
     unsigned DestReg = UseMI->getOperand(0).getReg();
     const TargetRegisterClass *DestRC

       MRI->getRegClass(DestReg) :
       TRI->getPhysRegClass(DestReg);
 
+    unsigned SrcReg  = UseMI->getOperand(1).getReg();
+    if (TargetRegisterInfo::isVirtualRegister(DestReg) &&
+      TargetRegisterInfo::isVirtualRegister(SrcReg)) {
+      const TargetRegisterClass * SrcRC = MRI->getRegClass(SrcReg);
+      if (TRI->isSGPRClass(SrcRC) && TRI->hasVGPRs(DestRC)) {
+        MachineRegisterInfo::use_iterator NextUse;
+        SmallVector<FoldCandidate, 4> CopyUses;
+        for (MachineRegisterInfo::use_iterator
+          Use = MRI->use_begin(DestReg), E = MRI->use_end();
+          Use != E; Use = NextUse) {
+          NextUse = std::next(Use);
+          FoldCandidate FC = FoldCandidate(Use->getParent(),
+           Use.getOperandNo(), &UseMI->getOperand(1));
+          CopyUses.push_back(FC);
+       }
+        for (auto & F : CopyUses) {
+          foldOperand(*F.OpToFold, F.UseMI, F.UseOpNo,
+           FoldList, CopiesToReplace);
+        }
+      }
+    }
+
+    // In order to fold immediates into copies, we need to change the
+    // copy to a MOV.
+
     unsigned MovOp = TII->getMovOpcode(DestRC);
     if (MovOp == AMDGPU::COPY)
       return;

test/CodeGen/AMDGPU/fold-imm-copy.mir

+# RUN: llc -march=amdgcn -run-pass si-fold-operands %s -o - | FileCheck -check-prefix=GCN %s
+
+# GCN-LABEL:       name: fold-imm-copy
+# GCN:             [[SREG:%[0-9+]]]:sreg_32_xm0 = S_MOV_B32 65535
+# GCN:             V_AND_B32_e32 [[SREG]]
+
+name: fold-imm-copy
+body:             |
+  bb.0:
+    liveins: $vgpr0, $sgpr0_sgpr1
+    %0:vgpr_32 = COPY $vgpr0
+    %1:sgpr_64 = COPY $sgpr0_sgpr1
+    %2:sreg_128 = S_LOAD_DWORDX4_IMM %1, 9, 0
+    %3:sreg_32_xm0 = S_MOV_B32 2
+    %4:vgpr_32 = V_LSHLREV_B32_e64 killed %3, %0, implicit $exec
+    %5:vgpr_32 = V_MOV_B32_e32 0, implicit $exec
+    %6:vreg_64 = REG_SEQUENCE killed %4, %subreg.sub0, killed %5, %subreg.sub1
+    %7:vgpr_32 = BUFFER_LOAD_DWORD_ADDR64 %6, %2, 0, 4, 0, 0, 0, implicit $exec
+    %8:sreg_32_xm0 = S_MOV_B32 65535
+    %9:vgpr_32 = COPY %8
+    %10:vgpr_32 = V_AND_B32_e32 %7, %9, implicit $exec
+...