Index: llvm/trunk/lib/Target/X86/X86.td =================================================================== --- llvm/trunk/lib/Target/X86/X86.td +++ llvm/trunk/lib/Target/X86/X86.td @@ -59,10 +59,7 @@ "Support xsaves instructions">; def FeatureSSE1 : SubtargetFeature<"sse", "X86SSELevel", "SSE1", - "Enable SSE instructions", - // SSE codegen depends on cmovs, and all - // SSE1+ processors support them. - [FeatureCMOV]>; + "Enable SSE instructions">; def FeatureSSE2 : SubtargetFeature<"sse2", "X86SSELevel", "SSE2", "Enable SSE2 instructions", [FeatureSSE1]>; @@ -93,8 +90,7 @@ // feature, because SSE2 can be disabled (e.g. for compiling OS kernels) // without disabling 64-bit mode. def Feature64Bit : SubtargetFeature<"64bit", "HasX86_64", "true", - "Support 64-bit instructions", - [FeatureCMOV]>; + "Support 64-bit instructions">; def FeatureCMPXCHG16B : SubtargetFeature<"cx16", "HasCmpxchg16b", "true", "64-bit with cmpxchg16b", [Feature64Bit]>; @@ -481,7 +477,7 @@ foreach P = ["pentium3", "pentium3m"] in { def : Proc; + FeatureFXSR, FeatureNOPL, FeatureCMOV]>; } // Enable the PostRAScheduler for SSE2 and SSE3 class cpus. @@ -496,12 +492,12 @@ def : ProcessorModel<"pentium-m", GenericPostRAModel, [FeatureX87, FeatureSlowUAMem16, FeatureMMX, - FeatureSSE2, FeatureFXSR, FeatureNOPL]>; + FeatureSSE2, FeatureFXSR, FeatureNOPL, FeatureCMOV]>; foreach P = ["pentium4", "pentium4m"] in { def : ProcessorModel; + FeatureSSE2, FeatureFXSR, FeatureNOPL, FeatureCMOV]>; } // Intel Quark. @@ -510,15 +506,16 @@ // Intel Core Duo. def : ProcessorModel<"yonah", SandyBridgeModel, [FeatureX87, FeatureSlowUAMem16, FeatureMMX, FeatureSSE3, - FeatureFXSR, FeatureNOPL]>; + FeatureFXSR, FeatureNOPL, FeatureCMOV]>; // NetBurst. def : ProcessorModel<"prescott", GenericPostRAModel, [FeatureX87, FeatureSlowUAMem16, FeatureMMX, FeatureSSE3, - FeatureFXSR, FeatureNOPL]>; + FeatureFXSR, FeatureNOPL, FeatureCMOV]>; def : ProcessorModel<"nocona", GenericPostRAModel, [ FeatureX87, FeatureSlowUAMem16, + FeatureCMOV, FeatureMMX, FeatureSSE3, FeatureFXSR, @@ -530,6 +527,7 @@ def : ProcessorModel<"core2", SandyBridgeModel, [ FeatureX87, FeatureSlowUAMem16, + FeatureCMOV, FeatureMMX, FeatureSSSE3, FeatureFXSR, @@ -541,6 +539,7 @@ def : ProcessorModel<"penryn", SandyBridgeModel, [ FeatureX87, FeatureSlowUAMem16, + FeatureCMOV, FeatureMMX, FeatureSSE41, FeatureFXSR, @@ -555,6 +554,7 @@ ProcIntelAtom, FeatureX87, FeatureSlowUAMem16, + FeatureCMOV, FeatureMMX, FeatureSSSE3, FeatureFXSR, @@ -575,6 +575,7 @@ class SilvermontProc : ProcessorModel : ProcessorModel : ProcessorModel; } foreach P = ["k8", "opteron", "athlon64", "athlon-fx"] in { def : Proc; + FeatureFXSR, FeatureNOPL, Feature64Bit, FeatureSlowSHLD, + FeatureCMOV]>; } foreach P = ["k8-sse3", "opteron-sse3", "athlon64-sse3"] in { def : Proc; + FeatureFXSR, FeatureNOPL, FeatureCMPXCHG16B, FeatureSlowSHLD, + FeatureCMOV]>; } foreach P = ["amdfam10", "barcelona"] in { def : Proc; + FeatureSlowSHLD, FeatureLAHFSAHF, FeatureCMOV]>; } // Bobcat def : Proc<"btver1", [ FeatureX87, + FeatureCMOV, FeatureMMX, FeatureSSSE3, FeatureSSE4A, @@ -949,6 +957,7 @@ // Jaguar def : ProcessorModel<"btver2", BtVer2Model, [ FeatureX87, + FeatureCMOV, FeatureMMX, FeatureAVX, FeatureFXSR, @@ -975,6 +984,7 @@ // Bulldozer def : Proc<"bdver1", [ FeatureX87, + FeatureCMOV, FeatureXOP, FeatureFMA4, FeatureCMPXCHG16B, @@ -998,6 +1008,7 @@ // Piledriver def : Proc<"bdver2", [ FeatureX87, + FeatureCMOV, FeatureXOP, FeatureFMA4, FeatureCMPXCHG16B, @@ -1026,6 +1037,7 @@ // Steamroller def : Proc<"bdver3", [ FeatureX87, + FeatureCMOV, FeatureXOP, FeatureFMA4, FeatureCMPXCHG16B, @@ -1056,6 +1068,7 @@ // Excavator def : Proc<"bdver4", [ FeatureX87, + FeatureCMOV, FeatureMMX, FeatureAVX2, FeatureFXSR, @@ -1093,6 +1106,7 @@ FeatureBMI2, FeatureCLFLUSHOPT, FeatureCLZERO, + FeatureCMOV, FeatureCMPXCHG16B, FeatureF16C, FeatureFMA, @@ -1127,7 +1141,7 @@ def : Proc<"winchip2", [FeatureX87, FeatureSlowUAMem16, Feature3DNow]>; def : Proc<"c3", [FeatureX87, FeatureSlowUAMem16, Feature3DNow]>; def : Proc<"c3-2", [FeatureX87, FeatureSlowUAMem16, FeatureMMX, - FeatureSSE1, FeatureFXSR]>; + FeatureSSE1, FeatureFXSR, FeatureCMOV]>; // We also provide a generic 64-bit specific x86 processor model which tries to // be good for modern chips without enabling instruction set encodings past the @@ -1141,6 +1155,7 @@ // forming a common base for them. def : ProcessorModel<"x86-64", SandyBridgeModel, [ FeatureX87, + FeatureCMOV, FeatureMMX, FeatureSSE2, FeatureFXSR, Index: llvm/trunk/lib/Target/X86/X86Subtarget.h =================================================================== --- llvm/trunk/lib/Target/X86/X86Subtarget.h +++ llvm/trunk/lib/Target/X86/X86Subtarget.h @@ -542,7 +542,9 @@ bool hasX87() const { return HasX87; } bool hasNOPL() const { return HasNOPL; } - bool hasCMov() const { return HasCMov; } + // SSE codegen depends on cmovs, and all SSE1+ processors support them. + // All 64-bit processors support cmov. + bool hasCMov() const { return HasCMov || X86SSELevel >= SSE1 || is64Bit(); } bool hasSSE1() const { return X86SSELevel >= SSE1; } bool hasSSE2() const { return X86SSELevel >= SSE2; } bool hasSSE3() const { return X86SSELevel >= SSE3; } Index: llvm/trunk/test/CodeGen/X86/atomic-minmax-i6432.ll =================================================================== --- llvm/trunk/test/CodeGen/X86/atomic-minmax-i6432.ll +++ llvm/trunk/test/CodeGen/X86/atomic-minmax-i6432.ll @@ -1,6 +1,6 @@ ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py -; RUN: llc -mattr=+cmov,cx16 -mtriple=i386-pc-linux -verify-machineinstrs < %s | FileCheck %s -check-prefix=LINUX -; RUN: llc -mattr=cx16 -mtriple=i386-macosx -relocation-model=pic -verify-machineinstrs < %s | FileCheck %s -check-prefix=PIC +; RUN: llc -mattr=+cmov -mtriple=i386-pc-linux -verify-machineinstrs < %s | FileCheck %s -check-prefix=LINUX +; RUN: llc -mattr=+cmov -mtriple=i386-macosx -relocation-model=pic -verify-machineinstrs < %s | FileCheck %s -check-prefix=PIC @sc64 = external global i64 Index: llvm/trunk/test/CodeGen/X86/atomic32.ll =================================================================== --- llvm/trunk/test/CodeGen/X86/atomic32.ll +++ llvm/trunk/test/CodeGen/X86/atomic32.ll @@ -1,7 +1,7 @@ ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py ; RUN: llc < %s -O0 -mtriple=x86_64-unknown-unknown -mcpu=corei7 -verify-machineinstrs | FileCheck %s -check-prefixes=X64,X64-CMOV ; RUN: llc < %s -O0 -mtriple=i686-unknown-unknown -mcpu=corei7 -verify-machineinstrs | FileCheck %s -check-prefixes=X86,X86-CMOV -; RUN: llc < %s -O0 -mtriple=i686-unknown-unknown -mcpu=corei7 -mattr=-cmov -verify-machineinstrs | FileCheck %s --check-prefixes=X86,X86-NOCMOV +; RUN: llc < %s -O0 -mtriple=i686-unknown-unknown -mcpu=corei7 -mattr=-cmov,-sse -verify-machineinstrs | FileCheck %s --check-prefixes=X86,X86-NOCMOV @sc32 = external global i32