Index: lib/Target/RISCV/RISCVInstrInfoA.td =================================================================== --- lib/Target/RISCV/RISCVInstrInfoA.td +++ lib/Target/RISCV/RISCVInstrInfoA.td @@ -44,6 +44,17 @@ def _AQ_RL : AMO_rr<funct5, 1, 1, funct3, opcodestr # ".aqrl">; } +multiclass AtomicStPat<PatFrag StoreOp, RVInst Inst, RegisterClass StTy> { + def : Pat<(StoreOp GPR:$rs1, StTy:$rs2), (Inst StTy:$rs2, GPR:$rs1, 0)>; + def : Pat<(StoreOp AddrFI:$rs1, StTy:$rs2), (Inst StTy:$rs2, AddrFI:$rs1, 0)>; + def : Pat<(StoreOp (add GPR:$rs1, simm12:$imm12), StTy:$rs2), + (Inst StTy:$rs2, GPR:$rs1, simm12:$imm12)>; + def : Pat<(StoreOp (add AddrFI:$rs1, simm12:$imm12), StTy:$rs2), + (Inst StTy:$rs2, AddrFI:$rs1, simm12:$imm12)>; + def : Pat<(StoreOp (IsOrAdd AddrFI:$rs1, simm12:$imm12), StTy:$rs2), + (Inst StTy:$rs2, AddrFI:$rs1, simm12:$imm12)>; +} + //===----------------------------------------------------------------------===// // Instructions //===----------------------------------------------------------------------===// @@ -91,7 +102,7 @@ defm : LdPat<atomic_load_16, LH>; defm : LdPat<atomic_load_32, LW>; -defm : StPat<atomic_store_8, SB, GPR>; -defm : StPat<atomic_store_16, SH, GPR>; -defm : StPat<atomic_store_32, SW, GPR>; -} // Predicates = [HasStdExtF] +defm : AtomicStPat<atomic_store_8, SB, GPR>; +defm : AtomicStPat<atomic_store_16, SH, GPR>; +defm : AtomicStPat<atomic_store_32, SW, GPR>; +} // Predicates = [HasStdExtA] Index: test/CodeGen/RISCV/atomic-load-store.ll =================================================================== --- test/CodeGen/RISCV/atomic-load-store.ll +++ test/CodeGen/RISCV/atomic-load-store.ll @@ -350,7 +350,7 @@ ; ; RV32IA-LABEL: atomic_store_i8_unordered: ; RV32IA: # %bb.0: -; RV32IA-NEXT: sb a0, 0(a1) +; RV32IA-NEXT: sb a1, 0(a0) ; RV32IA-NEXT: ret store atomic i8 %b, i8* %a unordered, align 1 ret void @@ -369,7 +369,7 @@ ; ; RV32IA-LABEL: atomic_store_i8_monotonic: ; RV32IA: # %bb.0: -; RV32IA-NEXT: sb a0, 0(a1) +; RV32IA-NEXT: sb a1, 0(a0) ; RV32IA-NEXT: ret store atomic i8 %b, i8* %a monotonic, align 1 ret void @@ -389,7 +389,7 @@ ; RV32IA-LABEL: atomic_store_i8_release: ; RV32IA: # %bb.0: ; RV32IA-NEXT: fence rw, w -; RV32IA-NEXT: sb a0, 0(a1) +; RV32IA-NEXT: sb a1, 0(a0) ; RV32IA-NEXT: ret store atomic i8 %b, i8* %a release, align 1 ret void @@ -409,7 +409,7 @@ ; RV32IA-LABEL: atomic_store_i8_seq_cst: ; RV32IA: # %bb.0: ; RV32IA-NEXT: fence rw, w -; RV32IA-NEXT: sb a0, 0(a1) +; RV32IA-NEXT: sb a1, 0(a0) ; RV32IA-NEXT: ret store atomic i8 %b, i8* %a seq_cst, align 1 ret void @@ -428,7 +428,7 @@ ; ; RV32IA-LABEL: atomic_store_i16_unordered: ; RV32IA: # %bb.0: -; RV32IA-NEXT: sh a0, 0(a1) +; RV32IA-NEXT: sh a1, 0(a0) ; RV32IA-NEXT: ret store atomic i16 %b, i16* %a unordered, align 2 ret void @@ -447,7 +447,7 @@ ; ; RV32IA-LABEL: atomic_store_i16_monotonic: ; RV32IA: # %bb.0: -; RV32IA-NEXT: sh a0, 0(a1) +; RV32IA-NEXT: sh a1, 0(a0) ; RV32IA-NEXT: ret store atomic i16 %b, i16* %a monotonic, align 2 ret void @@ -467,7 +467,7 @@ ; RV32IA-LABEL: atomic_store_i16_release: ; RV32IA: # %bb.0: ; RV32IA-NEXT: fence rw, w -; RV32IA-NEXT: sh a0, 0(a1) +; RV32IA-NEXT: sh a1, 0(a0) ; RV32IA-NEXT: ret store atomic i16 %b, i16* %a release, align 2 ret void @@ -487,7 +487,7 @@ ; RV32IA-LABEL: atomic_store_i16_seq_cst: ; RV32IA: # %bb.0: ; RV32IA-NEXT: fence rw, w -; RV32IA-NEXT: sh a0, 0(a1) +; RV32IA-NEXT: sh a1, 0(a0) ; RV32IA-NEXT: ret store atomic i16 %b, i16* %a seq_cst, align 2 ret void @@ -506,7 +506,7 @@ ; ; RV32IA-LABEL: atomic_store_i32_unordered: ; RV32IA: # %bb.0: -; RV32IA-NEXT: sw a0, 0(a1) +; RV32IA-NEXT: sw a1, 0(a0) ; RV32IA-NEXT: ret store atomic i32 %b, i32* %a unordered, align 4 ret void @@ -525,7 +525,7 @@ ; ; RV32IA-LABEL: atomic_store_i32_monotonic: ; RV32IA: # %bb.0: -; RV32IA-NEXT: sw a0, 0(a1) +; RV32IA-NEXT: sw a1, 0(a0) ; RV32IA-NEXT: ret store atomic i32 %b, i32* %a monotonic, align 4 ret void @@ -545,7 +545,7 @@ ; RV32IA-LABEL: atomic_store_i32_release: ; RV32IA: # %bb.0: ; RV32IA-NEXT: fence rw, w -; RV32IA-NEXT: sw a0, 0(a1) +; RV32IA-NEXT: sw a1, 0(a0) ; RV32IA-NEXT: ret store atomic i32 %b, i32* %a release, align 4 ret void @@ -565,7 +565,7 @@ ; RV32IA-LABEL: atomic_store_i32_seq_cst: ; RV32IA: # %bb.0: ; RV32IA-NEXT: fence rw, w -; RV32IA-NEXT: sw a0, 0(a1) +; RV32IA-NEXT: sw a1, 0(a0) ; RV32IA-NEXT: ret store atomic i32 %b, i32* %a seq_cst, align 4 ret void