Index: lib/Target/Mips/MicroMipsInstrFormats.td =================================================================== --- lib/Target/Mips/MicroMipsInstrFormats.td +++ lib/Target/Mips/MicroMipsInstrFormats.td @@ -41,6 +41,18 @@ // MicroMIPS 16-bit Instruction Formats //===----------------------------------------------------------------------===// +class LOGIC_FM_MM16 funct> { + bits<3> rt; + bits<3> rs; + + bits<16> Inst; + + let Inst{15-10} = 0x11; + let Inst{9-6} = funct; + let Inst{5-3} = rt; + let Inst{2-0} = rs; +} + class ADDIUS5_FM_MM16 { bits<5> rd; bits<4> imm; Index: lib/Target/Mips/MicroMipsInstrInfo.td =================================================================== --- lib/Target/Mips/MicroMipsInstrInfo.td +++ lib/Target/Mips/MicroMipsInstrInfo.td @@ -92,6 +92,23 @@ let mayLoad = 1; } +class LogicRMM16 : + MicroMipsInst16<(outs RO:$dst), (ins RO:$rs, RO:$rt), + !strconcat(opstr, "\t$rt, $rs"), + [(set RO:$dst, (OpNode RO:$rs, RO:$rt))], Itin, FrmR> { + let isCommutable = 1; + let Constraints = "$rt = $dst"; +} + +class NotMM16 : + MicroMipsInst16<(outs RO:$rt), (ins RO:$rs), + !strconcat(opstr, "\t$rt, $rs"), + [(set RO:$rt, (not RO:$rs))], NoItinerary, FrmR> { + let isCommutable = 0; +} + class AddImmUS5 : MicroMipsInst16<(outs RO:$dst), (ins RO:$rd, simm5_addius5:$imm), !strconcat(opstr, "\t$rd, $imm"), [], NoItinerary, FrmR> { @@ -183,6 +200,13 @@ !strconcat(opstr, "\t$rs, $offset"), [], IIBranch, FrmI, opstr>; } +def AND16_MM : LogicRMM16<"and16", GPRMM16Opnd, II_AND, and>, + LOGIC_FM_MM16<0x2>; +def OR16_MM : LogicRMM16<"or16", GPRMM16Opnd, II_OR, or>, + LOGIC_FM_MM16<0x3>; +def XOR16_MM : LogicRMM16<"xor16", GPRMM16Opnd, II_XOR, xor>, + LOGIC_FM_MM16<0x1>; +def NOT16_MM : NotMM16<"not16", GPRMM16Opnd>, LOGIC_FM_MM16<0x0>; def ADDIUS5_MM : AddImmUS5<"addius5", GPR32Opnd>, ADDIUS5_FM_MM16; def ADDIUSP_MM : AddImmUSP<"addiusp">, ADDIUSP_FM_MM16; def MFHI16_MM : MoveFromHILOMM<"mfhi", GPR32Opnd, AC0>, MFHILO_FM_MM16<0x10>; Index: test/MC/Mips/micromips-16-bit-instructions.s =================================================================== --- test/MC/Mips/micromips-16-bit-instructions.s +++ test/MC/Mips/micromips-16-bit-instructions.s @@ -9,6 +9,10 @@ #------------------------------------------------------------------------------ # Little endian #------------------------------------------------------------------------------ +# CHECK-EL: and16 $16, $2 # encoding: [0x82,0x44] +# CHECK-EL: not16 $17, $3 # encoding: [0x0b,0x44] +# CHECK-EL: or16 $16, $4 # encoding: [0xc4,0x44] +# CHECK-EL: xor16 $17, $5 # encoding: [0x4d,0x44] # CHECK-EL: addius5 $7, -2 # encoding: [0xfc,0x4c] # CHECK-EL: addiusp -255 # encoding: [0x03,0x4e] # CHECK-EL: mfhi $9 # encoding: [0x09,0x46] @@ -25,6 +29,10 @@ #------------------------------------------------------------------------------ # Big endian #------------------------------------------------------------------------------ +# CHECK-EB: and16 $16, $2 # encoding: [0x44,0x82] +# CHECK-EB: not16 $17, $3 # encoding: [0x44,0x0b] +# CHECK-EB: or16 $16, $4 # encoding: [0x44,0xc4] +# CHECK-EB: xor16 $17, $5 # encoding: [0x44,0x4d] # CHECK-EB: addius5 $7, -2 # encoding: [0x4c,0xfc] # CHECK-EB: addiusp -255 # encoding: [0x4e,0x03] # CHECK-EB: mfhi $9 # encoding: [0x46,0x09] @@ -39,6 +47,10 @@ # CHECK-EB: jalrs16 $9 # encoding: [0x45,0xe9] # CHECK-EB: move $zero, $zero # encoding: [0x0c,0x00] + and16 $16, $2 + not16 $17, $3 + or16 $16, $4 + xor16 $17, $5 addius5 $7, -2 addiusp -255 mfhi $9 Index: test/MC/Mips/micromips-invalid.s =================================================================== --- /dev/null +++ test/MC/Mips/micromips-invalid.s @@ -0,0 +1,7 @@ +# RUN: not llvm-mc %s -triple=mipsel -show-encoding -mattr=micromips 2>%t1 +# RUN: FileCheck %s < %t1 + + and16 $16, $8 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: invalid operand for instruction + not16 $18, $9 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: invalid operand for instruction + or16 $16, $10 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: invalid operand for instruction + xor16 $15, $5 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: invalid operand for instruction