Index: include/llvm/CodeGen/MachineScheduler.h =================================================================== --- include/llvm/CodeGen/MachineScheduler.h +++ include/llvm/CodeGen/MachineScheduler.h @@ -675,6 +675,10 @@ // scheduled instruction. SmallVector ReservedCycles; + // For each PIdx, stores first index into ReservedCycles that corresponds to + // it. + SmallVector ProcessorResourceList; + #ifndef NDEBUG // Remember the greatest possible stall as an upper bound on the number of // times we should retry the pending queue because of a hazard. @@ -749,7 +753,12 @@ /// cycle. unsigned getLatencyStallCycles(SUnit *SU); - unsigned getNextResourceCycle(unsigned PIdx, unsigned Cycles); + unsigned getNextResourceCycleByInstance(unsigned InstanceIndex, + unsigned Cycles); + + std::pair + getNextResourceCycle(unsigned PIdx, unsigned InstanceCount, + unsigned Cycles); bool checkHazard(SUnit *SU); Index: include/llvm/CodeGen/TargetSchedule.h =================================================================== --- include/llvm/CodeGen/TargetSchedule.h +++ include/llvm/CodeGen/TargetSchedule.h @@ -116,6 +116,11 @@ return SchedModel.getProcResource(PIdx); } + /// Get the processor resource table. + const MCProcResourceDesc *getProcResourceTable() const { + return SchedModel.ProcResourceTable; + } + #if !defined(NDEBUG) || defined(LLVM_ENABLE_DUMP) const char *getResourceName(unsigned PIdx) const { if (!PIdx) Index: lib/CodeGen/MachineScheduler.cpp =================================================================== --- lib/CodeGen/MachineScheduler.cpp +++ lib/CodeGen/MachineScheduler.cpp @@ -1846,6 +1846,7 @@ ZoneCritResIdx = 0; IsResourceLimited = false; ReservedCycles.clear(); + ProcessorResourceList.clear(); #ifndef NDEBUG // Track the maximum number of stall cycles that could arise either from the // latency of a DAG edge or the number of cycles that a processor resource is @@ -1884,8 +1885,18 @@ SchedModel = smodel; Rem = rem; if (SchedModel->hasInstrSchedModel()) { - ExecutedResCounts.resize(SchedModel->getNumProcResourceKinds()); - ReservedCycles.resize(SchedModel->getNumProcResourceKinds(), InvalidCycle); + const MCProcResourceDesc *Resources = SchedModel->getProcResourceTable(); + unsigned ResourceCount = SchedModel->getNumProcResourceKinds(); + ProcessorResourceList.resize(ResourceCount); + ExecutedResCounts.resize(ResourceCount); + unsigned NumUnits = 0; + + for (unsigned i = 0; i < ResourceCount; ++i) { + ProcessorResourceList[i] = NumUnits; + NumUnits += (Resources + i)->NumUnits; + } + + ReservedCycles.resize(NumUnits, InvalidCycle); } } @@ -1906,11 +1917,12 @@ return 0; } -/// Compute the next cycle at which the given processor resource can be -/// scheduled. + +/// Compute the next cycle at which the given processor resource unit +/// can be scheduled. unsigned SchedBoundary:: -getNextResourceCycle(unsigned PIdx, unsigned Cycles) { - unsigned NextUnreserved = ReservedCycles[PIdx]; +getNextResourceCycleByInstance(unsigned InstanceIndex, unsigned Cycles) { + unsigned NextUnreserved = ReservedCycles[InstanceIndex]; // If this resource has never been used, always return cycle zero. if (NextUnreserved == InvalidCycle) return 0; @@ -1920,6 +1932,35 @@ return NextUnreserved; } +/// Compute the next cycle at which the given processor resource can be +/// scheduled. Returns (NextCycle, InstanceIDAssignedTo). +std::pair SchedBoundary:: +getNextResourceCycle(unsigned PIdx, unsigned ResCount, unsigned Cycles) { + unsigned MinNextUnreserved = 0; + unsigned InstanceID = 0; + bool ResourceConsidered = false; + unsigned ResourceInstanceStartIndex = ProcessorResourceList[PIdx]; + unsigned NumberOfInstances = SchedModel->getProcResource(PIdx)->NumUnits; + + for (unsigned Offset; Offset < NumberOfInstances; ++Offset) { + unsigned InstanceIndex = ResourceInstanceStartIndex + Offset; + unsigned NextUnreserved = + getNextResourceCycleByInstance(InstanceIndex, + Cycles); + if (ResourceConsidered) { + if (MinNextUnreserved > NextUnreserved) { + InstanceID = InstanceIndex; + MinNextUnreserved = NextUnreserved; + } + } else { + ResourceConsidered = true; + MinNextUnreserved = NextUnreserved; + InstanceID = InstanceIndex; + } + } + return std::make_pair(MinNextUnreserved, InstanceID); +} + /// Does this SU have a hazard within the current instruction group. /// /// The scheduler supports two modes of hazard recognition. The first is the @@ -1960,8 +2001,11 @@ make_range(SchedModel->getWriteProcResBegin(SC), SchedModel->getWriteProcResEnd(SC))) { unsigned ResIdx = PE.ProcResourceIdx; + unsigned ResCount = SchedModel->getProcResource(ResIdx)->NumUnits; unsigned Cycles = PE.Cycles; - unsigned NRCycle = getNextResourceCycle(ResIdx, Cycles); + unsigned NRCycle, InstanceID; + std::tie(NRCycle, InstanceID) = + getNextResourceCycle(ResIdx, ResCount, Cycles); if (NRCycle > CurrCycle) { #ifndef NDEBUG MaxObservedStall = std::max(Cycles, MaxObservedStall); @@ -2123,10 +2167,14 @@ << "c\n"); } // For reserved resources, record the highest cycle using the resource. - unsigned NextAvailable = getNextResourceCycle(PIdx, Cycles); + unsigned ResCount = SchedModel->getProcResource(PIdx)->NumUnits; + unsigned NextAvailable, InstanceID; + std::tie(NextAvailable, InstanceID) = + getNextResourceCycle(PIdx, ResCount, Cycles); if (NextAvailable > CurrCycle) { LLVM_DEBUG(dbgs() << " Resource conflict: " << SchedModel->getProcResource(PIdx)->Name + << " instance " << InstanceID << " reserved until @" << NextAvailable << "\n"); } return NextAvailable; @@ -2214,12 +2262,16 @@ PE = SchedModel->getWriteProcResEnd(SC); PI != PE; ++PI) { unsigned PIdx = PI->ProcResourceIdx; if (SchedModel->getProcResource(PIdx)->BufferSize == 0) { + unsigned ResCount = SchedModel->getProcResource(PIdx)->NumUnits; + unsigned ReservedUntil, InstanceIndex; + std::tie(ReservedUntil, InstanceIndex) = + getNextResourceCycle(PIdx, ResCount, 0); if (isTop()) { - ReservedCycles[PIdx] = - std::max(getNextResourceCycle(PIdx, 0), NextCycle + PI->Cycles); + ReservedCycles[InstanceIndex] = + std::max(ReservedUntil, NextCycle + PI->Cycles); } else - ReservedCycles[PIdx] = NextCycle; + ReservedCycles[InstanceIndex] = NextCycle; } } } Index: test/CodeGen/AArch64/ldst-paired-aliasing.ll =================================================================== --- test/CodeGen/AArch64/ldst-paired-aliasing.ll +++ test/CodeGen/AArch64/ldst-paired-aliasing.ll @@ -13,8 +13,8 @@ ; CHECK: stp xzr, xzr, [sp, #72] ; CHECK: str w9, [sp, #80] ; CHECK: str q0, [sp, #48] -; CHECK: ldr w8, [sp, #48] ; CHECK: str q0, [sp, #64] +; CHECK: ldr w8, [sp, #48] for.body.lr.ph.i.i.i.i.i.i63: %b1 = alloca [10 x i32], align 16 Index: test/CodeGen/ARM/saxpy10-a9.ll =================================================================== --- test/CodeGen/ARM/saxpy10-a9.ll +++ test/CodeGen/ARM/saxpy10-a9.ll @@ -9,50 +9,54 @@ ; should be nicely pipelined. ; ; CHECK: saxpy10: -; CHECK: vldr -; CHECK: vldr -; CHECK: vldr -; CHECK: vldr -; CHECK: vldr +; CHECK: vmov ; CHECK-NEXT: vldr ; CHECK-NEXT: vmul -; CHECK-NEXT: vadd -; CHECK-NEXT: vadd ; CHECK-NEXT: vldr ; CHECK-NEXT: vldr -; CHECK-NEXT: vadd -; CHECK-NEXT: vadd ; CHECK-NEXT: vmul ; CHECK-NEXT: vldr -; CHECK-NEXT: vadd +; CHECK-NEXT: vldr ; CHECK-NEXT: vadd ; CHECK-NEXT: vldr ; CHECK-NEXT: vmul +; CHECK-NEXT: vadd ; CHECK-NEXT: vldr +; CHECK-NEXT: vmul ; CHECK-NEXT: vadd ; CHECK-NEXT: vldr ; CHECK-NEXT: vadd +; CHECK-NEXT: vadd +; CHECK-NEXT: vldr ; CHECK-NEXT: vldr ; CHECK-NEXT: vmul ; CHECK-NEXT: vadd -; CHECK-NEXT: vldr ; CHECK-NEXT: vadd ; CHECK-NEXT: vldr +; CHECK-NEXT: vldr ; CHECK-NEXT: vmul ; CHECK-NEXT: vadd -; CHECK-NEXT: vldr ; CHECK-NEXT: vadd ; CHECK-NEXT: vldr +; CHECK-NEXT: vldr ; CHECK-NEXT: vmul ; CHECK-NEXT: vadd +; CHECK-NEXT: vadd +; CHECK-NEXT: vldr ; CHECK-NEXT: vldr +; CHECK-NEXT: vmul ; CHECK-NEXT: vadd +; CHECK-NEXT: vadd +; CHECK-NEXT: vldr ; CHECK-NEXT: vldr ; CHECK-NEXT: vmul ; CHECK-NEXT: vadd +; CHECK-NEXT: vadd +; CHECK-NEXT: vldr ; CHECK-NEXT: vldr ; CHECK-NEXT: vmul ; CHECK-NEXT: vadd +; CHECK-NEXT: vadd ; CHECK-NEXT: vldr ; CHECK-NEXT: vadd ; CHECK-NEXT: vadd