Index: lib/Target/WebAssembly/WebAssemblyISelLowering.cpp
===================================================================
--- lib/Target/WebAssembly/WebAssemblyISelLowering.cpp
+++ lib/Target/WebAssembly/WebAssemblyISelLowering.cpp
@@ -124,6 +124,9 @@
     }
   }
 
+  if (Subtarget->hasSIMD128() && EnableUnimplementedWasmSIMDInstrs)
+    setOperationAction(ISD::MUL, MVT::v2i64, Expand);
+
   // As a special case, these operators use the type to mean the type to
   // sign-extend from.
   setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i1, Expand);
Index: lib/Target/WebAssembly/WebAssemblyInstrFormats.td
===================================================================
--- lib/Target/WebAssembly/WebAssemblyInstrFormats.td
+++ lib/Target/WebAssembly/WebAssemblyInstrFormats.td
@@ -119,46 +119,6 @@
                 !strconcat("f64.", !strconcat(name, "\t$dst, $lhs, $rhs")),
                 !strconcat("f64.", name), f64Inst>;
 }
-multiclass SIMDBinaryInt<SDNode node, string name, bits<32> baseInst> {
-  defm _I8x16 : SIMD_I<(outs V128:$dst), (ins V128:$lhs, V128:$rhs),
-                       (outs), (ins),
-                       [(set (v16i8 V128:$dst), (node V128:$lhs, V128:$rhs))],
-                       !strconcat("i8x16.",
-                         !strconcat(name, "\t$dst, $lhs, $rhs")),
-                       !strconcat("i8x16.", name), baseInst>;
-  defm _I16x8 : SIMD_I<(outs V128:$dst), (ins V128:$lhs, V128:$rhs),
-                       (outs), (ins),
-                       [(set (v8i16 V128:$dst), (node V128:$lhs, V128:$rhs))],
-                       !strconcat("i16x8.",
-                         !strconcat(name, "\t$dst, $lhs, $rhs")),
-                       !strconcat("i16x8.", name), !add(baseInst, 1)>;
-  defm _I32x4 : SIMD_I<(outs V128:$dst), (ins V128:$lhs, V128:$rhs),
-                       (outs), (ins),
-                       [(set (v4i32 V128:$dst), (node V128:$lhs, V128:$rhs))],
-                       !strconcat("i32x4.",
-                         !strconcat(name, "\t$dst, $lhs, $rhs")),
-                       !strconcat("i32x4.", name), !add(baseInst, 2)>;
-  defm _I64x2 : SIMD_I<(outs V128:$dst), (ins V128:$lhs, V128:$rhs),
-                       (outs), (ins),
-                       [(set (v2i64 V128:$dst), (node V128:$lhs, V128:$rhs))],
-                       !strconcat("i64x2.",
-                         !strconcat(name, "\t$dst, $lhs, $rhs")),
-                       !strconcat("i64x2.", name), !add(baseInst, 3)>;
-}
-multiclass SIMDBinaryFP<SDNode node, string name, bits<32> baseInst> {
-  defm _F32x4 : SIMD_I<(outs V128:$dst), (ins V128:$lhs, V128:$rhs),
-                       (outs), (ins),
-                       [(set (v4f32 V128:$dst), (node V128:$lhs, V128:$rhs))],
-                       !strconcat("f32x4.",
-                         !strconcat(name, "\t$dst, $lhs, $rhs")),
-                       !strconcat("f32x4.", name), baseInst>;
-  defm _F64x2 : SIMD_I<(outs V128:$dst), (ins V128:$lhs, V128:$rhs),
-                       (outs), (ins),
-                       [(set (v2f64 V128:$dst), (node V128:$lhs, V128:$rhs))],
-                       !strconcat("f64x2.",
-                         !strconcat(name, "\t$dst, $lhs, $rhs")),
-                       !strconcat("f64x2.", name), !add(baseInst, 1)>;
-}
 multiclass ComparisonInt<CondCode cond, string name, bits<32> i32Inst, bits<32> i64Inst> {
   defm _I32 : I<(outs I32:$dst), (ins I32:$lhs, I32:$rhs), (outs), (ins),
                 [(set I32:$dst, (setcc I32:$lhs, I32:$rhs, cond))],
Index: lib/Target/WebAssembly/WebAssemblyInstrSIMD.td
===================================================================
--- lib/Target/WebAssembly/WebAssemblyInstrSIMD.td
+++ lib/Target/WebAssembly/WebAssemblyInstrSIMD.td
@@ -18,59 +18,12 @@
 foreach SIZE = [2, 4, 8, 16, 32] in
 def LaneIdx#SIZE : ImmLeaf<i32, "return 0 <= Imm && Imm < "#SIZE#";">;
 
-// const vectors
 multiclass ConstVec<ValueType vec_t, dag ops, dag pat, string args> {
   defm CONST_V128_#vec_t : SIMD_I<(outs V128:$dst), ops, (outs), ops,
                                   [(set V128:$dst, (vec_t pat))],
                                   "v128.const\t$dst, "#args,
                                   "v128.const\t"#args, 0>;
 }
-defm "" : ConstVec<v16i8,
-                   (ins vec_i8imm_op:$i0, vec_i8imm_op:$i1,
-                        vec_i8imm_op:$i2, vec_i8imm_op:$i3,
-                        vec_i8imm_op:$i4, vec_i8imm_op:$i5,
-                        vec_i8imm_op:$i6, vec_i8imm_op:$i7,
-                        vec_i8imm_op:$i8, vec_i8imm_op:$i9,
-                        vec_i8imm_op:$iA, vec_i8imm_op:$iB,
-                        vec_i8imm_op:$iC, vec_i8imm_op:$iD,
-                        vec_i8imm_op:$iE, vec_i8imm_op:$iF),
-                   (build_vector ImmI8:$i0, ImmI8:$i1, ImmI8:$i2, ImmI8:$i3,
-                                 ImmI8:$i4, ImmI8:$i5, ImmI8:$i6, ImmI8:$i7,
-                                 ImmI8:$i8, ImmI8:$i9, ImmI8:$iA, ImmI8:$iB,
-                                 ImmI8:$iC, ImmI8:$iD, ImmI8:$iE, ImmI8:$iF),
-                   !strconcat("$i0, $i1, $i2, $i3, $i4, $i5, $i6, $i7, ",
-                              "$i8, $i9, $iA, $iB, $iC, $iD, $iE, $iF")>;
-defm "" : ConstVec<v8i16,
-                   (ins vec_i16imm_op:$i0, vec_i16imm_op:$i1,
-                        vec_i16imm_op:$i2, vec_i16imm_op:$i3,
-                        vec_i16imm_op:$i4, vec_i16imm_op:$i5,
-                        vec_i16imm_op:$i6, vec_i16imm_op:$i7),
-                   (build_vector
-                     ImmI16:$i0, ImmI16:$i1, ImmI16:$i2, ImmI16:$i3,
-                     ImmI16:$i4, ImmI16:$i5, ImmI16:$i6, ImmI16:$i7),
-                   "$i0, $i1, $i2, $i3, $i4, $i5, $i6, $i7">;
-defm "" : ConstVec<v4i32,
-                   (ins vec_i32imm_op:$i0, vec_i32imm_op:$i1,
-                        vec_i32imm_op:$i2, vec_i32imm_op:$i3),
-                   (build_vector (i32 imm:$i0), (i32 imm:$i1),
-                                 (i32 imm:$i2), (i32 imm:$i3)),
-                   "$i0, $i1, $i2, $i3">;
-defm "" : ConstVec<v2i64,
-                  (ins vec_i64imm_op:$i0, vec_i64imm_op:$i1),
-                  (build_vector (i64 imm:$i0), (i64 imm:$i1)),
-                  "$i0, $i1">;
-defm "" : ConstVec<v4f32,
-                   (ins f32imm_op:$i0, f32imm_op:$i1,
-                        f32imm_op:$i2, f32imm_op:$i3),
-                   (build_vector (f32 fpimm:$i0), (f32 fpimm:$i1),
-                                 (f32 fpimm:$i2), (f32 fpimm:$i3)),
-                   "$i0, $i1, $i2, $i3">;
-defm "" : ConstVec<v2f64,
-                  (ins f64imm_op:$i0, f64imm_op:$i1),
-                  (build_vector (f64 fpimm:$i0), (f64 fpimm:$i1)),
-                  "$i0, $i1">;
-
-// lane extraction
 multiclass ExtractLane<ValueType vec_t, string vec, ImmLeaf imm_t,
                        WebAssemblyRegClass reg_t, bits<32> simdop,
                        string suffix = "", SDNode extract = vector_extract> {
@@ -107,24 +60,9 @@
   defm "" : ExtractLane<v8i16, "i16x8", LaneIdx8, I32, !add(baseInst, 2), sign,
                         !cast<PatFrag>("extract_i16x8"#sign)>;
 }
-let Defs = [ARGUMENTS] in {
-defm "" : ExtractLaneExtended<"_s", 9>;
-defm "" : ExtractLaneExtended<"_u", 10>;
-defm "" : ExtractLane<v4i32, "i32x4", LaneIdx4, I32, 13>;
-defm "" : ExtractLane<v2i64, "i64x2", LaneIdx2, I64, 14>;
-defm "" : ExtractLane<v4f32, "f32x4", LaneIdx4, F32, 15>;
-defm "" : ExtractLane<v2f64, "f64x2", LaneIdx2, F64, 16>;
-} // Defs = [ARGUMENTS]
-
-// follow convention of making implicit expansions unsigned
-def : Pat<(i32 (vector_extract (v16i8 V128:$vec), (i32 LaneIdx16:$idx))),
-          (EXTRACT_LANE_v16i8_u V128:$vec, (i32 LaneIdx16:$idx))>;
-def : Pat<(i32 (vector_extract (v8i16 V128:$vec), (i32 LaneIdx8:$idx))),
-          (EXTRACT_LANE_v8i16_u V128:$vec, (i32 LaneIdx8:$idx))>;
-
-// lane replacement
-multiclass ReplaceLane<ValueType vec_t, string vec, WebAssemblyRegClass reg_t,
-                       ValueType lane_t, ImmLeaf imm_t, bits<32> simdop> {
+multiclass ReplaceLane<ValueType vec_t, string vec, ImmLeaf imm_t,
+                       WebAssemblyRegClass reg_t, ValueType lane_t,
+                       bits<32> simdop> {
   defm REPLACE_LANE_#vec_t :
       SIMD_I<(outs V128:$dst), (ins V128:$vec, i32imm_op:$idx, reg_t:$x),
              (outs), (ins i32imm_op:$idx),
@@ -133,16 +71,6 @@
              vec#".replace_lane\t$dst, $vec, $idx, $x",
              vec#".replace_lane\t$idx", simdop>;
 }
-let Defs = [ARGUMENTS] in {
-defm "" : ReplaceLane<v16i8, "i8x16", I32, i32, LaneIdx16, 17>;
-defm "" : ReplaceLane<v8i16, "i16x8", I32, i32, LaneIdx8, 18>;
-defm "" : ReplaceLane<v4i32, "i32x4", I32, i32, LaneIdx4, 19>;
-defm "" : ReplaceLane<v2i64, "i64x2", I64, i64, LaneIdx2, 20>;
-defm "" : ReplaceLane<v4f32, "f32x4", F32, f32, LaneIdx4, 21>;
-defm "" : ReplaceLane<v2f64, "f64x2", F64, f64, LaneIdx2, 22>;
-} // Defs = [ARGUMENTS]
-
-// splats
 def splat2 : PatFrag<(ops node:$x), (build_vector node:$x, node:$x)>;
 def splat4 : PatFrag<(ops node:$x), (build_vector
                        node:$x, node:$x, node:$x, node:$x)>;
@@ -160,26 +88,216 @@
                              [(set (vec_t V128:$dst), (splat_pat reg_t:$x))],
                              vec#".splat\t$dst, $x", vec#".splat", simdop>;
 }
+multiclass SIMDBinary<ValueType vec_t, string vec, SDNode node, string name,
+                      bits<32> simdop> {
+  defm _#vec_t : SIMD_I<(outs V128:$dst), (ins V128:$lhs, V128:$rhs),
+                        (outs), (ins),
+                        [(set (vec_t V128:$dst), (node V128:$lhs, V128:$rhs))],
+                        vec#"."#name#"\t$dst, $lhs, $rhs", vec#"."#name,
+                        simdop>;
+}
+multiclass SIMDBinaryIntNoI64x2<SDNode node, string name, bits<32> baseInst> {
+  defm "" : SIMDBinary<v16i8, "i8x16", node, name, baseInst>;
+  defm "" : SIMDBinary<v8i16, "i16x8", node, name, !add(baseInst, 1)>;
+  defm "" : SIMDBinary<v4i32, "i32x4", node, name, !add(baseInst, 2)>;
+}
+multiclass SIMDBinaryInt<SDNode node, string name, bits<32> baseInst> {
+  defm "" : SIMDBinaryIntNoI64x2<node, name, baseInst>;
+  defm "" : SIMDBinary<v2i64, "i64x2", node, name, !add(baseInst, 3)>;
+}
+multiclass SIMDBinaryFP<SDNode node, string name, bits<32> baseInst> {
+  defm "" : SIMDBinary<v4f32, "f32x4", node, name, baseInst>;
+  defm "" : SIMDBinary<v2f64, "f64x2", node, name, !add(baseInst, 1)>;
+}
+
 let Defs = [ARGUMENTS] in {
+defm "" : ConstVec<v16i8,
+                   (ins vec_i8imm_op:$i0, vec_i8imm_op:$i1,
+                        vec_i8imm_op:$i2, vec_i8imm_op:$i3,
+                        vec_i8imm_op:$i4, vec_i8imm_op:$i5,
+                        vec_i8imm_op:$i6, vec_i8imm_op:$i7,
+                        vec_i8imm_op:$i8, vec_i8imm_op:$i9,
+                        vec_i8imm_op:$iA, vec_i8imm_op:$iB,
+                        vec_i8imm_op:$iC, vec_i8imm_op:$iD,
+                        vec_i8imm_op:$iE, vec_i8imm_op:$iF),
+                   (build_vector ImmI8:$i0, ImmI8:$i1, ImmI8:$i2, ImmI8:$i3,
+                                 ImmI8:$i4, ImmI8:$i5, ImmI8:$i6, ImmI8:$i7,
+                                 ImmI8:$i8, ImmI8:$i9, ImmI8:$iA, ImmI8:$iB,
+                                 ImmI8:$iC, ImmI8:$iD, ImmI8:$iE, ImmI8:$iF),
+                   !strconcat("$i0, $i1, $i2, $i3, $i4, $i5, $i6, $i7, ",
+                              "$i8, $i9, $iA, $iB, $iC, $iD, $iE, $iF")>;
+defm "" : ConstVec<v8i16,
+                   (ins vec_i16imm_op:$i0, vec_i16imm_op:$i1,
+                        vec_i16imm_op:$i2, vec_i16imm_op:$i3,
+                        vec_i16imm_op:$i4, vec_i16imm_op:$i5,
+                        vec_i16imm_op:$i6, vec_i16imm_op:$i7),
+                   (build_vector
+                     ImmI16:$i0, ImmI16:$i1, ImmI16:$i2, ImmI16:$i3,
+                     ImmI16:$i4, ImmI16:$i5, ImmI16:$i6, ImmI16:$i7),
+                   "$i0, $i1, $i2, $i3, $i4, $i5, $i6, $i7">;
+defm "" : ConstVec<v4i32,
+                   (ins vec_i32imm_op:$i0, vec_i32imm_op:$i1,
+                        vec_i32imm_op:$i2, vec_i32imm_op:$i3),
+                   (build_vector (i32 imm:$i0), (i32 imm:$i1),
+                                 (i32 imm:$i2), (i32 imm:$i3)),
+                   "$i0, $i1, $i2, $i3">;
+defm "" : ConstVec<v2i64,
+                  (ins vec_i64imm_op:$i0, vec_i64imm_op:$i1),
+                  (build_vector (i64 imm:$i0), (i64 imm:$i1)),
+                  "$i0, $i1">;
+defm "" : ConstVec<v4f32,
+                   (ins f32imm_op:$i0, f32imm_op:$i1,
+                        f32imm_op:$i2, f32imm_op:$i3),
+                   (build_vector (f32 fpimm:$i0), (f32 fpimm:$i1),
+                                 (f32 fpimm:$i2), (f32 fpimm:$i3)),
+                   "$i0, $i1, $i2, $i3">;
+defm "" : ConstVec<v2f64,
+                  (ins f64imm_op:$i0, f64imm_op:$i1),
+                  (build_vector (f64 fpimm:$i0), (f64 fpimm:$i1)),
+                  "$i0, $i1">;
+defm "" : ExtractLaneExtended<"_s", 9>;
+defm "" : ExtractLaneExtended<"_u", 10>;
+defm "" : ExtractLane<v4i32, "i32x4", LaneIdx4, I32, 13>;
+defm "" : ExtractLane<v2i64, "i64x2", LaneIdx2, I64, 14>;
+defm "" : ExtractLane<v4f32, "f32x4", LaneIdx4, F32, 15>;
+defm "" : ExtractLane<v2f64, "f64x2", LaneIdx2, F64, 16>;
+defm "" : ReplaceLane<v16i8, "i8x16", LaneIdx16, I32, i32, 17>;
+defm "" : ReplaceLane<v8i16, "i16x8", LaneIdx8, I32, i32, 18>;
+defm "" : ReplaceLane<v4i32, "i32x4", LaneIdx4, I32, i32, 19>;
+defm "" : ReplaceLane<v2i64, "i64x2", LaneIdx2, I64, i64, 20>;
+defm "" : ReplaceLane<v4f32, "f32x4", LaneIdx4, F32, f32, 21>;
+defm "" : ReplaceLane<v2f64, "f64x2", LaneIdx2, F64, f64, 22>;
 defm "" : Splat<v16i8, "i8x16", I32, splat16, 3>;
 defm "" : Splat<v8i16, "i16x8", I32, splat8, 4>;
 defm "" : Splat<v4i32, "i32x4", I32, splat4, 5>;
 defm "" : Splat<v2i64, "i64x2", I64, splat2, 6>;
 defm "" : Splat<v4f32, "f32x4", F32, splat4, 7>;
 defm "" : Splat<v2f64, "f64x2", F64, splat2, 8>;
+let isCommutable = 1 in {
+defm ADD : SIMDBinaryInt<add, "add", 24>;
+defm ADD : SIMDBinaryFP<fadd, "add", 122>;
+defm MUL : SIMDBinaryIntNoI64x2<mul, "mul", 32>;
+defm MUL : SIMDBinaryFP<fmul, "mul", 128>;
+} // isCommutable = 1
+defm SUB : SIMDBinaryInt<sub, "sub", 28>;
+defm SUB : SIMDBinaryFP<fsub, "sub", 124>;
+defm DIV : SIMDBinaryFP<fdiv, "div", 126>;
 } // Defs = [ARGUMENTS]
 
-// arithmetic
-let Defs = [ARGUMENTS] in {
-let isCommutable = 1 in
-defm ADD : SIMDBinaryInt<add, "add ", 24>;
-defm SUB : SIMDBinaryInt<sub, "sub ", 28>;
-let isCommutable = 1 in
-defm MUL : SIMDBinaryInt<mul, "mul ", 32>;
-let isCommutable = 1 in
-defm ADD : SIMDBinaryFP<fadd, "add ", 122>;
-defm SUB : SIMDBinaryFP<fsub, "sub ", 124>;
-defm DIV : SIMDBinaryFP<fdiv, "div ", 126>;
-let isCommutable = 1 in
-defm MUL : SIMDBinaryFP<fmul, "mul ", 128>;
-} // Defs = [ARGUMENTS]
+// follow convention of making implicit expansions unsigned
+def : Pat<(i32 (vector_extract (v16i8 V128:$vec), (i32 LaneIdx16:$idx))),
+          (EXTRACT_LANE_v16i8_u V128:$vec, (i32 LaneIdx16:$idx))>;
+def : Pat<(i32 (vector_extract (v8i16 V128:$vec), (i32 LaneIdx8:$idx))),
+          (EXTRACT_LANE_v8i16_u V128:$vec, (i32 LaneIdx8:$idx))>;
+
+// arbitrary other BUILD_VECTOR patterns
+def : Pat<(v16i8 (build_vector
+            (i32 I32:$x0), (i32 I32:$x1), (i32 I32:$x2), (i32 I32:$x3),
+            (i32 I32:$x4), (i32 I32:$x5), (i32 I32:$x6), (i32 I32:$x7),
+            (i32 I32:$x8), (i32 I32:$x9), (i32 I32:$x10), (i32 I32:$x11),
+            (i32 I32:$x12), (i32 I32:$x13), (i32 I32:$x14), (i32 I32:$x15)
+          )),
+          (v16i8 (REPLACE_LANE_v16i8
+            (v16i8 (REPLACE_LANE_v16i8
+              (v16i8 (REPLACE_LANE_v16i8
+                (v16i8 (REPLACE_LANE_v16i8
+                  (v16i8 (REPLACE_LANE_v16i8
+                    (v16i8 (REPLACE_LANE_v16i8
+                      (v16i8 (REPLACE_LANE_v16i8
+                        (v16i8 (REPLACE_LANE_v16i8
+                          (v16i8 (REPLACE_LANE_v16i8
+                            (v16i8 (REPLACE_LANE_v16i8
+                              (v16i8 (REPLACE_LANE_v16i8
+                                (v16i8 (REPLACE_LANE_v16i8
+                                  (v16i8 (REPLACE_LANE_v16i8
+                                    (v16i8 (REPLACE_LANE_v16i8
+                                      (v16i8 (REPLACE_LANE_v16i8
+                                        (v16i8 (SPLAT_v16i8 (i32 I32:$x0))),
+                                        1, I32:$x1
+                                      )),
+                                      2, I32:$x2
+                                    )),
+                                    3, I32:$x3
+                                  )),
+                                  4, I32:$x4
+                                )),
+                                5, I32:$x5
+                              )),
+                              6, I32:$x6
+                            )),
+                            7, I32:$x7
+                          )),
+                          8, I32:$x8
+                        )),
+                        9, I32:$x9
+                      )),
+                      10, I32:$x10
+                    )),
+                    11, I32:$x11
+                  )),
+                  12, I32:$x12
+                )),
+                13, I32:$x13
+              )),
+              14, I32:$x14
+            )),
+            15, I32:$x15
+          ))>;
+def : Pat<(v8i16 (build_vector
+            (i32 I32:$x0), (i32 I32:$x1), (i32 I32:$x2), (i32 I32:$x3),
+            (i32 I32:$x4), (i32 I32:$x5), (i32 I32:$x6), (i32 I32:$x7)
+          )),
+          (v8i16 (REPLACE_LANE_v8i16
+            (v8i16 (REPLACE_LANE_v8i16
+              (v8i16 (REPLACE_LANE_v8i16
+                (v8i16 (REPLACE_LANE_v8i16
+                  (v8i16 (REPLACE_LANE_v8i16
+                    (v8i16 (REPLACE_LANE_v8i16
+                      (v8i16 (REPLACE_LANE_v8i16
+                        (v8i16 (SPLAT_v8i16 (i32 I32:$x0))),
+                        1, I32:$x1
+                      )),
+                      2, I32:$x2
+                    )),
+                    3, I32:$x3
+                  )),
+                  4, I32:$x4
+                )),
+                5, I32:$x5
+              )),
+              6, I32:$x6
+            )),
+            7, I32:$x7
+          ))>;
+def : Pat<(v4i32 (build_vector
+            (i32 I32:$x0), (i32 I32:$x1), (i32 I32:$x2), (i32 I32:$x3)
+          )),
+          (v4i32 (REPLACE_LANE_v4i32
+            (v4i32 (REPLACE_LANE_v4i32
+              (v4i32 (REPLACE_LANE_v4i32
+                (v4i32 (SPLAT_v4i32 (i32 I32:$x0))),
+                1, I32:$x1
+              )),
+              2, I32:$x2
+            )),
+            3, I32:$x3
+          ))>;
+def : Pat<(v2i64 (build_vector (i64 I64:$x0), (i64 I64:$x1))),
+          (v2i64 (REPLACE_LANE_v2i64
+            (v2i64 (SPLAT_v2i64 (i64 I64:$x0))), 1, I64:$x1))>;
+def : Pat<(v4f32 (build_vector
+            (f32 F32:$x0), (f32 F32:$x1), (f32 F32:$x2), (f32 F32:$x3)
+          )),
+          (v4f32 (REPLACE_LANE_v4f32
+            (v4f32 (REPLACE_LANE_v4f32
+              (v4f32 (REPLACE_LANE_v4f32
+                (v4f32 (SPLAT_v4f32 (f32 F32:$x0))),
+                1, F32:$x1
+              )),
+              2, F32:$x2
+            )),
+            3, F32:$x3
+          ))>;
+def : Pat<(v2f64 (build_vector (f64 F64:$x0), (f64 F64:$x1))),
+          (v2f64 (REPLACE_LANE_v2f64
+            (v2f64 (SPLAT_v2f64 (f64 F64:$x0))), 1, F64:$x1))>;
Index: test/CodeGen/WebAssembly/simd-arith.ll
===================================================================
--- test/CodeGen/WebAssembly/simd-arith.ll
+++ test/CodeGen/WebAssembly/simd-arith.ll
@@ -145,13 +145,13 @@
   ret <2 x i64> %a
 }
 
+; v2i64.mul is not in spec
 ; CHECK-LABEL: mul_v2i64
 ; NO-SIMD128-NOT: i64x2
 ; SIMD128-VM-NOT: i64x2
-; SIMD128: .param v128, v128{{$}}
-; SIMD128: .result v128{{$}}
-; SIMD128: i64x2.mul $push0=, $0, $1 # encoding: [0xfd,0x23]{{$}}
-; SIMD128: return $pop0 #
+; SIMD128-NOT: i64x2.mul
+; SIMD128: i64x2.extract_lane
+; SIMD128: i64.mul
 define <2 x i64> @mul_v2i64(<2 x i64> %x, <2 x i64> %y) {
   %a = mul <2 x i64> %x, %y
   ret <2 x i64> %a
Index: test/CodeGen/WebAssembly/simd.ll
===================================================================
--- test/CodeGen/WebAssembly/simd.ll
+++ test/CodeGen/WebAssembly/simd.ll
@@ -83,6 +83,50 @@
   ret <16 x i8> %res
 }
 
+; CHECK-LABEL: build_v16i8:
+; NO-SIMD128-NOT: i8x16
+; SIMD128: .param i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32{{$}}
+; SIMD128: .result v128{{$}}
+; SIMD128: i8x16.splat $push0=, $0 # encoding: [0xfd,0x03]
+; SIMD128: i8x16.replace_lane $push1=, $pop0, 1, $1 # encoding: [0xfd,0x11,0x01]
+; SIMD128: i8x16.replace_lane $push2=, $pop1, 2, $2 # encoding: [0xfd,0x11,0x02]
+; SIMD128: i8x16.replace_lane $push3=, $pop2, 3, $3 # encoding: [0xfd,0x11,0x03]
+; SIMD128: i8x16.replace_lane $push4=, $pop3, 4, $4 # encoding: [0xfd,0x11,0x04]
+; SIMD128: i8x16.replace_lane $push5=, $pop4, 5, $5 # encoding: [0xfd,0x11,0x05]
+; SIMD128: i8x16.replace_lane $push6=, $pop5, 6, $6 # encoding: [0xfd,0x11,0x06]
+; SIMD128: i8x16.replace_lane $push7=, $pop6, 7, $7 # encoding: [0xfd,0x11,0x07]
+; SIMD128: i8x16.replace_lane $push8=, $pop7, 8, $8 # encoding: [0xfd,0x11,0x08]
+; SIMD128: i8x16.replace_lane $push9=, $pop8, 9, $9 # encoding: [0xfd,0x11,0x09]
+; SIMD128: i8x16.replace_lane $push10=, $pop9, 10, $10 # encoding: [0xfd,0x11,0x0a]
+; SIMD128: i8x16.replace_lane $push11=, $pop10, 11, $11 # encoding: [0xfd,0x11,0x0b]
+; SIMD128: i8x16.replace_lane $push12=, $pop11, 12, $12 # encoding: [0xfd,0x11,0x0c]
+; SIMD128: i8x16.replace_lane $push13=, $pop12, 13, $13 # encoding: [0xfd,0x11,0x0d]
+; SIMD128: i8x16.replace_lane $push14=, $pop13, 14, $14 # encoding: [0xfd,0x11,0x0e]
+; SIMD128: i8x16.replace_lane $push15=, $pop14, 15, $15 # encoding: [0xfd,0x11,0x0f]
+; SIMD128: return $pop15 # encoding: [0x0f]
+define <16 x i8> @build_v16i8(i8 %x0, i8 %x1, i8 %x2, i8 %x3,
+                             i8 %x4, i8 %x5, i8 %x6, i8 %x7,
+                             i8 %x8, i8 %x9, i8 %x10, i8 %x11,
+                             i8 %x12, i8 %x13, i8 %x14, i8 %x15) {
+  %t0 = insertelement <16 x i8> undef, i8 %x0, i32 0
+  %t1 = insertelement <16 x i8> %t0, i8 %x1, i32 1
+  %t2 = insertelement <16 x i8> %t1, i8 %x2, i32 2
+  %t3 = insertelement <16 x i8> %t2, i8 %x3, i32 3
+  %t4 = insertelement <16 x i8> %t3, i8 %x4, i32 4
+  %t5 = insertelement <16 x i8> %t4, i8 %x5, i32 5
+  %t6 = insertelement <16 x i8> %t5, i8 %x6, i32 6
+  %t7 = insertelement <16 x i8> %t6, i8 %x7, i32 7
+  %t8 = insertelement <16 x i8> %t7, i8 %x8, i32 8
+  %t9 = insertelement <16 x i8> %t8, i8 %x9, i32 9
+  %t10 = insertelement <16 x i8> %t9, i8 %x10, i32 10
+  %t11 = insertelement <16 x i8> %t10, i8 %x11, i32 11
+  %t12 = insertelement <16 x i8> %t11, i8 %x12, i32 12
+  %t13 = insertelement <16 x i8> %t12, i8 %x13, i32 13
+  %t14 = insertelement <16 x i8> %t13, i8 %x14, i32 14
+  %res = insertelement <16 x i8> %t14, i8 %x15, i32 15
+  ret <16 x i8> %res
+}
+
 ; ==============================================================================
 ; 8 x i16
 ; ==============================================================================
@@ -157,6 +201,32 @@
   ret <8 x i16> %res
 }
 
+; CHECK-LABEL: build_v8i16:
+; NO-SIMD128-NOT: i16x8
+; SIMD128: .param i32, i32, i32, i32, i32, i32, i32, i32{{$}}
+; SIMD128: .result v128{{$}}
+; SIMD128: i16x8.splat $push0=, $0 # encoding: [0xfd,0x04]
+; SIMD128: i16x8.replace_lane $push1=, $pop0, 1, $1 # encoding: [0xfd,0x12,0x01]
+; SIMD128: i16x8.replace_lane $push2=, $pop1, 2, $2 # encoding: [0xfd,0x12,0x02]
+; SIMD128: i16x8.replace_lane $push3=, $pop2, 3, $3 # encoding: [0xfd,0x12,0x03]
+; SIMD128: i16x8.replace_lane $push4=, $pop3, 4, $4 # encoding: [0xfd,0x12,0x04]
+; SIMD128: i16x8.replace_lane $push5=, $pop4, 5, $5 # encoding: [0xfd,0x12,0x05]
+; SIMD128: i16x8.replace_lane $push6=, $pop5, 6, $6 # encoding: [0xfd,0x12,0x06]
+; SIMD128: i16x8.replace_lane $push7=, $pop6, 7, $7 # encoding: [0xfd,0x12,0x07]
+; SIMD128: return $pop7 # encoding: [0x0f]
+define <8 x i16> @build_v8i16(i16 %x0, i16 %x1, i16 %x2, i16 %x3,
+                              i16 %x4, i16 %x5, i16 %x6, i16 %x7) {
+  %t0 = insertelement <8 x i16> undef, i16 %x0, i32 0
+  %t1 = insertelement <8 x i16> %t0, i16 %x1, i32 1
+  %t2 = insertelement <8 x i16> %t1, i16 %x2, i32 2
+  %t3 = insertelement <8 x i16> %t2, i16 %x3, i32 3
+  %t4 = insertelement <8 x i16> %t3, i16 %x4, i32 4
+  %t5 = insertelement <8 x i16> %t4, i16 %x5, i32 5
+  %t6 = insertelement <8 x i16> %t5, i16 %x6, i32 6
+  %res = insertelement <8 x i16> %t6, i16 %x7, i32 7
+  ret <8 x i16> %res
+}
+
 ; ==============================================================================
 ; 4 x i32
 ; ==============================================================================
@@ -206,6 +276,23 @@
   ret <4 x i32> %res
 }
 
+; CHECK-LABEL: build_v4i32:
+; NO-SIMD128-NOT: i32x4
+; SIMD128: .param i32, i32, i32, i32{{$}}
+; SIMD128: .result v128{{$}}
+; SIMD128: i32x4.splat $push0=, $0 # encoding: [0xfd,0x05]
+; SIMD128: i32x4.replace_lane $push1=, $pop0, 1, $1 # encoding: [0xfd,0x13,0x01]
+; SIMD128: i32x4.replace_lane $push2=, $pop1, 2, $2 # encoding: [0xfd,0x13,0x02]
+; SIMD128: i32x4.replace_lane $push3=, $pop2, 3, $3 # encoding: [0xfd,0x13,0x03]
+; SIMD128: return $pop3 # encoding: [0x0f]
+define <4 x i32> @build_v4i32(i32 %x0, i32 %x1, i32 %x2, i32 %x3) {
+  %t0 = insertelement <4 x i32> undef, i32 %x0, i32 0
+  %t1 = insertelement <4 x i32> %t0, i32 %x1, i32 1
+  %t2 = insertelement <4 x i32> %t1, i32 %x2, i32 2
+  %res = insertelement <4 x i32> %t2, i32 %x3, i32 3
+  ret <4 x i32> %res
+}
+
 ; ==============================================================================
 ; 2 x i64
 ; ==============================================================================
@@ -258,6 +345,20 @@
   ret <2 x i64> %res
 }
 
+; CHECK-LABEL: build_v2i64:
+; NO-SIMD128-NOT: i64x2
+; SIMD128-VM-NOT: i64x2
+; SIMD128: .param i64, i64{{$}}
+; SIMD128: .result v128{{$}}
+; SIMD128: i64x2.splat $push0=, $0 # encoding: [0xfd,0x06]
+; SIMD128: i64x2.replace_lane $push1=, $pop0, 1, $1 # encoding: [0xfd,0x14,0x01]
+; SIMD128: return $pop1 # encoding: [0x0f]
+define <2 x i64> @build_v2i64(i64 %x0, i64 %x1) {
+  %t0 = insertelement <2 x i64> undef, i64 %x0, i32 0
+  %res = insertelement <2 x i64> %t0, i64 %x1, i32 1
+  ret <2 x i64> %res
+}
+
 ; ==============================================================================
 ; 4 x f32
 ; ==============================================================================
@@ -309,6 +410,23 @@
   ret <4 x float> %res
 }
 
+; CHECK-LABEL: build_v4f32:
+; NO-SIMD128-NOT: f32x4
+; SIMD128: .param f32, f32, f32, f32{{$}}
+; SIMD128: .result v128{{$}}
+; SIMD128: f32x4.splat $push0=, $0 # encoding: [0xfd,0x07]
+; SIMD128: f32x4.replace_lane $push1=, $pop0, 1, $1 # encoding: [0xfd,0x15,0x01]
+; SIMD128: f32x4.replace_lane $push2=, $pop1, 2, $2 # encoding: [0xfd,0x15,0x02]
+; SIMD128: f32x4.replace_lane $push3=, $pop2, 3, $3 # encoding: [0xfd,0x15,0x03]
+; SIMD128: return $pop3 # encoding: [0x0f]
+define <4 x float> @build_v4f32(float %x0, float %x1, float %x2, float %x3) {
+  %t0 = insertelement <4 x float> undef, float %x0, i32 0
+  %t1 = insertelement <4 x float> %t0, float %x1, i32 1
+  %t2 = insertelement <4 x float> %t1, float %x2, i32 2
+  %res = insertelement <4 x float> %t2, float %x3, i32 3
+  ret <4 x float> %res
+}
+
 ; ==============================================================================
 ; 2 x f64
 ; ==============================================================================
@@ -359,3 +477,17 @@
   %res = insertelement <2 x double> %v, double %x, i32 0
   ret <2 x double> %res
 }
+
+; CHECK-LABEL: build_v2f64:
+; NO-SIMD128-NOT: f64x2
+; SIMD128-VM-NOT: f64x2
+; SIMD128: .param f64, f64{{$}}
+; SIMD128: .result v128{{$}}
+; SIMD128: f64x2.splat $push0=, $0 # encoding: [0xfd,0x08]
+; SIMD128: f64x2.replace_lane $push1=, $pop0, 1, $1 # encoding: [0xfd,0x16,0x01]
+; SIMD128: return $pop1 # encoding: [0x0f]
+define <2 x double> @build_v2f64(double %x0, double %x1) {
+  %t0 = insertelement <2 x double> undef, double %x0, i32 0
+  %res = insertelement <2 x double> %t0, double %x1, i32 1
+  ret <2 x double> %res
+}