Index: lib/Target/AArch64/AArch64SystemOperands.td
===================================================================
--- lib/Target/AArch64/AArch64SystemOperands.td
+++ lib/Target/AArch64/AArch64SystemOperands.td
@@ -576,6 +576,12 @@
 def : ROSysReg<"ICH_EISR_EL2",       0b11, 0b100, 0b1100, 0b1011, 0b011>;
 def : ROSysReg<"ICH_ELRSR_EL2",      0b11, 0b100, 0b1100, 0b1011, 0b101>;
 
+// SVE control registers
+//                                   Op0   Op1    CRn     CRm     Op2
+let Requires = [{ {AArch64::FeatureSVE} }] in {
+def : ROSysReg<"ID_AA64ZFR0_EL1",    0b11, 0b000, 0b0000, 0b0100, 0b100>;
+}
+
 // v8.1a "Limited Ordering Regions" extension-specific system register
 //                         Op0    Op1     CRn     CRm    Op2
 let Requires = [{ {AArch64::HasV8_1aOps} }] in
@@ -1311,6 +1317,15 @@
 
 } // HasV8_4aOps
 
+// SVE control registers
+//                                 Op0   Op1    CRn     CRm     Op2
+let Requires = [{ {AArch64::FeatureSVE} }] in {
+def : RWSysReg<"ZCR_EL1",          0b11, 0b000, 0b0001, 0b0010, 0b000>;
+def : RWSysReg<"ZCR_EL2",          0b11, 0b100, 0b0001, 0b0010, 0b000>;
+def : RWSysReg<"ZCR_EL3",          0b11, 0b110, 0b0001, 0b0010, 0b000>;
+def : RWSysReg<"ZCR_EL12",         0b11, 0b101, 0b0001, 0b0010, 0b000>;
+}
+
 // Cyclone specific system registers
 //                                 Op0    Op1     CRn     CRm    Op2
 let Requires = [{ {AArch64::ProcCyclone} }] in
Index: test/MC/AArch64/arm64-system-encoding.s
===================================================================
--- test/MC/AArch64/arm64-system-encoding.s
+++ test/MC/AArch64/arm64-system-encoding.s
@@ -1,5 +1,6 @@
 ; RUN: not llvm-mc -triple arm64-apple-darwin -show-encoding < %s 2> %t | FileCheck %s
 ; RUN: not llvm-mc -triple arm64-apple-darwin -mattr=+v8.3a -show-encoding < %s 2> %t | FileCheck %s --check-prefix=CHECK-V83
+; RUN: not llvm-mc -triple arm64-apple-darwin -mattr=+sve -show-encoding < %s 2> %t | FileCheck %s --check-prefix=CHECK-SVE
 ; RUN: FileCheck --check-prefix=CHECK-ERRORS < %t %s
 
 foo:
@@ -87,6 +88,10 @@
   msr CPACR_EL1, x3
   msr CPTR_EL2, x3
   msr CPTR_EL3, x3
+  msr ZCR_EL1, x3
+  msr ZCR_EL2, x3
+  msr ZCR_EL3, x3
+  msr ZCR_EL12, x3
   msr CSSELR_EL1, x3
   msr CURRENTEL, x3
   msr DACR32_EL2, x3
@@ -167,6 +172,10 @@
 ; CHECK: msr CPACR_EL1, x3              ; encoding: [0x43,0x10,0x18,0xd5]
 ; CHECK: msr CPTR_EL2, x3               ; encoding: [0x43,0x11,0x1c,0xd5]
 ; CHECK: msr CPTR_EL3, x3               ; encoding: [0x43,0x11,0x1e,0xd5]
+; CHECK-SVE: msr ZCR_EL1, x3            ; encoding: [0x03,0x12,0x18,0xd5]
+; CHECK-SVE: msr ZCR_EL2, x3            ; encoding: [0x03,0x12,0x1c,0xd5]
+; CHECK-SVE: msr ZCR_EL3, x3            ; encoding: [0x03,0x12,0x1e,0xd5]
+; CHECK-SVE: msr ZCR_EL12, x3           ; encoding: [0x03,0x12,0x1d,0xd5]
 ; CHECK: msr CSSELR_EL1, x3             ; encoding: [0x03,0x00,0x1a,0xd5]
 ; CHECK: msr CurrentEL, x3              ; encoding: [0x43,0x42,0x18,0xd5]
 ; CHECK: msr DACR32_EL2, x3             ; encoding: [0x03,0x30,0x1c,0xd5]
@@ -254,6 +263,10 @@
   mrs x3, CPACR_EL1
   mrs x3, CPTR_EL2
   mrs x3, CPTR_EL3
+  mrs x3, ZCR_EL1
+  mrs x3, ZCR_EL2
+  mrs x3, ZCR_EL3
+  mrs x3, ZCR_EL12
   mrs x3, CSSELR_EL1
   mrs x3, CTR_EL0
   mrs x3, CURRENTEL
@@ -277,6 +290,7 @@
   mrs x3, ID_AA64ISAR1_EL1
   mrs x3, ID_AA64MMFR0_EL1
   mrs x3, ID_AA64MMFR1_EL1
+  mrs x3, ID_AA64ZFR0_EL1
   mrs x3, ID_AA64PFR0_EL1
   mrs x3, ID_AA64PFR1_EL1
   mrs x3, IFSR32_EL2
@@ -440,6 +454,10 @@
 ; CHECK: mrs x3, CPACR_EL1              ; encoding: [0x43,0x10,0x38,0xd5]
 ; CHECK: mrs x3, CPTR_EL2               ; encoding: [0x43,0x11,0x3c,0xd5]
 ; CHECK: mrs x3, CPTR_EL3               ; encoding: [0x43,0x11,0x3e,0xd5]
+; CHECK-SVE: mrs x3, ZCR_EL1            ; encoding: [0x03,0x12,0x38,0xd5]
+; CHECK-SVE: mrs x3, ZCR_EL2            ; encoding: [0x03,0x12,0x3c,0xd5]
+; CHECK-SVE: mrs x3, ZCR_EL3            ; encoding: [0x03,0x12,0x3e,0xd5]
+; CHECK-SVE: mrs x3, ZCR_EL12           ; encoding: [0x03,0x12,0x3d,0xd5]
 ; CHECK: mrs x3, CSSELR_EL1             ; encoding: [0x03,0x00,0x3a,0xd5]
 ; CHECK: mrs x3, CTR_EL0                ; encoding: [0x23,0x00,0x3b,0xd5]
 ; CHECK: mrs x3, CurrentEL              ; encoding: [0x43,0x42,0x38,0xd5]
@@ -463,6 +481,7 @@
 ; CHECK: mrs x3, ID_AA64ISAR1_EL1       ; encoding: [0x23,0x06,0x38,0xd5]
 ; CHECK: mrs x3, ID_AA64MMFR0_EL1       ; encoding: [0x03,0x07,0x38,0xd5]
 ; CHECK: mrs x3, ID_AA64MMFR1_EL1       ; encoding: [0x23,0x07,0x38,0xd5]
+; CHECK-SVE: mrs x3, ID_AA64ZFR0_EL1    ; encoding: [0x83,0x04,0x38,0xd5]
 ; CHECK: mrs x3, ID_AA64PFR0_EL1        ; encoding: [0x03,0x04,0x38,0xd5]
 ; CHECK: mrs x3, ID_AA64PFR1_EL1        ; encoding: [0x23,0x04,0x38,0xd5]
 ; CHECK: mrs x3, IFSR32_EL2             ; encoding: [0x23,0x50,0x3c,0xd5]
Index: test/MC/AArch64/basic-a64-diagnostics.s
===================================================================
--- test/MC/AArch64/basic-a64-diagnostics.s
+++ test/MC/AArch64/basic-a64-diagnostics.s
@@ -3623,6 +3623,7 @@
         msr MVFR0_EL1, x12
         msr MVFR1_EL1, x12
         msr MVFR2_EL1, x12
+        msr ID_AA64ZFR0_EL1, x12
         msr ID_AA64PFR0_EL1, x12
         msr ID_AA64PFR1_EL1, x12
         msr ID_AA64DFR0_EL1, x12
@@ -3740,6 +3741,9 @@
 // CHECK-ERROR-NEXT:         msr MVFR2_EL1, x12
 // CHECK-ERROR-NEXT:             ^
 // CHECK-ERROR-NEXT: error: expected writable system register or pstate
+// CHECK-ERROR-NEXT:         msr ID_AA64ZFR0_EL1, x12
+// CHECK-ERROR-NEXT:             ^
+// CHECK-ERROR-NEXT: error: expected writable system register or pstate
 // CHECK-ERROR-NEXT:         msr ID_AA64PFR0_EL1, x12
 // CHECK-ERROR-NEXT:             ^
 // CHECK-ERROR-NEXT: error: expected writable system register or pstate