Index: lib/Target/Mips/MCTargetDesc/MipsMCCodeEmitter.h
===================================================================
--- lib/Target/Mips/MCTargetDesc/MipsMCCodeEmitter.h
+++ lib/Target/Mips/MCTargetDesc/MipsMCCodeEmitter.h
@@ -86,6 +86,12 @@
                            SmallVectorImpl<MCFixup> &Fixups,
                            const MCSubtargetInfo &STI) const;
 
+  // getAddiuspValue - Return binary encoding of the microMIPS addiusp
+  // instruction immediate operand.
+  unsigned getAddiuspValue(const MCInst &MI, unsigned OpNo,
+                           SmallVectorImpl<MCFixup> &Fixups,
+                           const MCSubtargetInfo &STI) const;
+
   // getBranchTargetOpValue - Return binary encoding of the branch
   // target operand. If the machine operand requires relocation,
   // record the relocation and return zero.
Index: lib/Target/Mips/MCTargetDesc/MipsMCCodeEmitter.cpp
===================================================================
--- lib/Target/Mips/MCTargetDesc/MipsMCCodeEmitter.cpp
+++ lib/Target/Mips/MCTargetDesc/MipsMCCodeEmitter.cpp
@@ -371,6 +371,20 @@
 }
 
 unsigned MipsMCCodeEmitter::
+getAddiuspValue(const MCInst &MI, unsigned OpNo,
+                SmallVectorImpl<MCFixup> &Fixups,
+                const MCSubtargetInfo &STI) const {
+
+  const MCOperand &MO = MI.getOperand(OpNo);
+  if (MO.isImm()) {
+    unsigned binary = MO.getImm() & 0x0000ffff;
+    return (((binary & 0x8000) >> 7) | (binary & 0x00ff));
+  }
+
+  return 0;
+}
+
+unsigned MipsMCCodeEmitter::
 getExprOpValue(const MCExpr *Expr,SmallVectorImpl<MCFixup> &Fixups,
                const MCSubtargetInfo &STI) const {
   int64_t Res;
Index: lib/Target/Mips/MicroMipsInstrFormats.td
===================================================================
--- lib/Target/Mips/MicroMipsInstrFormats.td
+++ lib/Target/Mips/MicroMipsInstrFormats.td
@@ -53,6 +53,16 @@
   let Inst{0}     = 0;
 }
 
+class ADDIUSP_FM_MM16 {
+  bits<9> imm;
+
+  bits<16> Inst;
+
+  let Inst{15-10} = 0x13;
+  let Inst{9-1}   = imm;
+  let Inst{0}     = 1;
+}
+
 class MOVE_FM_MM16<bits<6> funct> {
   bits<5> rs;
   bits<5> rd;
Index: lib/Target/Mips/MicroMipsInstrInfo.td
===================================================================
--- lib/Target/Mips/MicroMipsInstrInfo.td
+++ lib/Target/Mips/MicroMipsInstrInfo.td
@@ -12,6 +12,10 @@
   let EncoderMethod = "getAddius5Value";
 }
 
+def addiusp_imm : Operand<i32> {
+  let EncoderMethod = "getAddiuspValue";
+}
+
 def mem_mm_12 : Operand<i32> {
   let PrintMethod = "printMemOperand";
   let MIOperandInfo = (ops GPR32, simm12);
@@ -95,6 +99,10 @@
   let isCommutable = 1;
 }
 
+class AddImmUSP<string opstr> :
+  MicroMipsInst16<(outs), (ins addiusp_imm:$imm),
+                  !strconcat(opstr, "\t$imm"), [], NoItinerary, FrmI>;
+
 class MoveFromHILOMM<string opstr, RegisterOperand RO, Register UseReg> :
       MicroMipsInst16<(outs RO:$rd), (ins), !strconcat(opstr, "\t$rd"),
   [], II_MFHI_MFLO, FrmR> {
@@ -175,6 +183,7 @@
 }
 
 def ADDIUS5_MM : AddImmUS5<"addius5", GPR32Opnd>, ADDIUS5_FM_MM16;
+def ADDIUSP_MM : AddImmUSP<"addiusp">, ADDIUSP_FM_MM16;
 def MFHI16_MM : MoveFromHILOMM<"mfhi", GPR32Opnd, AC0>, MFHILO_FM_MM16<0x10>;
 def MFLO16_MM : MoveFromHILOMM<"mflo", GPR32Opnd, AC0>, MFHILO_FM_MM16<0x12>;
 def MOVE16_MM : MoveMM16<"move", GPR32Opnd>, MOVE_FM_MM16<0x03>;
Index: lib/Target/Mips/MipsCodeEmitter.cpp
===================================================================
--- lib/Target/Mips/MipsCodeEmitter.cpp
+++ lib/Target/Mips/MipsCodeEmitter.cpp
@@ -109,6 +109,7 @@
   unsigned getJumpTargetOpValueMM(const MachineInstr &MI, unsigned OpNo) const;
   unsigned getImm5Shr2Value(const MachineInstr &MI, unsigned OpNo) const;
   unsigned getAddius5Value(const MachineInstr &MI, unsigned OpNo) const;
+  unsigned getAddiuspValue(const MachineInstr &MI, unsigned OpNo) const;
   unsigned getBranchTargetOpValueMM(const MachineInstr &MI,
                                     unsigned OpNo) const;
 
@@ -222,6 +223,12 @@
   return 0;
 }
 
+unsigned MipsCodeEmitter::getAddiuspValue(const MachineInstr &MI,
+                                          unsigned OpNo) const {
+  llvm_unreachable("Unimplemented function.");
+  return 0;
+}
+
 unsigned MipsCodeEmitter::getBranchTargetOpValueMM(const MachineInstr &MI,
                                                    unsigned OpNo) const {
   llvm_unreachable("Unimplemented function.");
Index: test/MC/Mips/micromips-16-bit-instructions.s
===================================================================
--- test/MC/Mips/micromips-16-bit-instructions.s
+++ test/MC/Mips/micromips-16-bit-instructions.s
@@ -10,6 +10,7 @@
 # Little endian
 #------------------------------------------------------------------------------
 # CHECK-EL: addius5 $7, -2          # encoding: [0xfc,0x4c]
+# CHECK-EL: addiusp -255            # encoding: [0x03,0x4e]
 # CHECK-EL: mfhi    $9              # encoding: [0x09,0x46]
 # CHECK-EL: mflo    $9              # encoding: [0x49,0x46]
 # CHECK-EL: move    $25, $1         # encoding: [0x21,0x0f]
@@ -26,6 +27,7 @@
 # Big endian
 #------------------------------------------------------------------------------
 # CHECK-EB: addius5 $7, -2          # encoding: [0x4c,0xfc]
+# CHECK-EB: addiusp -255            # encoding: [0x4e,0x03]
 # CHECK-EB: mfhi    $9              # encoding: [0x46,0x09]
 # CHECK-EB: mflo    $9              # encoding: [0x46,0x49]
 # CHECK-EB: move    $25, $1         # encoding: [0x0f,0x21]
@@ -40,6 +42,7 @@
 # CHECK-EB: nop                     # encoding: [0x00,0x00,0x00,0x00]
 
     addius5 $7, -2
+    addiusp -255
     mfhi    $9
     mflo    $9
     move    $25, $1