Index: lib/Target/RISCV/AsmParser/RISCVAsmParser.cpp
===================================================================
--- lib/Target/RISCV/AsmParser/RISCVAsmParser.cpp
+++ lib/Target/RISCV/AsmParser/RISCVAsmParser.cpp
@@ -666,7 +666,9 @@
                                              bool MatchingInlineAsm) {
   MCInst Inst;
 
-  switch (MatchInstructionImpl(Operands, Inst, ErrorInfo, MatchingInlineAsm)) {
+  auto Result =
+    MatchInstructionImpl(Operands, Inst, ErrorInfo, MatchingInlineAsm);
+  switch (Result) {
   default:
     break;
   case Match_Success:
@@ -687,6 +689,46 @@
     }
     return Error(ErrorLoc, "invalid operand for instruction");
   }
+  }
+
+  // Handle the case the error message is of specific type other than
+  // the generic Match_InvalidOperand, and the corresponding
+  // operand is missing.
+  switch (Result) {
+  default:
+    break;
+  case Match_InvalidImmXLen:
+  case Match_InvalidUImmLog2XLen:
+  case Match_InvalidUImmLog2XLenNonZero:
+  case Match_InvalidUImm5:
+  case Match_InvalidSImm6:
+  case Match_InvalidSImm6NonZero:
+  case Match_InvalidCLUIImm:
+  case Match_InvalidUImm7Lsb00:
+  case Match_InvalidUImm8Lsb00:
+  case Match_InvalidUImm8Lsb000:
+  case Match_InvalidSImm9Lsb0:
+  case Match_InvalidUImm9Lsb000:
+  case Match_InvalidUImm10Lsb00NonZero:
+  case Match_InvalidSImm10Lsb0000NonZero:
+  case Match_InvalidSImm12:
+  case Match_InvalidSImm12Lsb0:
+  case Match_InvalidUImm12:
+  case Match_InvalidSImm13Lsb0:
+  case Match_InvalidUImm20:
+  case Match_InvalidSImm21Lsb0:
+  case Match_InvalidFenceArg:
+  case Match_InvalidFRMArg:
+  case Match_InvalidBareSymbol: {
+    SMLoc ErrorLoc = IDLoc;
+    if (ErrorInfo != ~0U && ErrorInfo >= Operands.size())
+        return Error(ErrorLoc, "too few operands for instruction");
+  }
+  }
+
+  switch(Result) {
+  default:
+    break;
   case Match_InvalidImmXLen:
     if (isRV64()) {
       SMLoc ErrorLoc = ((RISCVOperand &)*Operands[ErrorInfo]).getStartLoc();
Index: test/MC/RISCV/rv32i-invalid.s
===================================================================
--- test/MC/RISCV/rv32i-invalid.s
+++ test/MC/RISCV/rv32i-invalid.s
@@ -138,6 +138,7 @@
 # Too few operands
 ori a0, a1 # CHECK: :[[@LINE]]:1: error: too few operands for instruction
 xor s2, s2 # CHECK: :[[@LINE]]:1: error: too few operands for instruction
+jal a3     # CHECK: :[[@LINE]]:1: error: too few operands for instruction
 
 # Instruction not in the base ISA
 mul a4, ra, s0 # CHECK: :[[@LINE]]:1: error: instruction use requires an option to be enabled