Index: lib/Target/SystemZ/SystemZISelLowering.cpp =================================================================== --- lib/Target/SystemZ/SystemZISelLowering.cpp +++ lib/Target/SystemZ/SystemZISelLowering.cpp @@ -2912,12 +2912,12 @@ DAG.getConstant(32, DL, MVT::i64)); } SDValue Out64 = DAG.getNode(ISD::BITCAST, DL, MVT::f64, In64); - return DAG.getTargetExtractSubreg(SystemZ::subreg_r32, + return DAG.getTargetExtractSubreg(SystemZ::subreg_h32, DL, MVT::f32, Out64); } if (InVT == MVT::f32 && ResVT == MVT::i32) { SDNode *U64 = DAG.getMachineNode(TargetOpcode::IMPLICIT_DEF, DL, MVT::f64); - SDValue In64 = DAG.getTargetInsertSubreg(SystemZ::subreg_r32, DL, + SDValue In64 = DAG.getTargetInsertSubreg(SystemZ::subreg_h32, DL, MVT::f64, SDValue(U64, 0), In); SDValue Out64 = DAG.getNode(ISD::BITCAST, DL, MVT::i64, In64); if (Subtarget.hasHighWord()) Index: lib/Target/SystemZ/SystemZInstrFP.td =================================================================== --- lib/Target/SystemZ/SystemZInstrFP.td +++ lib/Target/SystemZ/SystemZInstrFP.td @@ -97,7 +97,7 @@ (CPSDRsd FP32:$src1, (EXTRACT_SUBREG FP128:$src2, subreg_h64))>; let Predicates = [FeatureVectorEnhancements1] in def : Pat<(fcopysign FP32:$src1, (f32 (fpround (f128 VR128:$src2)))), - (CPSDRsd FP32:$src1, (EXTRACT_SUBREG VR128:$src2, subreg_r64))>; + (CPSDRsd FP32:$src1, (EXTRACT_SUBREG VR128:$src2, subreg_h64))>; // fcopysign with an FP64 result. let isCodeGenOnly = 1 in @@ -110,7 +110,7 @@ (CPSDRdd FP64:$src1, (EXTRACT_SUBREG FP128:$src2, subreg_h64))>; let Predicates = [FeatureVectorEnhancements1] in def : Pat<(fcopysign FP64:$src1, (f64 (fpround (f128 VR128:$src2)))), - (CPSDRdd FP64:$src1, (EXTRACT_SUBREG VR128:$src2, subreg_r64))>; + (CPSDRdd FP64:$src1, (EXTRACT_SUBREG VR128:$src2, subreg_h64))>; // fcopysign with an FP128 result. Use "upper" as the high half and leave // the low half as-is. @@ -187,7 +187,7 @@ let Predicates = [FeatureNoVectorEnhancements1] in { def : Pat<(f32 (fpround FP128:$src)), - (EXTRACT_SUBREG (LEXBR FP128:$src), subreg_hr32)>; + (EXTRACT_SUBREG (LEXBR FP128:$src), subreg_hh32)>; def : Pat<(f64 (fpround FP128:$src)), (EXTRACT_SUBREG (LDXBR FP128:$src), subreg_h64)>; } @@ -446,13 +446,13 @@ def MDEBR : BinaryRRE<"mdebr", 0xB30C, null_frag, FP64, FP32>; def : Pat<(fmul (f64 (fpextend FP32:$src1)), (f64 (fpextend FP32:$src2))), (MDEBR (INSERT_SUBREG (f64 (IMPLICIT_DEF)), - FP32:$src1, subreg_r32), FP32:$src2)>; + FP32:$src1, subreg_h32), FP32:$src2)>; // f64 multiplication of an FP32 register and an f32 memory. def MDEB : BinaryRXE<"mdeb", 0xED0C, null_frag, FP64, load, 4>; def : Pat<(fmul (f64 (fpextend FP32:$src1)), (f64 (extloadf32 bdxaddr12only:$addr))), - (MDEB (INSERT_SUBREG (f64 (IMPLICIT_DEF)), FP32:$src1, subreg_r32), + (MDEB (INSERT_SUBREG (f64 (IMPLICIT_DEF)), FP32:$src1, subreg_h32), bdxaddr12only:$addr)>; // f128 multiplication of two FP64 registers. Index: lib/Target/SystemZ/SystemZInstrInfo.cpp =================================================================== --- lib/Target/SystemZ/SystemZInstrInfo.cpp +++ lib/Target/SystemZ/SystemZInstrInfo.cpp @@ -880,10 +880,10 @@ SystemZ::FP128BitRegClass.contains(SrcReg)) { unsigned SrcRegHi = RI.getMatchingSuperReg(RI.getSubReg(SrcReg, SystemZ::subreg_h64), - SystemZ::subreg_r64, &SystemZ::VR128BitRegClass); + SystemZ::subreg_h64, &SystemZ::VR128BitRegClass); unsigned SrcRegLo = RI.getMatchingSuperReg(RI.getSubReg(SrcReg, SystemZ::subreg_l64), - SystemZ::subreg_r64, &SystemZ::VR128BitRegClass); + SystemZ::subreg_h64, &SystemZ::VR128BitRegClass); BuildMI(MBB, MBBI, DL, get(SystemZ::VMRHG), DestReg) .addReg(SrcRegHi, getKillRegState(KillSrc)) @@ -894,10 +894,10 @@ SystemZ::VR128BitRegClass.contains(SrcReg)) { unsigned DestRegHi = RI.getMatchingSuperReg(RI.getSubReg(DestReg, SystemZ::subreg_h64), - SystemZ::subreg_r64, &SystemZ::VR128BitRegClass); + SystemZ::subreg_h64, &SystemZ::VR128BitRegClass); unsigned DestRegLo = RI.getMatchingSuperReg(RI.getSubReg(DestReg, SystemZ::subreg_l64), - SystemZ::subreg_r64, &SystemZ::VR128BitRegClass); + SystemZ::subreg_h64, &SystemZ::VR128BitRegClass); if (DestRegHi != SrcReg) copyPhysReg(MBB, MBBI, DL, DestRegHi, SrcReg, false); Index: lib/Target/SystemZ/SystemZInstrVector.td =================================================================== --- lib/Target/SystemZ/SystemZInstrVector.td +++ lib/Target/SystemZ/SystemZInstrVector.td @@ -1405,8 +1405,8 @@ (vrep (INSERT_SUBREG (vt (IMPLICIT_DEF)), cls:$scalar, subreg), 0)>; } -defm : ScalarToVectorFP; -defm : ScalarToVectorFP; +defm : ScalarToVectorFP; +defm : ScalarToVectorFP; // Match v2f64 insertions. The AddedComplexity counters the 3 added by // TableGen for the base register operand in VLVG-based integer insertions @@ -1414,10 +1414,10 @@ let AddedComplexity = 4 in { def : Pat<(z_vector_insert (v2f64 VR128:$vec), FP64:$elt, 0), (VPDI (INSERT_SUBREG (v2f64 (IMPLICIT_DEF)), FP64:$elt, - subreg_r64), VR128:$vec, 1)>; + subreg_h64), VR128:$vec, 1)>; def : Pat<(z_vector_insert (v2f64 VR128:$vec), FP64:$elt, 1), (VPDI VR128:$vec, (INSERT_SUBREG (v2f64 (IMPLICIT_DEF)), FP64:$elt, - subreg_r64), 0)>; + subreg_h64), 0)>; } // We extract floating-point element X by replicating (for elements other @@ -1426,14 +1426,14 @@ // extractions and ensures that this version is strictly better. let AddedComplexity = 4 in { def : Pat<(f32 (z_vector_extract (v4f32 VR128:$vec), 0)), - (EXTRACT_SUBREG VR128:$vec, subreg_r32)>; + (EXTRACT_SUBREG VR128:$vec, subreg_h32)>; def : Pat<(f32 (z_vector_extract (v4f32 VR128:$vec), imm32zx2:$index)), - (EXTRACT_SUBREG (VREPF VR128:$vec, imm32zx2:$index), subreg_r32)>; + (EXTRACT_SUBREG (VREPF VR128:$vec, imm32zx2:$index), subreg_h32)>; def : Pat<(f64 (z_vector_extract (v2f64 VR128:$vec), 0)), - (EXTRACT_SUBREG VR128:$vec, subreg_r64)>; + (EXTRACT_SUBREG VR128:$vec, subreg_h64)>; def : Pat<(f64 (z_vector_extract (v2f64 VR128:$vec), imm32zx1:$index)), - (EXTRACT_SUBREG (VREPG VR128:$vec, imm32zx1:$index), subreg_r64)>; + (EXTRACT_SUBREG (VREPG VR128:$vec, imm32zx1:$index), subreg_h64)>; } //===----------------------------------------------------------------------===// Index: lib/Target/SystemZ/SystemZRegisterInfo.td =================================================================== --- lib/Target/SystemZ/SystemZRegisterInfo.td +++ lib/Target/SystemZ/SystemZRegisterInfo.td @@ -25,11 +25,8 @@ def subreg_h32 : SubRegIndex<32, 32>; // Also acts as subreg_lh32. def subreg_l64 : SubRegIndex<64, 0>; def subreg_h64 : SubRegIndex<64, 64>; -def subreg_r32 : SubRegIndex<32, 32>; // Reinterpret a wider reg as 32 bits. -def subreg_r64 : SubRegIndex<64, 64>; // Reinterpret a wider reg as 64 bits. def subreg_hh32 : ComposedSubRegIndex; def subreg_hl32 : ComposedSubRegIndex; -def subreg_hr32 : ComposedSubRegIndex; } // Define a register class that contains values of types TYPES and an @@ -188,7 +185,7 @@ class FPR64 num, string n, FPR32 high> : SystemZRegWithSubregs { let HWEncoding = num; - let SubRegIndices = [subreg_r32]; + let SubRegIndices = [subreg_h32]; } // 8 pairs of FPR64s, with a one-register gap inbetween. @@ -231,7 +228,7 @@ class VR128 num, string n, FPR64 high> : SystemZRegWithSubregs { let HWEncoding = num; - let SubRegIndices = [subreg_r64]; + let SubRegIndices = [subreg_h64]; } // Full vector registers.