Index: lib/CodeGen/RegisterCoalescer.cpp
===================================================================
--- lib/CodeGen/RegisterCoalescer.cpp
+++ lib/CodeGen/RegisterCoalescer.cpp
@@ -686,13 +686,16 @@
 
 /// Copy segments with value number @p SrcValNo from liverange @p Src to live
 /// range @Dst and use value number @p DstValNo there.
-static void addSegmentsWithValNo(LiveRange &Dst, VNInfo *DstValNo,
+static bool addSegmentsWithValNo(LiveRange &Dst, VNInfo *DstValNo,
                                  const LiveRange &Src, const VNInfo *SrcValNo) {
+  bool Added = false;
   for (const LiveRange::Segment &S : Src.segments) {
     if (S.valno != SrcValNo)
       continue;
+    Added = true;
     Dst.addSegment(LiveRange::Segment(S.start, S.end, DstValNo));
   }
+  return Added;
 }
 
 bool RegisterCoalescer::removeCopyByCommutingDef(const CoalescerPair &CP,
@@ -889,7 +892,8 @@
           ? SR.getNextValue(CopyIdx, Allocator)
           : SR.getVNInfoAt(CopyIdx);
         assert(BSubValNo != nullptr);
-        addSegmentsWithValNo(SR, BSubValNo, SA, ASubValNo);
+        if (addSegmentsWithValNo(SR, BSubValNo, SA, ASubValNo))
+          BSubValNo->def = ASubValNo->def;
       });
     }
   }
Index: lib/CodeGen/VirtRegMap.cpp
===================================================================
--- lib/CodeGen/VirtRegMap.cpp
+++ lib/CodeGen/VirtRegMap.cpp
@@ -525,7 +525,7 @@
         // Preserve semantics of sub-register operands.
         unsigned SubReg = MO.getSubReg();
         if (SubReg != 0) {
-          if (NoSubRegLiveness) {
+          if (NoSubRegLiveness || !MRI->shouldTrackSubRegLiveness(VirtReg)) {
             // A virtual register kill refers to the whole register, so we may
             // have to add implicit killed operands for the super-register.  A
             // partial redef always kills and redefines the super-register.
Index: lib/Target/SystemZ/SystemZSubtarget.h
===================================================================
--- lib/Target/SystemZ/SystemZSubtarget.h
+++ lib/Target/SystemZ/SystemZSubtarget.h
@@ -102,6 +102,8 @@
   // Always enable the early if-conversion pass.
   bool enableEarlyIfConversion() const override { return true; }
 
+  bool enableSubRegLiveness() const override { return true; }
+
   // Automatically generated by tblgen.
   void ParseSubtargetFeatures(StringRef CPU, StringRef FS);
 
Index: test/CodeGen/SystemZ/cmpxchg-06.ll
===================================================================
--- test/CodeGen/SystemZ/cmpxchg-06.ll
+++ test/CodeGen/SystemZ/cmpxchg-06.ll
@@ -116,9 +116,9 @@
 ; CHECK-LABEL: f10
 ; CHECK-DAG: lg %r1, 8(%r3)
 ; CHECK-DAG: lg %r0, 0(%r3)
-; CHECK-DAG: lg %r13, 8(%r2)
-; CHECK-DAG: lg %r12, 0(%r2)
-; CHECK:     cdsg %r12, %r0, 0(%r4)
+; CHECK-DAG: lg {{%r[0-9]+}}, 8(%r2)
+; CHECK-DAG: lg [[REG:%r[0-9]+]], 0(%r2)
+; CHECK:     cdsg [[REG]], %r0, 0(%r4)
 ; CHECK-NEXT: ipm %r2
 ; CHECK-NEXT: afi %r2, -268435456
 ; CHECK-NEXT: srl %r2, 31
@@ -134,15 +134,13 @@
 
 ; Check using the comparison result for a branch.
 ; CHECK-LABEL: f11
-; CHECK-DAG: lg %r1, 8(%r3)
-; CHECK-DAG: lg %r0, 0(%r3)
-; CHECK-DAG: lg %r13, 8(%r2)
-; CHECK-DAG: lg %r12, 0(%r2)
-; CHECK:     cdsg %r12, %r0, 0(%r4)
-; CHECK-NEXT: jl [[LABEL:\.[^ ]*]]
-; CHECK: jg g
-; CHECK: [[LABEL]]:
-; CHECK: br %r14
+; CHECK-DAG:  lg %r1, 8(%r3)
+; CHECK-DAG:  lg %r0, 0(%r3)
+; CHECK-DAG:  lg %r3, 8(%r2)
+; CHECK-DAG:  lg %r2, 0(%r2)
+; CHECK:      cdsg %r2, %r0, 0(%r4)
+; CHECK-NEXT: jge g
+; CHECK:      br %r14
 define void @f11(i128 %cmp, i128 %swap, i128 *%src) {
   %pairval = cmpxchg i128 *%src, i128 %cmp, i128 %swap seq_cst seq_cst
   %cond = extractvalue { i128, i1 } %pairval, 1
@@ -158,15 +156,13 @@
 
 ; ... and the same with the inverted direction.
 ; CHECK-LABEL: f12
-; CHECK-DAG: lg %r1, 8(%r3)
-; CHECK-DAG: lg %r0, 0(%r3)
-; CHECK-DAG: lg %r13, 8(%r2)
-; CHECK-DAG: lg %r12, 0(%r2)
-; CHECK:     cdsg %r12, %r0, 0(%r4)
-; CHECK-NEXT: jl [[LABEL:\.[^ ]*]]
-; CHECK: br %r14
-; CHECK: [[LABEL]]:
-; CHECK: jg g
+; CHECK-DAG:  lg %r1, 8(%r3)
+; CHECK-DAG:  lg %r0, 0(%r3)
+; CHECK-DAG:  lg %r3, 8(%r2)
+; CHECK-DAG:  lg %r2, 0(%r2)
+; CHECK:      cdsg %r2, %r0, 0(%r4)
+; CHECK-NEXT: jgl g
+; CHECK:      br %r14
 define void @f12(i128 %cmp, i128 %swap, i128 *%src) {
   %pairval = cmpxchg i128 *%src, i128 %cmp, i128 %swap seq_cst seq_cst
   %cond = extractvalue { i128, i1 } %pairval, 1
Index: test/CodeGen/SystemZ/int-ssub-06.ll
===================================================================
--- test/CodeGen/SystemZ/int-ssub-06.ll
+++ test/CodeGen/SystemZ/int-ssub-06.ll
@@ -73,7 +73,7 @@
 ; and must use a register.
 define zeroext i1 @f5(i32 %dummy, i32 %a, i32 *%res) {
 ; CHECK-LABEL: f5:
-; CHECK: llilh [[REG1:%r[0-5]]], 32768
+; CHECK: iilf [[REG1:%r[0-5]]], 2147483648
 ; CHECK: sr %r3, [[REG1]]
 ; CHECK-DAG: st %r3, 0(%r4)
 ; CHECK-DAG: ipm [[REG:%r[0-5]]]
@@ -171,7 +171,7 @@
 ; Check the next value down, which must use a register.
 define zeroext i1 @f11(i32 %dummy, i32 %a, i32 *%res) {
 ; CHECK-LABEL: f11:
-; CHECK: llilh [[REG1:%r[0-5]]], 32768
+; CHECK: iilf [[REG1:%r[0-5]]], 2147483648
 ; CHECK: sr %r3, [[REG1]]
 ; CHECK-DAG: st %r3, 0(%r4)
 ; CHECK-DAG: ipm [[REG:%r[0-5]]]