Index: lib/Target/Mips/MCTargetDesc/MipsMCCodeEmitter.h
===================================================================
--- lib/Target/Mips/MCTargetDesc/MipsMCCodeEmitter.h
+++ lib/Target/Mips/MCTargetDesc/MipsMCCodeEmitter.h
@@ -74,6 +74,12 @@
                                   SmallVectorImpl<MCFixup> &Fixups,
                                   const MCSubtargetInfo &STI) const;
 
+  // getImm5Shr2Value - Return binary encoding of the microMIPS jump
+  // target operand.
+  unsigned getImm5Shr2Value(const MCInst &MI, unsigned OpNo,
+                            SmallVectorImpl<MCFixup> &Fixups,
+                            const MCSubtargetInfo &STI) const;
+
   // getBranchTargetOpValue - Return binary encoding of the branch
   // target operand. If the machine operand requires relocation,
   // record the relocation and return zero.
Index: lib/Target/Mips/MCTargetDesc/MipsMCCodeEmitter.cpp
===================================================================
--- lib/Target/Mips/MCTargetDesc/MipsMCCodeEmitter.cpp
+++ lib/Target/Mips/MCTargetDesc/MipsMCCodeEmitter.cpp
@@ -345,6 +345,21 @@
 }
 
 unsigned MipsMCCodeEmitter::
+getImm5Shr2Value(const MCInst &MI, unsigned OpNo,
+                 SmallVectorImpl<MCFixup> &Fixups,
+                 const MCSubtargetInfo &STI) const {
+
+  const MCOperand &MO = MI.getOperand(OpNo);
+  // If the destination is an immediate, divide by 2.
+  if (MO.isImm()) return MO.getImm() >> 2;
+
+  assert(MO.isExpr() &&
+         "getImm5Shr2Value expects only expressions or an immediate");
+
+  return 0;
+}
+
+unsigned MipsMCCodeEmitter::
 getExprOpValue(const MCExpr *Expr,SmallVectorImpl<MCFixup> &Fixups,
                const MCSubtargetInfo &STI) const {
   int64_t Res;
Index: lib/Target/Mips/MicroMipsInstrFormats.td
===================================================================
--- lib/Target/Mips/MicroMipsInstrFormats.td
+++ lib/Target/Mips/MicroMipsInstrFormats.td
@@ -72,6 +72,17 @@
   let Inst{4-0}   = rd;
 }
 
+class JRADDIUSP_FM_MM16<bits<5> op> {
+  bits<5> rs;
+  bits<5> imm;
+
+  bits<16> Inst;
+
+  let Inst{15-10} = 0x11;
+  let Inst{9-5}   = op;
+  let Inst{4-0}   = imm;
+}
+
 //===----------------------------------------------------------------------===//
 // MicroMIPS 32-bit Instruction Formats
 //===----------------------------------------------------------------------===//
Index: lib/Target/Mips/MicroMipsInstrInfo.td
===================================================================
--- lib/Target/Mips/MicroMipsInstrInfo.td
+++ lib/Target/Mips/MicroMipsInstrInfo.td
@@ -4,6 +4,10 @@
   let DecoderMethod = "DecodeSimm12";
 }
 
+def imm5shr2 : Operand<OtherVT> {
+  let EncoderMethod = "getImm5Shr2Value";
+}
+
 def mem_mm_12 : Operand<i32> {
   let PrintMethod = "printMemOperand";
   let MIOperandInfo = (ops GPR32, simm12);
@@ -122,6 +126,17 @@
   let Defs = [RA];
 }
 
+// Base class for JRADDIUSP instruction.
+class JumpRAddiuStackMM16 :
+  MicroMipsInst16<(outs), (ins imm5shr2:$imm), "jraddiusp\t$imm",
+           [], IIBranch, FrmR> {
+  let isTerminator = 1;
+  let isBarrier = 1;
+  let hasDelaySlot = 1;
+  let isBranch = 1;
+  let isIndirectBranch = 1;
+}
+
 // MicroMIPS Jump and Link (Call) - Short Delay Slot
 let isCall=1, hasDelaySlot=1, Defs = [RA] in {
   class JumpLinkMM<string opstr, DAGOperand opnd> :
@@ -145,6 +160,7 @@
 def JALR16_MM : JumpLinkRegMM16<"jalr", GPR32Opnd>, JALR_FM_MM16<0x0e>;
 def JALRS16_MM : JumpLinkRegSMM16<"jalrs", GPR32Opnd>, JALR_FM_MM16<0x09>;
 def JRC16_MM : JumpLinkRegCMM16<"jrc", GPR32Opnd>, JALR_FM_MM16<0x0d>;
+def JRADDIUSP : JumpRAddiuStackMM16, JRADDIUSP_FM_MM16<0x18>;
 
 class WaitMM<string opstr> :
   InstSE<(outs), (ins uimm10:$code_), !strconcat(opstr, "\t$code_"), [],
Index: lib/Target/Mips/MipsCodeEmitter.cpp
===================================================================
--- lib/Target/Mips/MipsCodeEmitter.cpp
+++ lib/Target/Mips/MipsCodeEmitter.cpp
@@ -107,6 +107,7 @@
 
   unsigned getJumpTargetOpValue(const MachineInstr &MI, unsigned OpNo) const;
   unsigned getJumpTargetOpValueMM(const MachineInstr &MI, unsigned OpNo) const;
+  unsigned getImm5Shr2Value(const MachineInstr &MI, unsigned OpNo) const;
   unsigned getBranchTargetOpValueMM(const MachineInstr &MI,
                                     unsigned OpNo) const;
 
@@ -208,6 +209,12 @@
   return 0;
 }
 
+unsigned MipsCodeEmitter::getImm5Shr2Value(const MachineInstr &MI,
+                                           unsigned OpNo) const {
+  llvm_unreachable("Unimplemented function.");
+  return 0;
+}
+
 unsigned MipsCodeEmitter::getBranchTargetOpValueMM(const MachineInstr &MI,
                                                    unsigned OpNo) const {
   llvm_unreachable("Unimplemented function.");
Index: test/MC/Mips/micromips-16-bit-instructions.s
===================================================================
--- test/MC/Mips/micromips-16-bit-instructions.s
+++ test/MC/Mips/micromips-16-bit-instructions.s
@@ -17,6 +17,8 @@
 # CHECK-EL: nop                     # encoding: [0x00,0x00,0x00,0x00]
 # CHECK-EL: jalrs   $9              # encoding: [0x29,0x45]
 # CHECK-EL: move    $zero, $zero    # encoding: [0x00,0x0c]
+# CHECK-EL: jraddiusp 20            # encoding: [0x05,0x47]
+# CHECK-EL: nop                     # encoding: [0x00,0x00,0x00,0x00]
 #------------------------------------------------------------------------------
 # Big endian
 #------------------------------------------------------------------------------
@@ -28,6 +30,8 @@
 # CHECK-EB: nop                     # encoding: [0x00,0x00,0x00,0x00]
 # CHECK-EB: jalrs   $9              # encoding: [0x45,0x29]
 # CHECK-EB: move    $zero, $zero    # encoding: [0x0c,0x00]
+# CHECK-EB: jraddiusp 20            # encoding: [0x47,0x05]
+# CHECK-EB: nop                     # encoding: [0x00,0x00,0x00,0x00]
 
     mfhi    $9
     mflo    $9
@@ -35,3 +39,4 @@
     jrc     $9
     jalr    $9
     jalrs   $9
+    jraddiusp 20