Index: test/Transforms/InstCombine/signed-truncation-check.ll =================================================================== --- /dev/null +++ test/Transforms/InstCombine/signed-truncation-check.ll @@ -0,0 +1,634 @@ +; NOTE: Assertions have been autogenerated by utils/update_test_checks.py +; RUN: opt < %s -instcombine -S | FileCheck %s + +; General pattern: +; X & Y +; +; Where Y is checking that all the high bits (covered by a mask 4294967168) +; are uniform, i.e. %arg & 4294967168 can be either 4294967168 or 0 +; Pattern can be one of: +; %t = add i32 %arg, 128 +; %r = icmp ult i32 %t, 256 +; Or +; %t0 = shl i32 %arg, 24 +; %t1 = ashr i32 %t0, 24 +; %r = icmp eq i32 %t1, %arg +; Or +; %t0 = trunc i32 %arg to i8 +; %t1 = sext i8 %t0 to i32 +; %r = icmp eq i32 %t1, %arg +; This pattern is a signed truncation check. +; +; And X is checking that some bit in that same mask is zero. +; I.e. can be one of: +; %r = icmp sgt i32 %arg, -1 +; Or +; %t = and i32 %arg, 2147483648 +; %r = icmp eq i32 %t, 0 +; +; Since we are checking that all the bits in that mask are the same, +; and a particular bit is zero, what we are really checking is that all the +; masked bits are zero. +; So this should be transformed to: +; %r = icmp ult i32 %arg, 128 + +; ============================================================================ ; +; Basic positive test +; ============================================================================ ; + +define i1 @positive_with_signbit(i32 %arg) { +; CHECK-LABEL: @positive_with_signbit( +; CHECK-NEXT: [[TMP1:%.*]] = icmp sgt i32 [[ARG:%.*]], -1 +; CHECK-NEXT: [[TMP2:%.*]] = add i32 [[ARG]], 128 +; CHECK-NEXT: [[TMP3:%.*]] = icmp ult i32 [[TMP2]], 256 +; CHECK-NEXT: [[TMP4:%.*]] = and i1 [[TMP1]], [[TMP3]] +; CHECK-NEXT: ret i1 [[TMP4]] +; + %tmp1 = icmp sgt i32 %arg, -1 + %tmp2 = add i32 %arg, 128 + %tmp3 = icmp ult i32 %tmp2, 256 + %tmp4 = and i1 %tmp1, %tmp3 + ret i1 %tmp4 +} + +define i1 @positive_with_mask(i32 %arg) { +; CHECK-LABEL: @positive_with_mask( +; CHECK-NEXT: [[TMP1:%.*]] = and i32 [[ARG:%.*]], 1107296256 +; CHECK-NEXT: [[TMP2:%.*]] = icmp eq i32 [[TMP1]], 0 +; CHECK-NEXT: [[TMP3:%.*]] = add i32 [[ARG]], 128 +; CHECK-NEXT: [[TMP4:%.*]] = icmp ult i32 [[TMP3]], 256 +; CHECK-NEXT: [[TMP5:%.*]] = and i1 [[TMP2]], [[TMP4]] +; CHECK-NEXT: ret i1 [[TMP5]] +; + %tmp1 = and i32 %arg, 1107296256 + %tmp2 = icmp eq i32 %tmp1, 0 + %tmp3 = add i32 %arg, 128 + %tmp4 = icmp ult i32 %tmp3, 256 + %tmp5 = and i1 %tmp2, %tmp4 + ret i1 %tmp5 +} + +define i1 @positive_with_icmp(i32 %arg) { +; CHECK-LABEL: @positive_with_icmp( +; CHECK-NEXT: [[TMP1:%.*]] = icmp ult i32 [[ARG:%.*]], 512 +; CHECK-NEXT: [[TMP2:%.*]] = add i32 [[ARG]], 128 +; CHECK-NEXT: [[TMP3:%.*]] = icmp ult i32 [[TMP2]], 256 +; CHECK-NEXT: [[TMP4:%.*]] = and i1 [[TMP1]], [[TMP3]] +; CHECK-NEXT: ret i1 [[TMP4]] +; + %tmp1 = icmp ult i32 %arg, 512 + %tmp2 = add i32 %arg, 128 + %tmp3 = icmp ult i32 %tmp2, 256 + %tmp4 = and i1 %tmp1, %tmp3 + ret i1 %tmp4 +} + +; Still the same +define i1 @positive_with_aggressive_icmp(i32 %arg) { +; CHECK-LABEL: @positive_with_aggressive_icmp( +; CHECK-NEXT: [[TMP1:%.*]] = icmp ult i32 [[ARG:%.*]], 128 +; CHECK-NEXT: [[TMP2:%.*]] = add i32 [[ARG]], 256 +; CHECK-NEXT: [[TMP3:%.*]] = icmp ult i32 [[TMP2]], 512 +; CHECK-NEXT: [[TMP4:%.*]] = and i1 [[TMP1]], [[TMP3]] +; CHECK-NEXT: ret i1 [[TMP4]] +; + %tmp1 = icmp ult i32 %arg, 128 + %tmp2 = add i32 %arg, 256 + %tmp3 = icmp ult i32 %tmp2, 512 + %tmp4 = and i1 %tmp1, %tmp3 + ret i1 %tmp4 +} + +; I'm sure there is a bunch more patterns possible :/ + +; ============================================================================ ; +; Vector tests +; ============================================================================ ; + +define <2 x i1> @positive_vec_splat(<2 x i32> %arg) { +; CHECK-LABEL: @positive_vec_splat( +; CHECK-NEXT: [[TMP1:%.*]] = icmp sgt <2 x i32> [[ARG:%.*]], +; CHECK-NEXT: [[TMP2:%.*]] = add <2 x i32> [[ARG]], +; CHECK-NEXT: [[TMP3:%.*]] = icmp ult <2 x i32> [[TMP2]], +; CHECK-NEXT: [[TMP4:%.*]] = and <2 x i1> [[TMP1]], [[TMP3]] +; CHECK-NEXT: ret <2 x i1> [[TMP4]] +; + %tmp1 = icmp sgt <2 x i32> %arg, + %tmp2 = add <2 x i32> %arg, + %tmp3 = icmp ult <2 x i32> %tmp2, + %tmp4 = and <2 x i1> %tmp1, %tmp3 + ret <2 x i1> %tmp4 +} + +define <2 x i1> @positive_vec_nonsplat(<2 x i32> %arg) { +; CHECK-LABEL: @positive_vec_nonsplat( +; CHECK-NEXT: [[TMP1:%.*]] = icmp sgt <2 x i32> [[ARG:%.*]], +; CHECK-NEXT: [[TMP2:%.*]] = add <2 x i32> [[ARG]], +; CHECK-NEXT: [[TMP3:%.*]] = icmp ult <2 x i32> [[TMP2]], +; CHECK-NEXT: [[TMP4:%.*]] = and <2 x i1> [[TMP1]], [[TMP3]] +; CHECK-NEXT: ret <2 x i1> [[TMP4]] +; + %tmp1 = icmp sgt <2 x i32> %arg, + %tmp2 = add <2 x i32> %arg, + %tmp3 = icmp ult <2 x i32> %tmp2, + %tmp4 = and <2 x i1> %tmp1, %tmp3 + ret <2 x i1> %tmp4 +} + +define <3 x i1> @positive_vec_undef0(<3 x i32> %arg) { +; CHECK-LABEL: @positive_vec_undef0( +; CHECK-NEXT: [[TMP1:%.*]] = icmp sgt <3 x i32> [[ARG:%.*]], +; CHECK-NEXT: [[TMP2:%.*]] = add <3 x i32> [[ARG]], +; CHECK-NEXT: [[TMP3:%.*]] = icmp ult <3 x i32> [[TMP2]], +; CHECK-NEXT: [[TMP4:%.*]] = and <3 x i1> [[TMP1]], [[TMP3]] +; CHECK-NEXT: ret <3 x i1> [[TMP4]] +; + %tmp1 = icmp sgt <3 x i32> %arg, + %tmp2 = add <3 x i32> %arg, + %tmp3 = icmp ult <3 x i32> %tmp2, + %tmp4 = and <3 x i1> %tmp1, %tmp3 + ret <3 x i1> %tmp4 +} + +define <3 x i1> @positive_vec_undef1(<3 x i32> %arg) { +; CHECK-LABEL: @positive_vec_undef1( +; CHECK-NEXT: [[TMP1:%.*]] = icmp sgt <3 x i32> [[ARG:%.*]], +; CHECK-NEXT: [[TMP2:%.*]] = add <3 x i32> [[ARG]], +; CHECK-NEXT: [[TMP3:%.*]] = icmp ult <3 x i32> [[TMP2]], +; CHECK-NEXT: [[TMP4:%.*]] = and <3 x i1> [[TMP1]], [[TMP3]] +; CHECK-NEXT: ret <3 x i1> [[TMP4]] +; + %tmp1 = icmp sgt <3 x i32> %arg, + %tmp2 = add <3 x i32> %arg, + %tmp3 = icmp ult <3 x i32> %tmp2, + %tmp4 = and <3 x i1> %tmp1, %tmp3 + ret <3 x i1> %tmp4 +} + +define <3 x i1> @positive_vec_undef2(<3 x i32> %arg) { +; CHECK-LABEL: @positive_vec_undef2( +; CHECK-NEXT: [[TMP1:%.*]] = icmp sgt <3 x i32> [[ARG:%.*]], +; CHECK-NEXT: [[TMP2:%.*]] = add <3 x i32> [[ARG]], +; CHECK-NEXT: [[TMP3:%.*]] = icmp ult <3 x i32> [[TMP2]], +; CHECK-NEXT: [[TMP4:%.*]] = and <3 x i1> [[TMP1]], [[TMP3]] +; CHECK-NEXT: ret <3 x i1> [[TMP4]] +; + %tmp1 = icmp sgt <3 x i32> %arg, + %tmp2 = add <3 x i32> %arg, + %tmp3 = icmp ult <3 x i32> %tmp2, + %tmp4 = and <3 x i1> %tmp1, %tmp3 + ret <3 x i1> %tmp4 +} + +define <3 x i1> @positive_vec_undef3(<3 x i32> %arg) { +; CHECK-LABEL: @positive_vec_undef3( +; CHECK-NEXT: [[TMP1:%.*]] = icmp sgt <3 x i32> [[ARG:%.*]], +; CHECK-NEXT: [[TMP2:%.*]] = add <3 x i32> [[ARG]], +; CHECK-NEXT: [[TMP3:%.*]] = icmp ult <3 x i32> [[TMP2]], +; CHECK-NEXT: [[TMP4:%.*]] = and <3 x i1> [[TMP1]], [[TMP3]] +; CHECK-NEXT: ret <3 x i1> [[TMP4]] +; + %tmp1 = icmp sgt <3 x i32> %arg, + %tmp2 = add <3 x i32> %arg, + %tmp3 = icmp ult <3 x i32> %tmp2, + %tmp4 = and <3 x i1> %tmp1, %tmp3 + ret <3 x i1> %tmp4 +} + +define <3 x i1> @positive_vec_undef4(<3 x i32> %arg) { +; CHECK-LABEL: @positive_vec_undef4( +; CHECK-NEXT: [[TMP1:%.*]] = icmp sgt <3 x i32> [[ARG:%.*]], +; CHECK-NEXT: [[TMP2:%.*]] = add <3 x i32> [[ARG]], +; CHECK-NEXT: [[TMP3:%.*]] = icmp ult <3 x i32> [[TMP2]], +; CHECK-NEXT: [[TMP4:%.*]] = and <3 x i1> [[TMP1]], [[TMP3]] +; CHECK-NEXT: ret <3 x i1> [[TMP4]] +; + %tmp1 = icmp sgt <3 x i32> %arg, + %tmp2 = add <3 x i32> %arg, + %tmp3 = icmp ult <3 x i32> %tmp2, + %tmp4 = and <3 x i1> %tmp1, %tmp3 + ret <3 x i1> %tmp4 +} + +define <3 x i1> @positive_vec_undef5(<3 x i32> %arg) { +; CHECK-LABEL: @positive_vec_undef5( +; CHECK-NEXT: [[TMP1:%.*]] = icmp sgt <3 x i32> [[ARG:%.*]], +; CHECK-NEXT: [[TMP2:%.*]] = add <3 x i32> [[ARG]], +; CHECK-NEXT: [[TMP3:%.*]] = icmp ult <3 x i32> [[TMP2]], +; CHECK-NEXT: [[TMP4:%.*]] = and <3 x i1> [[TMP1]], [[TMP3]] +; CHECK-NEXT: ret <3 x i1> [[TMP4]] +; + %tmp1 = icmp sgt <3 x i32> %arg, + %tmp2 = add <3 x i32> %arg, + %tmp3 = icmp ult <3 x i32> %tmp2, + %tmp4 = and <3 x i1> %tmp1, %tmp3 + ret <3 x i1> %tmp4 +} + +define <3 x i1> @positive_vec_undef6(<3 x i32> %arg) { +; CHECK-LABEL: @positive_vec_undef6( +; CHECK-NEXT: [[TMP1:%.*]] = icmp sgt <3 x i32> [[ARG:%.*]], +; CHECK-NEXT: [[TMP2:%.*]] = add <3 x i32> [[ARG]], +; CHECK-NEXT: [[TMP3:%.*]] = icmp ult <3 x i32> [[TMP2]], +; CHECK-NEXT: [[TMP4:%.*]] = and <3 x i1> [[TMP1]], [[TMP3]] +; CHECK-NEXT: ret <3 x i1> [[TMP4]] +; + %tmp1 = icmp sgt <3 x i32> %arg, + %tmp2 = add <3 x i32> %arg, + %tmp3 = icmp ult <3 x i32> %tmp2, + %tmp4 = and <3 x i1> %tmp1, %tmp3 + ret <3 x i1> %tmp4 +} + +; ============================================================================ ; +; Commutativity tests. +; ============================================================================ ; + +declare i32 @gen32() + +define i1 @commutative() { +; CHECK-LABEL: @commutative( +; CHECK-NEXT: [[ARG:%.*]] = call i32 @gen32() +; CHECK-NEXT: [[TMP1:%.*]] = icmp sgt i32 [[ARG]], -1 +; CHECK-NEXT: [[TMP2:%.*]] = add i32 [[ARG]], 128 +; CHECK-NEXT: [[TMP3:%.*]] = icmp ult i32 [[TMP2]], 256 +; CHECK-NEXT: [[TMP4:%.*]] = and i1 [[TMP3]], [[TMP1]] +; CHECK-NEXT: ret i1 [[TMP4]] +; + %arg = call i32 @gen32() + %tmp1 = icmp sgt i32 %arg, -1 + %tmp2 = add i32 %arg, 128 + %tmp3 = icmp ult i32 %tmp2, 256 + %tmp4 = and i1 %tmp3, %tmp1 ; swapped order + ret i1 %tmp4 +} + +define i1 @commutative_with_icmp() { +; CHECK-LABEL: @commutative_with_icmp( +; CHECK-NEXT: [[ARG:%.*]] = call i32 @gen32() +; CHECK-NEXT: [[TMP1:%.*]] = icmp ult i32 [[ARG]], 512 +; CHECK-NEXT: [[TMP2:%.*]] = add i32 [[ARG]], 128 +; CHECK-NEXT: [[TMP3:%.*]] = icmp ult i32 [[TMP2]], 256 +; CHECK-NEXT: [[TMP4:%.*]] = and i1 [[TMP3]], [[TMP1]] +; CHECK-NEXT: ret i1 [[TMP4]] +; + %arg = call i32 @gen32() + %tmp1 = icmp ult i32 %arg, 512 + %tmp2 = add i32 %arg, 128 + %tmp3 = icmp ult i32 %tmp2, 256 + %tmp4 = and i1 %tmp3, %tmp1 ; swapped order + ret i1 %tmp4 +} + +; ============================================================================ ; +; Truncations. +; ============================================================================ ; + +define i1 @positive_trunc_signbit(i32 %arg) { +; CHECK-LABEL: @positive_trunc_signbit( +; CHECK-NEXT: [[TMP1:%.*]] = trunc i32 [[ARG:%.*]] to i8 +; CHECK-NEXT: [[TMP2:%.*]] = icmp sgt i8 [[TMP1]], -1 +; CHECK-NEXT: [[TMP3:%.*]] = add i32 [[ARG]], 128 +; CHECK-NEXT: [[TMP4:%.*]] = icmp ult i32 [[TMP3]], 256 +; CHECK-NEXT: [[TMP5:%.*]] = and i1 [[TMP2]], [[TMP4]] +; CHECK-NEXT: ret i1 [[TMP5]] +; + %tmp1 = trunc i32 %arg to i8 + %tmp2 = icmp sgt i8 %tmp1, -1 + %tmp3 = add i32 %arg, 128 + %tmp4 = icmp ult i32 %tmp3, 256 + %tmp5 = and i1 %tmp2, %tmp4 + ret i1 %tmp5 +} + +define i1 @positive_trunc_base(i32 %arg) { +; CHECK-LABEL: @positive_trunc_base( +; CHECK-NEXT: [[TMP1:%.*]] = trunc i32 [[ARG:%.*]] to i16 +; CHECK-NEXT: [[TMP2:%.*]] = icmp sgt i16 [[TMP1]], -1 +; CHECK-NEXT: [[TMP3:%.*]] = add i16 [[TMP1]], 128 +; CHECK-NEXT: [[TMP4:%.*]] = icmp ult i16 [[TMP3]], 256 +; CHECK-NEXT: [[TMP5:%.*]] = and i1 [[TMP2]], [[TMP4]] +; CHECK-NEXT: ret i1 [[TMP5]] +; + %tmp1 = trunc i32 %arg to i16 + %tmp2 = icmp sgt i16 %tmp1, -1 + %tmp3 = add i16 %tmp1, 128 + %tmp4 = icmp ult i16 %tmp3, 256 + %tmp5 = and i1 %tmp2, %tmp4 + ret i1 %tmp5 +} + +define i1 @positive_different_trunc_both(i32 %arg) { +; CHECK-LABEL: @positive_different_trunc_both( +; CHECK-NEXT: [[TMP1:%.*]] = trunc i32 [[ARG:%.*]] to i15 +; CHECK-NEXT: [[TMP2:%.*]] = icmp sgt i15 [[TMP1]], -1 +; CHECK-NEXT: [[TMP3:%.*]] = trunc i32 [[ARG]] to i16 +; CHECK-NEXT: [[TMP4:%.*]] = add i16 [[TMP3]], 128 +; CHECK-NEXT: [[TMP5:%.*]] = icmp ult i16 [[TMP4]], 256 +; CHECK-NEXT: [[TMP6:%.*]] = and i1 [[TMP2]], [[TMP5]] +; CHECK-NEXT: ret i1 [[TMP6]] +; + %tmp1 = trunc i32 %arg to i15 + %tmp2 = icmp sgt i15 %tmp1, -1 + %tmp3 = trunc i32 %arg to i16 + %tmp4 = add i16 %tmp3, 128 + %tmp5 = icmp ult i16 %tmp4, 256 + %tmp6 = and i1 %tmp2, %tmp5 + ret i1 %tmp6 +} + +; ============================================================================ ; +; One-use tests. +; +; We will only produce one instruction, so we do not care about one-use. +; But, we *could* handle more patterns that we weren't able to canonicalize +; because of extra-uses. +; ============================================================================ ; + +declare void @use32(i32) +declare void @use8(i8) +declare void @use1(i1) + +define i1 @oneuse_with_signbit(i32 %arg) { +; CHECK-LABEL: @oneuse_with_signbit( +; CHECK-NEXT: [[TMP1:%.*]] = icmp sgt i32 [[ARG:%.*]], -1 +; CHECK-NEXT: call void @use1(i1 [[TMP1]]) +; CHECK-NEXT: [[TMP2:%.*]] = add i32 [[ARG]], 128 +; CHECK-NEXT: call void @use32(i32 [[TMP2]]) +; CHECK-NEXT: [[TMP3:%.*]] = icmp ult i32 [[TMP2]], 256 +; CHECK-NEXT: call void @use1(i1 [[TMP3]]) +; CHECK-NEXT: [[TMP4:%.*]] = and i1 [[TMP1]], [[TMP3]] +; CHECK-NEXT: ret i1 [[TMP4]] +; + %tmp1 = icmp sgt i32 %arg, -1 + call void @use1(i1 %tmp1) + %tmp2 = add i32 %arg, 128 + call void @use32(i32 %tmp2) + %tmp3 = icmp ult i32 %tmp2, 256 + call void @use1(i1 %tmp3) + %tmp4 = and i1 %tmp1, %tmp3 + ret i1 %tmp4 +} + +define i1 @oneuse_with_mask(i32 %arg) { +; CHECK-LABEL: @oneuse_with_mask( +; CHECK-NEXT: [[TMP1:%.*]] = and i32 [[ARG:%.*]], 603979776 +; CHECK-NEXT: call void @use32(i32 [[TMP1]]) +; CHECK-NEXT: [[TMP2:%.*]] = icmp eq i32 [[TMP1]], 0 +; CHECK-NEXT: call void @use1(i1 [[TMP2]]) +; CHECK-NEXT: [[TMP3:%.*]] = add i32 [[ARG]], 128 +; CHECK-NEXT: call void @use32(i32 [[TMP3]]) +; CHECK-NEXT: [[TMP4:%.*]] = icmp ult i32 [[TMP3]], 256 +; CHECK-NEXT: call void @use1(i1 [[TMP4]]) +; CHECK-NEXT: [[TMP5:%.*]] = and i1 [[TMP2]], [[TMP4]] +; CHECK-NEXT: ret i1 [[TMP5]] +; + %tmp1 = and i32 %arg, 603979776 ; some bit within the target 4294967168 mask. + call void @use32(i32 %tmp1) + %tmp2 = icmp eq i32 %tmp1, 0 + call void @use1(i1 %tmp2) + %tmp3 = add i32 %arg, 128 + call void @use32(i32 %tmp3) + %tmp4 = icmp ult i32 %tmp3, 256 + call void @use1(i1 %tmp4) + %tmp5 = and i1 %tmp2, %tmp4 + ret i1 %tmp5 +} + +define i1 @oneuse_shl_ashr(i32 %arg) { +; CHECK-LABEL: @oneuse_shl_ashr( +; CHECK-NEXT: [[TMP1:%.*]] = trunc i32 [[ARG:%.*]] to i8 +; CHECK-NEXT: call void @use8(i8 [[TMP1]]) +; CHECK-NEXT: [[TMP2:%.*]] = icmp sgt i8 [[TMP1]], -1 +; CHECK-NEXT: call void @use1(i1 [[TMP2]]) +; CHECK-NEXT: [[TMP3:%.*]] = shl i32 [[ARG]], 24 +; CHECK-NEXT: call void @use32(i32 [[TMP3]]) +; CHECK-NEXT: [[TMP4:%.*]] = ashr exact i32 [[TMP3]], 24 +; CHECK-NEXT: call void @use32(i32 [[TMP4]]) +; CHECK-NEXT: [[TMP5:%.*]] = icmp eq i32 [[TMP4]], [[ARG]] +; CHECK-NEXT: call void @use1(i1 [[TMP5]]) +; CHECK-NEXT: [[TMP6:%.*]] = and i1 [[TMP2]], [[TMP5]] +; CHECK-NEXT: ret i1 [[TMP6]] +; + %tmp1 = trunc i32 %arg to i8 + call void @use8(i8 %tmp1) + %tmp2 = icmp sgt i8 %tmp1, -1 + call void @use1(i1 %tmp2) + %tmp3 = shl i32 %arg, 24 + call void @use32(i32 %tmp3) + %tmp4 = ashr i32 %tmp3, 24 + call void @use32(i32 %tmp4) + %tmp5 = icmp eq i32 %tmp4, %arg + call void @use1(i1 %tmp5) + %tmp6 = and i1 %tmp2, %tmp5 + ret i1 %tmp6 +} + +define zeroext i1 @oneuse_trunc_sext(i32 %arg) { +; CHECK-LABEL: @oneuse_trunc_sext( +; CHECK-NEXT: [[TMP1:%.*]] = trunc i32 [[ARG:%.*]] to i8 +; CHECK-NEXT: call void @use8(i8 [[TMP1]]) +; CHECK-NEXT: [[TMP2:%.*]] = icmp sgt i8 [[TMP1]], -1 +; CHECK-NEXT: call void @use1(i1 [[TMP2]]) +; CHECK-NEXT: [[TMP3:%.*]] = trunc i32 [[ARG]] to i8 +; CHECK-NEXT: call void @use8(i8 [[TMP3]]) +; CHECK-NEXT: [[TMP4:%.*]] = sext i8 [[TMP3]] to i32 +; CHECK-NEXT: call void @use32(i32 [[TMP4]]) +; CHECK-NEXT: [[TMP5:%.*]] = icmp eq i32 [[TMP4]], [[ARG]] +; CHECK-NEXT: call void @use1(i1 [[TMP5]]) +; CHECK-NEXT: [[TMP6:%.*]] = and i1 [[TMP2]], [[TMP5]] +; CHECK-NEXT: ret i1 [[TMP6]] +; + %tmp1 = trunc i32 %arg to i8 + call void @use8(i8 %tmp1) + %tmp2 = icmp sgt i8 %tmp1, -1 + call void @use1(i1 %tmp2) + %tmp3 = trunc i32 %arg to i8 + call void @use8(i8 %tmp3) + %tmp4 = sext i8 %tmp3 to i32 + call void @use32(i32 %tmp4) + %tmp5 = icmp eq i32 %tmp4, %arg + call void @use1(i1 %tmp5) + %tmp6 = and i1 %tmp2, %tmp5 + ret i1 %tmp6 +} + +; ============================================================================ ; +; Negative tests +; ============================================================================ ; + +define i1 @negative_not_arg(i32 %arg, i32 %arg2) { +; CHECK-LABEL: @negative_not_arg( +; CHECK-NEXT: [[TMP1:%.*]] = icmp sgt i32 [[ARG:%.*]], -1 +; CHECK-NEXT: [[TMP2:%.*]] = add i32 [[ARG2:%.*]], 128 +; CHECK-NEXT: [[TMP3:%.*]] = icmp ult i32 [[TMP2]], 256 +; CHECK-NEXT: [[TMP4:%.*]] = and i1 [[TMP1]], [[TMP3]] +; CHECK-NEXT: ret i1 [[TMP4]] +; + %tmp1 = icmp sgt i32 %arg, -1 + %tmp2 = add i32 %arg2, 128 ; not %arg + %tmp3 = icmp ult i32 %tmp2, 256 + %tmp4 = and i1 %tmp1, %tmp3 + ret i1 %tmp4 +} + +define i1 @negative_trunc_not_arg(i32 %arg, i32 %arg2) { +; CHECK-LABEL: @negative_trunc_not_arg( +; CHECK-NEXT: [[TMP1:%.*]] = trunc i32 [[ARG:%.*]] to i8 +; CHECK-NEXT: [[TMP2:%.*]] = icmp sgt i8 [[TMP1]], -1 +; CHECK-NEXT: [[TMP3:%.*]] = add i32 [[ARG2:%.*]], 128 +; CHECK-NEXT: [[TMP4:%.*]] = icmp ult i32 [[TMP3]], 256 +; CHECK-NEXT: [[TMP5:%.*]] = and i1 [[TMP2]], [[TMP4]] +; CHECK-NEXT: ret i1 [[TMP5]] +; + %tmp1 = trunc i32 %arg to i8 + %tmp2 = icmp sgt i8 %tmp1, -1 + %tmp3 = add i32 %arg2, 128 ; not %arg + %tmp4 = icmp ult i32 %tmp3, 256 + %tmp5 = and i1 %tmp2, %tmp4 + ret i1 %tmp5 +} + +define i1 @positive_with_mask_not_arg(i32 %arg, i32 %arg2) { +; CHECK-LABEL: @positive_with_mask_not_arg( +; CHECK-NEXT: [[TMP1:%.*]] = and i32 [[ARG:%.*]], 1140850688 +; CHECK-NEXT: [[TMP2:%.*]] = icmp eq i32 [[TMP1]], 0 +; CHECK-NEXT: [[TMP3:%.*]] = add i32 [[ARG2:%.*]], 128 +; CHECK-NEXT: [[TMP4:%.*]] = icmp ult i32 [[TMP3]], 256 +; CHECK-NEXT: [[TMP5:%.*]] = and i1 [[TMP2]], [[TMP4]] +; CHECK-NEXT: ret i1 [[TMP5]] +; + %tmp1 = and i32 %arg, 1140850688 + %tmp2 = icmp eq i32 %tmp1, 0 + %tmp3 = add i32 %arg2, 128 ; not %arg + %tmp4 = icmp ult i32 %tmp3, 256 + %tmp5 = and i1 %tmp2, %tmp4 + ret i1 %tmp5 +} + +define i1 @negative_with_nonuniform_bad_mask(i32 %arg) { +; CHECK-LABEL: @negative_with_nonuniform_bad_mask( +; CHECK-NEXT: [[TMP1:%.*]] = and i32 [[ARG:%.*]], 1711276033 +; CHECK-NEXT: [[TMP2:%.*]] = icmp eq i32 [[TMP1]], 0 +; CHECK-NEXT: [[TMP3:%.*]] = add i32 [[ARG]], 128 +; CHECK-NEXT: [[TMP4:%.*]] = icmp ult i32 [[TMP3]], 256 +; CHECK-NEXT: [[TMP5:%.*]] = and i1 [[TMP2]], [[TMP4]] +; CHECK-NEXT: ret i1 [[TMP5]] +; + %tmp1 = and i32 %arg, 1711276033 ; lowest bit is set + %tmp2 = icmp eq i32 %tmp1, 0 + %tmp3 = add i32 %arg, 128 + %tmp4 = icmp ult i32 %tmp3, 256 + %tmp5 = and i1 %tmp2, %tmp4 + ret i1 %tmp5 +} + +define i1 @negative_with_uniform_bad_mask(i32 %arg) { +; CHECK-LABEL: @negative_with_uniform_bad_mask( +; CHECK-NEXT: [[TMP1:%.*]] = and i32 [[ARG:%.*]], -16777152 +; CHECK-NEXT: [[TMP2:%.*]] = icmp eq i32 [[TMP1]], 0 +; CHECK-NEXT: [[TMP3:%.*]] = add i32 [[ARG]], 128 +; CHECK-NEXT: [[TMP4:%.*]] = icmp ult i32 [[TMP3]], 256 +; CHECK-NEXT: [[TMP5:%.*]] = and i1 [[TMP2]], [[TMP4]] +; CHECK-NEXT: ret i1 [[TMP5]] +; + %tmp1 = and i32 %arg, 4278190144 ; 7'th bit is set + %tmp2 = icmp eq i32 %tmp1, 0 + %tmp3 = add i32 %arg, 128 + %tmp4 = icmp ult i32 %tmp3, 256 + %tmp5 = and i1 %tmp2, %tmp4 + ret i1 %tmp5 +} + +define i1 @negative_with_wrong_mask(i32 %arg) { +; CHECK-LABEL: @negative_with_wrong_mask( +; CHECK-NEXT: [[TMP1:%.*]] = and i32 [[ARG:%.*]], 1 +; CHECK-NEXT: [[TMP2:%.*]] = icmp eq i32 [[TMP1]], 0 +; CHECK-NEXT: [[TMP3:%.*]] = add i32 [[ARG]], 128 +; CHECK-NEXT: [[TMP4:%.*]] = icmp ult i32 [[TMP3]], 256 +; CHECK-NEXT: [[TMP5:%.*]] = and i1 [[TMP2]], [[TMP4]] +; CHECK-NEXT: ret i1 [[TMP5]] +; + %tmp1 = and i32 %arg, 1 ; not even checking the right mask + %tmp2 = icmp eq i32 %tmp1, 0 + %tmp3 = add i32 %arg, 128 + %tmp4 = icmp ult i32 %tmp3, 256 + %tmp5 = and i1 %tmp2, %tmp4 + ret i1 %tmp5 +} + +define i1 @negative_not_less_than(i32 %arg) { +; CHECK-LABEL: @negative_not_less_than( +; CHECK-NEXT: ret i1 false +; + %tmp1 = icmp sgt i32 %arg, -1 + %tmp2 = add i32 %arg, 256 ; should be less than 256 + %tmp3 = icmp ult i32 %tmp2, 256 + %tmp4 = and i1 %tmp1, %tmp3 + ret i1 %tmp4 +} + +define i1 @negative_not_power_of_two(i32 %arg) { +; CHECK-LABEL: @negative_not_power_of_two( +; CHECK-NEXT: [[TMP1:%.*]] = icmp sgt i32 [[ARG:%.*]], -1 +; CHECK-NEXT: [[TMP2:%.*]] = add i32 [[ARG]], 255 +; CHECK-NEXT: [[TMP3:%.*]] = icmp ult i32 [[TMP2]], 256 +; CHECK-NEXT: [[TMP4:%.*]] = and i1 [[TMP1]], [[TMP3]] +; CHECK-NEXT: ret i1 [[TMP4]] +; + %tmp1 = icmp sgt i32 %arg, -1 + %tmp2 = add i32 %arg, 255 ; should be power of two + %tmp3 = icmp ult i32 %tmp2, 256 + %tmp4 = and i1 %tmp1, %tmp3 + ret i1 %tmp4 +} + +define i1 @negative_not_next_power_of_two(i32 %arg) { +; CHECK-LABEL: @negative_not_next_power_of_two( +; CHECK-NEXT: [[TMP1:%.*]] = icmp sgt i32 [[ARG:%.*]], -1 +; CHECK-NEXT: [[TMP2:%.*]] = add i32 [[ARG]], 64 +; CHECK-NEXT: [[TMP3:%.*]] = icmp ult i32 [[TMP2]], 256 +; CHECK-NEXT: [[TMP4:%.*]] = and i1 [[TMP1]], [[TMP3]] +; CHECK-NEXT: ret i1 [[TMP4]] +; + %tmp1 = icmp sgt i32 %arg, -1 + %tmp2 = add i32 %arg, 64 ; should be 256 >> 1 + %tmp3 = icmp ult i32 %tmp2, 256 + %tmp4 = and i1 %tmp1, %tmp3 + ret i1 %tmp4 +} + +; I don't think this can be folded, at least not into single instruction. +define i1 @two_signed_truncation_checks(i32 %arg) { +; CHECK-LABEL: @two_signed_truncation_checks( +; CHECK-NEXT: [[TMP1:%.*]] = add i32 [[ARG:%.*]], 512 +; CHECK-NEXT: [[TMP2:%.*]] = icmp ult i32 [[TMP1]], 1024 +; CHECK-NEXT: [[TMP3:%.*]] = add i32 [[ARG]], 128 +; CHECK-NEXT: [[TMP4:%.*]] = icmp ult i32 [[TMP3]], 256 +; CHECK-NEXT: [[TMP5:%.*]] = and i1 [[TMP2]], [[TMP4]] +; CHECK-NEXT: ret i1 [[TMP5]] +; + %tmp1 = add i32 %arg, 512 + %tmp2 = icmp ult i32 %tmp1, 1024 + %tmp3 = add i32 %arg, 128 + %tmp4 = icmp ult i32 %tmp3, 256 + %tmp5 = and i1 %tmp2, %tmp4 + ret i1 %tmp5 +} + +define i1 @bad_trunc_stc(i32 %arg) { +; CHECK-LABEL: @bad_trunc_stc( +; CHECK-NEXT: [[TMP1:%.*]] = icmp sgt i32 [[ARG:%.*]], -1 +; CHECK-NEXT: [[TMP2:%.*]] = trunc i32 [[ARG]] to i16 +; CHECK-NEXT: [[TMP3:%.*]] = add i16 [[TMP2]], 128 +; CHECK-NEXT: [[TMP4:%.*]] = icmp ult i16 [[TMP3]], 256 +; CHECK-NEXT: [[TMP5:%.*]] = and i1 [[TMP1]], [[TMP4]] +; CHECK-NEXT: ret i1 [[TMP5]] +; + %tmp1 = icmp sgt i32 %arg, -1 ; checks a bit outside of the i16 + %tmp2 = trunc i32 %arg to i16 + %tmp3 = add i16 %tmp2, 128 + %tmp4 = icmp ult i16 %tmp3, 256 + %tmp5 = and i1 %tmp1, %tmp4 + ret i1 %tmp5 +}