[ARM] Added FP16 VREV Vector Instrinsic CodeGen support

[LukeGeeson]

Summary

It adds FP16 vrev codegen support from test/CodeGen/ARM/armv8.2a-fp16-vector-intrinsics.ll

In line with Sjoerd Meijers' bug hunting report: https://bugs.llvm.org/show_bug.cgi?id=38404 and https://reviews.llvm.org/rL338568

[SjoerdMeijer]

Looks like a straight forward fix, but how about the v4f16 variant?

[LukeGeeson]

Ah Yep, for v4f16 I am waiting on the result of https://reviews.llvm.org/D49987

[SjoerdMeijer]

lib/Target/ARM/ARMInstrNEON.td

6561

I think we just need

def : Pat<(v4f16 (NEONvrev64 (v4f16 DPR:$Vm))), (VREV64d16 DPR:$Vm)>;

[LukeGeeson]

looks as though the vext codegen was added in L339241. Will add just the vrev64 codegen...

[LukeGeeson]

-removed vext since it was committed in rL339241
-added vrev64 4xf16 codegen support

[SjoerdMeijer]

Looks like a straight forward fix to me now.

Apologies for fixing vext, I forgot and was also not expecting you were fixing both vrev and vext in one ticket.

One nit you could think about in e.g. your commit message: it's true this adds support for vrev64q_f16, but the added pattern are generic patterns for vrev on f16 vector with 4 or 8 elements; so something along the lines of "FP16 vrev codegen support" is more generic, and perhaps capturing it better.

lib/Target/ARM/ARMInstrNEON.td

                     (VCVTs2hq QPR:$Qd, QPR:$Qm, pred:$p)>;
 def : NEONInstAlias<"vcvt${p}.f16.u16 $Qd, $Qm, #0",
                     (VCVTu2hq QPR:$Qd, QPR:$Qm, pred:$p)>;
 
 
 //   VCVT     : Vector Convert Between Half-Precision and Single-Precision.
 def  VCVTf2h  : N2VNInt<0b11, 0b11, 0b01, 0b10, 0b01100, 0, 0,
                         IIC_VUNAQ, "vcvt", "f16.f32",
                         v4i16, v4f32, int_arm_neon_vcvtfp2hf>,
                 Requires<[HasNEON, HasFP16]>;
 def  VCVTh2f  : N2VLInt<0b11, 0b11, 0b01, 0b10, 0b01110, 0, 0,
                         IIC_VUNAQ, "vcvt", "f32.f16",
                         v4f32, v4i16, int_arm_neon_vcvthf2fp>,
                 Requires<[HasNEON, HasFP16]>;
 
 // Vector Reverse.
 

 def VREV64d16 : VREV64D<0b01, "vrev64", "16", v4i16>;
 def VREV64d32 : VREV64D<0b10, "vrev64", "32", v2i32>;
 def : Pat<(v2f32 (NEONvrev64 (v2f32 DPR:$Vm))), (VREV64d32 DPR:$Vm)>;
 
 def VREV64q8  : VREV64Q<0b00, "vrev64", "8", v16i8>;
 def VREV64q16 : VREV64Q<0b01, "vrev64", "16", v8i16>;
 def VREV64q32 : VREV64Q<0b10, "vrev64", "32", v4i32>;
 def : Pat<(v4f32 (NEONvrev64 (v4f32 QPR:$Vm))), (VREV64q32 QPR:$Vm)>;
+def : Pat<(v8f16 (NEONvrev64 (v8f16 QPR:$Vm))), (VREV64q16 QPR:$Vm)>;
+def : Pat<(v4f16 (NEONvrev64 (v4f16 DPR:$Vm))), (VREV64d16 DPR:$Vm)>;
 
 //   VREV32   : Vector Reverse elements within 32-bit words
 
 class VREV32D<bits<2> op19_18, string OpcodeStr, string Dt, ValueType Ty>
   : N2V<0b11, 0b11, op19_18, 0b00, 0b00001, 0, 0, (outs DPR:$Vd),
         (ins DPR:$Vm), IIC_VMOVD,
         OpcodeStr, Dt, "$Vd, $Vm", "",
         [(set DPR:$Vd, (Ty (NEONvrev32 (Ty DPR:$Vm))))]>;

test/CodeGen/ARM/armv8.2a-fp16-vector-intrinsics.ll

 ; CHECK-LABEL: test_vextq_f16:
 ; CHECK:         vext.16 q0, q0, q1, #5
 ; CHECK-NEXT:    bx lr
 entry:
   %vext = shufflevector <8 x half> %a, <8 x half> %b, <8 x i32> <i32 5, i32 6, i32 7, i32 8, i32 9, i32 10, i32 11, i32 12>
   ret <8 x half> %vext
 }
 
-; FIXME (PR38404)
-;
-;define dso_local <4 x half> @test_vrev64_f16(<4 x half> %a) {
-;entry:
-;  %shuffle.i = shufflevector <4 x half> %a, <4 x half> undef, <4 x i32> <i32 3, i32 2, i32 1, i32 0>
-;  ret <4 x half> %shuffle.i
-;}
-;
-;define dso_local <8 x half> @test_vrev64q_f16(<8 x half> %a) {
-;entry:
-;  %shuffle.i = shufflevector <8 x half> %a, <8 x half> undef, <8 x i32> <i32 3, i32 2, i32 1, i32 0, i32 7, i32 6, i32 5, i32 4>
-;  ret <8 x half> %shuffle.i
-;}
+define dso_local <4 x half> @test_vrev64_f16(<4 x half> %a) {
+entry:
+  %shuffle.i = shufflevector <4 x half> %a, <4 x half> undef, <4 x i32> <i32 3, i32 2, i32 1, i32 0>
+  ret <4 x half> %shuffle.i
+}
 
+define dso_local <8 x half> @test_vrev64q_f16(<8 x half> %a) {
+entry:
+  %shuffle.i = shufflevector <8 x half> %a, <8 x half> undef, <8 x i32> <i32 3, i32 2, i32 1, i32 0, i32 7, i32 6, i32 5, i32 4>
+  ret <8 x half> %shuffle.i
+}
+
 declare <4 x half> @llvm.fabs.v4f16(<4 x half>)
 declare <8 x half> @llvm.fabs.v8f16(<8 x half>)
 declare <4 x i16> @llvm.arm.neon.vcvtas.v4i16.v4f16(<4 x half>)
 declare <4 x i16> @llvm.arm.neon.vcvtau.v4i16.v4f16(<4 x half>)
 declare <8 x i16> @llvm.arm.neon.vcvtas.v8i16.v8f16(<8 x half>)
 declare <4 x i16> @llvm.arm.neon.vcvtms.v4i16.v4f16(<4 x half>)
 declare <8 x i16> @llvm.arm.neon.vcvtms.v8i16.v8f16(<8 x half>)
 declare <4 x i16> @llvm.arm.neon.vcvtmu.v4i16.v4f16(<4 x half>)