Index: lib/Target/ARM/ARMISelLowering.cpp
===================================================================
--- lib/Target/ARM/ARMISelLowering.cpp
+++ lib/Target/ARM/ARMISelLowering.cpp
@@ -1144,6 +1144,18 @@
     setOperationAction(ISD::FMAXNAN, MVT::v2f32, Legal);
     setOperationAction(ISD::FMINNAN, MVT::v4f32, Legal);
     setOperationAction(ISD::FMAXNAN, MVT::v4f32, Legal);
+
+    if (Subtarget->hasFullFP16()) {
+      setOperationAction(ISD::FMINNUM, MVT::v4f16, Legal);
+      setOperationAction(ISD::FMAXNUM, MVT::v4f16, Legal);
+      setOperationAction(ISD::FMINNUM, MVT::v8f16, Legal);
+      setOperationAction(ISD::FMAXNUM, MVT::v8f16, Legal);
+
+      setOperationAction(ISD::FMINNAN, MVT::v4f16, Legal);
+      setOperationAction(ISD::FMAXNAN, MVT::v4f16, Legal);
+      setOperationAction(ISD::FMINNAN, MVT::v8f16, Legal);
+      setOperationAction(ISD::FMAXNAN, MVT::v8f16, Legal);
+    }
   }
 
   // We have target-specific dag combine patterns for the following nodes:
Index: test/CodeGen/ARM/armv8.2a-fp16-vector-intrinsics.ll
===================================================================
--- test/CodeGen/ARM/armv8.2a-fp16-vector-intrinsics.ll
+++ test/CodeGen/ARM/armv8.2a-fp16-vector-intrinsics.ll
@@ -782,43 +782,59 @@
   ret <8 x half> %vmaxq_v2.i
 }
 
-; FIXME (PR38404)
-;
-;define dso_local <4 x half> @test_vmaxnm_f16(<4 x half> %a, <4 x half> %b) {
-;entry:
-;  %vmaxnm_v2.i = tail call <4 x half> @llvm.arm.neon.vmaxnm.v4f16(<4 x half> %a, <4 x half> %b)
-;  ret <4 x half> %vmaxnm_v2.i
-;}
+define dso_local <4 x half> @test_vmaxnm_f16(<4 x half> %a, <4 x half> %b) {
+; CHECK-LABEL: test_vmaxnm_f16:
+; CHECK:         vmaxnm.f16 d0, d0, d1
+; CHECK-NEXT:    bx lr
+entry:
+  %vmaxnm_v2.i = tail call <4 x half> @llvm.arm.neon.vmaxnm.v4f16(<4 x half> %a, <4 x half> %b)
+  ret <4 x half> %vmaxnm_v2.i
+}
 
-;define dso_local <8 x half> @test_vmaxnmq_f16(<8 x half> %a, <8 x half> %b) {
-;entry:
-;  %vmaxnmq_v2.i = tail call <8 x half> @llvm.arm.neon.vmaxnm.v8f16(<8 x half> %a, <8 x half> %b)
-;  ret <8 x half> %vmaxnmq_v2.i
-;}
+define dso_local <8 x half> @test_vmaxnmq_f16(<8 x half> %a, <8 x half> %b) {
+; CHECK-LABEL: test_vmaxnmq_f16:
+; CHECK:         vmaxnm.f16 q0, q0, q1
+; CHECK-NEXT:    bx lr
+entry:
+  %vmaxnmq_v2.i = tail call <8 x half> @llvm.arm.neon.vmaxnm.v8f16(<8 x half> %a, <8 x half> %b)
+  ret <8 x half> %vmaxnmq_v2.i
+}
 
-;define dso_local <4 x half> @test_vmin_f16(<4 x half> %a, <4 x half> %b) {
-;entry:
-;  %vmin_v2.i = tail call <4 x half> @llvm.arm.neon.vmins.v4f16(<4 x half> %a, <4 x half> %b)
-;  ret <4 x half> %vmin_v2.i
-;}
+define dso_local <4 x half> @test_vmin_f16(<4 x half> %a, <4 x half> %b) {
+; CHECK-LABEL: test_vmin_f16:
+; CHECK:         vmin.f16 d0, d0, d1
+; CHECK-NEXT:    bx lr
+entry:
+  %vmin_v2.i = tail call <4 x half> @llvm.arm.neon.vmins.v4f16(<4 x half> %a, <4 x half> %b)
+  ret <4 x half> %vmin_v2.i
+}
 
-;define dso_local <8 x half> @test_vminq_f16(<8 x half> %a, <8 x half> %b) {
-;entry:
-;  %vminq_v2.i = tail call <8 x half> @llvm.arm.neon.vmins.v8f16(<8 x half> %a, <8 x half> %b)
-;  ret <8 x half> %vminq_v2.i
-;}
+define dso_local <8 x half> @test_vminq_f16(<8 x half> %a, <8 x half> %b) {
+; CHECK-LABEL: test_vminq_f16:
+; CHECK:         vmin.f16 q0, q0, q1
+; CHECK-NEXT:    bx lr
+entry:
+  %vminq_v2.i = tail call <8 x half> @llvm.arm.neon.vmins.v8f16(<8 x half> %a, <8 x half> %b)
+  ret <8 x half> %vminq_v2.i
+}
 
-;define dso_local <4 x half> @test_vminnm_f16(<4 x half> %a, <4 x half> %b) {
-;entry:
-;  %vminnm_v2.i = tail call <4 x half> @llvm.arm.neon.vminnm.v4f16(<4 x half> %a, <4 x half> %b)
-;  ret <4 x half> %vminnm_v2.i
-;}
+define dso_local <4 x half> @test_vminnm_f16(<4 x half> %a, <4 x half> %b) {
+; CHECK-LABEL: test_vminnm_f16:
+; CHECK:         vminnm.f16 d0, d0, d1
+; CHECK-NEXT:    bx lr
+entry:
+  %vminnm_v2.i = tail call <4 x half> @llvm.arm.neon.vminnm.v4f16(<4 x half> %a, <4 x half> %b)
+  ret <4 x half> %vminnm_v2.i
+}
 
-;define dso_local <8 x half> @test_vminnmq_f16(<8 x half> %a, <8 x half> %b) {
-;entry:
-;  %vminnmq_v2.i = tail call <8 x half> @llvm.arm.neon.vminnm.v8f16(<8 x half> %a, <8 x half> %b)
-;  ret <8 x half> %vminnmq_v2.i
-;}
+define dso_local <8 x half> @test_vminnmq_f16(<8 x half> %a, <8 x half> %b) {
+; CHECK-LABEL: test_vminnmq_f16:
+; CHECK:         vminnm.f16 q0, q0, q1
+; CHECK-NEXT:    bx lr
+entry:
+  %vminnmq_v2.i = tail call <8 x half> @llvm.arm.neon.vminnm.v8f16(<8 x half> %a, <8 x half> %b)
+  ret <8 x half> %vminnmq_v2.i
+}
 
 define dso_local <4 x half> @test_vmul_f16(<4 x half> %a, <4 x half> %b) {
 ; CHECKLABEL: test_vmul_f16: