Index: include/llvm/CodeGen/TargetLowering.h =================================================================== --- include/llvm/CodeGen/TargetLowering.h +++ include/llvm/CodeGen/TargetLowering.h @@ -3708,6 +3708,9 @@ SDValue N1, ISD::CondCode Cond, DAGCombinerInfo &DCI, const SDLoc &DL) const; + + SDValue BuildUREMEqFold(EVT VT, SDValue N0, SDValue N1, ISD::CondCode Cond, + DAGCombinerInfo &DCI, const SDLoc &DL) const; }; /// Given an LLVM IR type and return type attributes, compute the return value Index: lib/CodeGen/SelectionDAG/TargetLowering.cpp =================================================================== --- lib/CodeGen/SelectionDAG/TargetLowering.cpp +++ lib/CodeGen/SelectionDAG/TargetLowering.cpp @@ -2794,6 +2794,18 @@ return V; } + // Fold remainder of division by a a constant + if (N0.getOpcode() == ISD::UREM && N0.hasOneUse() && + (Cond == ISD::SETEQ || Cond == ISD::SETNE)) { + AttributeList Attr = DAG.getMachineFunction().getFunction().getAttributes(); + + // When division is cheap or optimizing for minimum size, + // fall through to DIVREM creation by skipping this fold. + if (!isIntDivCheap(VT, Attr) && !Attr.hasFnAttribute(Attribute::MinSize)) + if (SDValue Folded = BuildUREMEqFold(VT, N0, N1, Cond, DCI, dl)) + return Folded; + } + // Fold away ALL boolean setcc's. SDValue Temp; if (N0.getValueType().getScalarType() == MVT::i1 && foldBooleans) { @@ -3763,6 +3775,87 @@ return DAG.getSelect(dl, VT, IsOne, N0, Q); } +/// Given an ISD::UREM used only by an ISD::SETEQ or ISD::SETNE +/// where the divisor is constant and the comparison target is zero, +/// return a DAG expression that will generate the same comparison result +/// using only multiplications, additions and shifts/rotations. +/// Ref: "Hacker's Delight" 10-17. +SDValue TargetLowering::BuildUREMEqFold(EVT VT, SDValue REMNode, + SDValue CompNode, ISD::CondCode Cond, + DAGCombinerInfo &DCI, + const SDLoc &DL) const { + // fold (seteq/ne (urem N, D), 0) -> (setule/ugt (rotr (mul N, P), K), Q) + // - D must be constant with D = D0 * 2^K where D0 is odd and D0 != 1 + // - P is the multiplicative inverse of D0 modulo 2^W + // - Q = floor((2^W - 1) / D0) + // where W is the width of the common type of N and D + assert((Cond == ISD::SETEQ || Cond == ISD::SETNE) && + "Only applicable for (in)equality comparisons."); + + EVT REMVT = REMNode->getValueType(0); + + if (!isTypeLegal(REMVT)) + return SDValue(); + // If MUL is unavailable, we cannot proceed in any case + if (!(DCI.isBeforeLegalizeOps() ? isOperationLegalOrCustom(ISD::MUL, REMVT) + : isOperationLegal(ISD::MUL, REMVT))) + return SDValue(); + + // TODO: Add non-uniform constant support + ConstantSDNode *Divisor = isConstOrConstSplat(REMNode->getOperand(1)); + ConstantSDNode *CompTarget = isConstOrConstSplat(CompNode); + if (!Divisor || !CompTarget || Divisor->isNullValue() || + !CompTarget->isNullValue()) + return SDValue(); + + const APInt &D = Divisor->getAPIntValue(); + + // Decompose D into D0 * 2^K + unsigned K = D.countTrailingZeros(); + bool DivisorIsEven = (K != 0); + APInt D0 = D.lshr(K); + + // The fold is invalid when D0 == 1. + // This is reachable because visitSetCC happens before visitREM. + if (D0.isOneValue()) + return SDValue(); + + // P = inv(D0, 2^W) + // 2^W requires W + 1 bits, so we have to extend and then truncate + unsigned W = D.getBitWidth(); + APInt P = D0.zext(W + 1) + .multiplicativeInverse(APInt::getHighBitsSet(W + 1, 1)) + .trunc(W); + + // Q = floor((2^W - 1) / D0) + APInt Q = APInt::getAllOnesValue(W).udiv(D0); + + SelectionDAG &DAG = DCI.DAG; + + SDValue PVal = DAG.getConstant(P, DL, REMVT); + SDValue QVal = DAG.getConstant(Q, DL, REMVT); + // (mul N, P) + SDValue Op1 = DAG.getNode(ISD::MUL, DL, REMVT, REMNode->getOperand(0), PVal); + + // Rotate right only if D was even + if (DivisorIsEven) { + // We need ROTR to do this + if (!(DCI.isBeforeLegalizeOps() ? isOperationLegalOrCustom(ISD::ROTR, REMVT) + : isOperationLegal(ISD::ROTR, REMVT))) + return SDValue(); + SDValue ShAmt = + DAG.getConstant(K, DL, getShiftAmountTy(REMVT, DAG.getDataLayout())); + SDNodeFlags Flags; + Flags.setExact(true); + // UREM: (rotr (mul N, P), K) + Op1 = DAG.getNode(ISD::ROTR, DL, REMVT, Op1, ShAmt, Flags); + } + + // UREM: (setule/setugt (rotr (mul N, P), K), Q) + return DAG.getSetCC(DL, VT, Op1, QVal, + ((Cond == ISD::SETEQ) ? ISD::SETULE : ISD::SETUGT)); +} + bool TargetLowering:: verifyReturnAddressArgumentIsConstant(SDValue Op, SelectionDAG &DAG) const { if (!isa(Op.getOperand(0))) { Index: test/CodeGen/AArch64/urem-seteq-optsize.ll =================================================================== --- test/CodeGen/AArch64/urem-seteq-optsize.ll +++ test/CodeGen/AArch64/urem-seteq-optsize.ll @@ -26,13 +26,13 @@ ; CHECK: // %bb.0: ; CHECK-NEXT: mov w8, #52429 ; CHECK-NEXT: movk w8, #52428, lsl #16 -; CHECK-NEXT: umull x8, w0, w8 -; CHECK-NEXT: lsr x8, x8, #34 -; CHECK-NEXT: add w8, w8, w8, lsl #2 -; CHECK-NEXT: mov w9, #-10 -; CHECK-NEXT: cmp w0, w8 +; CHECK-NEXT: mov w9, #13108 +; CHECK-NEXT: movk w9, #13107, lsl #16 +; CHECK-NEXT: mul w8, w0, w8 +; CHECK-NEXT: mov w10, #-10 +; CHECK-NEXT: cmp w8, w9 ; CHECK-NEXT: mov w8, #42 -; CHECK-NEXT: csel w0, w8, w9, eq +; CHECK-NEXT: csel w0, w8, w10, lo ; CHECK-NEXT: ret %rem = urem i32 %X, 5 %cmp = icmp eq i32 %rem, 0 Index: test/CodeGen/AArch64/urem-seteq-vec-nonsplat.ll =================================================================== --- test/CodeGen/AArch64/urem-seteq-vec-nonsplat.ll +++ test/CodeGen/AArch64/urem-seteq-vec-nonsplat.ll @@ -3,8 +3,8 @@ ; At the moment, BuildUREMEqFold does not handle nonsplat vectors. -define <4 x i32> @test_urem_odd_div_nonsplat(<4 x i32> %X) nounwind readnone { -; CHECK-LABEL: test_urem_odd_div_nonsplat: +define <4 x i32> @test_urem_odd_div(<4 x i32> %X) nounwind readnone { +; CHECK-LABEL: test_urem_odd_div: ; CHECK: // %bb.0: ; CHECK-NEXT: adrp x8, .LCPI0_0 ; CHECK-NEXT: ldr q1, [x8, :lo12:.LCPI0_0] @@ -35,8 +35,8 @@ ret <4 x i32> %ret } -define <4 x i32> @test_urem_even_div_nonsplat(<4 x i32> %X) nounwind readnone { -; CHECK-LABEL: test_urem_even_div_nonsplat: +define <4 x i32> @test_urem_even_div(<4 x i32> %X) nounwind readnone { +; CHECK-LABEL: test_urem_even_div: ; CHECK: // %bb.0: ; CHECK-NEXT: adrp x8, .LCPI1_0 ; CHECK-NEXT: ldr q1, [x8, :lo12:.LCPI1_0] @@ -64,8 +64,8 @@ ret <4 x i32> %ret } -define <4 x i32> @test_urem_pow2_nonsplat(<4 x i32> %X) nounwind readnone { -; CHECK-LABEL: test_urem_pow2_nonsplat: +define <4 x i32> @test_urem_pow2(<4 x i32> %X) nounwind readnone { +; CHECK-LABEL: test_urem_pow2: ; CHECK: // %bb.0: ; CHECK-NEXT: adrp x8, .LCPI2_0 ; CHECK-NEXT: ldr q1, [x8, :lo12:.LCPI2_0] @@ -89,8 +89,8 @@ ret <4 x i32> %ret } -define <4 x i32> @test_urem_one_nonsplat(<4 x i32> %X) nounwind readnone { -; CHECK-LABEL: test_urem_one_nonsplat: +define <4 x i32> @test_urem_one(<4 x i32> %X) nounwind readnone { +; CHECK-LABEL: test_urem_one: ; CHECK: // %bb.0: ; CHECK-NEXT: adrp x8, .LCPI3_0 ; CHECK-NEXT: ldr q1, [x8, :lo12:.LCPI3_0] @@ -121,8 +121,8 @@ ret <4 x i32> %ret } -define <4 x i32> @test_urem_comp_nonsplat(<4 x i32> %X) nounwind readnone { -; CHECK-LABEL: test_urem_comp_nonsplat: +define <4 x i32> @test_urem_comp(<4 x i32> %X) nounwind readnone { +; CHECK-LABEL: test_urem_comp: ; CHECK: // %bb.0: ; CHECK-NEXT: mov w8, #52429 ; CHECK-NEXT: movk w8, #52428, lsl #16 @@ -145,8 +145,8 @@ ret <4 x i32> %ret } -define <4 x i32> @test_urem_both_nonsplat(<4 x i32> %X) nounwind readnone { -; CHECK-LABEL: test_urem_both_nonsplat: +define <4 x i32> @test_urem_both(<4 x i32> %X) nounwind readnone { +; CHECK-LABEL: test_urem_both: ; CHECK: // %bb.0: ; CHECK-NEXT: adrp x8, .LCPI5_0 ; CHECK-NEXT: ldr q1, [x8, :lo12:.LCPI5_0] Index: test/CodeGen/AArch64/urem-seteq-vec-splat.ll =================================================================== --- test/CodeGen/AArch64/urem-seteq-vec-splat.ll +++ test/CodeGen/AArch64/urem-seteq-vec-splat.ll @@ -9,13 +9,9 @@ ; CHECK-NEXT: mov w8, #52429 ; CHECK-NEXT: movk w8, #52428, lsl #16 ; CHECK-NEXT: dup v2.4s, w8 -; CHECK-NEXT: umull2 v3.2d, v0.4s, v2.4s -; CHECK-NEXT: umull v2.2d, v0.2s, v2.2s -; CHECK-NEXT: uzp2 v2.4s, v2.4s, v3.4s -; CHECK-NEXT: movi v1.4s, #5 -; CHECK-NEXT: ushr v2.4s, v2.4s, #2 -; CHECK-NEXT: mls v0.4s, v2.4s, v1.4s -; CHECK-NEXT: cmeq v0.4s, v0.4s, #0 +; CHECK-NEXT: movi v1.16b, #51 +; CHECK-NEXT: mul v0.4s, v0.4s, v2.4s +; CHECK-NEXT: cmhs v0.4s, v1.4s, v0.4s ; CHECK-NEXT: movi v1.4s, #1 ; CHECK-NEXT: and v0.16b, v0.16b, v1.16b ; CHECK-NEXT: ret @@ -25,45 +21,24 @@ ret <4 x i32> %ret } -; Like test_urem_odd_vec_i32, but with 4 x i16 vectors. -define <4 x i16> @test_urem_odd_vec_i16(<4 x i16> %X) nounwind readnone { +; Like test_urem_odd_vec_i32, but with 8 x i16 vectors. +define <8 x i16> @test_urem_odd_vec_i16(<8 x i16> %X) nounwind readnone { ; CHECK-LABEL: test_urem_odd_vec_i16: ; CHECK: // %bb.0: -; CHECK-NEXT: mov w9, #52429 -; CHECK-NEXT: // kill: def $d0 killed $d0 def $q0 -; CHECK-NEXT: umov w8, v0.h[1] -; CHECK-NEXT: movk w9, #52428, lsl #16 -; CHECK-NEXT: umull x12, w8, w9 -; CHECK-NEXT: lsr x12, x12, #34 -; CHECK-NEXT: umov w10, v0.h[0] -; CHECK-NEXT: add w12, w12, w12, lsl #2 -; CHECK-NEXT: sub w8, w8, w12 -; CHECK-NEXT: umull x12, w10, w9 -; CHECK-NEXT: lsr x12, x12, #34 -; CHECK-NEXT: umov w11, v0.h[2] -; CHECK-NEXT: add w12, w12, w12, lsl #2 -; CHECK-NEXT: sub w10, w10, w12 -; CHECK-NEXT: umull x12, w11, w9 -; CHECK-NEXT: lsr x12, x12, #34 -; CHECK-NEXT: add w12, w12, w12, lsl #2 -; CHECK-NEXT: sub w11, w11, w12 -; CHECK-NEXT: umov w12, v0.h[3] -; CHECK-NEXT: umull x9, w12, w9 -; CHECK-NEXT: lsr x9, x9, #34 -; CHECK-NEXT: fmov s0, w10 -; CHECK-NEXT: add w9, w9, w9, lsl #2 -; CHECK-NEXT: mov v0.h[1], w8 -; CHECK-NEXT: sub w9, w12, w9 -; CHECK-NEXT: mov v0.h[2], w11 -; CHECK-NEXT: mov v0.h[3], w9 -; CHECK-NEXT: cmeq v0.4h, v0.4h, #0 -; CHECK-NEXT: movi v1.4h, #1 -; CHECK-NEXT: and v0.8b, v0.8b, v1.8b +; CHECK-NEXT: mov w8, #52429 +; CHECK-NEXT: dup v2.8h, w8 +; CHECK-NEXT: movi v1.16b, #51 +; CHECK-NEXT: mul v0.8h, v0.8h, v2.8h +; CHECK-NEXT: cmhs v0.8h, v1.8h, v0.8h +; CHECK-NEXT: movi v1.8h, #1 +; CHECK-NEXT: and v0.16b, v0.16b, v1.16b ; CHECK-NEXT: ret - %urem = urem <4 x i16> %X, - %cmp = icmp eq <4 x i16> %urem, - %ret = zext <4 x i1> %cmp to <4 x i16> - ret <4 x i16> %ret + %urem = urem <8 x i16> %X, + %cmp = icmp eq <8 x i16> %urem, + %ret = zext <8 x i1> %cmp to <8 x i16> + ret <8 x i16> %ret } ; Tests BuildUREMEqFold for 4 x i32 splat vectors with even divisor. @@ -92,48 +67,31 @@ ret <4 x i32> %ret } -; Like test_urem_even_vec_i32, but with 4 x i16 vectors. +; Like test_urem_even_vec_i32, but with 8 x i16 vectors. ; i16 is not legal for ROTR on AArch64, but ROTR also cannot be promoted to i32, ; so this would crash if BuildUREMEqFold was applied. -define <4 x i16> @test_urem_even_vec_i16(<4 x i16> %X) nounwind readnone { +define <8 x i16> @test_urem_even_vec_i16(<8 x i16> %X) nounwind readnone { ; CHECK-LABEL: test_urem_even_vec_i16: ; CHECK: // %bb.0: -; CHECK-NEXT: // kill: def $d0 killed $d0 def $q0 -; CHECK-NEXT: umov w8, v0.h[1] -; CHECK-NEXT: mov w9, #9363 -; CHECK-NEXT: movk w9, #37449, lsl #16 -; CHECK-NEXT: umov w10, v0.h[0] -; CHECK-NEXT: umov w11, v0.h[2] -; CHECK-NEXT: umov w12, v0.h[3] -; CHECK-NEXT: ubfx w13, w8, #1, #15 -; CHECK-NEXT: ubfx w14, w10, #1, #15 -; CHECK-NEXT: ubfx w15, w11, #1, #15 -; CHECK-NEXT: ubfx w16, w12, #1, #15 -; CHECK-NEXT: umull x13, w13, w9 -; CHECK-NEXT: umull x14, w14, w9 -; CHECK-NEXT: umull x15, w15, w9 -; CHECK-NEXT: umull x9, w16, w9 -; CHECK-NEXT: orr w16, wzr, #0xe -; CHECK-NEXT: lsr x13, x13, #34 -; CHECK-NEXT: msub w8, w13, w16, w8 -; CHECK-NEXT: lsr x13, x14, #34 -; CHECK-NEXT: msub w10, w13, w16, w10 -; CHECK-NEXT: lsr x13, x15, #34 -; CHECK-NEXT: fmov s0, w10 -; CHECK-NEXT: msub w11, w13, w16, w11 -; CHECK-NEXT: lsr x9, x9, #34 -; CHECK-NEXT: mov v0.h[1], w8 -; CHECK-NEXT: msub w9, w9, w16, w12 -; CHECK-NEXT: mov v0.h[2], w11 -; CHECK-NEXT: mov v0.h[3], w9 -; CHECK-NEXT: cmeq v0.4h, v0.4h, #0 -; CHECK-NEXT: movi v1.4h, #1 -; CHECK-NEXT: and v0.8b, v0.8b, v1.8b +; CHECK-NEXT: mov w8, #18725 +; CHECK-NEXT: ushr v1.8h, v0.8h, #1 +; CHECK-NEXT: dup v3.8h, w8 +; CHECK-NEXT: umull2 v4.4s, v1.8h, v3.8h +; CHECK-NEXT: umull v1.4s, v1.4h, v3.4h +; CHECK-NEXT: uzp2 v1.8h, v1.8h, v4.8h +; CHECK-NEXT: movi v2.8h, #14 +; CHECK-NEXT: ushr v1.8h, v1.8h, #1 +; CHECK-NEXT: mls v0.8h, v1.8h, v2.8h +; CHECK-NEXT: cmeq v0.8h, v0.8h, #0 +; CHECK-NEXT: movi v1.8h, #1 +; CHECK-NEXT: and v0.16b, v0.16b, v1.16b ; CHECK-NEXT: ret - %urem = urem <4 x i16> %X, - %cmp = icmp eq <4 x i16> %urem, - %ret = zext <4 x i1> %cmp to <4 x i16> - ret <4 x i16> %ret + %urem = urem <8 x i16> %X, + %cmp = icmp eq <8 x i16> %urem, + %ret = zext <8 x i1> %cmp to <8 x i16> + ret <8 x i16> %ret } ; We should not proceed with this fold if the divisor is 1 or -1 Index: test/CodeGen/AArch64/urem-seteq.ll =================================================================== --- test/CodeGen/AArch64/urem-seteq.ll +++ test/CodeGen/AArch64/urem-seteq.ll @@ -10,11 +10,11 @@ ; CHECK: // %bb.0: ; CHECK-NEXT: mov w8, #52429 ; CHECK-NEXT: movk w8, #52428, lsl #16 -; CHECK-NEXT: umull x8, w0, w8 -; CHECK-NEXT: lsr x8, x8, #34 -; CHECK-NEXT: add w8, w8, w8, lsl #2 -; CHECK-NEXT: cmp w0, w8 -; CHECK-NEXT: cset w0, eq +; CHECK-NEXT: mov w9, #13108 +; CHECK-NEXT: mul w8, w0, w8 +; CHECK-NEXT: movk w9, #13107, lsl #16 +; CHECK-NEXT: cmp w8, w9 +; CHECK-NEXT: cset w0, lo ; CHECK-NEXT: ret %urem = urem i32 %X, 5 %cmp = icmp eq i32 %urem, 0 @@ -26,14 +26,11 @@ define i32 @test_urem_odd_bit30(i32 %X) nounwind readnone { ; CHECK-LABEL: test_urem_odd_bit30: ; CHECK: // %bb.0: -; CHECK-NEXT: mov w8, #-11 -; CHECK-NEXT: umull x8, w0, w8 -; CHECK-NEXT: mov w9, #3 -; CHECK-NEXT: lsr x8, x8, #62 -; CHECK-NEXT: movk w9, #16384, lsl #16 -; CHECK-NEXT: msub w8, w8, w9, w0 -; CHECK-NEXT: cmp w8, #0 // =0 -; CHECK-NEXT: cset w0, eq +; CHECK-NEXT: mov w8, #43691 +; CHECK-NEXT: movk w8, #27306, lsl #16 +; CHECK-NEXT: mul w8, w0, w8 +; CHECK-NEXT: cmp w8, #4 // =4 +; CHECK-NEXT: cset w0, lo ; CHECK-NEXT: ret %urem = urem i32 %X, 1073741827 %cmp = icmp eq i32 %urem, 0 @@ -45,14 +42,11 @@ define i32 @test_urem_odd_bit31(i32 %X) nounwind readnone { ; CHECK-LABEL: test_urem_odd_bit31: ; CHECK: // %bb.0: -; CHECK-NEXT: mov w8, w0 -; CHECK-NEXT: lsl x9, x8, #30 -; CHECK-NEXT: sub x8, x9, x8 -; CHECK-NEXT: lsr x8, x8, #61 -; CHECK-NEXT: mov w9, #-2147483645 -; CHECK-NEXT: msub w8, w8, w9, w0 -; CHECK-NEXT: cmp w8, #0 // =0 -; CHECK-NEXT: cset w0, eq +; CHECK-NEXT: mov w8, #43691 +; CHECK-NEXT: movk w8, #10922, lsl #16 +; CHECK-NEXT: mul w8, w0, w8 +; CHECK-NEXT: cmp w8, #2 // =2 +; CHECK-NEXT: cset w0, lo ; CHECK-NEXT: ret %urem = urem i32 %X, 2147483651 %cmp = icmp eq i32 %urem, 0 @@ -69,16 +63,15 @@ define i16 @test_urem_even(i16 %X) nounwind readnone { ; CHECK-LABEL: test_urem_even: ; CHECK: // %bb.0: -; CHECK-NEXT: mov w10, #9363 -; CHECK-NEXT: ubfx w9, w0, #1, #15 -; CHECK-NEXT: movk w10, #37449, lsl #16 -; CHECK-NEXT: umull x9, w9, w10 +; CHECK-NEXT: mov w9, #28087 ; CHECK-NEXT: and w8, w0, #0xffff -; CHECK-NEXT: lsr x9, x9, #34 -; CHECK-NEXT: orr w10, wzr, #0xe -; CHECK-NEXT: msub w8, w9, w10, w8 -; CHECK-NEXT: cmp w8, #0 // =0 -; CHECK-NEXT: cset w0, ne +; CHECK-NEXT: movk w9, #46811, lsl #16 +; CHECK-NEXT: mul w8, w8, w9 +; CHECK-NEXT: mov w9, #18724 +; CHECK-NEXT: ror w8, w8, #1 +; CHECK-NEXT: movk w9, #9362, lsl #16 +; CHECK-NEXT: cmp w8, w9 +; CHECK-NEXT: cset w0, hi ; CHECK-NEXT: ret %urem = urem i16 %X, 14 %cmp = icmp ne i16 %urem, 0 @@ -90,14 +83,12 @@ define i32 @test_urem_even_bit30(i32 %X) nounwind readnone { ; CHECK-LABEL: test_urem_even_bit30: ; CHECK: // %bb.0: -; CHECK-NEXT: mov w8, #-415 -; CHECK-NEXT: umull x8, w0, w8 -; CHECK-NEXT: mov w9, #104 -; CHECK-NEXT: lsr x8, x8, #62 -; CHECK-NEXT: movk w9, #16384, lsl #16 -; CHECK-NEXT: msub w8, w8, w9, w0 -; CHECK-NEXT: cmp w8, #0 // =0 -; CHECK-NEXT: cset w0, eq +; CHECK-NEXT: mov w8, #20165 +; CHECK-NEXT: movk w8, #64748, lsl #16 +; CHECK-NEXT: mul w8, w0, w8 +; CHECK-NEXT: ror w8, w8, #3 +; CHECK-NEXT: cmp w8, #32 // =32 +; CHECK-NEXT: cset w0, lo ; CHECK-NEXT: ret %urem = urem i32 %X, 1073741928 %cmp = icmp eq i32 %urem, 0 @@ -109,15 +100,12 @@ define i32 @test_urem_even_bit31(i32 %X) nounwind readnone { ; CHECK-LABEL: test_urem_even_bit31: ; CHECK: // %bb.0: -; CHECK-NEXT: mov w8, #65435 -; CHECK-NEXT: movk w8, #32767, lsl #16 -; CHECK-NEXT: umull x8, w0, w8 -; CHECK-NEXT: mov w9, #102 -; CHECK-NEXT: lsr x8, x8, #62 -; CHECK-NEXT: movk w9, #32768, lsl #16 -; CHECK-NEXT: msub w8, w8, w9, w0 -; CHECK-NEXT: cmp w8, #0 // =0 -; CHECK-NEXT: cset w0, eq +; CHECK-NEXT: mov w8, #64251 +; CHECK-NEXT: movk w8, #47866, lsl #16 +; CHECK-NEXT: mul w8, w0, w8 +; CHECK-NEXT: ror w8, w8, #1 +; CHECK-NEXT: cmp w8, #4 // =4 +; CHECK-NEXT: cset w0, lo ; CHECK-NEXT: ret %urem = urem i32 %X, 2147483750 %cmp = icmp eq i32 %urem, 0 Index: test/CodeGen/X86/jump_sign.ll =================================================================== --- test/CodeGen/X86/jump_sign.ll +++ test/CodeGen/X86/jump_sign.ll @@ -236,13 +236,11 @@ ; CHECK-NEXT: jne .LBB12_8 ; CHECK-NEXT: # %bb.4: # %if.end29 ; CHECK-NEXT: movzwl (%eax), %eax +; CHECK-NEXT: imull $-13107, %eax, %eax # imm = 0xCCCD +; CHECK-NEXT: rorw $1, %ax ; CHECK-NEXT: movzwl %ax, %eax -; CHECK-NEXT: imull $52429, %eax, %ecx # imm = 0xCCCD -; CHECK-NEXT: shrl $19, %ecx -; CHECK-NEXT: addl %ecx, %ecx -; CHECK-NEXT: leal (%ecx,%ecx,4), %ecx -; CHECK-NEXT: cmpw %cx, %ax -; CHECK-NEXT: jne .LBB12_5 +; CHECK-NEXT: cmpl $13108, %eax # imm = 0x3334 +; CHECK-NEXT: jae .LBB12_5 ; CHECK-NEXT: .LBB12_8: # %if.then44 ; CHECK-NEXT: xorl %eax, %eax ; CHECK-NEXT: testb %al, %al @@ -398,15 +396,20 @@ define i32 @func_test1(i32 %p1) nounwind uwtable { ; CHECK-LABEL: func_test1: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: movl b, %eax -; CHECK-NEXT: cmpl {{[0-9]+}}(%esp), %eax -; CHECK-NEXT: setb %cl -; CHECK-NEXT: movl a, %eax -; CHECK-NEXT: testb %al, %cl -; CHECK-NEXT: je .LBB18_2 +; CHECK-NEXT: movl b, %ecx +; CHECK-NEXT: xorl %eax, %eax +; CHECK-NEXT: cmpl {{[0-9]+}}(%esp), %ecx +; CHECK-NEXT: setb %al +; CHECK-NEXT: movl a, %ecx +; CHECK-NEXT: andl %ecx, %eax +; CHECK-NEXT: movb $-85, %dl +; CHECK-NEXT: # kill: def $al killed $al killed $eax +; CHECK-NEXT: mulb %dl +; CHECK-NEXT: cmpb $86, %al +; CHECK-NEXT: jb .LBB18_2 ; CHECK-NEXT: # %bb.1: # %if.then -; CHECK-NEXT: decl %eax -; CHECK-NEXT: movl %eax, a +; CHECK-NEXT: decl %ecx +; CHECK-NEXT: movl %ecx, a ; CHECK-NEXT: .LBB18_2: # %if.end ; CHECK-NEXT: retl entry: Index: test/CodeGen/X86/urem-seteq-optsize.ll =================================================================== --- test/CodeGen/X86/urem-seteq-optsize.ll +++ test/CodeGen/X86/urem-seteq-optsize.ll @@ -47,15 +47,10 @@ define i32 @test_optsize(i32 %X) optsize nounwind readnone { ; X86-LABEL: test_optsize: ; X86: # %bb.0: -; X86-NEXT: movl {{[0-9]+}}(%esp), %ecx -; X86-NEXT: movl $-858993459, %edx # imm = 0xCCCCCCCD -; X86-NEXT: movl %ecx, %eax -; X86-NEXT: mull %edx -; X86-NEXT: shrl $2, %edx -; X86-NEXT: leal (%edx,%edx,4), %eax -; X86-NEXT: cmpl %eax, %ecx +; X86-NEXT: imull $-858993459, {{[0-9]+}}(%esp), %eax # imm = 0xCCCCCCCD +; X86-NEXT: cmpl $858993460, %eax # imm = 0x33333334 ; X86-NEXT: movl $42, %eax -; X86-NEXT: je .LBB1_2 +; X86-NEXT: jb .LBB1_2 ; X86-NEXT: # %bb.1: ; X86-NEXT: movl $-10, %eax ; X86-NEXT: .LBB1_2: @@ -63,15 +58,11 @@ ; ; X64-LABEL: test_optsize: ; X64: # %bb.0: -; X64-NEXT: movl %edi, %eax -; X64-NEXT: movl $3435973837, %ecx # imm = 0xCCCCCCCD -; X64-NEXT: imulq %rax, %rcx -; X64-NEXT: shrq $34, %rcx -; X64-NEXT: leal (%rcx,%rcx,4), %eax -; X64-NEXT: cmpl %eax, %edi +; X64-NEXT: imull $-858993459, %edi, %eax # imm = 0xCCCCCCCD +; X64-NEXT: cmpl $858993460, %eax # imm = 0x33333334 ; X64-NEXT: movl $42, %ecx ; X64-NEXT: movl $-10, %eax -; X64-NEXT: cmovel %ecx, %eax +; X64-NEXT: cmovbl %ecx, %eax ; X64-NEXT: retq %rem = urem i32 %X, 5 %cmp = icmp eq i32 %rem, 0 Index: test/CodeGen/X86/urem-seteq-vec-nonsplat.ll =================================================================== --- test/CodeGen/X86/urem-seteq-vec-nonsplat.ll +++ test/CodeGen/X86/urem-seteq-vec-nonsplat.ll @@ -7,8 +7,8 @@ ; At the moment, BuildUREMEqFold does not handle nonsplat vectors. -define <4 x i32> @test_urem_odd_div_nonsplat(<4 x i32> %X) nounwind readnone { -; CHECK-SSE2-LABEL: test_urem_odd_div_nonsplat: +define <4 x i32> @test_urem_odd_div(<4 x i32> %X) nounwind readnone { +; CHECK-SSE2-LABEL: test_urem_odd_div: ; CHECK-SSE2: # %bb.0: ; CHECK-SSE2-NEXT: movdqa {{.*#+}} xmm1 = [2863311531,3435973837,613566757,954437177] ; CHECK-SSE2-NEXT: movdqa %xmm0, %xmm2 @@ -44,7 +44,7 @@ ; CHECK-SSE2-NEXT: psrld $31, %xmm0 ; CHECK-SSE2-NEXT: retq ; -; CHECK-SSE41-LABEL: test_urem_odd_div_nonsplat: +; CHECK-SSE41-LABEL: test_urem_odd_div: ; CHECK-SSE41: # %bb.0: ; CHECK-SSE41-NEXT: movdqa {{.*#+}} xmm1 = [2863311531,3435973837,613566757,954437177] ; CHECK-SSE41-NEXT: pshufd {{.*#+}} xmm2 = xmm1[1,1,3,3] @@ -69,7 +69,7 @@ ; CHECK-SSE41-NEXT: psrld $31, %xmm0 ; CHECK-SSE41-NEXT: retq ; -; CHECK-AVX1-LABEL: test_urem_odd_div_nonsplat: +; CHECK-AVX1-LABEL: test_urem_odd_div: ; CHECK-AVX1: # %bb.0: ; CHECK-AVX1-NEXT: vmovdqa {{.*#+}} xmm1 = [2863311531,3435973837,613566757,954437177] ; CHECK-AVX1-NEXT: vpshufd {{.*#+}} xmm2 = xmm1[1,1,3,3] @@ -92,7 +92,7 @@ ; CHECK-AVX1-NEXT: vpsrld $31, %xmm0, %xmm0 ; CHECK-AVX1-NEXT: retq ; -; CHECK-AVX2-LABEL: test_urem_odd_div_nonsplat: +; CHECK-AVX2-LABEL: test_urem_odd_div: ; CHECK-AVX2: # %bb.0: ; CHECK-AVX2-NEXT: vmovdqa {{.*#+}} xmm1 = [2863311531,3435973837,613566757,954437177] ; CHECK-AVX2-NEXT: vpshufd {{.*#+}} xmm2 = xmm1[1,1,3,3] @@ -113,7 +113,7 @@ ; CHECK-AVX2-NEXT: vpsrld $31, %xmm0, %xmm0 ; CHECK-AVX2-NEXT: retq ; -; CHECK-AVX512VL-LABEL: test_urem_odd_div_nonsplat: +; CHECK-AVX512VL-LABEL: test_urem_odd_div: ; CHECK-AVX512VL: # %bb.0: ; CHECK-AVX512VL-NEXT: vmovdqa {{.*#+}} xmm1 = [2863311531,3435973837,613566757,954437177] ; CHECK-AVX512VL-NEXT: vpshufd {{.*#+}} xmm2 = xmm1[1,1,3,3] @@ -140,8 +140,8 @@ ret <4 x i32> %ret } -define <4 x i32> @test_urem_even_div_nonsplat(<4 x i32> %X) nounwind readnone { -; CHECK-SSE2-LABEL: test_urem_even_div_nonsplat: +define <4 x i32> @test_urem_even_div(<4 x i32> %X) nounwind readnone { +; CHECK-SSE2-LABEL: test_urem_even_div: ; CHECK-SSE2: # %bb.0: ; CHECK-SSE2-NEXT: movdqa %xmm0, %xmm1 ; CHECK-SSE2-NEXT: psrld $1, %xmm1 @@ -177,7 +177,7 @@ ; CHECK-SSE2-NEXT: psrld $31, %xmm0 ; CHECK-SSE2-NEXT: retq ; -; CHECK-SSE41-LABEL: test_urem_even_div_nonsplat: +; CHECK-SSE41-LABEL: test_urem_even_div: ; CHECK-SSE41: # %bb.0: ; CHECK-SSE41-NEXT: movdqa %xmm0, %xmm1 ; CHECK-SSE41-NEXT: psrld $1, %xmm1 @@ -200,7 +200,7 @@ ; CHECK-SSE41-NEXT: psrld $31, %xmm0 ; CHECK-SSE41-NEXT: retq ; -; CHECK-AVX1-LABEL: test_urem_even_div_nonsplat: +; CHECK-AVX1-LABEL: test_urem_even_div: ; CHECK-AVX1: # %bb.0: ; CHECK-AVX1-NEXT: vpsrld $1, %xmm0, %xmm1 ; CHECK-AVX1-NEXT: vpblendw {{.*#+}} xmm1 = xmm0[0,1,2,3,4,5],xmm1[6,7] @@ -221,7 +221,7 @@ ; CHECK-AVX1-NEXT: vpsrld $31, %xmm0, %xmm0 ; CHECK-AVX1-NEXT: retq ; -; CHECK-AVX2-LABEL: test_urem_even_div_nonsplat: +; CHECK-AVX2-LABEL: test_urem_even_div: ; CHECK-AVX2: # %bb.0: ; CHECK-AVX2-NEXT: vmovdqa {{.*#+}} xmm1 = [2863311531,3435973837,2863311531,2454267027] ; CHECK-AVX2-NEXT: vpshufd {{.*#+}} xmm2 = xmm1[1,1,3,3] @@ -239,7 +239,7 @@ ; CHECK-AVX2-NEXT: vpsrld $31, %xmm0, %xmm0 ; CHECK-AVX2-NEXT: retq ; -; CHECK-AVX512VL-LABEL: test_urem_even_div_nonsplat: +; CHECK-AVX512VL-LABEL: test_urem_even_div: ; CHECK-AVX512VL: # %bb.0: ; CHECK-AVX512VL-NEXT: vmovdqa {{.*#+}} xmm1 = [2863311531,3435973837,2863311531,2454267027] ; CHECK-AVX512VL-NEXT: vpshufd {{.*#+}} xmm2 = xmm1[1,1,3,3] @@ -262,8 +262,8 @@ ret <4 x i32> %ret } -define <4 x i32> @test_urem_pow2_nonsplat(<4 x i32> %X) nounwind readnone { -; CHECK-SSE2-LABEL: test_urem_pow2_nonsplat: +define <4 x i32> @test_urem_pow2(<4 x i32> %X) nounwind readnone { +; CHECK-SSE2-LABEL: test_urem_pow2: ; CHECK-SSE2: # %bb.0: ; CHECK-SSE2-NEXT: movdqa {{.*#+}} xmm1 = [2863311531,3435973837,2863311531,268435456] ; CHECK-SSE2-NEXT: movdqa %xmm0, %xmm2 @@ -296,7 +296,7 @@ ; CHECK-SSE2-NEXT: psrld $31, %xmm0 ; CHECK-SSE2-NEXT: retq ; -; CHECK-SSE41-LABEL: test_urem_pow2_nonsplat: +; CHECK-SSE41-LABEL: test_urem_pow2: ; CHECK-SSE41: # %bb.0: ; CHECK-SSE41-NEXT: movdqa {{.*#+}} xmm1 = [2863311531,3435973837,2863311531,268435456] ; CHECK-SSE41-NEXT: pshufd {{.*#+}} xmm2 = xmm1[1,1,3,3] @@ -319,7 +319,7 @@ ; CHECK-SSE41-NEXT: psrld $31, %xmm0 ; CHECK-SSE41-NEXT: retq ; -; CHECK-AVX1-LABEL: test_urem_pow2_nonsplat: +; CHECK-AVX1-LABEL: test_urem_pow2: ; CHECK-AVX1: # %bb.0: ; CHECK-AVX1-NEXT: vmovdqa {{.*#+}} xmm1 = [2863311531,3435973837,2863311531,268435456] ; CHECK-AVX1-NEXT: vpshufd {{.*#+}} xmm2 = xmm1[1,1,3,3] @@ -340,7 +340,7 @@ ; CHECK-AVX1-NEXT: vpsrld $31, %xmm0, %xmm0 ; CHECK-AVX1-NEXT: retq ; -; CHECK-AVX2-LABEL: test_urem_pow2_nonsplat: +; CHECK-AVX2-LABEL: test_urem_pow2: ; CHECK-AVX2: # %bb.0: ; CHECK-AVX2-NEXT: vmovdqa {{.*#+}} xmm1 = [2863311531,3435973837,2863311531,268435456] ; CHECK-AVX2-NEXT: vpshufd {{.*#+}} xmm2 = xmm1[1,1,3,3] @@ -357,7 +357,7 @@ ; CHECK-AVX2-NEXT: vpsrld $31, %xmm0, %xmm0 ; CHECK-AVX2-NEXT: retq ; -; CHECK-AVX512VL-LABEL: test_urem_pow2_nonsplat: +; CHECK-AVX512VL-LABEL: test_urem_pow2: ; CHECK-AVX512VL: # %bb.0: ; CHECK-AVX512VL-NEXT: vmovdqa {{.*#+}} xmm1 = [2863311531,3435973837,2863311531,268435456] ; CHECK-AVX512VL-NEXT: vpshufd {{.*#+}} xmm2 = xmm1[1,1,3,3] @@ -379,8 +379,8 @@ ret <4 x i32> %ret } -define <4 x i32> @test_urem_one_nonsplat(<4 x i32> %X) nounwind readnone { -; CHECK-SSE2-LABEL: test_urem_one_nonsplat: +define <4 x i32> @test_urem_one(<4 x i32> %X) nounwind readnone { +; CHECK-SSE2-LABEL: test_urem_one: ; CHECK-SSE2: # %bb.0: ; CHECK-SSE2-NEXT: movdqa %xmm0, %xmm1 ; CHECK-SSE2-NEXT: psrld $1, %xmm1 @@ -418,7 +418,7 @@ ; CHECK-SSE2-NEXT: psrld $31, %xmm0 ; CHECK-SSE2-NEXT: retq ; -; CHECK-SSE41-LABEL: test_urem_one_nonsplat: +; CHECK-SSE41-LABEL: test_urem_one: ; CHECK-SSE41: # %bb.0: ; CHECK-SSE41-NEXT: movdqa %xmm0, %xmm1 ; CHECK-SSE41-NEXT: psrld $1, %xmm1 @@ -445,7 +445,7 @@ ; CHECK-SSE41-NEXT: psrld $31, %xmm0 ; CHECK-SSE41-NEXT: retq ; -; CHECK-AVX1-LABEL: test_urem_one_nonsplat: +; CHECK-AVX1-LABEL: test_urem_one: ; CHECK-AVX1: # %bb.0: ; CHECK-AVX1-NEXT: vpsrld $1, %xmm0, %xmm1 ; CHECK-AVX1-NEXT: vpblendw {{.*#+}} xmm1 = xmm0[0,1,2,3,4,5],xmm1[6,7] @@ -469,7 +469,7 @@ ; CHECK-AVX1-NEXT: vpsrld $31, %xmm0, %xmm0 ; CHECK-AVX1-NEXT: retq ; -; CHECK-AVX2-LABEL: test_urem_one_nonsplat: +; CHECK-AVX2-LABEL: test_urem_one: ; CHECK-AVX2: # %bb.0: ; CHECK-AVX2-NEXT: vmovdqa {{.*#+}} xmm1 = [2863311531,0,2863311531,2454267027] ; CHECK-AVX2-NEXT: vpshufd {{.*#+}} xmm2 = xmm1[1,1,3,3] @@ -488,7 +488,7 @@ ; CHECK-AVX2-NEXT: vpsrld $31, %xmm0, %xmm0 ; CHECK-AVX2-NEXT: retq ; -; CHECK-AVX512VL-LABEL: test_urem_one_nonsplat: +; CHECK-AVX512VL-LABEL: test_urem_one: ; CHECK-AVX512VL: # %bb.0: ; CHECK-AVX512VL-NEXT: vmovdqa {{.*#+}} xmm1 = [2863311531,0,2863311531,2454267027] ; CHECK-AVX512VL-NEXT: vpshufd {{.*#+}} xmm2 = xmm1[1,1,3,3] @@ -512,8 +512,8 @@ ret <4 x i32> %ret } -define <4 x i32> @test_urem_comp_nonsplat(<4 x i32> %X) nounwind readnone { -; CHECK-SSE2-LABEL: test_urem_comp_nonsplat: +define <4 x i32> @test_urem_comp(<4 x i32> %X) nounwind readnone { +; CHECK-SSE2-LABEL: test_urem_comp: ; CHECK-SSE2: # %bb.0: ; CHECK-SSE2-NEXT: movdqa {{.*#+}} xmm1 = [3435973837,3435973837,3435973837,3435973837] ; CHECK-SSE2-NEXT: movdqa %xmm0, %xmm2 @@ -536,7 +536,7 @@ ; CHECK-SSE2-NEXT: psrld $31, %xmm0 ; CHECK-SSE2-NEXT: retq ; -; CHECK-SSE41-LABEL: test_urem_comp_nonsplat: +; CHECK-SSE41-LABEL: test_urem_comp: ; CHECK-SSE41: # %bb.0: ; CHECK-SSE41-NEXT: pshufd {{.*#+}} xmm1 = xmm0[1,1,3,3] ; CHECK-SSE41-NEXT: movdqa {{.*#+}} xmm2 = [3435973837,3435973837,3435973837,3435973837] @@ -551,7 +551,7 @@ ; CHECK-SSE41-NEXT: psrld $31, %xmm0 ; CHECK-SSE41-NEXT: retq ; -; CHECK-AVX1-LABEL: test_urem_comp_nonsplat: +; CHECK-AVX1-LABEL: test_urem_comp: ; CHECK-AVX1: # %bb.0: ; CHECK-AVX1-NEXT: vpshufd {{.*#+}} xmm1 = xmm0[1,1,3,3] ; CHECK-AVX1-NEXT: vmovdqa {{.*#+}} xmm2 = [3435973837,3435973837,3435973837,3435973837] @@ -566,7 +566,7 @@ ; CHECK-AVX1-NEXT: vpsrld $31, %xmm0, %xmm0 ; CHECK-AVX1-NEXT: retq ; -; CHECK-AVX2-LABEL: test_urem_comp_nonsplat: +; CHECK-AVX2-LABEL: test_urem_comp: ; CHECK-AVX2: # %bb.0: ; CHECK-AVX2-NEXT: vpshufd {{.*#+}} xmm1 = xmm0[1,1,3,3] ; CHECK-AVX2-NEXT: vpbroadcastd {{.*#+}} xmm2 = [3435973837,3435973837,3435973837,3435973837] @@ -582,7 +582,7 @@ ; CHECK-AVX2-NEXT: vpsrld $31, %xmm0, %xmm0 ; CHECK-AVX2-NEXT: retq ; -; CHECK-AVX512VL-LABEL: test_urem_comp_nonsplat: +; CHECK-AVX512VL-LABEL: test_urem_comp: ; CHECK-AVX512VL: # %bb.0: ; CHECK-AVX512VL-NEXT: vpshufd {{.*#+}} xmm1 = xmm0[1,1,3,3] ; CHECK-AVX512VL-NEXT: vpbroadcastd {{.*#+}} xmm2 = [3435973837,3435973837,3435973837,3435973837] @@ -602,8 +602,8 @@ ret <4 x i32> %ret } -define <4 x i32> @test_urem_both_nonsplat(<4 x i32> %X) nounwind readnone { -; CHECK-SSE2-LABEL: test_urem_both_nonsplat: +define <4 x i32> @test_urem_both(<4 x i32> %X) nounwind readnone { +; CHECK-SSE2-LABEL: test_urem_both: ; CHECK-SSE2: # %bb.0: ; CHECK-SSE2-NEXT: movdqa {{.*#+}} xmm1 = [2863311531,3435973837,2863311531,3435973837] ; CHECK-SSE2-NEXT: movdqa %xmm0, %xmm2 @@ -628,7 +628,7 @@ ; CHECK-SSE2-NEXT: psrld $31, %xmm0 ; CHECK-SSE2-NEXT: retq ; -; CHECK-SSE41-LABEL: test_urem_both_nonsplat: +; CHECK-SSE41-LABEL: test_urem_both: ; CHECK-SSE41: # %bb.0: ; CHECK-SSE41-NEXT: movdqa {{.*#+}} xmm1 = [2863311531,3435973837,2863311531,3435973837] ; CHECK-SSE41-NEXT: pshufd {{.*#+}} xmm2 = xmm1[1,1,3,3] @@ -644,7 +644,7 @@ ; CHECK-SSE41-NEXT: psrld $31, %xmm0 ; CHECK-SSE41-NEXT: retq ; -; CHECK-AVX1-LABEL: test_urem_both_nonsplat: +; CHECK-AVX1-LABEL: test_urem_both: ; CHECK-AVX1: # %bb.0: ; CHECK-AVX1-NEXT: vmovddup {{.*#+}} xmm1 = mem[0,0] ; CHECK-AVX1-NEXT: vpmuludq %xmm1, %xmm0, %xmm1 @@ -659,7 +659,7 @@ ; CHECK-AVX1-NEXT: vpsrld $31, %xmm0, %xmm0 ; CHECK-AVX1-NEXT: retq ; -; CHECK-AVX2-LABEL: test_urem_both_nonsplat: +; CHECK-AVX2-LABEL: test_urem_both: ; CHECK-AVX2: # %bb.0: ; CHECK-AVX2-NEXT: vpbroadcastq {{.*#+}} xmm1 = [14757395262689946283,14757395262689946283] ; CHECK-AVX2-NEXT: vpshufd {{.*#+}} xmm2 = xmm1[1,1,3,3] @@ -675,7 +675,7 @@ ; CHECK-AVX2-NEXT: vpsrld $31, %xmm0, %xmm0 ; CHECK-AVX2-NEXT: retq ; -; CHECK-AVX512VL-LABEL: test_urem_both_nonsplat: +; CHECK-AVX512VL-LABEL: test_urem_both: ; CHECK-AVX512VL: # %bb.0: ; CHECK-AVX512VL-NEXT: vpbroadcastq {{.*#+}} xmm1 = [14757395262689946283,14757395262689946283] ; CHECK-AVX512VL-NEXT: vpshufd {{.*#+}} xmm2 = xmm1[1,1,3,3] Index: test/CodeGen/X86/urem-seteq-vec-splat.ll =================================================================== --- test/CodeGen/X86/urem-seteq-vec-splat.ll +++ test/CodeGen/X86/urem-seteq-vec-splat.ll @@ -11,88 +11,48 @@ ; CHECK-SSE2-LABEL: test_urem_odd_vec_i32: ; CHECK-SSE2: # %bb.0: ; CHECK-SSE2-NEXT: movdqa {{.*#+}} xmm1 = [3435973837,3435973837,3435973837,3435973837] -; CHECK-SSE2-NEXT: movdqa %xmm0, %xmm2 +; CHECK-SSE2-NEXT: pshufd {{.*#+}} xmm2 = xmm0[1,1,3,3] +; CHECK-SSE2-NEXT: pmuludq %xmm1, %xmm0 +; CHECK-SSE2-NEXT: pshufd {{.*#+}} xmm0 = xmm0[0,2,2,3] ; CHECK-SSE2-NEXT: pmuludq %xmm1, %xmm2 -; CHECK-SSE2-NEXT: pshufd {{.*#+}} xmm2 = xmm2[1,3,2,3] -; CHECK-SSE2-NEXT: pshufd {{.*#+}} xmm3 = xmm0[1,1,3,3] -; CHECK-SSE2-NEXT: pmuludq %xmm1, %xmm3 -; CHECK-SSE2-NEXT: pshufd {{.*#+}} xmm1 = xmm3[1,3,2,3] -; CHECK-SSE2-NEXT: punpckldq {{.*#+}} xmm2 = xmm2[0],xmm1[0],xmm2[1],xmm1[1] -; CHECK-SSE2-NEXT: psrld $2, %xmm2 -; CHECK-SSE2-NEXT: movdqa {{.*#+}} xmm1 = [5,5,5,5] -; CHECK-SSE2-NEXT: pshufd {{.*#+}} xmm3 = xmm2[1,1,3,3] -; CHECK-SSE2-NEXT: pmuludq %xmm1, %xmm2 -; CHECK-SSE2-NEXT: pshufd {{.*#+}} xmm2 = xmm2[0,2,2,3] -; CHECK-SSE2-NEXT: pmuludq %xmm1, %xmm3 -; CHECK-SSE2-NEXT: pshufd {{.*#+}} xmm1 = xmm3[0,2,2,3] -; CHECK-SSE2-NEXT: punpckldq {{.*#+}} xmm2 = xmm2[0],xmm1[0],xmm2[1],xmm1[1] -; CHECK-SSE2-NEXT: psubd %xmm2, %xmm0 -; CHECK-SSE2-NEXT: pxor %xmm1, %xmm1 -; CHECK-SSE2-NEXT: pcmpeqd %xmm1, %xmm0 -; CHECK-SSE2-NEXT: psrld $31, %xmm0 +; CHECK-SSE2-NEXT: pshufd {{.*#+}} xmm1 = xmm2[0,2,2,3] +; CHECK-SSE2-NEXT: punpckldq {{.*#+}} xmm0 = xmm0[0],xmm1[0],xmm0[1],xmm1[1] +; CHECK-SSE2-NEXT: pxor {{.*}}(%rip), %xmm0 +; CHECK-SSE2-NEXT: pcmpgtd {{.*}}(%rip), %xmm0 +; CHECK-SSE2-NEXT: pandn {{.*}}(%rip), %xmm0 ; CHECK-SSE2-NEXT: retq ; ; CHECK-SSE41-LABEL: test_urem_odd_vec_i32: ; CHECK-SSE41: # %bb.0: -; CHECK-SSE41-NEXT: pshufd {{.*#+}} xmm1 = xmm0[1,1,3,3] -; CHECK-SSE41-NEXT: movdqa {{.*#+}} xmm2 = [3435973837,3435973837,3435973837,3435973837] -; CHECK-SSE41-NEXT: pmuludq %xmm2, %xmm1 -; CHECK-SSE41-NEXT: pmuludq %xmm0, %xmm2 -; CHECK-SSE41-NEXT: pshufd {{.*#+}} xmm2 = xmm2[1,1,3,3] -; CHECK-SSE41-NEXT: pblendw {{.*#+}} xmm2 = xmm2[0,1],xmm1[2,3],xmm2[4,5],xmm1[6,7] -; CHECK-SSE41-NEXT: psrld $2, %xmm2 -; CHECK-SSE41-NEXT: pmulld {{.*}}(%rip), %xmm2 -; CHECK-SSE41-NEXT: psubd %xmm2, %xmm0 -; CHECK-SSE41-NEXT: pxor %xmm1, %xmm1 +; CHECK-SSE41-NEXT: pmulld {{.*}}(%rip), %xmm0 +; CHECK-SSE41-NEXT: movdqa {{.*#+}} xmm1 = [858993459,858993459,858993459,858993459] +; CHECK-SSE41-NEXT: pminud %xmm0, %xmm1 ; CHECK-SSE41-NEXT: pcmpeqd %xmm1, %xmm0 ; CHECK-SSE41-NEXT: psrld $31, %xmm0 ; CHECK-SSE41-NEXT: retq ; ; CHECK-AVX1-LABEL: test_urem_odd_vec_i32: ; CHECK-AVX1: # %bb.0: -; CHECK-AVX1-NEXT: vpshufd {{.*#+}} xmm1 = xmm0[1,1,3,3] -; CHECK-AVX1-NEXT: vmovdqa {{.*#+}} xmm2 = [3435973837,3435973837,3435973837,3435973837] -; CHECK-AVX1-NEXT: vpmuludq %xmm2, %xmm1, %xmm1 -; CHECK-AVX1-NEXT: vpmuludq %xmm2, %xmm0, %xmm2 -; CHECK-AVX1-NEXT: vpshufd {{.*#+}} xmm2 = xmm2[1,1,3,3] -; CHECK-AVX1-NEXT: vpblendw {{.*#+}} xmm1 = xmm2[0,1],xmm1[2,3],xmm2[4,5],xmm1[6,7] -; CHECK-AVX1-NEXT: vpsrld $2, %xmm1, %xmm1 -; CHECK-AVX1-NEXT: vpmulld {{.*}}(%rip), %xmm1, %xmm1 -; CHECK-AVX1-NEXT: vpsubd %xmm1, %xmm0, %xmm0 -; CHECK-AVX1-NEXT: vpxor %xmm1, %xmm1, %xmm1 +; CHECK-AVX1-NEXT: vpmulld {{.*}}(%rip), %xmm0, %xmm0 +; CHECK-AVX1-NEXT: vpminud {{.*}}(%rip), %xmm0, %xmm1 ; CHECK-AVX1-NEXT: vpcmpeqd %xmm1, %xmm0, %xmm0 ; CHECK-AVX1-NEXT: vpsrld $31, %xmm0, %xmm0 ; CHECK-AVX1-NEXT: retq ; ; CHECK-AVX2-LABEL: test_urem_odd_vec_i32: ; CHECK-AVX2: # %bb.0: -; CHECK-AVX2-NEXT: vpshufd {{.*#+}} xmm1 = xmm0[1,1,3,3] -; CHECK-AVX2-NEXT: vpbroadcastd {{.*#+}} xmm2 = [3435973837,3435973837,3435973837,3435973837] -; CHECK-AVX2-NEXT: vpmuludq %xmm2, %xmm1, %xmm1 -; CHECK-AVX2-NEXT: vpmuludq %xmm2, %xmm0, %xmm2 -; CHECK-AVX2-NEXT: vpshufd {{.*#+}} xmm2 = xmm2[1,1,3,3] -; CHECK-AVX2-NEXT: vpblendd {{.*#+}} xmm1 = xmm2[0],xmm1[1],xmm2[2],xmm1[3] -; CHECK-AVX2-NEXT: vpsrld $2, %xmm1, %xmm1 -; CHECK-AVX2-NEXT: vpbroadcastd {{.*#+}} xmm2 = [5,5,5,5] -; CHECK-AVX2-NEXT: vpmulld %xmm2, %xmm1, %xmm1 -; CHECK-AVX2-NEXT: vpsubd %xmm1, %xmm0, %xmm0 -; CHECK-AVX2-NEXT: vpxor %xmm1, %xmm1, %xmm1 +; CHECK-AVX2-NEXT: vpbroadcastd {{.*#+}} xmm1 = [3435973837,3435973837,3435973837,3435973837] +; CHECK-AVX2-NEXT: vpmulld %xmm1, %xmm0, %xmm0 +; CHECK-AVX2-NEXT: vpbroadcastd {{.*#+}} xmm1 = [858993459,858993459,858993459,858993459] +; CHECK-AVX2-NEXT: vpminud %xmm1, %xmm0, %xmm1 ; CHECK-AVX2-NEXT: vpcmpeqd %xmm1, %xmm0, %xmm0 ; CHECK-AVX2-NEXT: vpsrld $31, %xmm0, %xmm0 ; CHECK-AVX2-NEXT: retq ; ; CHECK-AVX512VL-LABEL: test_urem_odd_vec_i32: ; CHECK-AVX512VL: # %bb.0: -; CHECK-AVX512VL-NEXT: vpshufd {{.*#+}} xmm1 = xmm0[1,1,3,3] -; CHECK-AVX512VL-NEXT: vpbroadcastd {{.*#+}} xmm2 = [3435973837,3435973837,3435973837,3435973837] -; CHECK-AVX512VL-NEXT: vpmuludq %xmm2, %xmm1, %xmm1 -; CHECK-AVX512VL-NEXT: vpmuludq %xmm2, %xmm0, %xmm2 -; CHECK-AVX512VL-NEXT: vpshufd {{.*#+}} xmm2 = xmm2[1,1,3,3] -; CHECK-AVX512VL-NEXT: vpblendd {{.*#+}} xmm1 = xmm2[0],xmm1[1],xmm2[2],xmm1[3] -; CHECK-AVX512VL-NEXT: vpsrld $2, %xmm1, %xmm1 -; CHECK-AVX512VL-NEXT: vpmulld {{.*}}(%rip){1to4}, %xmm1, %xmm1 -; CHECK-AVX512VL-NEXT: vpsubd %xmm1, %xmm0, %xmm0 -; CHECK-AVX512VL-NEXT: vpxor %xmm1, %xmm1, %xmm1 +; CHECK-AVX512VL-NEXT: vpmulld {{.*}}(%rip){1to4}, %xmm0, %xmm0 +; CHECK-AVX512VL-NEXT: vpminud {{.*}}(%rip){1to4}, %xmm0, %xmm1 ; CHECK-AVX512VL-NEXT: vpcmpeqd %xmm1, %xmm0, %xmm0 ; CHECK-AVX512VL-NEXT: vpsrld $31, %xmm0, %xmm0 ; CHECK-AVX512VL-NEXT: retq @@ -102,105 +62,39 @@ ret <4 x i32> %ret } -; Like test_urem_odd_vec_i32, but with 4 x i16 vectors. -define <4 x i16> @test_urem_odd_vec_i16(<4 x i16> %X) nounwind readnone { +; Like test_urem_odd_vec_i32, but with 8 x i16 vectors. +define <8 x i16> @test_urem_odd_vec_i16(<8 x i16> %X) nounwind readnone { ; CHECK-SSE2-LABEL: test_urem_odd_vec_i16: ; CHECK-SSE2: # %bb.0: -; CHECK-SSE2-NEXT: pand {{.*}}(%rip), %xmm0 -; CHECK-SSE2-NEXT: movdqa {{.*#+}} xmm1 = [3435973837,3435973837,3435973837,3435973837] -; CHECK-SSE2-NEXT: movdqa %xmm0, %xmm2 -; CHECK-SSE2-NEXT: pmuludq %xmm1, %xmm2 -; CHECK-SSE2-NEXT: pshufd {{.*#+}} xmm2 = xmm2[1,3,2,3] -; CHECK-SSE2-NEXT: pshufd {{.*#+}} xmm3 = xmm0[1,1,3,3] -; CHECK-SSE2-NEXT: pmuludq %xmm1, %xmm3 -; CHECK-SSE2-NEXT: pshufd {{.*#+}} xmm1 = xmm3[1,3,2,3] -; CHECK-SSE2-NEXT: punpckldq {{.*#+}} xmm2 = xmm2[0],xmm1[0],xmm2[1],xmm1[1] -; CHECK-SSE2-NEXT: psrld $2, %xmm2 -; CHECK-SSE2-NEXT: movdqa {{.*#+}} xmm1 = [5,5,5,5] -; CHECK-SSE2-NEXT: pshufd {{.*#+}} xmm3 = xmm2[1,1,3,3] -; CHECK-SSE2-NEXT: pmuludq %xmm1, %xmm2 -; CHECK-SSE2-NEXT: pshufd {{.*#+}} xmm2 = xmm2[0,2,2,3] -; CHECK-SSE2-NEXT: pmuludq %xmm1, %xmm3 -; CHECK-SSE2-NEXT: pshufd {{.*#+}} xmm1 = xmm3[0,2,2,3] -; CHECK-SSE2-NEXT: punpckldq {{.*#+}} xmm2 = xmm2[0],xmm1[0],xmm2[1],xmm1[1] -; CHECK-SSE2-NEXT: psubd %xmm2, %xmm0 +; CHECK-SSE2-NEXT: pmullw {{.*}}(%rip), %xmm0 +; CHECK-SSE2-NEXT: psubusw {{.*}}(%rip), %xmm0 ; CHECK-SSE2-NEXT: pxor %xmm1, %xmm1 -; CHECK-SSE2-NEXT: pcmpeqd %xmm1, %xmm0 -; CHECK-SSE2-NEXT: psrld $31, %xmm0 +; CHECK-SSE2-NEXT: pcmpeqw %xmm1, %xmm0 +; CHECK-SSE2-NEXT: psrlw $15, %xmm0 ; CHECK-SSE2-NEXT: retq ; ; CHECK-SSE41-LABEL: test_urem_odd_vec_i16: ; CHECK-SSE41: # %bb.0: -; CHECK-SSE41-NEXT: pxor %xmm1, %xmm1 -; CHECK-SSE41-NEXT: pblendw {{.*#+}} xmm0 = xmm0[0],xmm1[1],xmm0[2],xmm1[3],xmm0[4],xmm1[5],xmm0[6],xmm1[7] -; CHECK-SSE41-NEXT: pshufd {{.*#+}} xmm2 = xmm0[1,1,3,3] -; CHECK-SSE41-NEXT: movdqa {{.*#+}} xmm3 = [3435973837,3435973837,3435973837,3435973837] -; CHECK-SSE41-NEXT: pmuludq %xmm3, %xmm2 -; CHECK-SSE41-NEXT: pmuludq %xmm0, %xmm3 -; CHECK-SSE41-NEXT: pshufd {{.*#+}} xmm3 = xmm3[1,1,3,3] -; CHECK-SSE41-NEXT: pblendw {{.*#+}} xmm3 = xmm3[0,1],xmm2[2,3],xmm3[4,5],xmm2[6,7] -; CHECK-SSE41-NEXT: psrld $2, %xmm3 -; CHECK-SSE41-NEXT: pmulld {{.*}}(%rip), %xmm3 -; CHECK-SSE41-NEXT: psubd %xmm3, %xmm0 -; CHECK-SSE41-NEXT: pcmpeqd %xmm1, %xmm0 -; CHECK-SSE41-NEXT: psrld $31, %xmm0 +; CHECK-SSE41-NEXT: pmullw {{.*}}(%rip), %xmm0 +; CHECK-SSE41-NEXT: movdqa {{.*#+}} xmm1 = [13107,13107,13107,13107,13107,13107,13107,13107] +; CHECK-SSE41-NEXT: pminuw %xmm0, %xmm1 +; CHECK-SSE41-NEXT: pcmpeqw %xmm1, %xmm0 +; CHECK-SSE41-NEXT: psrlw $15, %xmm0 ; CHECK-SSE41-NEXT: retq ; -; CHECK-AVX1-LABEL: test_urem_odd_vec_i16: -; CHECK-AVX1: # %bb.0: -; CHECK-AVX1-NEXT: vpxor %xmm1, %xmm1, %xmm1 -; CHECK-AVX1-NEXT: vpblendw {{.*#+}} xmm0 = xmm0[0],xmm1[1],xmm0[2],xmm1[3],xmm0[4],xmm1[5],xmm0[6],xmm1[7] -; CHECK-AVX1-NEXT: vpshufd {{.*#+}} xmm2 = xmm0[1,1,3,3] -; CHECK-AVX1-NEXT: vmovdqa {{.*#+}} xmm3 = [3435973837,3435973837,3435973837,3435973837] -; CHECK-AVX1-NEXT: vpmuludq %xmm3, %xmm2, %xmm2 -; CHECK-AVX1-NEXT: vpmuludq %xmm3, %xmm0, %xmm3 -; CHECK-AVX1-NEXT: vpshufd {{.*#+}} xmm3 = xmm3[1,1,3,3] -; CHECK-AVX1-NEXT: vpblendw {{.*#+}} xmm2 = xmm3[0,1],xmm2[2,3],xmm3[4,5],xmm2[6,7] -; CHECK-AVX1-NEXT: vpsrld $2, %xmm2, %xmm2 -; CHECK-AVX1-NEXT: vpmulld {{.*}}(%rip), %xmm2, %xmm2 -; CHECK-AVX1-NEXT: vpsubd %xmm2, %xmm0, %xmm0 -; CHECK-AVX1-NEXT: vpcmpeqd %xmm1, %xmm0, %xmm0 -; CHECK-AVX1-NEXT: vpsrld $31, %xmm0, %xmm0 -; CHECK-AVX1-NEXT: retq -; -; CHECK-AVX2-LABEL: test_urem_odd_vec_i16: -; CHECK-AVX2: # %bb.0: -; CHECK-AVX2-NEXT: vpxor %xmm1, %xmm1, %xmm1 -; CHECK-AVX2-NEXT: vpblendw {{.*#+}} xmm0 = xmm0[0],xmm1[1],xmm0[2],xmm1[3],xmm0[4],xmm1[5],xmm0[6],xmm1[7] -; CHECK-AVX2-NEXT: vpshufd {{.*#+}} xmm2 = xmm0[1,1,3,3] -; CHECK-AVX2-NEXT: vpbroadcastd {{.*#+}} xmm3 = [3435973837,3435973837,3435973837,3435973837] -; CHECK-AVX2-NEXT: vpmuludq %xmm3, %xmm2, %xmm2 -; CHECK-AVX2-NEXT: vpmuludq %xmm3, %xmm0, %xmm3 -; CHECK-AVX2-NEXT: vpshufd {{.*#+}} xmm3 = xmm3[1,1,3,3] -; CHECK-AVX2-NEXT: vpblendd {{.*#+}} xmm2 = xmm3[0],xmm2[1],xmm3[2],xmm2[3] -; CHECK-AVX2-NEXT: vpsrld $2, %xmm2, %xmm2 -; CHECK-AVX2-NEXT: vpbroadcastd {{.*#+}} xmm3 = [5,5,5,5] -; CHECK-AVX2-NEXT: vpmulld %xmm3, %xmm2, %xmm2 -; CHECK-AVX2-NEXT: vpsubd %xmm2, %xmm0, %xmm0 -; CHECK-AVX2-NEXT: vpcmpeqd %xmm1, %xmm0, %xmm0 -; CHECK-AVX2-NEXT: vpsrld $31, %xmm0, %xmm0 -; CHECK-AVX2-NEXT: retq -; -; CHECK-AVX512VL-LABEL: test_urem_odd_vec_i16: -; CHECK-AVX512VL: # %bb.0: -; CHECK-AVX512VL-NEXT: vpxor %xmm1, %xmm1, %xmm1 -; CHECK-AVX512VL-NEXT: vpblendw {{.*#+}} xmm0 = xmm0[0],xmm1[1],xmm0[2],xmm1[3],xmm0[4],xmm1[5],xmm0[6],xmm1[7] -; CHECK-AVX512VL-NEXT: vpshufd {{.*#+}} xmm2 = xmm0[1,1,3,3] -; CHECK-AVX512VL-NEXT: vpbroadcastd {{.*#+}} xmm3 = [3435973837,3435973837,3435973837,3435973837] -; CHECK-AVX512VL-NEXT: vpmuludq %xmm3, %xmm2, %xmm2 -; CHECK-AVX512VL-NEXT: vpmuludq %xmm3, %xmm0, %xmm3 -; CHECK-AVX512VL-NEXT: vpshufd {{.*#+}} xmm3 = xmm3[1,1,3,3] -; CHECK-AVX512VL-NEXT: vpblendd {{.*#+}} xmm2 = xmm3[0],xmm2[1],xmm3[2],xmm2[3] -; CHECK-AVX512VL-NEXT: vpsrld $2, %xmm2, %xmm2 -; CHECK-AVX512VL-NEXT: vpmulld {{.*}}(%rip){1to4}, %xmm2, %xmm2 -; CHECK-AVX512VL-NEXT: vpsubd %xmm2, %xmm0, %xmm0 -; CHECK-AVX512VL-NEXT: vpcmpeqd %xmm1, %xmm0, %xmm0 -; CHECK-AVX512VL-NEXT: vpsrld $31, %xmm0, %xmm0 -; CHECK-AVX512VL-NEXT: retq - %urem = urem <4 x i16> %X, - %cmp = icmp eq <4 x i16> %urem, - %ret = zext <4 x i1> %cmp to <4 x i16> - ret <4 x i16> %ret +; CHECK-AVX-LABEL: test_urem_odd_vec_i16: +; CHECK-AVX: # %bb.0: +; CHECK-AVX-NEXT: vpmullw {{.*}}(%rip), %xmm0, %xmm0 +; CHECK-AVX-NEXT: vpminuw {{.*}}(%rip), %xmm0, %xmm1 +; CHECK-AVX-NEXT: vpcmpeqw %xmm1, %xmm0, %xmm0 +; CHECK-AVX-NEXT: vpsrlw $15, %xmm0, %xmm0 +; CHECK-AVX-NEXT: retq + %urem = urem <8 x i16> %X, + %cmp = icmp eq <8 x i16> %urem, + %ret = zext <8 x i1> %cmp to <8 x i16> + ret <8 x i16> %ret } ; Tests BuildUREMEqFold for 4 x i32 splat vectors with even divisor. @@ -287,17 +181,9 @@ ; ; CHECK-AVX512VL-LABEL: test_urem_even_vec_i32: ; CHECK-AVX512VL: # %bb.0: -; CHECK-AVX512VL-NEXT: vpsrld $1, %xmm0, %xmm1 -; CHECK-AVX512VL-NEXT: vpshufd {{.*#+}} xmm2 = xmm1[1,1,3,3] -; CHECK-AVX512VL-NEXT: vpbroadcastd {{.*#+}} xmm3 = [2454267027,2454267027,2454267027,2454267027] -; CHECK-AVX512VL-NEXT: vpmuludq %xmm3, %xmm2, %xmm2 -; CHECK-AVX512VL-NEXT: vpmuludq %xmm3, %xmm1, %xmm1 -; CHECK-AVX512VL-NEXT: vpshufd {{.*#+}} xmm1 = xmm1[1,1,3,3] -; CHECK-AVX512VL-NEXT: vpblendd {{.*#+}} xmm1 = xmm1[0],xmm2[1],xmm1[2],xmm2[3] -; CHECK-AVX512VL-NEXT: vpsrld $2, %xmm1, %xmm1 -; CHECK-AVX512VL-NEXT: vpmulld {{.*}}(%rip){1to4}, %xmm1, %xmm1 -; CHECK-AVX512VL-NEXT: vpsubd %xmm1, %xmm0, %xmm0 -; CHECK-AVX512VL-NEXT: vpxor %xmm1, %xmm1, %xmm1 +; CHECK-AVX512VL-NEXT: vpmulld {{.*}}(%rip){1to4}, %xmm0, %xmm0 +; CHECK-AVX512VL-NEXT: vprord $1, %xmm0, %xmm0 +; CHECK-AVX512VL-NEXT: vpminud {{.*}}(%rip){1to4}, %xmm0, %xmm1 ; CHECK-AVX512VL-NEXT: vpcmpeqd %xmm1, %xmm0, %xmm0 ; CHECK-AVX512VL-NEXT: vpsrld $31, %xmm0, %xmm0 ; CHECK-AVX512VL-NEXT: retq @@ -307,111 +193,38 @@ ret <4 x i32> %ret } -; Like test_urem_even_vec_i32, but with 4 x i16 vectors. -define <4 x i16> @test_urem_even_vec_i16(<4 x i16> %X) nounwind readnone { -; CHECK-SSE2-LABEL: test_urem_even_vec_i16: -; CHECK-SSE2: # %bb.0: -; CHECK-SSE2-NEXT: pand {{.*}}(%rip), %xmm0 -; CHECK-SSE2-NEXT: movdqa %xmm0, %xmm1 -; CHECK-SSE2-NEXT: psrld $1, %xmm1 -; CHECK-SSE2-NEXT: movdqa {{.*#+}} xmm2 = [2454267027,2454267027,2454267027,2454267027] -; CHECK-SSE2-NEXT: pshufd {{.*#+}} xmm3 = xmm1[1,1,3,3] -; CHECK-SSE2-NEXT: pmuludq %xmm2, %xmm1 -; CHECK-SSE2-NEXT: pshufd {{.*#+}} xmm1 = xmm1[1,3,2,3] -; CHECK-SSE2-NEXT: pmuludq %xmm2, %xmm3 -; CHECK-SSE2-NEXT: pshufd {{.*#+}} xmm2 = xmm3[1,3,2,3] -; CHECK-SSE2-NEXT: punpckldq {{.*#+}} xmm1 = xmm1[0],xmm2[0],xmm1[1],xmm2[1] -; CHECK-SSE2-NEXT: psrld $2, %xmm1 -; CHECK-SSE2-NEXT: movdqa {{.*#+}} xmm2 = [14,14,14,14] -; CHECK-SSE2-NEXT: pshufd {{.*#+}} xmm3 = xmm1[1,1,3,3] -; CHECK-SSE2-NEXT: pmuludq %xmm2, %xmm1 -; CHECK-SSE2-NEXT: pshufd {{.*#+}} xmm1 = xmm1[0,2,2,3] -; CHECK-SSE2-NEXT: pmuludq %xmm2, %xmm3 -; CHECK-SSE2-NEXT: pshufd {{.*#+}} xmm2 = xmm3[0,2,2,3] -; CHECK-SSE2-NEXT: punpckldq {{.*#+}} xmm1 = xmm1[0],xmm2[0],xmm1[1],xmm2[1] -; CHECK-SSE2-NEXT: psubd %xmm1, %xmm0 -; CHECK-SSE2-NEXT: pxor %xmm1, %xmm1 -; CHECK-SSE2-NEXT: pcmpeqd %xmm1, %xmm0 -; CHECK-SSE2-NEXT: psrld $31, %xmm0 -; CHECK-SSE2-NEXT: retq -; -; CHECK-SSE41-LABEL: test_urem_even_vec_i16: -; CHECK-SSE41: # %bb.0: -; CHECK-SSE41-NEXT: pxor %xmm1, %xmm1 -; CHECK-SSE41-NEXT: pblendw {{.*#+}} xmm0 = xmm0[0],xmm1[1],xmm0[2],xmm1[3],xmm0[4],xmm1[5],xmm0[6],xmm1[7] -; CHECK-SSE41-NEXT: movdqa %xmm0, %xmm2 -; CHECK-SSE41-NEXT: psrld $1, %xmm2 -; CHECK-SSE41-NEXT: pshufd {{.*#+}} xmm3 = xmm2[1,1,3,3] -; CHECK-SSE41-NEXT: movdqa {{.*#+}} xmm4 = [2454267027,2454267027,2454267027,2454267027] -; CHECK-SSE41-NEXT: pmuludq %xmm4, %xmm3 -; CHECK-SSE41-NEXT: pmuludq %xmm4, %xmm2 -; CHECK-SSE41-NEXT: pshufd {{.*#+}} xmm2 = xmm2[1,1,3,3] -; CHECK-SSE41-NEXT: pblendw {{.*#+}} xmm2 = xmm2[0,1],xmm3[2,3],xmm2[4,5],xmm3[6,7] -; CHECK-SSE41-NEXT: psrld $2, %xmm2 -; CHECK-SSE41-NEXT: pmulld {{.*}}(%rip), %xmm2 -; CHECK-SSE41-NEXT: psubd %xmm2, %xmm0 -; CHECK-SSE41-NEXT: pcmpeqd %xmm1, %xmm0 -; CHECK-SSE41-NEXT: psrld $31, %xmm0 -; CHECK-SSE41-NEXT: retq -; -; CHECK-AVX1-LABEL: test_urem_even_vec_i16: -; CHECK-AVX1: # %bb.0: -; CHECK-AVX1-NEXT: vpxor %xmm1, %xmm1, %xmm1 -; CHECK-AVX1-NEXT: vpblendw {{.*#+}} xmm0 = xmm0[0],xmm1[1],xmm0[2],xmm1[3],xmm0[4],xmm1[5],xmm0[6],xmm1[7] -; CHECK-AVX1-NEXT: vpsrld $1, %xmm0, %xmm2 -; CHECK-AVX1-NEXT: vpshufd {{.*#+}} xmm3 = xmm2[1,1,3,3] -; CHECK-AVX1-NEXT: vmovdqa {{.*#+}} xmm4 = [2454267027,2454267027,2454267027,2454267027] -; CHECK-AVX1-NEXT: vpmuludq %xmm4, %xmm3, %xmm3 -; CHECK-AVX1-NEXT: vpmuludq %xmm4, %xmm2, %xmm2 -; CHECK-AVX1-NEXT: vpshufd {{.*#+}} xmm2 = xmm2[1,1,3,3] -; CHECK-AVX1-NEXT: vpblendw {{.*#+}} xmm2 = xmm2[0,1],xmm3[2,3],xmm2[4,5],xmm3[6,7] -; CHECK-AVX1-NEXT: vpsrld $2, %xmm2, %xmm2 -; CHECK-AVX1-NEXT: vpmulld {{.*}}(%rip), %xmm2, %xmm2 -; CHECK-AVX1-NEXT: vpsubd %xmm2, %xmm0, %xmm0 -; CHECK-AVX1-NEXT: vpcmpeqd %xmm1, %xmm0, %xmm0 -; CHECK-AVX1-NEXT: vpsrld $31, %xmm0, %xmm0 -; CHECK-AVX1-NEXT: retq -; -; CHECK-AVX2-LABEL: test_urem_even_vec_i16: -; CHECK-AVX2: # %bb.0: -; CHECK-AVX2-NEXT: vpxor %xmm1, %xmm1, %xmm1 -; CHECK-AVX2-NEXT: vpblendw {{.*#+}} xmm0 = xmm0[0],xmm1[1],xmm0[2],xmm1[3],xmm0[4],xmm1[5],xmm0[6],xmm1[7] -; CHECK-AVX2-NEXT: vpsrld $1, %xmm0, %xmm2 -; CHECK-AVX2-NEXT: vpshufd {{.*#+}} xmm3 = xmm2[1,1,3,3] -; CHECK-AVX2-NEXT: vpbroadcastd {{.*#+}} xmm4 = [2454267027,2454267027,2454267027,2454267027] -; CHECK-AVX2-NEXT: vpmuludq %xmm4, %xmm3, %xmm3 -; CHECK-AVX2-NEXT: vpmuludq %xmm4, %xmm2, %xmm2 -; CHECK-AVX2-NEXT: vpshufd {{.*#+}} xmm2 = xmm2[1,1,3,3] -; CHECK-AVX2-NEXT: vpblendd {{.*#+}} xmm2 = xmm2[0],xmm3[1],xmm2[2],xmm3[3] -; CHECK-AVX2-NEXT: vpsrld $2, %xmm2, %xmm2 -; CHECK-AVX2-NEXT: vpbroadcastd {{.*#+}} xmm3 = [14,14,14,14] -; CHECK-AVX2-NEXT: vpmulld %xmm3, %xmm2, %xmm2 -; CHECK-AVX2-NEXT: vpsubd %xmm2, %xmm0, %xmm0 -; CHECK-AVX2-NEXT: vpcmpeqd %xmm1, %xmm0, %xmm0 -; CHECK-AVX2-NEXT: vpsrld $31, %xmm0, %xmm0 -; CHECK-AVX2-NEXT: retq +; Like test_urem_even_vec_i32, but with 8 x i16 vectors. +define <8 x i16> @test_urem_even_vec_i16(<8 x i16> %X) nounwind readnone { +; CHECK-SSE-LABEL: test_urem_even_vec_i16: +; CHECK-SSE: # %bb.0: +; CHECK-SSE-NEXT: movdqa %xmm0, %xmm1 +; CHECK-SSE-NEXT: psrlw $1, %xmm1 +; CHECK-SSE-NEXT: pmulhuw {{.*}}(%rip), %xmm1 +; CHECK-SSE-NEXT: psrlw $1, %xmm1 +; CHECK-SSE-NEXT: pmullw {{.*}}(%rip), %xmm1 +; CHECK-SSE-NEXT: psubw %xmm1, %xmm0 +; CHECK-SSE-NEXT: pxor %xmm1, %xmm1 +; CHECK-SSE-NEXT: pcmpeqw %xmm1, %xmm0 +; CHECK-SSE-NEXT: psrlw $15, %xmm0 +; CHECK-SSE-NEXT: retq ; -; CHECK-AVX512VL-LABEL: test_urem_even_vec_i16: -; CHECK-AVX512VL: # %bb.0: -; CHECK-AVX512VL-NEXT: vpxor %xmm1, %xmm1, %xmm1 -; CHECK-AVX512VL-NEXT: vpblendw {{.*#+}} xmm0 = xmm0[0],xmm1[1],xmm0[2],xmm1[3],xmm0[4],xmm1[5],xmm0[6],xmm1[7] -; CHECK-AVX512VL-NEXT: vpsrld $1, %xmm0, %xmm2 -; CHECK-AVX512VL-NEXT: vpshufd {{.*#+}} xmm3 = xmm2[1,1,3,3] -; CHECK-AVX512VL-NEXT: vpbroadcastd {{.*#+}} xmm4 = [2454267027,2454267027,2454267027,2454267027] -; CHECK-AVX512VL-NEXT: vpmuludq %xmm4, %xmm3, %xmm3 -; CHECK-AVX512VL-NEXT: vpmuludq %xmm4, %xmm2, %xmm2 -; CHECK-AVX512VL-NEXT: vpshufd {{.*#+}} xmm2 = xmm2[1,1,3,3] -; CHECK-AVX512VL-NEXT: vpblendd {{.*#+}} xmm2 = xmm2[0],xmm3[1],xmm2[2],xmm3[3] -; CHECK-AVX512VL-NEXT: vpsrld $2, %xmm2, %xmm2 -; CHECK-AVX512VL-NEXT: vpmulld {{.*}}(%rip){1to4}, %xmm2, %xmm2 -; CHECK-AVX512VL-NEXT: vpsubd %xmm2, %xmm0, %xmm0 -; CHECK-AVX512VL-NEXT: vpcmpeqd %xmm1, %xmm0, %xmm0 -; CHECK-AVX512VL-NEXT: vpsrld $31, %xmm0, %xmm0 -; CHECK-AVX512VL-NEXT: retq - %urem = urem <4 x i16> %X, - %cmp = icmp eq <4 x i16> %urem, - %ret = zext <4 x i1> %cmp to <4 x i16> - ret <4 x i16> %ret +; CHECK-AVX-LABEL: test_urem_even_vec_i16: +; CHECK-AVX: # %bb.0: +; CHECK-AVX-NEXT: vpsrlw $1, %xmm0, %xmm1 +; CHECK-AVX-NEXT: vpmulhuw {{.*}}(%rip), %xmm1, %xmm1 +; CHECK-AVX-NEXT: vpsrlw $1, %xmm1, %xmm1 +; CHECK-AVX-NEXT: vpmullw {{.*}}(%rip), %xmm1, %xmm1 +; CHECK-AVX-NEXT: vpsubw %xmm1, %xmm0, %xmm0 +; CHECK-AVX-NEXT: vpxor %xmm1, %xmm1, %xmm1 +; CHECK-AVX-NEXT: vpcmpeqw %xmm1, %xmm0, %xmm0 +; CHECK-AVX-NEXT: vpsrlw $15, %xmm0, %xmm0 +; CHECK-AVX-NEXT: retq + %urem = urem <8 x i16> %X, + %cmp = icmp eq <8 x i16> %urem, + %ret = zext <8 x i1> %cmp to <8 x i16> + ret <8 x i16> %ret } ; We should not proceed with this fold if the divisor is 1 or -1 Index: test/CodeGen/X86/urem-seteq.ll =================================================================== --- test/CodeGen/X86/urem-seteq.ll +++ test/CodeGen/X86/urem-seteq.ll @@ -9,27 +9,18 @@ define i32 @test_urem_odd(i32 %X) nounwind readnone { ; X86-LABEL: test_urem_odd: ; X86: # %bb.0: -; X86-NEXT: movl {{[0-9]+}}(%esp), %ecx -; X86-NEXT: movl $-858993459, %edx # imm = 0xCCCCCCCD -; X86-NEXT: movl %ecx, %eax -; X86-NEXT: mull %edx -; X86-NEXT: shrl $2, %edx -; X86-NEXT: leal (%edx,%edx,4), %edx +; X86-NEXT: imull $-858993459, {{[0-9]+}}(%esp), %ecx # imm = 0xCCCCCCCD ; X86-NEXT: xorl %eax, %eax -; X86-NEXT: cmpl %edx, %ecx -; X86-NEXT: sete %al +; X86-NEXT: cmpl $858993460, %ecx # imm = 0x33333334 +; X86-NEXT: setb %al ; X86-NEXT: retl ; ; X64-LABEL: test_urem_odd: ; X64: # %bb.0: -; X64-NEXT: movl %edi, %eax -; X64-NEXT: movl $3435973837, %ecx # imm = 0xCCCCCCCD -; X64-NEXT: imulq %rax, %rcx -; X64-NEXT: shrq $34, %rcx -; X64-NEXT: leal (%rcx,%rcx,4), %ecx +; X64-NEXT: imull $-858993459, %edi, %ecx # imm = 0xCCCCCCCD ; X64-NEXT: xorl %eax, %eax -; X64-NEXT: cmpl %ecx, %edi -; X64-NEXT: sete %al +; X64-NEXT: cmpl $858993460, %ecx # imm = 0x33333334 +; X64-NEXT: setb %al ; X64-NEXT: retq %urem = urem i32 %X, 5 %cmp = icmp eq i32 %urem, 0 @@ -41,27 +32,18 @@ define i32 @test_urem_odd_bit30(i32 %X) nounwind readnone { ; X86-LABEL: test_urem_odd_bit30: ; X86: # %bb.0: -; X86-NEXT: movl {{[0-9]+}}(%esp), %ecx -; X86-NEXT: movl $-11, %edx -; X86-NEXT: movl %ecx, %eax -; X86-NEXT: mull %edx -; X86-NEXT: shrl $30, %edx -; X86-NEXT: imull $1073741827, %edx, %edx # imm = 0x40000003 +; X86-NEXT: imull $1789569707, {{[0-9]+}}(%esp), %ecx # imm = 0x6AAAAAAB ; X86-NEXT: xorl %eax, %eax -; X86-NEXT: cmpl %edx, %ecx -; X86-NEXT: sete %al +; X86-NEXT: cmpl $4, %ecx +; X86-NEXT: setb %al ; X86-NEXT: retl ; ; X64-LABEL: test_urem_odd_bit30: ; X64: # %bb.0: -; X64-NEXT: movl %edi, %eax -; X64-NEXT: movl $4294967285, %ecx # imm = 0xFFFFFFF5 -; X64-NEXT: imulq %rax, %rcx -; X64-NEXT: shrq $62, %rcx -; X64-NEXT: imull $1073741827, %ecx, %ecx # imm = 0x40000003 +; X64-NEXT: imull $1789569707, %edi, %ecx # imm = 0x6AAAAAAB ; X64-NEXT: xorl %eax, %eax -; X64-NEXT: cmpl %ecx, %edi -; X64-NEXT: sete %al +; X64-NEXT: cmpl $4, %ecx +; X64-NEXT: setb %al ; X64-NEXT: retq %urem = urem i32 %X, 1073741827 %cmp = icmp eq i32 %urem, 0 @@ -73,28 +55,18 @@ define i32 @test_urem_odd_bit31(i32 %X) nounwind readnone { ; X86-LABEL: test_urem_odd_bit31: ; X86: # %bb.0: -; X86-NEXT: movl {{[0-9]+}}(%esp), %ecx -; X86-NEXT: movl $1073741823, %edx # imm = 0x3FFFFFFF -; X86-NEXT: movl %ecx, %eax -; X86-NEXT: mull %edx -; X86-NEXT: shrl $29, %edx -; X86-NEXT: imull $-2147483645, %edx, %edx # imm = 0x80000003 +; X86-NEXT: imull $715827883, {{[0-9]+}}(%esp), %ecx # imm = 0x2AAAAAAB ; X86-NEXT: xorl %eax, %eax -; X86-NEXT: cmpl %edx, %ecx -; X86-NEXT: sete %al +; X86-NEXT: cmpl $2, %ecx +; X86-NEXT: setb %al ; X86-NEXT: retl ; ; X64-LABEL: test_urem_odd_bit31: ; X64: # %bb.0: -; X64-NEXT: movl %edi, %eax -; X64-NEXT: movq %rax, %rcx -; X64-NEXT: shlq $30, %rcx -; X64-NEXT: subq %rax, %rcx -; X64-NEXT: shrq $61, %rcx -; X64-NEXT: imull $-2147483645, %ecx, %ecx # imm = 0x80000003 +; X64-NEXT: imull $715827883, %edi, %ecx # imm = 0x2AAAAAAB ; X64-NEXT: xorl %eax, %eax -; X64-NEXT: cmpl %ecx, %edi -; X64-NEXT: sete %al +; X64-NEXT: cmpl $2, %ecx +; X64-NEXT: setb %al ; X64-NEXT: retq %urem = urem i32 %X, 2147483651 %cmp = icmp eq i32 %urem, 0 @@ -111,35 +83,23 @@ define i16 @test_urem_even(i16 %X) nounwind readnone { ; X86-LABEL: test_urem_even: ; X86: # %bb.0: -; X86-NEXT: movzwl {{[0-9]+}}(%esp), %ecx -; X86-NEXT: movl %ecx, %eax -; X86-NEXT: shrl %eax -; X86-NEXT: imull $18725, %eax, %eax # imm = 0x4925 -; X86-NEXT: shrl $17, %eax -; X86-NEXT: movl %eax, %edx -; X86-NEXT: shll $4, %edx -; X86-NEXT: subl %eax, %edx -; X86-NEXT: subl %eax, %edx +; X86-NEXT: imull $28087, {{[0-9]+}}(%esp), %eax # imm = 0x6DB7 +; X86-NEXT: rorw $1, %ax +; X86-NEXT: movzwl %ax, %ecx ; X86-NEXT: xorl %eax, %eax -; X86-NEXT: cmpw %dx, %cx -; X86-NEXT: setne %al +; X86-NEXT: cmpl $9362, %ecx # imm = 0x2492 +; X86-NEXT: seta %al ; X86-NEXT: # kill: def $ax killed $ax killed $eax ; X86-NEXT: retl ; ; X64-LABEL: test_urem_even: ; X64: # %bb.0: -; X64-NEXT: movzwl %di, %ecx -; X64-NEXT: movl %ecx, %eax -; X64-NEXT: shrl %eax -; X64-NEXT: imull $18725, %eax, %eax # imm = 0x4925 -; X64-NEXT: shrl $17, %eax -; X64-NEXT: movl %eax, %edx -; X64-NEXT: shll $4, %edx -; X64-NEXT: subl %eax, %edx -; X64-NEXT: subl %eax, %edx +; X64-NEXT: imull $28087, %edi, %eax # imm = 0x6DB7 +; X64-NEXT: rorw $1, %ax +; X64-NEXT: movzwl %ax, %ecx ; X64-NEXT: xorl %eax, %eax -; X64-NEXT: cmpw %dx, %cx -; X64-NEXT: setne %al +; X64-NEXT: cmpl $9362, %ecx # imm = 0x2492 +; X64-NEXT: seta %al ; X64-NEXT: # kill: def $ax killed $ax killed $eax ; X64-NEXT: retq %urem = urem i16 %X, 14 @@ -152,27 +112,20 @@ define i32 @test_urem_even_bit30(i32 %X) nounwind readnone { ; X86-LABEL: test_urem_even_bit30: ; X86: # %bb.0: -; X86-NEXT: movl {{[0-9]+}}(%esp), %ecx -; X86-NEXT: movl $-415, %edx # imm = 0xFE61 -; X86-NEXT: movl %ecx, %eax -; X86-NEXT: mull %edx -; X86-NEXT: shrl $30, %edx -; X86-NEXT: imull $1073741928, %edx, %edx # imm = 0x40000068 +; X86-NEXT: imull $-51622203, {{[0-9]+}}(%esp), %ecx # imm = 0xFCEC4EC5 +; X86-NEXT: rorl $3, %ecx ; X86-NEXT: xorl %eax, %eax -; X86-NEXT: cmpl %edx, %ecx -; X86-NEXT: sete %al +; X86-NEXT: cmpl $32, %ecx +; X86-NEXT: setb %al ; X86-NEXT: retl ; ; X64-LABEL: test_urem_even_bit30: ; X64: # %bb.0: -; X64-NEXT: movl %edi, %eax -; X64-NEXT: movl $4294966881, %ecx # imm = 0xFFFFFE61 -; X64-NEXT: imulq %rax, %rcx -; X64-NEXT: shrq $62, %rcx -; X64-NEXT: imull $1073741928, %ecx, %ecx # imm = 0x40000068 +; X64-NEXT: imull $-51622203, %edi, %ecx # imm = 0xFCEC4EC5 +; X64-NEXT: rorl $3, %ecx ; X64-NEXT: xorl %eax, %eax -; X64-NEXT: cmpl %ecx, %edi -; X64-NEXT: sete %al +; X64-NEXT: cmpl $32, %ecx +; X64-NEXT: setb %al ; X64-NEXT: retq %urem = urem i32 %X, 1073741928 %cmp = icmp eq i32 %urem, 0 @@ -184,26 +137,20 @@ define i32 @test_urem_even_bit31(i32 %X) nounwind readnone { ; X86-LABEL: test_urem_even_bit31: ; X86: # %bb.0: -; X86-NEXT: movl {{[0-9]+}}(%esp), %ecx -; X86-NEXT: movl $2147483547, %edx # imm = 0x7FFFFF9B -; X86-NEXT: movl %ecx, %eax -; X86-NEXT: mull %edx -; X86-NEXT: shrl $30, %edx -; X86-NEXT: imull $-2147483546, %edx, %edx # imm = 0x80000066 +; X86-NEXT: imull $-1157956869, {{[0-9]+}}(%esp), %ecx # imm = 0xBAFAFAFB +; X86-NEXT: rorl $1, %ecx ; X86-NEXT: xorl %eax, %eax -; X86-NEXT: cmpl %edx, %ecx -; X86-NEXT: sete %al +; X86-NEXT: cmpl $4, %ecx +; X86-NEXT: setb %al ; X86-NEXT: retl ; ; X64-LABEL: test_urem_even_bit31: ; X64: # %bb.0: -; X64-NEXT: movl %edi, %eax -; X64-NEXT: imulq $2147483547, %rax, %rax # imm = 0x7FFFFF9B -; X64-NEXT: shrq $62, %rax -; X64-NEXT: imull $-2147483546, %eax, %ecx # imm = 0x80000066 +; X64-NEXT: imull $-1157956869, %edi, %ecx # imm = 0xBAFAFAFB +; X64-NEXT: rorl $1, %ecx ; X64-NEXT: xorl %eax, %eax -; X64-NEXT: cmpl %ecx, %edi -; X64-NEXT: sete %al +; X64-NEXT: cmpl $4, %ecx +; X64-NEXT: setb %al ; X64-NEXT: retq %urem = urem i32 %X, 2147483750 %cmp = icmp eq i32 %urem, 0