Index: llvm/trunk/tools/llvm-exegesis/lib/BenchmarkRunner.h =================================================================== --- llvm/trunk/tools/llvm-exegesis/lib/BenchmarkRunner.h +++ llvm/trunk/tools/llvm-exegesis/lib/BenchmarkRunner.h @@ -67,7 +67,7 @@ // Given a snippet, computes which registers the setup code needs to define. std::vector - computeRegsToDef(const std::vector &Snippet) const; + computeRegsToDef(const std::vector &Snippet) const; // Scratch space to run instructions that touch memory. struct ScratchSpace { Index: llvm/trunk/tools/llvm-exegesis/lib/BenchmarkRunner.cpp =================================================================== --- llvm/trunk/tools/llvm-exegesis/lib/BenchmarkRunner.cpp +++ llvm/trunk/tools/llvm-exegesis/lib/BenchmarkRunner.cpp @@ -131,12 +131,12 @@ // TODO: Generate as many configurations as needed here. BenchmarkConfiguration Configuration; Configuration.Info = Prototype.Explanation; - for (InstructionInstance &II : Prototype.Snippet) { - II.randomizeUnsetVariables( + for (InstructionBuilder &IB : Prototype.Snippet) { + IB.randomizeUnsetVariables( Prototype.ScratchSpaceReg ? RATC.getRegister(Prototype.ScratchSpaceReg).aliasedBits() : RATC.emptyRegisters()); - Configuration.Snippet.push_back(II.build()); + Configuration.Snippet.push_back(IB.build()); } if (Prototype.ScratchSpaceReg) Configuration.SnippetSetup.LiveIns.push_back(Prototype.ScratchSpaceReg); @@ -147,27 +147,27 @@ } std::vector BenchmarkRunner::computeRegsToDef( - const std::vector &Snippet) const { + const std::vector &Snippet) const { // Collect all register uses and create an assignment for each of them. // Ignore memory operands which are handled separately. // Loop invariant: DefinedRegs[i] is true iif it has been set at least once // before the current instruction. llvm::BitVector DefinedRegs = RATC.emptyRegisters(); std::vector RegsToDef; - for (const InstructionInstance &II : Snippet) { + for (const InstructionBuilder &IB : Snippet) { // Returns the register that this Operand sets or uses, or 0 if this is not // a register. - const auto GetOpReg = [&II](const Operand &Op) -> unsigned { + const auto GetOpReg = [&IB](const Operand &Op) -> unsigned { if (Op.IsMem) return 0; if (Op.ImplicitReg) return *Op.ImplicitReg; - if (Op.IsExplicit && II.getValueFor(Op).isReg()) - return II.getValueFor(Op).getReg(); + if (Op.IsExplicit && IB.getValueFor(Op).isReg()) + return IB.getValueFor(Op).getReg(); return 0; }; // Collect used registers that have never been def'ed. - for (const Operand &Op : II.Instr.Operands) { + for (const Operand &Op : IB.Instr.Operands) { if (!Op.IsDef) { const unsigned Reg = GetOpReg(Op); if (Reg > 0 && !DefinedRegs.test(Reg)) { @@ -177,7 +177,7 @@ } } // Mark defs as having been def'ed. - for (const Operand &Op : II.Instr.Operands) { + for (const Operand &Op : IB.Instr.Operands) { if (Op.IsDef) { const unsigned Reg = GetOpReg(Op); if (Reg > 0) @@ -209,17 +209,17 @@ return llvm::make_error("empty self aliasing"); } SnippetPrototype Prototype; - InstructionInstance II(Instr); + InstructionBuilder IB(Instr); if (SelfAliasing.hasImplicitAliasing()) { Prototype.Explanation = "implicit Self cycles, picking random values."; } else { Prototype.Explanation = "explicit self cycles, selecting one aliasing Conf."; // This is a self aliasing instruction so defs and uses are from the same - // instance, hence twice II in the following call. - setRandomAliasing(SelfAliasing, II, II); + // instance, hence twice IB in the following call. + setRandomAliasing(SelfAliasing, IB, IB); } - Prototype.Snippet.push_back(std::move(II)); + Prototype.Snippet.push_back(std::move(IB)); return std::move(Prototype); } Index: llvm/trunk/tools/llvm-exegesis/lib/Latency.cpp =================================================================== --- llvm/trunk/tools/llvm-exegesis/lib/Latency.cpp +++ llvm/trunk/tools/llvm-exegesis/lib/Latency.cpp @@ -62,18 +62,18 @@ const AliasingConfigurations Back(OtherInstr, Instr); if (Forward.empty() || Back.empty()) continue; - InstructionInstance ThisII(Instr); - InstructionInstance OtherII(OtherInstr); + InstructionBuilder ThisIB(Instr); + InstructionBuilder OtherIB(OtherInstr); if (!Forward.hasImplicitAliasing()) - setRandomAliasing(Forward, ThisII, OtherII); + setRandomAliasing(Forward, ThisIB, OtherIB); if (!Back.hasImplicitAliasing()) - setRandomAliasing(Back, OtherII, ThisII); + setRandomAliasing(Back, OtherIB, ThisIB); SnippetPrototype Prototype; Prototype.Explanation = llvm::formatv("creating cycle through {0}.", State.getInstrInfo().getName(OtherOpcode)); - Prototype.Snippet.push_back(std::move(ThisII)); - Prototype.Snippet.push_back(std::move(OtherII)); + Prototype.Snippet.push_back(std::move(ThisIB)); + Prototype.Snippet.push_back(std::move(OtherIB)); return std::move(Prototype); } return llvm::make_error( Index: llvm/trunk/tools/llvm-exegesis/lib/MCInstrDescView.h =================================================================== --- llvm/trunk/tools/llvm-exegesis/lib/MCInstrDescView.h +++ llvm/trunk/tools/llvm-exegesis/lib/MCInstrDescView.h @@ -39,7 +39,7 @@ llvm::SmallVector TiedOperands; llvm::MCOperand AssignedValue; // The index of this Variable in Instruction.Variables and its associated - // Value in InstructionInstance.VariableValues. + // Value in InstructionBuilder.VariableValues. unsigned Index = -1; }; @@ -82,14 +82,14 @@ llvm::BitVector UseRegisters; // The union of the aliased use registers. }; -// An instance of an Instruction holding values for each of its Variables. -struct InstructionInstance { - InstructionInstance(const Instruction &Instr); - - InstructionInstance(const InstructionInstance &); - InstructionInstance &operator=(const InstructionInstance &); - InstructionInstance(InstructionInstance &&); - InstructionInstance &operator=(InstructionInstance &&); +// A builder for an Instruction holding values for each of its Variables. +struct InstructionBuilder { + InstructionBuilder(const Instruction &Instr); + + InstructionBuilder(const InstructionBuilder &); + InstructionBuilder &operator=(const InstructionBuilder &); + InstructionBuilder(InstructionBuilder &&); + InstructionBuilder &operator=(InstructionBuilder &&); unsigned getOpcode() const; llvm::MCOperand &getValueFor(const Variable &Var); @@ -102,7 +102,7 @@ // Do not use any of the registers in `ForbiddenRegs`. void randomizeUnsetVariables(const llvm::BitVector &ForbiddenRegs); - // Returns the instance as an llvm::MCInst. The InstructionInstance must be + // Returns the instance as an llvm::MCInst. The InstructionBuilder must be // fully allocated (no invalid variables). llvm::MCInst build() const; @@ -129,7 +129,7 @@ // If the prototype uses the provided scratch memory, the register in which // the pointer to this memory is passed in to the function. unsigned ScratchSpaceReg = 0; - std::vector Snippet; + std::vector Snippet; }; // Represents the assignment of a Register to an Operand. @@ -186,7 +186,7 @@ // Picks a random configuration, then selects a random def and a random use from // it and finally set the selected values in the provided InstructionInstances. void setRandomAliasing(const AliasingConfigurations &AliasingConfigurations, - InstructionInstance &DefII, InstructionInstance &UseII); + InstructionBuilder &DefIB, InstructionBuilder &UseIB); // Writes MCInst to OS. // This is not assembly but the internal LLVM's name for instructions and Index: llvm/trunk/tools/llvm-exegesis/lib/MCInstrDescView.cpp =================================================================== --- llvm/trunk/tools/llvm-exegesis/lib/MCInstrDescView.cpp +++ llvm/trunk/tools/llvm-exegesis/lib/MCInstrDescView.cpp @@ -89,39 +89,39 @@ [](const Operand &Op) { return Op.IsMem; }); } -InstructionInstance::InstructionInstance(const Instruction &Instr) +InstructionBuilder::InstructionBuilder(const Instruction &Instr) : Instr(Instr), VariableValues(Instr.Variables.size()) {} -InstructionInstance::InstructionInstance(InstructionInstance &&) = default; +InstructionBuilder::InstructionBuilder(InstructionBuilder &&) = default; -InstructionInstance &InstructionInstance:: -operator=(InstructionInstance &&) = default; +InstructionBuilder &InstructionBuilder:: +operator=(InstructionBuilder &&) = default; -InstructionInstance::InstructionInstance(const InstructionInstance &) = default; +InstructionBuilder::InstructionBuilder(const InstructionBuilder &) = default; -InstructionInstance &InstructionInstance:: -operator=(const InstructionInstance &) = default; +InstructionBuilder &InstructionBuilder:: +operator=(const InstructionBuilder &) = default; -unsigned InstructionInstance::getOpcode() const { +unsigned InstructionBuilder::getOpcode() const { return Instr.Description->getOpcode(); } -llvm::MCOperand &InstructionInstance::getValueFor(const Variable &Var) { +llvm::MCOperand &InstructionBuilder::getValueFor(const Variable &Var) { return VariableValues[Var.Index]; } const llvm::MCOperand & -InstructionInstance::getValueFor(const Variable &Var) const { +InstructionBuilder::getValueFor(const Variable &Var) const { return VariableValues[Var.Index]; } -llvm::MCOperand &InstructionInstance::getValueFor(const Operand &Op) { +llvm::MCOperand &InstructionBuilder::getValueFor(const Operand &Op) { assert(Op.VariableIndex >= 0); return getValueFor(Instr.Variables[Op.VariableIndex]); } const llvm::MCOperand & -InstructionInstance::getValueFor(const Operand &Op) const { +InstructionBuilder::getValueFor(const Operand &Op) const { assert(Op.VariableIndex >= 0); return getValueFor(Instr.Variables[Op.VariableIndex]); } @@ -131,7 +131,7 @@ llvm::MCOperand &AssignedValue, const llvm::BitVector &ForbiddenRegs); -bool InstructionInstance::hasImmediateVariables() const { +bool InstructionBuilder::hasImmediateVariables() const { return llvm::any_of(Instr.Variables, [this](const Variable &Var) { assert(!Var.TiedOperands.empty()); const unsigned OpIndex = Var.TiedOperands[0]; @@ -141,7 +141,7 @@ }); } -void InstructionInstance::randomizeUnsetVariables( +void InstructionBuilder::randomizeUnsetVariables( const llvm::BitVector &ForbiddenRegs) { for (const Variable &Var : Instr.Variables) { llvm::MCOperand &AssignedValue = getValueFor(Var); @@ -150,7 +150,7 @@ } } -llvm::MCInst InstructionInstance::build() const { +llvm::MCInst InstructionBuilder::build() const { llvm::MCInst Result; Result.setOpcode(Instr.Description->Opcode); for (const auto &Op : Instr.Operands) @@ -261,10 +261,10 @@ } static void setRegisterOperandValue(const RegisterOperandAssignment &ROV, - InstructionInstance &II) { + InstructionBuilder &IB) { assert(ROV.Op); if (ROV.Op->IsExplicit) { - auto &AssignedValue = II.getValueFor(*ROV.Op); + auto &AssignedValue = IB.getValueFor(*ROV.Op); if (AssignedValue.isValid()) { assert(AssignedValue.isReg() && AssignedValue.getReg() == ROV.Reg); return; @@ -285,12 +285,12 @@ } void setRandomAliasing(const AliasingConfigurations &AliasingConfigurations, - InstructionInstance &DefII, InstructionInstance &UseII) { + InstructionBuilder &DefIB, InstructionBuilder &UseIB) { assert(!AliasingConfigurations.empty()); assert(!AliasingConfigurations.hasImplicitAliasing()); const auto &RandomConf = randomElement(AliasingConfigurations.Configurations); - setRegisterOperandValue(randomElement(RandomConf.Defs), DefII); - setRegisterOperandValue(randomElement(RandomConf.Uses), UseII); + setRegisterOperandValue(randomElement(RandomConf.Defs), DefIB); + setRegisterOperandValue(randomElement(RandomConf.Uses), UseIB); } void DumpMCOperand(const llvm::MCRegisterInfo &MCRegisterInfo, Index: llvm/trunk/tools/llvm-exegesis/lib/Target.h =================================================================== --- llvm/trunk/tools/llvm-exegesis/lib/Target.h +++ llvm/trunk/tools/llvm-exegesis/lib/Target.h @@ -48,7 +48,7 @@ } // Fills memory operands with references to the address at [Reg] + Offset. - virtual void fillMemoryOperands(InstructionInstance &II, unsigned Reg, + virtual void fillMemoryOperands(InstructionBuilder &IB, unsigned Reg, unsigned Offset) const { llvm_unreachable( "fillMemoryOperands() requires getScratchMemoryRegister() > 0"); Index: llvm/trunk/tools/llvm-exegesis/lib/Uops.h =================================================================== --- llvm/trunk/tools/llvm-exegesis/lib/Uops.h +++ llvm/trunk/tools/llvm-exegesis/lib/Uops.h @@ -62,7 +62,7 @@ // mov eax, [rdi + 256] void instantiateMemoryOperands(unsigned ScratchSpaceReg, - std::vector &Snippet) const; + std::vector &Snippet) const; }; } // namespace exegesis Index: llvm/trunk/tools/llvm-exegesis/lib/Uops.cpp =================================================================== --- llvm/trunk/tools/llvm-exegesis/lib/Uops.cpp +++ llvm/trunk/tools/llvm-exegesis/lib/Uops.cpp @@ -126,23 +126,23 @@ void UopsBenchmarkRunner::instantiateMemoryOperands( const unsigned ScratchSpaceReg, - std::vector &Snippet) const { + std::vector &Snippet) const { if (ScratchSpaceReg == 0) - return; // no memory operands. + return; // no memory operands. const auto &ET = State.getExegesisTarget(); const unsigned MemStep = ET.getMaxMemoryAccessSize(); const size_t OriginalSnippetSize = Snippet.size(); size_t I = 0; - for (InstructionInstance &II : Snippet) { - ET.fillMemoryOperands(II, ScratchSpaceReg, I * MemStep); + for (InstructionBuilder &IB : Snippet) { + ET.fillMemoryOperands(IB, ScratchSpaceReg, I * MemStep); ++I; } while (Snippet.size() < kMinNumDifferentAddresses) { - InstructionInstance II = Snippet[I % OriginalSnippetSize]; - ET.fillMemoryOperands(II, ScratchSpaceReg, I * MemStep); + InstructionBuilder IB = Snippet[I % OriginalSnippetSize]; + ET.fillMemoryOperands(IB, ScratchSpaceReg, I * MemStep); ++I; - Snippet.push_back(std::move(II)); + Snippet.push_back(std::move(IB)); } assert(I * MemStep < ScratchSpace::kSize && "not enough scratch space"); } @@ -176,16 +176,16 @@ } const AliasingConfigurations SelfAliasing(Instr, Instr); - InstructionInstance II(Instr); + InstructionBuilder IB(Instr); if (SelfAliasing.empty()) { Prototype.Explanation = "instruction is parallel, repeating a random one."; - Prototype.Snippet.push_back(std::move(II)); + Prototype.Snippet.push_back(std::move(IB)); instantiateMemoryOperands(Prototype.ScratchSpaceReg, Prototype.Snippet); return std::move(Prototype); } if (SelfAliasing.hasImplicitAliasing()) { Prototype.Explanation = "instruction is serial, repeating a random one."; - Prototype.Snippet.push_back(std::move(II)); + Prototype.Snippet.push_back(std::move(IB)); instantiateMemoryOperands(Prototype.ScratchSpaceReg, Prototype.Snippet); return std::move(Prototype); } @@ -205,9 +205,9 @@ for (const llvm::MCPhysReg Reg : Op.Tracker->sourceBits().set_bits()) { if (ScratchSpaceAliasedRegs && ScratchSpaceAliasedRegs->test(Reg)) continue; // Do not use the scratch memory address register. - InstructionInstance TmpII = II; - TmpII.getValueFor(*Var) = llvm::MCOperand::createReg(Reg); - Prototype.Snippet.push_back(std::move(TmpII)); + InstructionBuilder TmpIB = IB; + TmpIB.getValueFor(*Var) = llvm::MCOperand::createReg(Reg); + Prototype.Snippet.push_back(std::move(TmpIB)); } instantiateMemoryOperands(Prototype.ScratchSpaceReg, Prototype.Snippet); return std::move(Prototype); @@ -224,7 +224,7 @@ assert(PossibleRegisters.any() && "No register left to choose from"); const auto RandomReg = randomBit(PossibleRegisters); Defs.set(RandomReg); - II.getValueFor(Op) = llvm::MCOperand::createReg(RandomReg); + IB.getValueFor(Op) = llvm::MCOperand::createReg(RandomReg); } } // And pick random use values that are not reserved and don't alias with defs. @@ -239,12 +239,12 @@ remove(PossibleRegisters, DefAliases); assert(PossibleRegisters.any() && "No register left to choose from"); const auto RandomReg = randomBit(PossibleRegisters); - II.getValueFor(Op) = llvm::MCOperand::createReg(RandomReg); + IB.getValueFor(Op) = llvm::MCOperand::createReg(RandomReg); } } Prototype.Explanation = "instruction has no tied variables picking Uses different from defs"; - Prototype.Snippet.push_back(std::move(II)); + Prototype.Snippet.push_back(std::move(IB)); instantiateMemoryOperands(Prototype.ScratchSpaceReg, Prototype.Snippet); return std::move(Prototype); } Index: llvm/trunk/tools/llvm-exegesis/lib/X86/Target.cpp =================================================================== --- llvm/trunk/tools/llvm-exegesis/lib/X86/Target.cpp +++ llvm/trunk/tools/llvm-exegesis/lib/X86/Target.cpp @@ -120,32 +120,32 @@ unsigned getMaxMemoryAccessSize() const override { return 64; } - void fillMemoryOperands(InstructionInstance &II, unsigned Reg, + void fillMemoryOperands(InstructionBuilder &IB, unsigned Reg, unsigned Offset) const override { // FIXME: For instructions that read AND write to memory, we use the same // value for input and output. - for (size_t I = 0, E = II.Instr.Operands.size(); I < E; ++I) { - const Operand *Op = &II.Instr.Operands[I]; + for (size_t I = 0, E = IB.Instr.Operands.size(); I < E; ++I) { + const Operand *Op = &IB.Instr.Operands[I]; if (Op->IsExplicit && Op->IsMem) { // Case 1: 5-op memory. assert((I + 5 <= E) && "x86 memory references are always 5 ops"); - II.getValueFor(*Op) = llvm::MCOperand::createReg(Reg); // BaseReg - Op = &II.Instr.Operands[++I]; + IB.getValueFor(*Op) = llvm::MCOperand::createReg(Reg); // BaseReg + Op = &IB.Instr.Operands[++I]; assert(Op->IsMem); assert(Op->IsExplicit); - II.getValueFor(*Op) = llvm::MCOperand::createImm(1); // ScaleAmt - Op = &II.Instr.Operands[++I]; + IB.getValueFor(*Op) = llvm::MCOperand::createImm(1); // ScaleAmt + Op = &IB.Instr.Operands[++I]; assert(Op->IsMem); assert(Op->IsExplicit); - II.getValueFor(*Op) = llvm::MCOperand::createReg(0); // IndexReg - Op = &II.Instr.Operands[++I]; + IB.getValueFor(*Op) = llvm::MCOperand::createReg(0); // IndexReg + Op = &IB.Instr.Operands[++I]; assert(Op->IsMem); assert(Op->IsExplicit); - II.getValueFor(*Op) = llvm::MCOperand::createImm(Offset); // Disp - Op = &II.Instr.Operands[++I]; + IB.getValueFor(*Op) = llvm::MCOperand::createImm(Offset); // Disp + Op = &IB.Instr.Operands[++I]; assert(Op->IsMem); assert(Op->IsExplicit); - II.getValueFor(*Op) = llvm::MCOperand::createReg(0); // Segment + IB.getValueFor(*Op) = llvm::MCOperand::createReg(0); // Segment // Case2: segment:index addressing. We assume that ES is 0. } } Index: llvm/trunk/unittests/tools/llvm-exegesis/X86/SnippetGeneratorTest.cpp =================================================================== --- llvm/trunk/unittests/tools/llvm-exegesis/X86/SnippetGeneratorTest.cpp +++ llvm/trunk/unittests/tools/llvm-exegesis/X86/SnippetGeneratorTest.cpp @@ -88,10 +88,10 @@ const SnippetPrototype Proto = checkAndGetConfigurations(Opcode); EXPECT_THAT(Proto.Explanation, HasSubstr("implicit")); ASSERT_THAT(Proto.Snippet, SizeIs(1)); - const InstructionInstance &II = Proto.Snippet[0]; - EXPECT_THAT(II.getOpcode(), Opcode); - ASSERT_THAT(II.VariableValues, SizeIs(1)); // Imm. - EXPECT_THAT(II.VariableValues[0], IsInvalid()) << "Immediate is not set"; + const InstructionBuilder &IB = Proto.Snippet[0]; + EXPECT_THAT(IB.getOpcode(), Opcode); + ASSERT_THAT(IB.VariableValues, SizeIs(1)); // Imm. + EXPECT_THAT(IB.VariableValues[0], IsInvalid()) << "Immediate is not set"; } TEST_F(LatencySnippetGeneratorTest, ExplicitSelfDependency) { @@ -106,11 +106,11 @@ const SnippetPrototype Proto = checkAndGetConfigurations(Opcode); EXPECT_THAT(Proto.Explanation, HasSubstr("explicit")); ASSERT_THAT(Proto.Snippet, SizeIs(1)); - const InstructionInstance &II = Proto.Snippet[0]; - EXPECT_THAT(II.getOpcode(), Opcode); - ASSERT_THAT(II.VariableValues, SizeIs(2)); - EXPECT_THAT(II.VariableValues[0], IsReg()) << "Operand 0 and 1"; - EXPECT_THAT(II.VariableValues[1], IsInvalid()) << "Operand 2 is not set"; + const InstructionBuilder &IB = Proto.Snippet[0]; + EXPECT_THAT(IB.getOpcode(), Opcode); + ASSERT_THAT(IB.VariableValues, SizeIs(2)); + EXPECT_THAT(IB.VariableValues[0], IsReg()) << "Operand 0 and 1"; + EXPECT_THAT(IB.VariableValues[1], IsInvalid()) << "Operand 2 is not set"; } TEST_F(LatencySnippetGeneratorTest, DependencyThroughOtherOpcode) { @@ -123,10 +123,10 @@ const SnippetPrototype Proto = checkAndGetConfigurations(Opcode); EXPECT_THAT(Proto.Explanation, HasSubstr("cycle through")); ASSERT_THAT(Proto.Snippet, SizeIs(2)); - const InstructionInstance &II = Proto.Snippet[0]; - EXPECT_THAT(II.getOpcode(), Opcode); - ASSERT_THAT(II.VariableValues, SizeIs(2)); - EXPECT_THAT(II.VariableValues, AnyOf(ElementsAre(IsReg(), IsInvalid()), + const InstructionBuilder &IB = Proto.Snippet[0]; + EXPECT_THAT(IB.getOpcode(), Opcode); + ASSERT_THAT(IB.VariableValues, SizeIs(2)); + EXPECT_THAT(IB.VariableValues, AnyOf(ElementsAre(IsReg(), IsInvalid()), ElementsAre(IsInvalid(), IsReg()))); EXPECT_THAT(Proto.Snippet[1].getOpcode(), Not(Opcode)); // TODO: check that the two instructions alias each other. @@ -137,9 +137,9 @@ const SnippetPrototype Proto = checkAndGetConfigurations(Opcode); EXPECT_THAT(Proto.Explanation, HasSubstr("cycle through")); ASSERT_THAT(Proto.Snippet, SizeIs(2)); - const InstructionInstance &II = Proto.Snippet[0]; - EXPECT_THAT(II.getOpcode(), Opcode); - ASSERT_THAT(II.VariableValues, SizeIs(0)); + const InstructionBuilder &IB = Proto.Snippet[0]; + EXPECT_THAT(IB.getOpcode(), Opcode); + ASSERT_THAT(IB.VariableValues, SizeIs(0)); } TEST_F(UopsSnippetGeneratorTest, ParallelInstruction) { @@ -152,11 +152,11 @@ const SnippetPrototype Proto = checkAndGetConfigurations(Opcode); EXPECT_THAT(Proto.Explanation, HasSubstr("parallel")); ASSERT_THAT(Proto.Snippet, SizeIs(1)); - const InstructionInstance &II = Proto.Snippet[0]; - EXPECT_THAT(II.getOpcode(), Opcode); - ASSERT_THAT(II.VariableValues, SizeIs(2)); - EXPECT_THAT(II.VariableValues[0], IsInvalid()); - EXPECT_THAT(II.VariableValues[1], IsInvalid()); + const InstructionBuilder &IB = Proto.Snippet[0]; + EXPECT_THAT(IB.getOpcode(), Opcode); + ASSERT_THAT(IB.VariableValues, SizeIs(2)); + EXPECT_THAT(IB.VariableValues[0], IsInvalid()); + EXPECT_THAT(IB.VariableValues[1], IsInvalid()); } TEST_F(UopsSnippetGeneratorTest, SerialInstruction) { @@ -169,9 +169,9 @@ const SnippetPrototype Proto = checkAndGetConfigurations(Opcode); EXPECT_THAT(Proto.Explanation, HasSubstr("serial")); ASSERT_THAT(Proto.Snippet, SizeIs(1)); - const InstructionInstance &II = Proto.Snippet[0]; - EXPECT_THAT(II.getOpcode(), Opcode); - ASSERT_THAT(II.VariableValues, SizeIs(0)); + const InstructionBuilder &IB = Proto.Snippet[0]; + EXPECT_THAT(IB.getOpcode(), Opcode); + ASSERT_THAT(IB.VariableValues, SizeIs(0)); } TEST_F(UopsSnippetGeneratorTest, StaticRenaming) { @@ -188,9 +188,9 @@ constexpr const unsigned kInstructionCount = 15; ASSERT_THAT(Proto.Snippet, SizeIs(kInstructionCount)); std::unordered_set AllDefRegisters; - for (const auto &II : Proto.Snippet) { - ASSERT_THAT(II.VariableValues, SizeIs(2)); - AllDefRegisters.insert(II.VariableValues[0].getReg()); + for (const auto &IB : Proto.Snippet) { + ASSERT_THAT(IB.VariableValues, SizeIs(2)); + AllDefRegisters.insert(IB.VariableValues[0].getReg()); } EXPECT_THAT(AllDefRegisters, SizeIs(kInstructionCount)) << "Each instruction writes to a different register"; @@ -209,14 +209,14 @@ const SnippetPrototype Proto = checkAndGetConfigurations(Opcode); EXPECT_THAT(Proto.Explanation, HasSubstr("no tied variables")); ASSERT_THAT(Proto.Snippet, SizeIs(1)); - const InstructionInstance &II = Proto.Snippet[0]; - EXPECT_THAT(II.getOpcode(), Opcode); - ASSERT_THAT(II.VariableValues, SizeIs(4)); - EXPECT_THAT(II.VariableValues[0].getReg(), Not(II.VariableValues[1].getReg())) + const InstructionBuilder &IB = Proto.Snippet[0]; + EXPECT_THAT(IB.getOpcode(), Opcode); + ASSERT_THAT(IB.VariableValues, SizeIs(4)); + EXPECT_THAT(IB.VariableValues[0].getReg(), Not(IB.VariableValues[1].getReg())) << "Def is different from first Use"; - EXPECT_THAT(II.VariableValues[0].getReg(), Not(II.VariableValues[2].getReg())) + EXPECT_THAT(IB.VariableValues[0].getReg(), Not(IB.VariableValues[2].getReg())) << "Def is different from second Use"; - EXPECT_THAT(II.VariableValues[3], IsInvalid()); + EXPECT_THAT(IB.VariableValues[3], IsInvalid()); } TEST_F(UopsSnippetGeneratorTest, MemoryUse) { @@ -226,13 +226,13 @@ EXPECT_THAT(Proto.Explanation, HasSubstr("no tied variables")); ASSERT_THAT(Proto.Snippet, SizeIs(UopsBenchmarkRunner::kMinNumDifferentAddresses)); - const InstructionInstance &II = Proto.Snippet[0]; - EXPECT_THAT(II.getOpcode(), Opcode); - ASSERT_THAT(II.VariableValues, SizeIs(6)); - EXPECT_EQ(II.VariableValues[2].getImm(), 1); - EXPECT_EQ(II.VariableValues[3].getReg(), 0u); - EXPECT_EQ(II.VariableValues[4].getImm(), 0); - EXPECT_EQ(II.VariableValues[5].getReg(), 0u); + const InstructionBuilder &IB = Proto.Snippet[0]; + EXPECT_THAT(IB.getOpcode(), Opcode); + ASSERT_THAT(IB.VariableValues, SizeIs(6)); + EXPECT_EQ(IB.VariableValues[2].getImm(), 1); + EXPECT_EQ(IB.VariableValues[3].getReg(), 0u); + EXPECT_EQ(IB.VariableValues[4].getImm(), 0); + EXPECT_EQ(IB.VariableValues[5].getReg(), 0u); } TEST_F(UopsSnippetGeneratorTest, MemoryUse_Movsb) { @@ -274,11 +274,11 @@ // explicit use 1 : reg RegClass=GR16 | TIED_TO:0 // explicit use 2 : imm // implicit def : EFLAGS - InstructionInstance II(Runner.createInstruction(llvm::X86::ADD16ri)); - II.getValueFor(II.Instr.Variables[0]) = + InstructionBuilder IB(Runner.createInstruction(llvm::X86::ADD16ri)); + IB.getValueFor(IB.Instr.Variables[0]) = llvm::MCOperand::createReg(llvm::X86::AX); - std::vector Snippet; - Snippet.push_back(std::move(II)); + std::vector Snippet; + Snippet.push_back(std::move(IB)); const auto RegsToDef = Runner.computeRegsToDef(Snippet); EXPECT_THAT(RegsToDef, UnorderedElementsAre(llvm::X86::AX)); } @@ -288,16 +288,16 @@ // mov64ri rax, 42 // add64rr rax, rax, rbx // -> only rbx needs defining. - std::vector Snippet; + std::vector Snippet; { - InstructionInstance Mov(Runner.createInstruction(llvm::X86::MOV64ri)); + InstructionBuilder Mov(Runner.createInstruction(llvm::X86::MOV64ri)); Mov.getValueFor(Mov.Instr.Variables[0]) = llvm::MCOperand::createReg(llvm::X86::RAX); Mov.getValueFor(Mov.Instr.Variables[1]) = llvm::MCOperand::createImm(42); Snippet.push_back(std::move(Mov)); } { - InstructionInstance Add(Runner.createInstruction(llvm::X86::ADD64rr)); + InstructionBuilder Add(Runner.createInstruction(llvm::X86::ADD64rr)); Add.getValueFor(Add.Instr.Variables[0]) = llvm::MCOperand::createReg(llvm::X86::RAX); Add.getValueFor(Add.Instr.Variables[1]) =