Index: llvm/trunk/lib/Target/X86/X86InstrInfo.td =================================================================== --- llvm/trunk/lib/Target/X86/X86InstrInfo.td +++ llvm/trunk/lib/Target/X86/X86InstrInfo.td @@ -2061,7 +2061,7 @@ } -let SchedRW = [WriteALU], hasSideEffects = 0 in { +let SchedRW = [WriteCMPXCHG], hasSideEffects = 0 in { let Defs = [AL, EFLAGS], Uses = [AL] in def CMPXCHG8rr : I<0xB0, MRMDestReg, (outs GR8:$dst), (ins GR8:$src), "cmpxchg{b}\t{$src, $dst|$dst, $src}", []>, TB, @@ -2080,7 +2080,7 @@ NotMemoryFoldable; } // SchedRW, hasSideEffects -let SchedRW = [WriteALULd, WriteRMW], mayLoad = 1, mayStore = 1, +let SchedRW = [WriteCMPXCHGRMW], mayLoad = 1, mayStore = 1, hasSideEffects = 0 in { let Defs = [AL, EFLAGS], Uses = [AL] in def CMPXCHG8rm : I<0xB0, MRMDestMem, (outs), (ins i8mem:$dst, GR8:$src), Index: llvm/trunk/lib/Target/X86/X86SchedBroadwell.td =================================================================== --- llvm/trunk/lib/Target/X86/X86SchedBroadwell.td +++ llvm/trunk/lib/Target/X86/X86SchedBroadwell.td @@ -119,6 +119,8 @@ defm : BWWriteResPair; defm : BWWriteResPair; +defm : X86WriteRes; +defm : X86WriteRes; defm : X86WriteRes; defm : X86WriteRes; defm : X86WriteRes; @@ -939,13 +941,6 @@ } def: InstRW<[BWWriteResGroup55], (instrs XSETBV)>; -def BWWriteResGroup56 : SchedWriteRes<[BWPort06,BWPort0156]> { - let Latency = 5; - let NumMicroOps = 5; - let ResourceCycles = [2,3]; -} -def: InstRW<[BWWriteResGroup56], (instregex "CMPXCHG(8|16|32|64)rr")>; - def BWWriteResGroup57 : SchedWriteRes<[BWPort4,BWPort237,BWPort0156]> { let Latency = 5; let NumMicroOps = 6; @@ -1214,8 +1209,7 @@ let ResourceCycles = [1,1,1,2,1]; } def : SchedAlias; -def: InstRW<[BWWriteResGroup100], (instregex "CMPXCHG(8|16|32|64)rm", - "ROL(8|16|32|64)mCL", +def: InstRW<[BWWriteResGroup100], (instregex "ROL(8|16|32|64)mCL", "SAR(8|16|32|64)mCL", "SHL(8|16|32|64)mCL", "SHR(8|16|32|64)mCL")>; Index: llvm/trunk/lib/Target/X86/X86SchedHaswell.td =================================================================== --- llvm/trunk/lib/Target/X86/X86SchedHaswell.td +++ llvm/trunk/lib/Target/X86/X86SchedHaswell.td @@ -126,6 +126,8 @@ defm : X86WriteRes; defm : X86WriteRes; +defm : X86WriteRes; +defm : X86WriteRes; defm : X86WriteRes; def : WriteRes { let Latency = 3; } @@ -1349,8 +1351,7 @@ let NumMicroOps = 6; let ResourceCycles = [1,1,1,2,1]; } -def: InstRW<[HWWriteResGroup69], (instregex "CMPXCHG(8|16|32|64)rm", - "ROL(8|16|32|64)mCL", +def: InstRW<[HWWriteResGroup69], (instregex "ROL(8|16|32|64)mCL", "SAR(8|16|32|64)mCL", "SHL(8|16|32|64)mCL", "SHR(8|16|32|64)mCL")>; @@ -1578,13 +1579,6 @@ } def: InstRW<[HWWriteResGroup100], (instrs XSETBV)>; -def HWWriteResGroup101 : SchedWriteRes<[HWPort06,HWPort0156]> { - let Latency = 5; - let NumMicroOps = 5; - let ResourceCycles = [2,3]; -} -def: InstRW<[HWWriteResGroup101], (instregex "CMPXCHG(8|16|32|64)rr")>; - def HWWriteResGroup102 : SchedWriteRes<[HWPort1,HWPort5]> { let Latency = 6; let NumMicroOps = 2; Index: llvm/trunk/lib/Target/X86/X86SchedSandyBridge.td =================================================================== --- llvm/trunk/lib/Target/X86/X86SchedSandyBridge.td +++ llvm/trunk/lib/Target/X86/X86SchedSandyBridge.td @@ -114,7 +114,9 @@ defm : X86WriteRes; defm : X86WriteRes; -defm : X86WriteRes; +defm : X86WriteRes; +defm : X86WriteRes; +defm : X86WriteRes; defm : SBWriteResPair; defm : SBWriteResPair; @@ -770,13 +772,6 @@ } def: InstRW<[SBWriteResGroup41], (instrs FNINIT)>; -def SBWriteResGroup42 : SchedWriteRes<[SBPort05,SBPort015]> { - let Latency = 5; - let NumMicroOps = 4; - let ResourceCycles = [1,3]; -} -def: InstRW<[SBWriteResGroup42], (instregex "CMPXCHG(8|16|32|64)rr")>; - def SBWriteResGroup43 : SchedWriteRes<[SBPort4,SBPort23,SBPort05]> { let Latency = 3; let NumMicroOps = 4; @@ -953,12 +948,12 @@ } def: InstRW<[SBWriteResGroup77], (instregex "(V?)(U?)COMI(SD|SS)rm")>; -def SBWriteResGroup81 : SchedWriteRes<[SBPort23,SBPort015]> { - let Latency = 8; - let NumMicroOps = 4; - let ResourceCycles = [1,3]; +def SBWriteResGroup81 : SchedWriteRes<[SBPort4, SBPort23, SBPort015]> { + let Latency = 6; + let NumMicroOps = 3; + let ResourceCycles = [1, 2, 1]; } -def: InstRW<[SBWriteResGroup81], (instregex "CMPXCHG(8|16|32|64)rm")>; +def: InstRW<[SBWriteResGroup81], (instregex "CMPXCHG(8|16)B")>; def SBWriteResGroup83 : SchedWriteRes<[SBPort23,SBPort015]> { let Latency = 8; Index: llvm/trunk/lib/Target/X86/X86SchedSkylakeClient.td =================================================================== --- llvm/trunk/lib/Target/X86/X86SchedSkylakeClient.td +++ llvm/trunk/lib/Target/X86/X86SchedSkylakeClient.td @@ -112,6 +112,8 @@ defm : X86WriteRes; defm : X86WriteRes; +defm : X86WriteRes; +defm : X86WriteRes; defm : X86WriteRes; defm : SKLWriteResPair; @@ -965,13 +967,6 @@ } def: InstRW<[SKLWriteResGroup63], (instrs XSETBV)>; -def SKLWriteResGroup64 : SchedWriteRes<[SKLPort06,SKLPort0156]> { - let Latency = 5; - let NumMicroOps = 5; - let ResourceCycles = [2,3]; -} -def: InstRW<[SKLWriteResGroup64], (instregex "CMPXCHG(8|16|32|64)rr")>; - def SKLWriteResGroup65 : SchedWriteRes<[SKLPort4,SKLPort237,SKLPort0156]> { let Latency = 5; let NumMicroOps = 6; @@ -1311,7 +1306,6 @@ let ResourceCycles = [1,1,1,2,1]; } def: SchedAlias; -def: InstRW<[SKLWriteResGroup119], (instregex "CMPXCHG(8|16|32|64)rm")>; def SKLWriteResGroup120 : SchedWriteRes<[SKLPort0,SKLPort23]> { let Latency = 9; Index: llvm/trunk/lib/Target/X86/X86SchedSkylakeServer.td =================================================================== --- llvm/trunk/lib/Target/X86/X86SchedSkylakeServer.td +++ llvm/trunk/lib/Target/X86/X86SchedSkylakeServer.td @@ -112,6 +112,8 @@ defm : X86WriteRes; defm : X86WriteRes; +defm : X86WriteRes; +defm : X86WriteRes; defm : X86WriteRes; defm : SKXWriteResPair; @@ -1126,13 +1128,6 @@ } def: InstRW<[SKXWriteResGroup67], (instrs XSETBV)>; -def SKXWriteResGroup68 : SchedWriteRes<[SKXPort06,SKXPort0156]> { - let Latency = 5; - let NumMicroOps = 5; - let ResourceCycles = [2,3]; -} -def: InstRW<[SKXWriteResGroup68], (instregex "CMPXCHG(8|16|32|64)rr")>; - def SKXWriteResGroup69 : SchedWriteRes<[SKXPort4,SKXPort237,SKXPort0156]> { let Latency = 5; let NumMicroOps = 6; @@ -1664,7 +1659,6 @@ let ResourceCycles = [1,1,1,2,1]; } def: SchedAlias; -def: InstRW<[SKXWriteResGroup130], (instregex "CMPXCHG(8|16|32|64)rm")>; def SKXWriteResGroup131 : SchedWriteRes<[SKXPort0,SKXPort4,SKXPort5,SKXPort237,SKXPort0156]> { let Latency = 8; Index: llvm/trunk/lib/Target/X86/X86Schedule.td =================================================================== --- llvm/trunk/lib/Target/X86/X86Schedule.td +++ llvm/trunk/lib/Target/X86/X86Schedule.td @@ -120,7 +120,9 @@ def WriteBSWAP32 : SchedWrite; // Byte Order (Endianness) 32-bit Swap. def WriteBSWAP64 : SchedWrite; // Byte Order (Endianness) 64-bit Swap. -def WriteXCHG : SchedWrite; // Compare+Exchange - TODO RMW support. +defm WriteCMPXCHG : X86SchedWritePair; // Compare and set, compare and swap. +def WriteCMPXCHGRMW : SchedWrite; // Compare and set, compare and swap. +def WriteXCHG : SchedWrite; // Compare+Exchange - TODO RMW support. // Integer division. defm WriteDiv8 : X86SchedWritePair; Index: llvm/trunk/lib/Target/X86/X86ScheduleAtom.td =================================================================== --- llvm/trunk/lib/Target/X86/X86ScheduleAtom.td +++ llvm/trunk/lib/Target/X86/X86ScheduleAtom.td @@ -84,6 +84,8 @@ defm : X86WriteRes; defm : X86WriteRes; defm : X86WriteRes; +defm : AtomWriteResPair; +defm : X86WriteRes; defm : AtomWriteResPair; defm : AtomWriteResPair; @@ -676,12 +678,6 @@ } def : InstRW<[AtomWrite01_14], (instrs CMPXCHG16rm, CMPXCHG32rm, CMPXCHG64rm)>; -def AtomWrite01_15 : SchedWriteRes<[AtomPort01]> { - let Latency = 15; - let ResourceCycles = [15]; -} -def : InstRW<[AtomWrite01_15], (instrs CMPXCHG16rr, CMPXCHG32rr, CMPXCHG64rr)>; - def AtomWrite01_17 : SchedWriteRes<[AtomPort01]> { let Latency = 17; let ResourceCycles = [17]; Index: llvm/trunk/lib/Target/X86/X86ScheduleBtVer2.td =================================================================== --- llvm/trunk/lib/Target/X86/X86ScheduleBtVer2.td +++ llvm/trunk/lib/Target/X86/X86ScheduleBtVer2.td @@ -170,6 +170,8 @@ defm : X86WriteRes; defm : X86WriteRes; +defm : X86WriteRes; +defm : X86WriteRes; defm : X86WriteRes; defm : JWriteResIntPair; Index: llvm/trunk/lib/Target/X86/X86ScheduleSLM.td =================================================================== --- llvm/trunk/lib/Target/X86/X86ScheduleSLM.td +++ llvm/trunk/lib/Target/X86/X86ScheduleSLM.td @@ -100,7 +100,9 @@ defm : X86WriteRes; defm : X86WriteRes; -defm : X86WriteRes; +defm : X86WriteRes; +defm : X86WriteRes; +defm : X86WriteRes; defm : SLMWriteResPair; Index: llvm/trunk/lib/Target/X86/X86ScheduleZnver1.td =================================================================== --- llvm/trunk/lib/Target/X86/X86ScheduleZnver1.td +++ llvm/trunk/lib/Target/X86/X86ScheduleZnver1.td @@ -182,6 +182,8 @@ defm : X86WriteRes; defm : X86WriteRes; +defm : X86WriteRes; +defm : X86WriteRes; defm : X86WriteRes; defm : ZnWriteResPair; @@ -743,13 +745,6 @@ def : InstRW<[WriteMicrocoded], (instregex "SH(R|L)D(16|32|64)mrCL")>; //-- Misc instructions --// -// CMPXCHG. -def ZnWriteCMPXCHG : SchedWriteRes<[ZnAGU, ZnALU]> { - let Latency = 8; - let NumMicroOps = 5; -} -def : InstRW<[ZnWriteCMPXCHG], (instregex "CMPXCHG(8|16|32|64)rm")>; - // CMPXCHG8B. def ZnWriteCMPXCHG8B : SchedWriteRes<[ZnAGU, ZnALU]> { let NumMicroOps = 18; Index: llvm/trunk/test/CodeGen/X86/schedule-x86_64.ll =================================================================== --- llvm/trunk/test/CodeGen/X86/schedule-x86_64.ll +++ llvm/trunk/test/CodeGen/X86/schedule-x86_64.ll @@ -4307,7 +4307,7 @@ ; GENERIC: # %bb.0: ; GENERIC-NEXT: #APP ; GENERIC-NEXT: cmpxchgb %dil, %sil # sched: [5:1.33] -; GENERIC-NEXT: cmpxchgb %dil, (%rdx) # sched: [8:1.00] +; GENERIC-NEXT: cmpxchgb %dil, (%rdx) # sched: [8:2.00] ; GENERIC-NEXT: #NO_APP ; GENERIC-NEXT: retq # sched: [1:1.00] ; @@ -4331,7 +4331,7 @@ ; SANDY: # %bb.0: ; SANDY-NEXT: #APP ; SANDY-NEXT: cmpxchgb %dil, %sil # sched: [5:1.33] -; SANDY-NEXT: cmpxchgb %dil, (%rdx) # sched: [8:1.00] +; SANDY-NEXT: cmpxchgb %dil, (%rdx) # sched: [8:2.00] ; SANDY-NEXT: #NO_APP ; SANDY-NEXT: retq # sched: [1:1.00] ; @@ -4390,7 +4390,7 @@ ; GENERIC: # %bb.0: ; GENERIC-NEXT: #APP ; GENERIC-NEXT: cmpxchgw %di, %si # sched: [5:1.33] -; GENERIC-NEXT: cmpxchgw %di, (%rdx) # sched: [8:1.00] +; GENERIC-NEXT: cmpxchgw %di, (%rdx) # sched: [8:2.00] ; GENERIC-NEXT: #NO_APP ; GENERIC-NEXT: retq # sched: [1:1.00] ; @@ -4414,7 +4414,7 @@ ; SANDY: # %bb.0: ; SANDY-NEXT: #APP ; SANDY-NEXT: cmpxchgw %di, %si # sched: [5:1.33] -; SANDY-NEXT: cmpxchgw %di, (%rdx) # sched: [8:1.00] +; SANDY-NEXT: cmpxchgw %di, (%rdx) # sched: [8:2.00] ; SANDY-NEXT: #NO_APP ; SANDY-NEXT: retq # sched: [1:1.00] ; @@ -4473,7 +4473,7 @@ ; GENERIC: # %bb.0: ; GENERIC-NEXT: #APP ; GENERIC-NEXT: cmpxchgl %edi, %esi # sched: [5:1.33] -; GENERIC-NEXT: cmpxchgl %edi, (%rdx) # sched: [8:1.00] +; GENERIC-NEXT: cmpxchgl %edi, (%rdx) # sched: [8:2.00] ; GENERIC-NEXT: #NO_APP ; GENERIC-NEXT: retq # sched: [1:1.00] ; @@ -4497,7 +4497,7 @@ ; SANDY: # %bb.0: ; SANDY-NEXT: #APP ; SANDY-NEXT: cmpxchgl %edi, %esi # sched: [5:1.33] -; SANDY-NEXT: cmpxchgl %edi, (%rdx) # sched: [8:1.00] +; SANDY-NEXT: cmpxchgl %edi, (%rdx) # sched: [8:2.00] ; SANDY-NEXT: #NO_APP ; SANDY-NEXT: retq # sched: [1:1.00] ; @@ -4556,7 +4556,7 @@ ; GENERIC: # %bb.0: ; GENERIC-NEXT: #APP ; GENERIC-NEXT: cmpxchgq %rdi, %rsi # sched: [5:1.33] -; GENERIC-NEXT: cmpxchgq %rdi, (%rdx) # sched: [8:1.00] +; GENERIC-NEXT: cmpxchgq %rdi, (%rdx) # sched: [8:2.00] ; GENERIC-NEXT: #NO_APP ; GENERIC-NEXT: retq # sched: [1:1.00] ; @@ -4580,7 +4580,7 @@ ; SANDY: # %bb.0: ; SANDY-NEXT: #APP ; SANDY-NEXT: cmpxchgq %rdi, %rsi # sched: [5:1.33] -; SANDY-NEXT: cmpxchgq %rdi, (%rdx) # sched: [8:1.00] +; SANDY-NEXT: cmpxchgq %rdi, (%rdx) # sched: [8:2.00] ; SANDY-NEXT: #NO_APP ; SANDY-NEXT: retq # sched: [1:1.00] ; Index: llvm/trunk/test/tools/llvm-mca/X86/Generic/resources-x86_64.s =================================================================== --- llvm/trunk/test/tools/llvm-mca/X86/Generic/resources-x86_64.s +++ llvm/trunk/test/tools/llvm-mca/X86/Generic/resources-x86_64.s @@ -1057,13 +1057,13 @@ # CHECK-NEXT: 5 8 1.00 U cmpsl %es:(%rdi), (%rsi) # CHECK-NEXT: 5 8 1.00 U cmpsq %es:(%rdi), (%rsi) # CHECK-NEXT: 4 5 1.33 cmpxchgb %cl, %bl -# CHECK-NEXT: 4 8 1.00 * * cmpxchgb %cl, (%rbx) +# CHECK-NEXT: 6 8 2.00 * * cmpxchgb %cl, (%rbx) # CHECK-NEXT: 4 5 1.33 cmpxchgw %cx, %bx -# CHECK-NEXT: 4 8 1.00 * * cmpxchgw %cx, (%rbx) +# CHECK-NEXT: 6 8 2.00 * * cmpxchgw %cx, (%rbx) # CHECK-NEXT: 4 5 1.33 cmpxchgl %ecx, %ebx -# CHECK-NEXT: 4 8 1.00 * * cmpxchgl %ecx, (%rbx) +# CHECK-NEXT: 6 8 2.00 * * cmpxchgl %ecx, (%rbx) # CHECK-NEXT: 4 5 1.33 cmpxchgq %rcx, %rbx -# CHECK-NEXT: 4 8 1.00 * * cmpxchgq %rcx, (%rbx) +# CHECK-NEXT: 6 8 2.00 * * cmpxchgq %rcx, (%rbx) # CHECK-NEXT: 1 100 0.33 U cpuid # CHECK-NEXT: 1 1 0.33 decb %dil # CHECK-NEXT: 3 7 1.00 * * decb (%rax) @@ -1620,7 +1620,7 @@ # CHECK: Resource pressure per iteration: # CHECK-NEXT: [0] [1] [2] [3] [4] [5] [6.0] [6.1] -# CHECK-NEXT: 160.00 - 438.50 224.00 242.00 430.50 290.00 290.00 +# CHECK-NEXT: 160.00 - 435.83 221.33 246.00 435.83 292.00 292.00 # CHECK: Resource pressure by instruction: # CHECK-NEXT: [0] [1] [2] [3] [4] [5] [6.0] [6.1] Instructions: @@ -1820,13 +1820,13 @@ # CHECK-NEXT: - - 1.00 1.00 - 1.00 1.00 1.00 cmpsl %es:(%rdi), (%rsi) # CHECK-NEXT: - - 1.00 1.00 - 1.00 1.00 1.00 cmpsq %es:(%rdi), (%rsi) # CHECK-NEXT: - - 1.50 1.00 - 1.50 - - cmpxchgb %cl, %bl -# CHECK-NEXT: - - 1.00 1.00 - 1.00 0.50 0.50 cmpxchgb %cl, (%rbx) +# CHECK-NEXT: - - 0.33 0.33 1.00 2.33 1.00 1.00 cmpxchgb %cl, (%rbx) # CHECK-NEXT: - - 1.50 1.00 - 1.50 - - cmpxchgw %cx, %bx -# CHECK-NEXT: - - 1.00 1.00 - 1.00 0.50 0.50 cmpxchgw %cx, (%rbx) +# CHECK-NEXT: - - 0.33 0.33 1.00 2.33 1.00 1.00 cmpxchgw %cx, (%rbx) # CHECK-NEXT: - - 1.50 1.00 - 1.50 - - cmpxchgl %ecx, %ebx -# CHECK-NEXT: - - 1.00 1.00 - 1.00 0.50 0.50 cmpxchgl %ecx, (%rbx) +# CHECK-NEXT: - - 0.33 0.33 1.00 2.33 1.00 1.00 cmpxchgl %ecx, (%rbx) # CHECK-NEXT: - - 1.50 1.00 - 1.50 - - cmpxchgq %rcx, %rbx -# CHECK-NEXT: - - 1.00 1.00 - 1.00 0.50 0.50 cmpxchgq %rcx, (%rbx) +# CHECK-NEXT: - - 0.33 0.33 1.00 2.33 1.00 1.00 cmpxchgq %rcx, (%rbx) # CHECK-NEXT: - - 0.33 0.33 - 0.33 - - cpuid # CHECK-NEXT: - - 0.33 0.33 - 0.33 - - decb %dil # CHECK-NEXT: - - 0.33 0.33 1.00 0.33 1.00 1.00 decb (%rax) Index: llvm/trunk/test/tools/llvm-mca/X86/SandyBridge/resources-x86_64.s =================================================================== --- llvm/trunk/test/tools/llvm-mca/X86/SandyBridge/resources-x86_64.s +++ llvm/trunk/test/tools/llvm-mca/X86/SandyBridge/resources-x86_64.s @@ -852,6 +852,8 @@ xorq %rsi, (%rax) xorq (%rax), %rdi +# CCHECK-NEXT: 160.00 - 439.83 221.33 250.00 431.83 294.00 294.00 + # CHECK: Instruction Info: # CHECK-NEXT: [1]: #uOps # CHECK-NEXT: [2]: Latency @@ -1057,13 +1059,13 @@ # CHECK-NEXT: 5 8 1.00 U cmpsl %es:(%rdi), (%rsi) # CHECK-NEXT: 5 8 1.00 U cmpsq %es:(%rdi), (%rsi) # CHECK-NEXT: 4 5 1.33 cmpxchgb %cl, %bl -# CHECK-NEXT: 4 8 1.00 * * cmpxchgb %cl, (%rbx) +# CHECK-NEXT: 6 8 2.00 * * cmpxchgb %cl, (%rbx) # CHECK-NEXT: 4 5 1.33 cmpxchgw %cx, %bx -# CHECK-NEXT: 4 8 1.00 * * cmpxchgw %cx, (%rbx) +# CHECK-NEXT: 6 8 2.00 * * cmpxchgw %cx, (%rbx) # CHECK-NEXT: 4 5 1.33 cmpxchgl %ecx, %ebx -# CHECK-NEXT: 4 8 1.00 * * cmpxchgl %ecx, (%rbx) +# CHECK-NEXT: 6 8 2.00 * * cmpxchgl %ecx, (%rbx) # CHECK-NEXT: 4 5 1.33 cmpxchgq %rcx, %rbx -# CHECK-NEXT: 4 8 1.00 * * cmpxchgq %rcx, (%rbx) +# CHECK-NEXT: 6 8 2.00 * * cmpxchgq %rcx, (%rbx) # CHECK-NEXT: 1 100 0.33 U cpuid # CHECK-NEXT: 1 1 0.33 decb %dil # CHECK-NEXT: 3 7 1.00 * * decb (%rax) @@ -1620,7 +1622,7 @@ # CHECK: Resource pressure per iteration: # CHECK-NEXT: [0] [1] [2] [3] [4] [5] [6.0] [6.1] -# CHECK-NEXT: 160.00 - 438.50 224.00 242.00 430.50 290.00 290.00 +# CHECK-NEXT: 160.00 - 435.83 221.33 246.00 435.83 292.00 292.00 # CHECK: Resource pressure by instruction: # CHECK-NEXT: [0] [1] [2] [3] [4] [5] [6.0] [6.1] Instructions: @@ -1820,13 +1822,13 @@ # CHECK-NEXT: - - 1.00 1.00 - 1.00 1.00 1.00 cmpsl %es:(%rdi), (%rsi) # CHECK-NEXT: - - 1.00 1.00 - 1.00 1.00 1.00 cmpsq %es:(%rdi), (%rsi) # CHECK-NEXT: - - 1.50 1.00 - 1.50 - - cmpxchgb %cl, %bl -# CHECK-NEXT: - - 1.00 1.00 - 1.00 0.50 0.50 cmpxchgb %cl, (%rbx) +# CHECK-NEXT: - - 0.33 0.33 1.00 2.33 1.00 1.00 cmpxchgb %cl, (%rbx) # CHECK-NEXT: - - 1.50 1.00 - 1.50 - - cmpxchgw %cx, %bx -# CHECK-NEXT: - - 1.00 1.00 - 1.00 0.50 0.50 cmpxchgw %cx, (%rbx) +# CHECK-NEXT: - - 0.33 0.33 1.00 2.33 1.00 1.00 cmpxchgw %cx, (%rbx) # CHECK-NEXT: - - 1.50 1.00 - 1.50 - - cmpxchgl %ecx, %ebx -# CHECK-NEXT: - - 1.00 1.00 - 1.00 0.50 0.50 cmpxchgl %ecx, (%rbx) +# CHECK-NEXT: - - 0.33 0.33 1.00 2.33 1.00 1.00 cmpxchgl %ecx, (%rbx) # CHECK-NEXT: - - 1.50 1.00 - 1.50 - - cmpxchgq %rcx, %rbx -# CHECK-NEXT: - - 1.00 1.00 - 1.00 0.50 0.50 cmpxchgq %rcx, (%rbx) +# CHECK-NEXT: - - 0.33 0.33 1.00 2.33 1.00 1.00 cmpxchgq %rcx, (%rbx) # CHECK-NEXT: - - 0.33 0.33 - 0.33 - - cpuid # CHECK-NEXT: - - 0.33 0.33 - 0.33 - - decb %dil # CHECK-NEXT: - - 0.33 0.33 1.00 0.33 1.00 1.00 decb (%rax)