Index: lib/Target/X86/X86InstrInfo.td
===================================================================
--- lib/Target/X86/X86InstrInfo.td
+++ lib/Target/X86/X86InstrInfo.td
@@ -2061,7 +2061,7 @@
 
 }
 
-let SchedRW = [WriteALU], hasSideEffects = 0 in {
+let SchedRW = [WriteCMPXCHG], hasSideEffects = 0 in {
 let Defs = [AL, EFLAGS], Uses = [AL] in
 def CMPXCHG8rr : I<0xB0, MRMDestReg, (outs GR8:$dst), (ins GR8:$src),
                    "cmpxchg{b}\t{$src, $dst|$dst, $src}", []>, TB,
@@ -2080,7 +2080,7 @@
                       NotMemoryFoldable;
 } // SchedRW, hasSideEffects
 
-let SchedRW = [WriteALULd, WriteRMW], mayLoad = 1, mayStore = 1,
+let SchedRW = [WriteCMPXCHGLd, WriteRMW], mayLoad = 1, mayStore = 1,
     hasSideEffects = 0 in {
 let Defs = [AL, EFLAGS], Uses = [AL] in
 def CMPXCHG8rm   : I<0xB0, MRMDestMem, (outs), (ins i8mem:$dst, GR8:$src),
Index: lib/Target/X86/X86SchedBroadwell.td
===================================================================
--- lib/Target/X86/X86SchedBroadwell.td
+++ lib/Target/X86/X86SchedBroadwell.td
@@ -119,6 +119,8 @@
 defm : BWWriteResPair<WriteIDiv32, [BWPort0, BWDivider], 25, [1, 10]>;
 defm : BWWriteResPair<WriteIDiv64, [BWPort0, BWDivider], 25, [1, 10]>;
 
+defm : X86WriteRes<WriteCMPXCHG,[BWPort06, BWPort0156], 5, [2, 3], 5>;
+defm : X86WriteRes<WriteCMPXCHGLd,[BWPort23, BWPort06, BWPort0156], 8, [1, 2, 1], 5>;
 defm : X86WriteRes<WriteBSWAP32,   [BWPort15], 1, [1], 1>;
 defm : X86WriteRes<WriteBSWAP64,   [BWPort06, BWPort15], 2, [1, 1], 2>;
 defm : X86WriteRes<WriteXCHG,      [BWPort0156], 2, [3], 3>;
@@ -949,13 +951,6 @@
 }
 def: InstRW<[BWWriteResGroup55], (instrs XSETBV)>;
 
-def BWWriteResGroup56 : SchedWriteRes<[BWPort06,BWPort0156]> {
-  let Latency = 5;
-  let NumMicroOps = 5;
-  let ResourceCycles = [2,3];
-}
-def: InstRW<[BWWriteResGroup56], (instregex "CMPXCHG(8|16|32|64)rr")>;
-
 def BWWriteResGroup57 : SchedWriteRes<[BWPort4,BWPort237,BWPort0156]> {
   let Latency = 5;
   let NumMicroOps = 6;
@@ -1230,8 +1225,7 @@
   let ResourceCycles = [1,1,1,2,1];
 }
 def : SchedAlias<WriteADCRMW, BWWriteResGroup100>;
-def: InstRW<[BWWriteResGroup100], (instregex "CMPXCHG(8|16|32|64)rm",
-                                             "ROL(8|16|32|64)mCL",
+def: InstRW<[BWWriteResGroup100], (instregex "ROL(8|16|32|64)mCL",
                                              "SAR(8|16|32|64)mCL",
                                              "SHL(8|16|32|64)mCL",
                                              "SHR(8|16|32|64)mCL")>;
Index: lib/Target/X86/X86SchedHaswell.td
===================================================================
--- lib/Target/X86/X86SchedHaswell.td
+++ lib/Target/X86/X86SchedHaswell.td
@@ -126,6 +126,8 @@
 
 defm : X86WriteRes<WriteBSWAP32,   [HWPort15], 1, [1], 1>;
 defm : X86WriteRes<WriteBSWAP64,   [HWPort06, HWPort15], 2, [1,1], 2>;
+defm : X86WriteRes<WriteCMPXCHG,[HWPort06, HWPort0156], 5, [2,3], 5>;
+defm : X86WriteRes<WriteCMPXCHGLd,[HWPort23,HWPort06,HWPort0156], 9, [1,2,1], 5>;
 defm : X86WriteRes<WriteXCHG, [HWPort0156], 2, [3], 3>;
 
 def  : WriteRes<WriteIMulH, []> { let Latency = 3; }
@@ -1369,8 +1371,7 @@
   let NumMicroOps = 6;
   let ResourceCycles = [1,1,1,2,1];
 }
-def: InstRW<[HWWriteResGroup69], (instregex "CMPXCHG(8|16|32|64)rm",
-                                            "ROL(8|16|32|64)mCL",
+def: InstRW<[HWWriteResGroup69], (instregex "ROL(8|16|32|64)mCL",
                                             "SAR(8|16|32|64)mCL",
                                             "SHL(8|16|32|64)mCL",
                                             "SHR(8|16|32|64)mCL")>;
@@ -1592,13 +1593,6 @@
 }
 def: InstRW<[HWWriteResGroup100], (instrs XSETBV)>;
 
-def HWWriteResGroup101 : SchedWriteRes<[HWPort06,HWPort0156]> {
-  let Latency = 5;
-  let NumMicroOps = 5;
-  let ResourceCycles = [2,3];
-}
-def: InstRW<[HWWriteResGroup101], (instregex "CMPXCHG(8|16|32|64)rr")>;
-
 def HWWriteResGroup102 : SchedWriteRes<[HWPort1,HWPort5]> {
   let Latency = 6;
   let NumMicroOps = 2;
Index: lib/Target/X86/X86SchedSandyBridge.td
===================================================================
--- lib/Target/X86/X86SchedSandyBridge.td
+++ lib/Target/X86/X86SchedSandyBridge.td
@@ -115,6 +115,8 @@
 
 defm : X86WriteRes<WriteBSWAP32,   [SBPort1], 1, [1], 1>;
 defm : X86WriteRes<WriteBSWAP64,   [SBPort1,SBPort05], 2, [1,1], 2>;
+defm : X86WriteRes<WriteCMPXCHG,   [SBPort05,SBPort015], 5, [1,3], 4>;
+defm : X86WriteRes<WriteCMPXCHGLd, [SBPort015], 8, [3], 3>;
 
 defm : SBWriteResPair<WriteDiv8,   [SBPort0, SBDivider], 25, [1, 10]>;
 defm : SBWriteResPair<WriteDiv16,  [SBPort0, SBDivider], 25, [1, 10]>;
@@ -771,13 +773,6 @@
 }
 def: InstRW<[SBWriteResGroup41], (instrs FNINIT)>;
 
-def SBWriteResGroup42 : SchedWriteRes<[SBPort05,SBPort015]> {
-  let Latency = 5;
-  let NumMicroOps = 4;
-  let ResourceCycles = [1,3];
-}
-def: InstRW<[SBWriteResGroup42], (instregex "CMPXCHG(8|16|32|64)rr")>;
-
 def SBWriteResGroup43 : SchedWriteRes<[SBPort4,SBPort23,SBPort05]> {
   let Latency = 3;
   let NumMicroOps = 4;
@@ -953,12 +948,12 @@
 }
 def: InstRW<[SBWriteResGroup77], (instregex "(V?)(U?)COMI(SD|SS)rm")>;
 
-def SBWriteResGroup81 : SchedWriteRes<[SBPort23,SBPort015]> {
-  let Latency = 8;
-  let NumMicroOps = 4;
-  let ResourceCycles = [1,3];
+def SBWriteResGroup81 : SchedWriteRes<[SBPort015, SBPort4, SBPort23]> {
+  let Latency = 6;
+  let NumMicroOps = 3;
+  let ResourceCycles = [3, 1, 1];
 }
-def: InstRW<[SBWriteResGroup81], (instregex "CMPXCHG(8|16|32|64)rm")>;
+def: InstRW<[SBWriteResGroup81], (instregex "CMPXCHG(8|16)B")>;
 
 def SBWriteResGroup83 : SchedWriteRes<[SBPort23,SBPort015]> {
   let Latency = 8;
Index: lib/Target/X86/X86SchedSkylakeClient.td
===================================================================
--- lib/Target/X86/X86SchedSkylakeClient.td
+++ lib/Target/X86/X86SchedSkylakeClient.td
@@ -112,6 +112,8 @@
 
 defm : X86WriteRes<WriteBSWAP32,    [SKLPort15], 1, [1], 1>;
 defm : X86WriteRes<WriteBSWAP64,    [SKLPort06, SKLPort15], 2, [1,1], 2>;
+defm : X86WriteRes<WriteCMPXCHG,[SKLPort06, SKLPort0156], 5, [2,3], 5>;
+defm : X86WriteRes<WriteCMPXCHGLd,[SKLPort23,SKLPort06,SKLPort0156], 8, [1,2,1], 5>;
 defm : X86WriteRes<WriteXCHG, [SKLPort0156], 2, [3], 3>;
 
 defm : SKLWriteResPair<WriteDiv8,   [SKLPort0, SKLDivider], 25, [1,10], 1, 4>;
@@ -975,13 +977,6 @@
 }
 def: InstRW<[SKLWriteResGroup63], (instrs XSETBV)>;
 
-def SKLWriteResGroup64 : SchedWriteRes<[SKLPort06,SKLPort0156]> {
-  let Latency = 5;
-  let NumMicroOps = 5;
-  let ResourceCycles = [2,3];
-}
-def: InstRW<[SKLWriteResGroup64], (instregex "CMPXCHG(8|16|32|64)rr")>;
-
 def SKLWriteResGroup65 : SchedWriteRes<[SKLPort4,SKLPort237,SKLPort0156]> {
   let Latency = 5;
   let NumMicroOps = 6;
@@ -1327,7 +1322,6 @@
   let ResourceCycles = [1,1,1,2,1];
 }
 def: SchedAlias<WriteADCRMW, SKLWriteResGroup119>;
-def: InstRW<[SKLWriteResGroup119], (instregex "CMPXCHG(8|16|32|64)rm")>;
 
 def SKLWriteResGroup120 : SchedWriteRes<[SKLPort0,SKLPort23]> {
   let Latency = 9;
Index: lib/Target/X86/X86SchedSkylakeServer.td
===================================================================
--- lib/Target/X86/X86SchedSkylakeServer.td
+++ lib/Target/X86/X86SchedSkylakeServer.td
@@ -112,6 +112,8 @@
 
 defm : X86WriteRes<WriteBSWAP32, [SKXPort15], 1, [1], 1>;
 defm : X86WriteRes<WriteBSWAP64, [SKXPort06, SKXPort15], 2, [1,1], 2>;
+defm : X86WriteRes<WriteCMPXCHG,[SKXPort06, SKXPort0156], 5, [2,3], 5>;
+defm : X86WriteRes<WriteCMPXCHGLd,[SKXPort23,SKXPort06,SKXPort0156], 8, [1,2,1], 5>;
 defm : X86WriteRes<WriteXCHG,       [SKXPort0156], 2, [3], 3>;
 
 defm : SKXWriteResPair<WriteDiv8,   [SKXPort0, SKXDivider], 25, [1,10], 1, 4>;
@@ -1142,13 +1144,6 @@
 }
 def: InstRW<[SKXWriteResGroup67], (instrs XSETBV)>;
 
-def SKXWriteResGroup68 : SchedWriteRes<[SKXPort06,SKXPort0156]> {
-  let Latency = 5;
-  let NumMicroOps = 5;
-  let ResourceCycles = [2,3];
-}
-def: InstRW<[SKXWriteResGroup68], (instregex "CMPXCHG(8|16|32|64)rr")>;
-
 def SKXWriteResGroup69 : SchedWriteRes<[SKXPort4,SKXPort237,SKXPort0156]> {
   let Latency = 5;
   let NumMicroOps = 6;
@@ -1686,7 +1681,6 @@
   let ResourceCycles = [1,1,1,2,1];
 }
 def: SchedAlias<WriteADCRMW, SKXWriteResGroup130>;
-def: InstRW<[SKXWriteResGroup130], (instregex "CMPXCHG(8|16|32|64)rm")>;
 
 def SKXWriteResGroup131 : SchedWriteRes<[SKXPort0,SKXPort4,SKXPort5,SKXPort237,SKXPort0156]> {
   let Latency = 8;
Index: lib/Target/X86/X86Schedule.td
===================================================================
--- lib/Target/X86/X86Schedule.td
+++ lib/Target/X86/X86Schedule.td
@@ -120,7 +120,8 @@
 
 def  WriteBSWAP32 : SchedWrite; // Byte Order (Endianness) 32-bit Swap.
 def  WriteBSWAP64 : SchedWrite; // Byte Order (Endianness) 64-bit Swap.
-def  WriteXCHG   : SchedWrite;        // Compare+Exchange - TODO RMW support.
+defm WriteCMPXCHG : X86SchedWritePair; // Compare and set, compare and swap.
+def  WriteXCHG    : SchedWrite;        // Compare+Exchange - TODO RMW support.
 
 // Integer division.
 defm WriteDiv8   : X86SchedWritePair;
Index: lib/Target/X86/X86ScheduleAtom.td
===================================================================
--- lib/Target/X86/X86ScheduleAtom.td
+++ lib/Target/X86/X86ScheduleAtom.td
@@ -84,6 +84,7 @@
 defm : X86WriteRes<WriteXCHG,        [AtomPort01], 2, [2], 1>;
 defm : X86WriteRes<WriteBSWAP32,     [AtomPort0], 1, [1], 1>;
 defm : X86WriteRes<WriteBSWAP64,     [AtomPort0], 1, [1], 1>;
+defm : AtomWriteResPair<WriteCMPXCHG,    [AtomPort01], [AtomPort01], 15, 15, [15]>;
 
 defm : AtomWriteResPair<WriteDiv8,   [AtomPort01], [AtomPort01], 50, 68, [50], [68]>;
 defm : AtomWriteResPair<WriteDiv16,  [AtomPort01], [AtomPort01], 50, 50, [50], [50]>;
@@ -676,12 +677,6 @@
 }
 def : InstRW<[AtomWrite01_14], (instrs CMPXCHG16rm, CMPXCHG32rm, CMPXCHG64rm)>;
 
-def AtomWrite01_15 : SchedWriteRes<[AtomPort01]> {
-  let Latency = 15;
-  let ResourceCycles = [15];
-}
-def : InstRW<[AtomWrite01_15], (instrs CMPXCHG16rr, CMPXCHG32rr, CMPXCHG64rr)>;
-
 def AtomWrite01_17 : SchedWriteRes<[AtomPort01]> {
   let Latency = 17;
   let ResourceCycles = [17];
Index: lib/Target/X86/X86ScheduleBtVer2.td
===================================================================
--- lib/Target/X86/X86ScheduleBtVer2.td
+++ lib/Target/X86/X86ScheduleBtVer2.td
@@ -170,6 +170,7 @@
 
 defm : X86WriteRes<WriteBSWAP32, [JALU01], 1, [1], 1>;
 defm : X86WriteRes<WriteBSWAP64, [JALU01], 1, [1], 1>;
+defm : JWriteResIntPair<WriteCMPXCHG,[JALU01], 1>;
 defm : X86WriteRes<WriteXCHG,        [JALU01], 1, [1], 1>;
 
 defm : JWriteResIntPair<WriteDiv8,   [JALU1, JDiv], 12, [1, 12], 1>;
Index: lib/Target/X86/X86ScheduleSLM.td
===================================================================
--- lib/Target/X86/X86ScheduleSLM.td
+++ lib/Target/X86/X86ScheduleSLM.td
@@ -100,6 +100,7 @@
 
 defm : X86WriteRes<WriteBSWAP32, [SLM_IEC_RSV01], 1, [1], 1>;
 defm : X86WriteRes<WriteBSWAP64, [SLM_IEC_RSV01], 1, [1], 1>;
+defm : SLMWriteResPair<WriteCMPXCHG,[SLM_IEC_RSV01], 1>;
 defm : X86WriteRes<WriteXCHG,       [SLM_IEC_RSV01], 1, [1], 1>;
 
 defm : SLMWriteResPair<WriteShift,  [SLM_IEC_RSV0],  1>;
Index: lib/Target/X86/X86ScheduleZnver1.td
===================================================================
--- lib/Target/X86/X86ScheduleZnver1.td
+++ lib/Target/X86/X86ScheduleZnver1.td
@@ -182,6 +182,8 @@
 
 defm : X86WriteRes<WriteBSWAP32, [ZnALU], 1, [4], 1>;
 defm : X86WriteRes<WriteBSWAP64, [ZnALU], 1, [4], 1>;
+defm : X86WriteRes<WriteCMPXCHG, [ZnALU], 1, [1], 1>;
+defm : X86WriteRes<WriteCMPXCHGLd,[ZnALU], 8, [1], 4>;
 defm : X86WriteRes<WriteXCHG, [ZnALU], 1, [2], 2>;
 
 defm : ZnWriteResPair<WriteShift, [ZnALU], 1>;
@@ -743,13 +745,6 @@
 def : InstRW<[WriteMicrocoded], (instregex "SH(R|L)D(16|32|64)mrCL")>;
 
 //-- Misc instructions --//
-// CMPXCHG.
-def ZnWriteCMPXCHG : SchedWriteRes<[ZnAGU, ZnALU]> {
-  let Latency = 8;
-  let NumMicroOps = 5;
-}
-def : InstRW<[ZnWriteCMPXCHG], (instregex "CMPXCHG(8|16|32|64)rm")>;
-
 // CMPXCHG8B.
 def ZnWriteCMPXCHG8B : SchedWriteRes<[ZnAGU, ZnALU]> {
   let NumMicroOps = 18;
Index: test/tools/llvm-mca/X86/Generic/resources-cmpxchg.s
===================================================================
--- test/tools/llvm-mca/X86/Generic/resources-cmpxchg.s
+++ test/tools/llvm-mca/X86/Generic/resources-cmpxchg.s
@@ -28,9 +28,9 @@
 
 # CHECK:      Resource pressure per iteration:
 # CHECK-NEXT: [0]    [1]    [2]    [3]    [4]    [5]    [6.0]  [6.1]
-# CHECK-NEXT:  -      -     0.67   0.67   2.00   0.67   2.00   2.00
+# CHECK-NEXT:  -      -     2.00   2.00   2.00   2.00   1.00   1.00
 
 # CHECK:      Resource pressure by instruction:
 # CHECK-NEXT: [0]    [1]    [2]    [3]    [4]    [5]    [6.0]  [6.1]  Instructions:
-# CHECK-NEXT:  -      -     0.33   0.33   1.00   0.33   1.00   1.00   cmpxchg8b	(%rax)
-# CHECK-NEXT:  -      -     0.33   0.33   1.00   0.33   1.00   1.00   cmpxchg16b	(%rax)
+# CHECK-NEXT:  -      -     1.00   1.00   1.00   1.00   0.50   0.50   cmpxchg8b	(%rax)
+# CHECK-NEXT:  -      -     1.00   1.00   1.00   1.00   0.50   0.50   cmpxchg16b	(%rax)
Index: test/tools/llvm-mca/X86/Generic/resources-x86_64.s
===================================================================
--- test/tools/llvm-mca/X86/Generic/resources-x86_64.s
+++ test/tools/llvm-mca/X86/Generic/resources-x86_64.s
@@ -1620,7 +1620,7 @@
 
 # CHECK:      Resource pressure per iteration:
 # CHECK-NEXT: [0]    [1]    [2]    [3]    [4]    [5]    [6.0]  [6.1]
-# CHECK-NEXT: 160.00  -     438.50 224.00 242.00 430.50 290.00 290.00
+# CHECK-NEXT: 160.00  -     438.50 224.00 246.00 430.50 290.00 290.00
 
 # CHECK:      Resource pressure by instruction:
 # CHECK-NEXT: [0]    [1]    [2]    [3]    [4]    [5]    [6.0]  [6.1]  Instructions:
@@ -1820,13 +1820,13 @@
 # CHECK-NEXT:  -      -     1.00   1.00    -     1.00   1.00   1.00   cmpsl	%es:(%rdi), (%rsi)
 # CHECK-NEXT:  -      -     1.00   1.00    -     1.00   1.00   1.00   cmpsq	%es:(%rdi), (%rsi)
 # CHECK-NEXT:  -      -     1.50   1.00    -     1.50    -      -     cmpxchgb	%cl, %bl
-# CHECK-NEXT:  -      -     1.00   1.00    -     1.00   0.50   0.50   cmpxchgb	%cl, (%rbx)
+# CHECK-NEXT:  -      -     1.00   1.00   1.00   1.00   0.50   0.50   cmpxchgb	%cl, (%rbx)
 # CHECK-NEXT:  -      -     1.50   1.00    -     1.50    -      -     cmpxchgw	%cx, %bx
-# CHECK-NEXT:  -      -     1.00   1.00    -     1.00   0.50   0.50   cmpxchgw	%cx, (%rbx)
+# CHECK-NEXT:  -      -     1.00   1.00   1.00   1.00   0.50   0.50   cmpxchgw	%cx, (%rbx)
 # CHECK-NEXT:  -      -     1.50   1.00    -     1.50    -      -     cmpxchgl	%ecx, %ebx
-# CHECK-NEXT:  -      -     1.00   1.00    -     1.00   0.50   0.50   cmpxchgl	%ecx, (%rbx)
+# CHECK-NEXT:  -      -     1.00   1.00   1.00   1.00   0.50   0.50   cmpxchgl	%ecx, (%rbx)
 # CHECK-NEXT:  -      -     1.50   1.00    -     1.50    -      -     cmpxchgq	%rcx, %rbx
-# CHECK-NEXT:  -      -     1.00   1.00    -     1.00   0.50   0.50   cmpxchgq	%rcx, (%rbx)
+# CHECK-NEXT:  -      -     1.00   1.00   1.00   1.00   0.50   0.50   cmpxchgq	%rcx, (%rbx)
 # CHECK-NEXT:  -      -     0.33   0.33    -     0.33    -      -     cpuid
 # CHECK-NEXT:  -      -     0.33   0.33    -     0.33    -      -     decb	%dil
 # CHECK-NEXT:  -      -     0.33   0.33   1.00   0.33   1.00   1.00   decb	(%rax)
Index: test/tools/llvm-mca/X86/SandyBridge/resources-cmpxchg.s
===================================================================
--- test/tools/llvm-mca/X86/SandyBridge/resources-cmpxchg.s
+++ test/tools/llvm-mca/X86/SandyBridge/resources-cmpxchg.s
@@ -28,9 +28,9 @@
 
 # CHECK:      Resource pressure per iteration:
 # CHECK-NEXT: [0]    [1]    [2]    [3]    [4]    [5]    [6.0]  [6.1]
-# CHECK-NEXT:  -      -     0.67   0.67   2.00   0.67   2.00   2.00
+# CHECK-NEXT:  -      -     2.00   2.00   2.00   2.00   1.00   1.00
 
 # CHECK:      Resource pressure by instruction:
 # CHECK-NEXT: [0]    [1]    [2]    [3]    [4]    [5]    [6.0]  [6.1]  Instructions:
-# CHECK-NEXT:  -      -     0.33   0.33   1.00   0.33   1.00   1.00   cmpxchg8b	(%rax)
-# CHECK-NEXT:  -      -     0.33   0.33   1.00   0.33   1.00   1.00   cmpxchg16b	(%rax)
+# CHECK-NEXT:  -      -     1.00   1.00   1.00   1.00   0.50   0.50   cmpxchg8b	(%rax)
+# CHECK-NEXT:  -      -     1.00   1.00   1.00   1.00   0.50   0.50   cmpxchg16b	(%rax)
Index: test/tools/llvm-mca/X86/SandyBridge/resources-x86_64.s
===================================================================
--- test/tools/llvm-mca/X86/SandyBridge/resources-x86_64.s
+++ test/tools/llvm-mca/X86/SandyBridge/resources-x86_64.s
@@ -1620,7 +1620,7 @@
 
 # CHECK:      Resource pressure per iteration:
 # CHECK-NEXT: [0]    [1]    [2]    [3]    [4]    [5]    [6.0]  [6.1]
-# CHECK-NEXT: 160.00  -     438.50 224.00 242.00 430.50 290.00 290.00
+# CHECK-NEXT: 160.00  -     438.50 224.00 246.00 430.50 290.00 290.00
 
 # CHECK:      Resource pressure by instruction:
 # CHECK-NEXT: [0]    [1]    [2]    [3]    [4]    [5]    [6.0]  [6.1]  Instructions:
@@ -1820,13 +1820,13 @@
 # CHECK-NEXT:  -      -     1.00   1.00    -     1.00   1.00   1.00   cmpsl	%es:(%rdi), (%rsi)
 # CHECK-NEXT:  -      -     1.00   1.00    -     1.00   1.00   1.00   cmpsq	%es:(%rdi), (%rsi)
 # CHECK-NEXT:  -      -     1.50   1.00    -     1.50    -      -     cmpxchgb	%cl, %bl
-# CHECK-NEXT:  -      -     1.00   1.00    -     1.00   0.50   0.50   cmpxchgb	%cl, (%rbx)
+# CHECK-NEXT:  -      -     1.00   1.00   1.00   1.00   0.50   0.50   cmpxchgb	%cl, (%rbx)
 # CHECK-NEXT:  -      -     1.50   1.00    -     1.50    -      -     cmpxchgw	%cx, %bx
-# CHECK-NEXT:  -      -     1.00   1.00    -     1.00   0.50   0.50   cmpxchgw	%cx, (%rbx)
+# CHECK-NEXT:  -      -     1.00   1.00   1.00   1.00   0.50   0.50   cmpxchgw	%cx, (%rbx)
 # CHECK-NEXT:  -      -     1.50   1.00    -     1.50    -      -     cmpxchgl	%ecx, %ebx
-# CHECK-NEXT:  -      -     1.00   1.00    -     1.00   0.50   0.50   cmpxchgl	%ecx, (%rbx)
+# CHECK-NEXT:  -      -     1.00   1.00   1.00   1.00   0.50   0.50   cmpxchgl	%ecx, (%rbx)
 # CHECK-NEXT:  -      -     1.50   1.00    -     1.50    -      -     cmpxchgq	%rcx, %rbx
-# CHECK-NEXT:  -      -     1.00   1.00    -     1.00   0.50   0.50   cmpxchgq	%rcx, (%rbx)
+# CHECK-NEXT:  -      -     1.00   1.00   1.00   1.00   0.50   0.50   cmpxchgq	%rcx, (%rbx)
 # CHECK-NEXT:  -      -     0.33   0.33    -     0.33    -      -     cpuid
 # CHECK-NEXT:  -      -     0.33   0.33    -     0.33    -      -     decb	%dil
 # CHECK-NEXT:  -      -     0.33   0.33   1.00   0.33   1.00   1.00   decb	(%rax)