Index: include/llvm/Target/Target.td
===================================================================
--- include/llvm/Target/Target.td
+++ include/llvm/Target/Target.td
@@ -1553,3 +1553,8 @@
 // Pull in the common support for the Global ISel DAG-based selector generation.
 //
 include "llvm/Target/GlobalISel/SelectionDAGCompat.td"
+
+//===----------------------------------------------------------------------===//
+// Pull in the common support for exegesis.
+//
+include "llvm/Target/TargetExegesis.td"
Index: include/llvm/Target/TargetExegesis.td
===================================================================
--- /dev/null
+++ include/llvm/Target/TargetExegesis.td
@@ -0,0 +1,52 @@
+//===- TargetSchedule.td - Target Independent Scheduling ---*- tablegen -*-===//
+//
+//                     The LLVM Compiler Infrastructure
+//
+// This file is distributed under the University of Illinois Open Source
+// License. See LICENSE.TXT for details.
+//
+//===----------------------------------------------------------------------===//
+
+class OperandValue;
+
+class ExegesisConfiguration {
+  Instruction Instruction = ?;
+  list<OperandValue> OperandValues;
+}
+
+class ScalarValue : OperandValue;
+
+class PackedValue : OperandValue {
+  ScalarValue       BroadcastValue;
+}
+
+// Floating Point description
+
+class Ieee754Precision;
+def HalfPrecision   : Ieee754Precision;
+def SinglePrecision : Ieee754Precision;
+def DoublePrecision : Ieee754Precision;
+def X87Precision    : Ieee754Precision;
+
+class RawExponentValue;
+def RawExponentZero  : RawExponentValue;
+def RawExponentMax   : RawExponentValue;
+def RawExponentBias  : RawExponentValue;
+
+class MantissaValue;
+def MantissaZero : MantissaValue;
+def MantissaOne  : MantissaValue;
+def MantissaMax  : MantissaValue;
+
+class Ieee754 : ScalarValue {
+  Ieee754Precision  Precision;
+  bit               Sign;
+  RawExponentValue  Exponent;
+  MantissaValue     Mantissa;
+}
+
+// Integer Description.
+
+class Integer : ScalarValue {
+  list<bit> Bits;
+}
Index: lib/Target/X86/CMakeLists.txt
===================================================================
--- lib/Target/X86/CMakeLists.txt
+++ lib/Target/X86/CMakeLists.txt
@@ -10,6 +10,7 @@
 tablegen(LLVM X86GenFastISel.inc -gen-fast-isel)
 tablegen(LLVM X86GenGlobalISel.inc -gen-global-isel)
 tablegen(LLVM X86GenInstrInfo.inc -gen-instr-info)
+tablegen(LLVM X86GenInstrSemInfo.inc -gen-instr-sem-info)
 tablegen(LLVM X86GenRegisterBank.inc -gen-register-bank)
 tablegen(LLVM X86GenRegisterInfo.inc -gen-register-info)
 tablegen(LLVM X86GenSubtargetInfo.inc -gen-subtarget)
Index: lib/Target/X86/X86.td
===================================================================
--- lib/Target/X86/X86.td
+++ lib/Target/X86/X86.td
@@ -1200,3 +1200,9 @@
 //===----------------------------------------------------------------------===//
 
 include "X86PfmCounters.td"
+
+//===----------------------------------------------------------------------===//
+// Exegesis Configurations
+//===----------------------------------------------------------------------===//
+
+include "X86ExegesisConfigurations.td"
Index: lib/Target/X86/X86ExegesisConfigurations.td
===================================================================
--- /dev/null
+++ lib/Target/X86/X86ExegesisConfigurations.td
@@ -0,0 +1,27 @@
+def One : Ieee754 {
+  let Precision = SinglePrecision;
+  let Sign = 0;
+  let Exponent = RawExponentBias;
+  let Mantissa = MantissaZero;
+}
+
+def OnePlusEpsilon : Ieee754 {
+  let Precision = SinglePrecision;
+  let Sign = 0;
+  let Exponent = RawExponentBias;
+  let Mantissa = MantissaOne;
+}
+
+def PackedOnes : PackedValue {
+  let BroadcastValue = One;
+}
+
+def PackedOnePlusEpsilons : PackedValue {
+  let BroadcastValue = OnePlusEpsilon;
+}
+
+let Instruction = VDIVPDrr in {
+  def VDIVPDrrExegesisConfiguration : ExegesisConfiguration {
+    let OperandValues = [PackedOnes, PackedOnePlusEpsilons];
+  }
+}
Index: utils/TableGen/CMakeLists.txt
===================================================================
--- utils/TableGen/CMakeLists.txt
+++ utils/TableGen/CMakeLists.txt
@@ -27,6 +27,7 @@
   InfoByHwMode.cpp
   InstrInfoEmitter.cpp
   InstrDocsEmitter.cpp
+  InstrSemInfoEmitter.cpp
   IntrinsicEmitter.cpp
   OptParserEmitter.cpp
   PredicateExpander.cpp
Index: utils/TableGen/InstrSemInfoEmitter.cpp
===================================================================
--- /dev/null
+++ utils/TableGen/InstrSemInfoEmitter.cpp
@@ -0,0 +1,56 @@
+
+#include "llvm/Support/raw_ostream.h"
+#include "llvm/TableGen/Record.h"
+#include "llvm/TableGen/TableGenBackend.h"
+
+using namespace llvm;
+
+namespace {
+
+class InstrInfoSemEmitter {
+  RecordKeeper &Records;
+
+public:
+  InstrInfoSemEmitter(RecordKeeper &R) : Records(R) {}
+
+  void run(raw_ostream &OS);
+};
+
+void InstrInfoSemEmitter::run(raw_ostream &OS) {
+  { // FPI
+    Record *Class = Records.getClass("FPI");
+    assert(Class);
+    OS << "#FPI\n";
+    for (const auto &D : Records.getDefs())
+      if (D.second->isSubClassOf(Class))
+        OS << D.second->getName() << "\n";
+  }
+  { // PD
+    Record *Class = Records.getClass("PD");
+    assert(Class);
+    OS << "#PD\n";
+    for (const auto &D : Records.getDefs())
+      if (D.second->isSubClassOf(Class))
+        OS << D.second->getName() << "\n";
+  }
+  { // PS
+    Record *Class = Records.getClass("PS");
+    assert(Class);
+    OS << "#PS\n";
+    for (const auto &D : Records.getDefs())
+      if (D.second->isSubClassOf(Class))
+        OS << D.second->getName() << "\n";
+  }
+}
+
+} // end namespace
+
+namespace llvm {
+
+void EmitInstrSemInfo(RecordKeeper &RK, raw_ostream &OS) {
+  InstrInfoSemEmitter(RK).run(OS);
+}
+
+} // namespace llvm
+
+// 0b 0 01111100 01000000000000000000000
Index: utils/TableGen/TableGen.cpp
===================================================================
--- utils/TableGen/TableGen.cpp
+++ utils/TableGen/TableGen.cpp
@@ -28,6 +28,7 @@
   GenRegisterInfo,
   GenInstrInfo,
   GenInstrDocs,
+  GenInstrSemInfo,
   GenAsmWriter,
   GenAsmMatcher,
   GenDisassembler,
@@ -67,6 +68,8 @@
                                "Generate instruction descriptions"),
                     clEnumValN(GenInstrDocs, "gen-instr-docs",
                                "Generate instruction documentation"),
+                    clEnumValN(GenInstrSemInfo, "gen-instr-sem-info",
+                               "Generate instruction semantic descriptions"),
                     clEnumValN(GenCallingConv, "gen-callingconv",
                                "Generate calling convention descriptions"),
                     clEnumValN(GenAsmWriter, "gen-asm-writer",
@@ -138,6 +141,9 @@
   case GenInstrDocs:
     EmitInstrDocs(Records, OS);
     break;
+  case GenInstrSemInfo:
+    EmitInstrSemInfo(Records, OS);
+    break;
   case GenCallingConv:
     EmitCallingConv(Records, OS);
     break;
Index: utils/TableGen/TableGenBackends.h
===================================================================
--- utils/TableGen/TableGenBackends.h
+++ utils/TableGen/TableGenBackends.h
@@ -76,6 +76,7 @@
 void EmitFastISel(RecordKeeper &RK, raw_ostream &OS);
 void EmitInstrInfo(RecordKeeper &RK, raw_ostream &OS);
 void EmitInstrDocs(RecordKeeper &RK, raw_ostream &OS);
+void EmitInstrSemInfo(RecordKeeper &RK, raw_ostream &OS);
 void EmitPseudoLowering(RecordKeeper &RK, raw_ostream &OS);
 void EmitCompressInst(RecordKeeper &RK, raw_ostream &OS);
 void EmitRegisterInfo(RecordKeeper &RK, raw_ostream &OS);