Index: lib/CodeGen/TargetInfo.cpp =================================================================== --- lib/CodeGen/TargetInfo.cpp +++ lib/CodeGen/TargetInfo.cpp @@ -5533,11 +5533,20 @@ return ABIArgInfo::getDirect(); // O32 returns integer vectors in registers. - if (IsO32 && RetTy->isVectorType() && !RetTy->hasFloatingRepresentation()) - return ABIArgInfo::getDirect(returnAggregateInRegs(RetTy, Size)); + if (IsO32 && RetTy->isVectorType() && + !RetTy->hasFloatingRepresentation()) { + ABIArgInfo ArgInfo = + ABIArgInfo::getDirect(returnAggregateInRegs(RetTy, Size)); + ArgInfo.setInReg(true); + return ArgInfo; + } - if (!IsO32) - return ABIArgInfo::getDirect(returnAggregateInRegs(RetTy, Size)); + if (!IsO32) { + ABIArgInfo ArgInfo = + ABIArgInfo::getDirect(returnAggregateInRegs(RetTy, Size)); + ArgInfo.setInReg(true); + return ArgInfo; + } } return ABIArgInfo::getIndirect(0); Index: test/CodeGen/mips-vector-return.c =================================================================== --- test/CodeGen/mips-vector-return.c +++ test/CodeGen/mips-vector-return.c @@ -9,7 +9,7 @@ typedef int v4i32 __attribute__ ((__vector_size__ (16))); // O32-LABEL: define void @test_v4sf(<4 x float>* noalias nocapture sret -// N64: define { i64, i64 } @test_v4sf +// N64: define inreg { i64, i64 } @test_v4sf v4sf test_v4sf(float a) { return (v4sf){0.0f, a, 0.0f, 0.0f}; } @@ -23,8 +23,8 @@ // O32 returns integer vectors whose size is equal to or smaller than 16-bytes // in integer registers. // -// O32: define { i32, i32, i32, i32 } @test_v4i32 -// N64: define { i64, i64 } @test_v4i32 +// O32: define inreg { i32, i32, i32, i32 } @test_v4i32 +// N64: define inreg { i64, i64 } @test_v4i32 v4i32 test_v4i32(int a) { return (v4i32){0, a, 0, 0}; } Index: test/CodeGen/mips64-class-return.cpp =================================================================== --- test/CodeGen/mips64-class-return.cpp +++ test/CodeGen/mips64-class-return.cpp @@ -24,17 +24,17 @@ extern D1 gd1; extern D2 gd2; -// CHECK: define { i64, i64 } @_Z4foo1v() +// CHECK: define inreg { i64, i64 } @_Z4foo1v() D0 foo1(void) { return gd0; } -// CHECK: define { double, float } @_Z4foo2v() +// CHECK: define inreg { double, float } @_Z4foo2v() D1 foo2(void) { return gd1; } -// CHECK-LABEL: define void @_Z4foo32D2(i64 %a0.coerce0, double %a0.coerce1) +// CHECK-LABEL: define void @_Z4foo32D2(i64 %a0.coerce0, double %a0.coerce1) void foo3(D2 a0) { gd2 = a0; }