Index: lib/Target/RISCV/RISCVInstrInfo.td =================================================================== --- lib/Target/RISCV/RISCVInstrInfo.td +++ lib/Target/RISCV/RISCVInstrInfo.td @@ -550,6 +550,27 @@ def : InstAlias<"sfence.vma", (SFENCE_VMA X0, X0)>; def : InstAlias<"sfence.vma $rs", (SFENCE_VMA GPR:$rs, X0)>; +let EmitPriority = 0 in { +def : InstAlias<"add $rd, $rs1, $imm12", + (ADDI GPR:$rd, GPR:$rs1, simm12:$imm12)>; +def : InstAlias<"and $rd, $rs1, $imm12", + (ANDI GPR:$rd, GPR:$rs1, simm12:$imm12)>; +def : InstAlias<"xor $rd, $rs1, $imm12", + (XORI GPR:$rd, GPR:$rs1, simm12:$imm12)>; +def : InstAlias<"or $rd, $rs1, $imm12", + (ORI GPR:$rd, GPR:$rs1, simm12:$imm12)>; +def : InstAlias<"sll $rd, $rs1, $imm12", + (SLLI GPR:$rd, GPR:$rs1, simm12:$imm12)>; +def : InstAlias<"srl $rd, $rs1, $imm12", + (SRLI GPR:$rd, GPR:$rs1, simm12:$imm12)>; +def : InstAlias<"sra $rd, $rs1, $imm12", + (SRAI GPR:$rd, GPR:$rs1, simm12:$imm12)>; +def : InstAlias<"slt $rd, $rs1, $imm12", + (SLTI GPR:$rd, GPR:$rs1, simm12:$imm12)>; +def : InstAlias<"sltu $rd, $rs1, $imm12", + (SLTIU GPR:$rd, GPR:$rs1, simm12:$imm12)>; +} + //===----------------------------------------------------------------------===// // Pseudo-instructions and codegen patterns // Index: test/MC/RISCV/rvi-aliases-valid.s =================================================================== --- test/MC/RISCV/rvi-aliases-valid.s +++ test/MC/RISCV/rvi-aliases-valid.s @@ -155,3 +155,39 @@ # CHECK-INST: sfence.vma a0, zero # CHECK-ALIAS: sfence.vma a0 sfence.vma a0 + +# CHECK-INST: addi a2, a3, 4 +# CHECK: encoding: [0x13,0x86,0x46,0x00] +add a2,a3,4 + +# CHECK-INST: andi a2, a3, 4 +# CHECK: encoding: [0x13,0xf6,0x46,0x00] +and a2,a3,4 + +# CHECK-INST: xori a2, a3, 4 +# CHECK: encoding: [0x13,0xc6,0x46,0x00] +xor a2,a3,4 + +# CHECK-INST: ori a2, a3, 4 +# CHECK: encoding: [0x13,0xe6,0x46,0x00] +or a2,a3,4 + +# CHECK-INST: slli a2, a3, 4 +# CHECK: encoding: [0x13,0x96,0x46,0x00] +sll a2,a3,4 + +# CHECK-INST: srli a2, a3, 4 +# CHECK: encoding: [0x13,0xd6,0x46,0x00] +srl a2,a3,4 + +# CHECK-INST: srai a2, a3, 4 +# CHECK: encoding: [0x13,0xd6,0x46,0x40] +sra a2,a3,4 + +# CHECK-INST: slti a2, a3, 4 +# CHECK: encoding: [0x13,0xa6,0x46,0x00] +slt a2,a3,4 + +# CHECK-INST: sltiu a2, a3, 4 +# CHECK: encoding: [0x13,0xb6,0x46,0x00] +sltu a2,a3,4