Index: lib/Target/AMDGPU/AMDGPUInstructions.td
===================================================================
--- lib/Target/AMDGPU/AMDGPUInstructions.td
+++ lib/Target/AMDGPU/AMDGPUInstructions.td
@@ -167,6 +167,9 @@
 
 def select_oneuse : HasOneUseTernaryOp<select>;
 
+def AMDGPUmul_u24_oneuse : HasOneUseBinOp<AMDGPUmul_u24>;
+def AMDGPUmul_i24_oneuse : HasOneUseBinOp<AMDGPUmul_i24>;
+
 def srl_16 : PatFrag<
   (ops node:$src0), (srl_oneuse node:$src0, (i32 16))
 >;
Index: lib/Target/AMDGPU/VOP3PInstructions.td
===================================================================
--- lib/Target/AMDGPU/VOP3PInstructions.td
+++ lib/Target/AMDGPU/VOP3PInstructions.td
@@ -165,6 +165,24 @@
 defm : MadFmaMixPats<fma, V_FMA_MIX_F32, V_FMA_MIXLO_F16, V_FMA_MIXHI_F16>;
 }
 
+class UDot2Pat<Instruction Inst> : GCNPat <
+  (add (add_oneuse (AMDGPUmul_u24_oneuse (srl i32:$src0, (i32 16)),
+                                         (srl i32:$src1, (i32 16))), i32:$src2),
+       (AMDGPUmul_u24_oneuse (and i32:$src0, (i32 65535)),
+                             (and i32:$src1, (i32 65535)))
+   ),
+  (Inst (i32 8), $src0, (i32 8), $src1, (i32 8), $src2, (i1 0))
+>;
+
+class SDot2Pat<Instruction Inst> : GCNPat <
+  (add (add_oneuse (AMDGPUmul_i24_oneuse (sra i32:$src0, (i32 16)),
+                                         (sra i32:$src1, (i32 16))), i32:$src2),
+       (AMDGPUmul_i24_oneuse (sext_inreg i32:$src0, i16),
+                             (sext_inreg i32:$src1, i16))
+   ),
+  (Inst (i32 8), $src0, (i32 8), $src1, (i32 8), $src2, (i1 0))
+>;
+
 let SubtargetPredicate = HasDLInsts in {
 
 def V_DOT2_F32_F16 : VOP3PInst<"v_dot2_f32_f16", VOP3_Profile<VOP_F32_V2F16_V2F16_F32>, AMDGPUfdot2>;
@@ -175,6 +193,9 @@
 def V_DOT8_I32_I4  : VOP3PInst<"v_dot8_i32_i4", VOP3_Profile<VOP_I32_I32_I32_I32, VOP3_PACKED>, int_amdgcn_sdot8>;
 def V_DOT8_U32_U4  : VOP3PInst<"v_dot8_u32_u4", VOP3_Profile<VOP_I32_I32_I32_I32, VOP3_PACKED>, int_amdgcn_udot8>;
 
+def : UDot2Pat<V_DOT2_U32_U16>;
+def : SDot2Pat<V_DOT2_I32_I16>;
+
 } // End SubtargetPredicate = HasDLInsts
 
 multiclass VOP3P_Real_vi<bits<10> op> {
Index: test/CodeGen/AMDGPU/idot2.ll
===================================================================
--- /dev/null
+++ test/CodeGen/AMDGPU/idot2.ll
@@ -0,0 +1,600 @@
+; RUN: llc -march=amdgcn -mcpu=gfx900 -verify-machineinstrs < %s | FileCheck %s  -check-prefixes=GCN,GFX900
+; RUN: llc -march=amdgcn -mcpu=gfx906 -verify-machineinstrs < %s | FileCheck %s  -check-prefixes=GCN,GFX906
+
+; add(mul(S0.x, S1.y),
+;     add (mul (S0.y, S1.y), S3)) -> v_dot2_{I|U}32_{I|U}16(S1, S2, S3)
+
+; GCN-LABEL: {{^}}udot2
+
+; GFX900: v_mad_u32_u24
+; GFX900: v_mad_u32_u24
+
+; GFX906: v_dot2_u32_u16
+define amdgpu_kernel void @udot2(<2 x i16> addrspace(1)* %src1,
+                                 <2 x i16> addrspace(1)* %src2,
+                                 i32 addrspace(1)* nocapture %dst) {
+entry:
+  %vec1 = load <2 x i16>, <2 x i16> addrspace(1)* %src1
+  %vec2 = load <2 x i16>, <2 x i16> addrspace(1)* %src2
+
+  %s1.elt1 = extractelement <2 x i16> %vec1, i64 0
+  %conv = zext i16 %s1.elt1 to i32
+  %s2.elt1 = extractelement <2 x i16> %vec2, i64 0
+  %conv2 = zext i16 %s2.elt1 to i32
+  %mul1 = mul nuw i32 %conv2, %conv
+
+  %s1.elt2 = extractelement <2 x i16> %vec1, i64 1
+  %conv3 = zext i16 %s1.elt2 to i32
+  %s2.elt2 = extractelement <2 x i16> %vec2, i64 1
+  %conv4 = zext i16 %s2.elt2 to i32
+  %mul2 = mul nuw i32 %conv4, %conv3
+
+  %s3 = load i32, i32 addrspace(1)* %dst, align 4
+  %add = add i32 %mul2, %s3
+  %add6 = add i32 %add, %mul1
+  store i32 %add6, i32 addrspace(1)* %dst, align 4
+  ret void
+}
+
+; TODO: Support this pattern
+;      add(S3,
+;          add (mul (S0.y, S1.y), mul (S0.y, S1.y))) -> v_dot2_{I|U}32_{I|U}16(S1, S2, S3)
+; GCN-LABEL: {{^}}udot2_MulMul
+
+; GFX900: v_add_u32_e32
+
+; GFX906: v_add_u32_e32
+define amdgpu_kernel void @udot2_MulMul(<2 x i16> addrspace(1)* %src1,
+                                        <2 x i16> addrspace(1)* %src2,
+                                        i32 addrspace(1)* nocapture %dst) {
+entry:
+  %vec1 = load <2 x i16>, <2 x i16> addrspace(1)* %src1
+  %vec2 = load <2 x i16>, <2 x i16> addrspace(1)* %src2
+
+  %s1.elt1 = extractelement <2 x i16> %vec1, i64 0
+  %conv = zext i16 %s1.elt1 to i32
+  %s2.elt1 = extractelement <2 x i16> %vec2, i64 0
+  %conv2 = zext i16 %s2.elt1 to i32
+  %mul1 = mul nuw i32 %conv2, %conv
+
+  %s1.elt2 = extractelement <2 x i16> %vec1, i64 1
+  %conv3 = zext i16 %s1.elt2 to i32
+  %s2.elt2 = extractelement <2 x i16> %vec2, i64 1
+  %conv4 = zext i16 %s2.elt2 to i32
+  %mul2 = mul nuw i32 %conv4, %conv3
+
+  %s3 = load i32, i32 addrspace(1)* %dst, align 4
+  %add = add i32 %mul2, %mul1
+  %add6 = add i32 %add, %s3
+  store i32 %add6, i32 addrspace(1)* %dst, align 4
+  ret void
+}
+
+; GCN-LABEL: {{^}}idot2
+
+; GFX900: v_mad_i32_i24
+; GFX900: v_mad_i32_i24
+
+; GFX906: v_dot2_i32_i16
+define amdgpu_kernel void @idot2(<2 x i16> addrspace(1)* %src1,
+                                 <2 x i16> addrspace(1)* %src2,
+                                 i32 addrspace(1)* nocapture %dst) {
+entry:
+  %vec1 = load <2 x i16>, <2 x i16> addrspace(1)* %src1
+  %vec2 = load <2 x i16>, <2 x i16> addrspace(1)* %src2
+
+  %s1.elt1 = extractelement <2 x i16> %vec1, i64 0
+  %conv = sext i16 %s1.elt1 to i32
+  %s2.elt1 = extractelement <2 x i16> %vec2, i64 0
+  %conv2 = sext i16 %s2.elt1 to i32
+  %mul1 = mul nuw i32 %conv2, %conv
+
+  %s1.elt2 = extractelement <2 x i16> %vec1, i64 1
+  %conv3 = sext i16 %s1.elt2 to i32
+  %s2.elt2 = extractelement <2 x i16> %vec2, i64 1
+  %conv4 = sext i16 %s2.elt2 to i32
+  %mul2 = mul nuw i32 %conv4, %conv3
+
+  %s3 = load i32, i32 addrspace(1)* %dst, align 4
+  %add = add i32 %mul2, %s3
+  %add6 = add i32 %add, %mul1
+  store i32 %add6, i32 addrspace(1)* %dst, align 4
+  ret void
+}
+
+; GCN-LABEL: {{^}}idot2_MixedTypedMul
+
+; GFX900: v_mad_i32_i24
+
+; GFX906: v_mad_i32_i24
+define amdgpu_kernel void @idot2_MixedTypedMul(<2 x i16> addrspace(1)* %src1,
+                                               <2 x i16> addrspace(1)* %src2,
+                                               i32 addrspace(1)* nocapture %dst) {
+entry:
+  %vec1 = load <2 x i16>, <2 x i16> addrspace(1)* %src1
+  %vec2 = load <2 x i16>, <2 x i16> addrspace(1)* %src2
+
+  %s1.elt1 = extractelement <2 x i16> %vec1, i64 0
+  %conv = sext i16 %s1.elt1 to i32
+  %s2.elt1 = extractelement <2 x i16> %vec2, i64 0
+  %conv2 = sext i16 %s2.elt1 to i32
+  %mul1 = mul nuw i32 %conv2, %conv
+
+  %s1.elt2 = extractelement <2 x i16> %vec1, i64 1
+  %conv3 = zext i16 %s1.elt2 to i32
+  %s2.elt2 = extractelement <2 x i16> %vec2, i64 1
+  %conv4 = zext i16 %s2.elt2 to i32
+  %mul2 = mul nuw i32 %conv4, %conv3
+
+  %s3 = load i32, i32 addrspace(1)* %dst, align 4
+  %add = add i32 %mul2, %s3
+  %add6 = add i32 %add, %mul1
+  store i32 %add6, i32 addrspace(1)* %dst, align 4
+  ret void
+}
+
+; GCN-LABEL: {{^}}udot2_alt_AddOperands
+
+; GFX900: v_mad_u32_u24
+; GFX900: v_mad_u32_u24
+
+; GFX906: v_dot2_u32_u16
+define amdgpu_kernel void @udot2_alt_AddOperands(<2 x i16> addrspace(1)* %src1,
+                                                 <2 x i16> addrspace(1)* %src2,
+                                                 i32 addrspace(1)* nocapture %dst) {
+entry:
+  %vec1 = load <2 x i16>, <2 x i16> addrspace(1)* %src1
+  %vec2 = load <2 x i16>, <2 x i16> addrspace(1)* %src2
+
+  %s1.elt1 = extractelement <2 x i16> %vec1, i64 0
+  %conv = zext i16 %s1.elt1 to i32
+  %s2.elt1 = extractelement <2 x i16> %vec2, i64 0
+  %conv2 = zext i16 %s2.elt1 to i32
+  %mul1 = mul nuw i32 %conv2, %conv
+
+  %s1.elt2 = extractelement <2 x i16> %vec1, i64 1
+  %conv3 = zext i16 %s1.elt2 to i32
+  %s2.elt2 = extractelement <2 x i16> %vec2, i64 1
+  %conv4 = zext i16 %s2.elt2 to i32
+  %mul2 = mul nuw i32 %conv4, %conv3
+
+  %s3 = load i32, i32 addrspace(1)* %dst, align 4
+  %add = add i32 %s3, %mul2
+  %add6 = add i32 %mul1, %add
+  store i32 %add6, i32 addrspace(1)* %dst, align 4
+  ret void
+}
+
+; GCN-LABEL: {{^}}idot2_MixedExt
+
+; GFX900: v_mad_i32_i24
+; GFX900: v_mad_i32_i24
+
+; GFX906: v_mad_i32_i24
+define amdgpu_kernel void @idot2_MixedExt(<2 x i16> addrspace(1)* %src1,
+                                          <2 x i16> addrspace(1)* %src2,
+                                          i32 addrspace(1)* nocapture %dst) {
+entry:
+  %vec1 = load <2 x i16>, <2 x i16> addrspace(1)* %src1
+  %vec2 = load <2 x i16>, <2 x i16> addrspace(1)* %src2
+
+  %s1.elt1 = extractelement <2 x i16> %vec1, i64 0
+  %conv = sext i16 %s1.elt1 to i32
+  %s2.elt1 = extractelement <2 x i16> %vec2, i64 0
+  %conv2 = zext i16 %s2.elt1 to i32
+  %mul1 = mul nuw i32 %conv2, %conv
+
+  %s1.elt2 = extractelement <2 x i16> %vec1, i64 1
+  %conv3 = sext i16 %s1.elt2 to i32
+  %s2.elt2 = extractelement <2 x i16> %vec2, i64 1
+  %conv4 = sext i16 %s2.elt2 to i32
+  %mul2 = mul nuw i32 %conv4, %conv3
+
+  %s3 = load i32, i32 addrspace(1)* %dst, align 4
+  %add = add i32 %mul2, %s3
+  %add6 = add i32 %add, %mul1
+  store i32 %add6, i32 addrspace(1)* %dst, align 4
+  ret void
+}
+
+; GCN-LABEL: {{^}}notudot2_SameVec
+
+; GFX900: v_mad_u32_u24
+
+; GFX906: v_mad_u32_u24
+define amdgpu_kernel void @notudot2_SameVec(<2 x i16> addrspace(1)* %src1,
+                                            <2 x i16> addrspace(1)* %src2,
+                                            i32 addrspace(1)* nocapture %dst) {
+entry:
+  %vec1 = load <2 x i16>, <2 x i16> addrspace(1)* %src1
+  %vec2 = load <2 x i16>, <2 x i16> addrspace(1)* %src2
+
+  %s1.elt1 = extractelement <2 x i16> %vec1, i64 0
+  %conv = zext i16 %s1.elt1 to i32
+  %s2.elt1 = extractelement <2 x i16> %vec1, i64 0
+  %conv2 = zext i16 %s2.elt1 to i32
+  %mul1 = mul i32 %conv2, %conv
+
+  %s1.elt2 = extractelement <2 x i16> %vec2, i64 1
+  %conv3 = zext i16 %s1.elt2 to i32
+  %s2.elt2 = extractelement <2 x i16> %vec2, i64 1
+  %conv4 = zext i16 %s2.elt2 to i32
+  %mul2 = mul i32 %conv4, %conv3
+
+  %s3 = load i32, i32 addrspace(1)* %dst, align 4
+  %add = add i32 %mul2, %s3
+  %add6 = add i32 %add, %mul1
+  store i32 %add6, i32 addrspace(1)* %dst, align 4
+  ret void
+}
+
+; GCN-LABEL: {{^}}udot2_v4i16
+
+; GFX900: v_mad_u32_u24
+
+; GFX906: v_dot2_u32_u16 v2
+define amdgpu_kernel void @udot2_v4i16(<4 x i16> addrspace(1)* %src1,
+                                       <4 x i16> addrspace(1)* %src2,
+                                       i32 addrspace(1)* nocapture %dst) {
+entry:
+  %vec1 = load <4 x i16>, <4 x i16> addrspace(1)* %src1
+  %vec2 = load <4 x i16>, <4 x i16> addrspace(1)* %src2
+
+  %s1.elt1 = extractelement <4 x i16> %vec1, i64 0
+  %conv = zext i16 %s1.elt1 to i32
+  %s2.elt1 = extractelement <4 x i16> %vec2, i64 0
+  %conv2 = zext i16 %s2.elt1 to i32
+  %mul1 = mul i32 %conv2, %conv
+
+  %s1.elt2 = extractelement <4 x i16> %vec1, i64 1
+  %conv3 = zext i16 %s1.elt2 to i32
+  %s2.elt2 = extractelement <4 x i16> %vec2, i64 1
+  %conv4 = zext i16 %s2.elt2 to i32
+  %mul2 = mul i32 %conv4, %conv3
+
+  %s3 = load i32, i32 addrspace(1)* %dst, align 4
+  %add = add i32 %mul2, %s3
+  %add6 = add i32 %add, %mul1
+  store i32 %add6, i32 addrspace(1)* %dst, align 4
+  ret void
+}
+
+; GCN-LABEL: {{^}}udot2_v4i16_Hi
+
+; GFX900: v_mad_u32_u24
+
+; GFX906: v_dot2_u32_u16 v2
+define amdgpu_kernel void @udot2_v4i16_Hi(<4 x i16> addrspace(1)* %src1,
+                                          <4 x i16> addrspace(1)* %src2,
+                                          i32 addrspace(1)* nocapture %dst) {
+entry:
+  %vec1 = load <4 x i16>, <4 x i16> addrspace(1)* %src1
+  %vec2 = load <4 x i16>, <4 x i16> addrspace(1)* %src2
+
+  %s1.elt1 = extractelement <4 x i16> %vec1, i64 2
+  %conv = zext i16 %s1.elt1 to i32
+  %s2.elt1 = extractelement <4 x i16> %vec2, i64 2
+  %conv2 = zext i16 %s2.elt1 to i32
+  %mul1 = mul i32 %conv2, %conv
+
+  %s1.elt2 = extractelement <4 x i16> %vec1, i64 3
+  %conv3 = zext i16 %s1.elt2 to i32
+  %s2.elt2 = extractelement <4 x i16> %vec2, i64 3
+  %conv4 = zext i16 %s2.elt2 to i32
+  %mul2 = mul i32 %conv4, %conv3
+
+  %s3 = load i32, i32 addrspace(1)* %dst, align 4
+  %add = add i32 %mul2, %s3
+  %add6 = add i32 %add, %mul1
+  store i32 %add6, i32 addrspace(1)* %dst, align 4
+  ret void
+}
+
+
+; GCN-LABEL: {{^}}notudot2_v4i16_Even
+
+; GFX900: v_mad_u32_u24
+
+; GFX906-NOT: v_dot2_u32_u16
+; GFX906-NOT: v_dot2_i32_i16
+define amdgpu_kernel void @notudot2_v4i16_Even(<4 x i16> addrspace(1)* %src1,
+                                               <4 x i16> addrspace(1)* %src2,
+                                               i32 addrspace(1)* nocapture %dst) {
+entry:
+  %vec1 = load <4 x i16>, <4 x i16> addrspace(1)* %src1
+  %vec2 = load <4 x i16>, <4 x i16> addrspace(1)* %src2
+
+  %s1.elt1 = extractelement <4 x i16> %vec1, i64 0
+  %conv = zext i16 %s1.elt1 to i32
+  %s2.elt1 = extractelement <4 x i16> %vec2, i64 0
+  %conv2 = zext i16 %s2.elt1 to i32
+  %mul1 = mul i32 %conv2, %conv
+
+  %s1.elt2 = extractelement <4 x i16> %vec1, i64 2
+  %conv3 = zext i16 %s1.elt2 to i32
+  %s2.elt2 = extractelement <4 x i16> %vec2, i64 2
+  %conv4 = zext i16 %s2.elt2 to i32
+  %mul2 = mul i32 %conv4, %conv3
+
+  %s3 = load i32, i32 addrspace(1)* %dst, align 4
+  %add = add i32 %mul2, %s3
+  %add6 = add i32 %add, %mul1
+  store i32 %add6, i32 addrspace(1)* %dst, align 4
+  ret void
+}
+
+; GCN-LABEL: {{^}}notudot2_v4i16_Middle
+
+; GFX900: v_mad_u32_u24
+
+; GFX906-NOT: v_dot2_u32_u16
+; GFX906-NOT: v_dot2_i32_i16
+define amdgpu_kernel void @notudot2_v4i16_Middle(<4 x i16> addrspace(1)* %src1,
+                                                 <4 x i16> addrspace(1)* %src2,
+                                                 i32 addrspace(1)* nocapture %dst) {
+entry:
+  %vec1 = load <4 x i16>, <4 x i16> addrspace(1)* %src1
+  %vec2 = load <4 x i16>, <4 x i16> addrspace(1)* %src2
+
+  %s1.elt1 = extractelement <4 x i16> %vec1, i64 1
+  %conv = zext i16 %s1.elt1 to i32
+  %s2.elt1 = extractelement <4 x i16> %vec2, i64 1
+  %conv2 = zext i16 %s2.elt1 to i32
+  %mul1 = mul i32 %conv2, %conv
+
+  %s1.elt2 = extractelement <4 x i16> %vec1, i64 2
+  %conv3 = zext i16 %s1.elt2 to i32
+  %s2.elt2 = extractelement <4 x i16> %vec2, i64 2
+  %conv4 = zext i16 %s2.elt2 to i32
+  %mul2 = mul i32 %conv4, %conv3
+
+  %s3 = load i32, i32 addrspace(1)* %dst, align 4
+  %add = add i32 %mul2, %s3
+  %add6 = add i32 %add, %mul1
+  store i32 %add6, i32 addrspace(1)* %dst, align 4
+  ret void
+}
+
+; GCN-LABEL: {{^}}notudot2_DiffIndex
+
+; GFX900: v_mad_u32_u24
+
+; GFX906-NOT: v_dot2_u32_u16
+; GFX906-NOT: v_dot2_i32_i16
+define amdgpu_kernel void @notudot2_DiffIndex(<2 x i16> addrspace(1)* %src1,
+                                              <2 x i16> addrspace(1)* %src2,
+                                              i32 addrspace(1)* nocapture %dst) {
+entry:
+  %vec1 = load <2 x i16>, <2 x i16> addrspace(1)* %src1
+  %vec2 = load <2 x i16>, <2 x i16> addrspace(1)* %src2
+
+  %s1.elt1 = extractelement <2 x i16> %vec1, i64 0
+  %conv = zext i16 %s1.elt1 to i32
+  %s2.elt1 = extractelement <2 x i16> %vec2, i64 1
+  %conv2 = zext i16 %s2.elt1 to i32
+  %mul1 = mul i32 %conv2, %conv
+
+  %s1.elt2 = extractelement <2 x i16> %vec1, i64 1
+  %conv3 = zext i16 %s1.elt2 to i32
+  %s2.elt2 = extractelement <2 x i16> %vec2, i64 0
+  %conv4 = zext i16 %s2.elt2 to i32
+  %mul2 = mul i32 %conv4, %conv3
+
+  %s3 = load i32, i32 addrspace(1)* %dst, align 4
+  %add = add i32 %mul2, %s3
+  %add6 = add i32 %add, %mul1
+  store i32 %add6, i32 addrspace(1)* %dst, align 4
+  ret void
+}
+
+; GCN-LABEL: {{^}}udot2_MultipleUses_add1
+
+; GFX900: v_mad_u32_u24
+
+; GFX906-NOT: v_dot2_u32_u16
+; GFX906-NOT: v_dot2_i32_i16
+define amdgpu_kernel void @udot2_MultipleUses_add1(<2 x i16> addrspace(1)* %src1,
+                                                  <2 x i16> addrspace(1)* %src2,
+                                                  i32 addrspace(1)* nocapture %dst) {
+entry:
+  %vec1 = load <2 x i16>, <2 x i16> addrspace(1)* %src1
+  %vec2 = load <2 x i16>, <2 x i16> addrspace(1)* %src2
+
+  %s1.elt1 = extractelement <2 x i16> %vec1, i64 0
+  %conv = zext i16 %s1.elt1 to i32
+  %s2.elt1 = extractelement <2 x i16> %vec2, i64 0
+  %conv2 = zext i16 %s2.elt1 to i32
+  %mul1 = mul i32 %conv2, %conv
+
+  %s1.elt2 = extractelement <2 x i16> %vec1, i64 1
+  %conv3 = zext i16 %s1.elt2 to i32
+  %s2.elt2 = extractelement <2 x i16> %vec2, i64 1
+  %conv4 = zext i16 %s2.elt2 to i32
+  %mul2 = mul i32 %conv4, %conv3
+
+  %s3 = load i32, i32 addrspace(1)* %dst, align 4
+  %add1 = add i32 %mul2, %s3
+  %add2 = add i32 %add1, %mul1
+
+  %res = add i32 %add2, %add1
+  store i32 %res, i32 addrspace(1)* %dst, align 4
+  ret void
+}
+
+; GCN-LABEL: {{^}}idot2_MultipleUses_add1
+
+; GFX900: v_mad_i32_i24
+
+; GFX906-NOT: v_dot2_i32_i16
+; GFX906-NOT: v_dot2_u32_u16
+define amdgpu_kernel void @idot2_MultipleUses_add1(<2 x i16> addrspace(1)* %src1,
+                                                   <2 x i16> addrspace(1)* %src2,
+                                                   i32 addrspace(1)* nocapture %dst) {
+entry:
+  %vec1 = load <2 x i16>, <2 x i16> addrspace(1)* %src1
+  %vec2 = load <2 x i16>, <2 x i16> addrspace(1)* %src2
+
+  %s1.elt1 = extractelement <2 x i16> %vec1, i64 0
+  %conv = sext i16 %s1.elt1 to i32
+  %s2.elt1 = extractelement <2 x i16> %vec2, i64 0
+  %conv2 = sext i16 %s2.elt1 to i32
+  %mul1 = mul i32 %conv2, %conv
+
+  %s1.elt2 = extractelement <2 x i16> %vec1, i64 1
+  %conv3 = sext i16 %s1.elt2 to i32
+  %s2.elt2 = extractelement <2 x i16> %vec2, i64 1
+  %conv4 = sext i16 %s2.elt2 to i32
+  %mul2 = mul i32 %conv4, %conv3
+
+  %s3 = load i32, i32 addrspace(1)* %dst, align 4
+  %add1 = add i32 %mul2, %s3
+  %add2 = add i32 %add1, %mul1
+
+  %res = add i32 %add2, %add1
+  store i32 %res, i32 addrspace(1)* %dst, align 4
+  ret void
+}
+
+; GCN-LABEL: {{^}}udot2_MultipleUses_mul1
+
+; GFX900: v_mad_u32_u24
+
+; GFX906-NOT: v_dot2_u32_u16
+; GFX906-NOT: v_dot2_i32_i16
+define amdgpu_kernel void @udot2_MultipleUses_mul1(<2 x i16> addrspace(1)* %src1,
+                                                   <2 x i16> addrspace(1)* %src2,
+                                                   i32 addrspace(1)* nocapture %dst) {
+entry:
+  %vec1 = load <2 x i16>, <2 x i16> addrspace(1)* %src1
+  %vec2 = load <2 x i16>, <2 x i16> addrspace(1)* %src2
+
+  %s1.elt1 = extractelement <2 x i16> %vec1, i64 0
+  %conv = zext i16 %s1.elt1 to i32
+  %s2.elt1 = extractelement <2 x i16> %vec2, i64 0
+  %conv2 = zext i16 %s2.elt1 to i32
+  %mul1 = mul i32 %conv2, %conv
+
+  %s1.elt2 = extractelement <2 x i16> %vec1, i64 1
+  %conv3 = zext i16 %s1.elt2 to i32
+  %s2.elt2 = extractelement <2 x i16> %vec2, i64 1
+  %conv4 = zext i16 %s2.elt2 to i32
+  %mul2 = mul i32 %conv4, %conv3
+
+  %s3 = load i32, i32 addrspace(1)* %dst, align 4
+  %add0 = add i32 %mul1, %s3
+
+  %add1 = add i32 %mul2, %add0
+  %add2 = add i32 %add1, %mul1
+
+  store i32 %add2, i32 addrspace(1)* %dst, align 4
+  ret void
+}
+
+; GCN-LABEL: {{^}}idot2_MultipleUses_mul1
+
+; GFX900: v_mad_i32_i24
+
+; GFX906-NOT: v_dot2_i32_i16
+; GFX906-NOT: v_dot2_u32_u16
+define amdgpu_kernel void @idot2_MultipleUses_mul1(<2 x i16> addrspace(1)* %src1,
+                                                   <2 x i16> addrspace(1)* %src2,
+                                                   i32 addrspace(1)* nocapture %dst) {
+entry:
+  %vec1 = load <2 x i16>, <2 x i16> addrspace(1)* %src1
+  %vec2 = load <2 x i16>, <2 x i16> addrspace(1)* %src2
+
+  %s1.elt1 = extractelement <2 x i16> %vec1, i64 0
+  %conv = sext i16 %s1.elt1 to i32
+  %s2.elt1 = extractelement <2 x i16> %vec2, i64 0
+  %conv2 = sext i16 %s2.elt1 to i32
+  %mul1 = mul i32 %conv2, %conv
+
+  %s1.elt2 = extractelement <2 x i16> %vec1, i64 1
+  %conv3 = sext i16 %s1.elt2 to i32
+  %s2.elt2 = extractelement <2 x i16> %vec2, i64 1
+  %conv4 = sext i16 %s2.elt2 to i32
+  %mul2 = mul i32 %conv4, %conv3
+
+  %s3 = load i32, i32 addrspace(1)* %dst, align 4
+  %add0 = add i32 %mul1, %s3
+
+  %add1 = add i32 %mul2, %add0
+  %add2 = add i32 %add1, %mul1
+
+  store i32 %add2, i32 addrspace(1)* %dst, align 4
+  ret void
+}
+
+; GCN-LABEL: {{^}}udot2_MultipleUses_mul2
+
+; GFX900: v_mad_u32_u24
+; GFX900: v_mad_u32_u24
+; GFX900: v_mad_u32_u24
+
+; GFX906-NOT: v_dot2_i32_i16
+; GFX906-NOT: v_dot2_u32_u16
+define amdgpu_kernel void @udot2_MultipleUses_mul2(<2 x i16> addrspace(1)* %src1,
+                                                   <2 x i16> addrspace(1)* %src2,
+                                                   i32 addrspace(1)* nocapture %dst) {
+entry:
+  %vec1 = load <2 x i16>, <2 x i16> addrspace(1)* %src1
+  %vec2 = load <2 x i16>, <2 x i16> addrspace(1)* %src2
+
+  %s1.elt1 = extractelement <2 x i16> %vec1, i64 0
+  %conv = zext i16 %s1.elt1 to i32
+  %s2.elt1 = extractelement <2 x i16> %vec2, i64 0
+  %conv2 = zext i16 %s2.elt1 to i32
+  %mul1 = mul i32 %conv2, %conv
+
+  %s1.elt2 = extractelement <2 x i16> %vec1, i64 1
+  %conv3 = zext i16 %s1.elt2 to i32
+  %s2.elt2 = extractelement <2 x i16> %vec2, i64 1
+  %conv4 = zext i16 %s2.elt2 to i32
+  %mul2 = mul i32 %conv4, %conv3
+
+  %s3 = load i32, i32 addrspace(1)* %dst, align 4
+  %add0 = add i32 %mul2, %s3
+
+  %add1 = add i32 %mul2, %add0
+  %add2 = add i32 %add1, %mul1
+
+  store i32 %add2, i32 addrspace(1)* %dst, align 4
+  ret void
+}
+
+; GCN-LABEL: {{^}}idot2_MultipleUses_mul2
+
+; GFX900: v_mad_i32_i24
+; GFX900: v_mad_i32_i24
+; GFX900: v_mad_i32_i24
+
+; GFX906-NOT: v_dot2_i32_i16
+; GFX906-NOT: v_dot2_u32_u16
+define amdgpu_kernel void @idot2_MultipleUses_mul2(<2 x i16> addrspace(1)* %src1,
+                                                   <2 x i16> addrspace(1)* %src2,
+                                                   i32 addrspace(1)* nocapture %dst) {
+entry:
+  %vec1 = load <2 x i16>, <2 x i16> addrspace(1)* %src1
+  %vec2 = load <2 x i16>, <2 x i16> addrspace(1)* %src2
+
+  %s1.elt1 = extractelement <2 x i16> %vec1, i64 0
+  %conv = sext i16 %s1.elt1 to i32
+  %s2.elt1 = extractelement <2 x i16> %vec2, i64 0
+  %conv2 = sext i16 %s2.elt1 to i32
+  %mul1 = mul i32 %conv2, %conv
+
+  %s1.elt2 = extractelement <2 x i16> %vec1, i64 1
+  %conv3 = sext i16 %s1.elt2 to i32
+  %s2.elt2 = extractelement <2 x i16> %vec2, i64 1
+  %conv4 = sext i16 %s2.elt2 to i32
+  %mul2 = mul i32 %conv4, %conv3
+
+  %s3 = load i32, i32 addrspace(1)* %dst, align 4
+  %add0 = add i32 %mul2, %s3
+
+  %add1 = add i32 %mul2, %add0
+  %add2 = add i32 %add1, %mul1
+
+  store i32 %add2, i32 addrspace(1)* %dst, align 4
+  ret void
+}