Index: llvm/lib/Target/PowerPC/PPCInstrInfo.cpp =================================================================== --- llvm/lib/Target/PowerPC/PPCInstrInfo.cpp +++ llvm/lib/Target/PowerPC/PPCInstrInfo.cpp @@ -987,7 +987,7 @@ Opc = PPC::XXLOR; else if (PPC::VSFRCRegClass.contains(DestReg, SrcReg) || PPC::VSSRCRegClass.contains(DestReg, SrcReg)) - Opc = PPC::XXLORf; + Opc = (Subtarget.hasP9Vector()) ? PPC::XSCPSGNDP : PPC::XXLORf; else if (PPC::QFRCRegClass.contains(DestReg, SrcReg)) Opc = PPC::QVFMR; else if (PPC::QSRCRegClass.contains(DestReg, SrcReg)) Index: llvm/test/CodeGen/PowerPC/builtins-ppc-p9-f128.ll =================================================================== --- llvm/test/CodeGen/PowerPC/builtins-ppc-p9-f128.ll +++ llvm/test/CodeGen/PowerPC/builtins-ppc-p9-f128.ll @@ -96,7 +96,7 @@ ret double %0 ; CHECK-LABEL: testTruncOdd ; CHECK: xscvqpdpo v2, v2 -; CHECK: xxlor f1, v2, v2 +; CHECK: xscpsgndp f1, v2, v2 ; CHECK: blr } Index: llvm/test/CodeGen/PowerPC/f128-conv.ll =================================================================== --- llvm/test/CodeGen/PowerPC/f128-conv.ll +++ llvm/test/CodeGen/PowerPC/f128-conv.ll @@ -26,7 +26,7 @@ ; Function Attrs: norecurse nounwind define void @sdwConv2qp_02(fp128* nocapture %a) { entry: - %0 = load i64, i64* getelementptr inbounds + %0 = load i64, i64* getelementptr inbounds ([5 x i64], [5 x i64]* @mem, i64 0, i64 2), align 8 %conv = sitofp i64 %0 to fp128 store fp128 %conv, fp128* %a, align 16 @@ -362,7 +362,7 @@ ; Function Attrs: norecurse nounwind define void @ubConv2qp_03(fp128* nocapture %a) { entry: - %0 = load i8, i8* getelementptr inbounds + %0 = load i8, i8* getelementptr inbounds ([5 x i8], [5 x i8]* @ubMem, i64 0, i64 2), align 1 %conv = uitofp i8 %0 to fp128 store fp128 %conv, fp128* %a, align 16 @@ -414,7 +414,7 @@ ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: lxv v2, 0(r3) ; CHECK-NEXT: xscvqpdp v2, v2 -; CHECK-NEXT: xxlor f1, v2, v2 +; CHECK-NEXT: xscpsgndp f1, v2, v2 ; CHECK-NEXT: blr entry: %0 = load fp128, fp128* %a, align 16 @@ -559,7 +559,7 @@ define fp128 @dpConv2qp(double %a) { ; CHECK-LABEL: dpConv2qp: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: xxlor v2, f1, f1 +; CHECK-NEXT: xscpsgndp v2, f1, f1 ; CHECK-NEXT: xscvdpqp v2, v2 ; CHECK-NEXT: blr entry: @@ -608,7 +608,7 @@ define void @dpConv2qp_03(fp128* nocapture %res, i32 signext %idx, double %a) { ; CHECK-LABEL: dpConv2qp_03: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: xxlor v2, f1, f1 +; CHECK-NEXT: xscpsgndp v2, f1, f1 ; CHECK-NEXT: sldi r4, r4, 4 ; CHECK-NEXT: xscvdpqp v2, v2 ; CHECK-NEXT: stxvx v2, r3, r4 @@ -625,7 +625,7 @@ define void @dpConv2qp_04(double %a, fp128* nocapture %res) { ; CHECK-LABEL: dpConv2qp_04: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: xxlor v2, f1, f1 +; CHECK-NEXT: xscpsgndp v2, f1, f1 ; CHECK-NEXT: xscvdpqp v2, v2 ; CHECK-NEXT: stxv v2, 0(r4) ; CHECK-NEXT: blr @@ -639,7 +639,7 @@ define fp128 @spConv2qp(float %a) { ; CHECK-LABEL: spConv2qp: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: xxlor v2, f1, f1 +; CHECK-NEXT: xscpsgndp v2, f1, f1 ; CHECK-NEXT: xscvdpqp v2, v2 ; CHECK-NEXT: blr entry: @@ -688,7 +688,7 @@ define void @spConv2qp_03(fp128* nocapture %res, i32 signext %idx, float %a) { ; CHECK-LABEL: spConv2qp_03: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: xxlor v2, f1, f1 +; CHECK-NEXT: xscpsgndp v2, f1, f1 ; CHECK-NEXT: sldi r4, r4, 4 ; CHECK-NEXT: xscvdpqp v2, v2 ; CHECK-NEXT: stxvx v2, r3, r4 @@ -705,7 +705,7 @@ define void @spConv2qp_04(float %a, fp128* nocapture %res) { ; CHECK-LABEL: spConv2qp_04: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: xxlor v2, f1, f1 +; CHECK-NEXT: xscpsgndp v2, f1, f1 ; CHECK-NEXT: xscvdpqp v2, v2 ; CHECK-NEXT: stxv v2, 0(r4) ; CHECK-NEXT: blr Index: llvm/test/CodeGen/PowerPC/f128-passByValue.ll =================================================================== --- llvm/test/CodeGen/PowerPC/f128-passByValue.ll +++ llvm/test/CodeGen/PowerPC/f128-passByValue.ll @@ -154,7 +154,7 @@ ; CHECK: # %bb.0: # %entry ; CHECK-DAG: lwz r3, 96(r1) ; CHECK: add r4, r7, r9 -; CHECK-NEXT: xxlor v[[REG0:[0-9]+]], f1, f1 +; CHECK-NEXT: xscpsgndp v[[REG0:[0-9]+]], f1, f1 ; CHECK-DAG: add r4, r4, r10 ; CHECK: xscvdpqp v[[REG0]], v[[REG0]] ; CHECK-NEXT: add r3, r4, r3 @@ -186,7 +186,7 @@ ; CHECK-LABEL: mixParam_02f: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: add r4, r4, r6 -; CHECK-NEXT: xxlor v[[REG0:[0-9]+]], f1, f1 +; CHECK-NEXT: xscpsgndp v[[REG0:[0-9]+]], f1, f1 ; CHECK-NEXT: add r4, r4, r7 ; CHECK-NEXT: xscvdpqp v[[REG0]], v[[REG0]] ; CHECK-NEXT: add r4, r4, r8 Index: llvm/test/CodeGen/PowerPC/p8-scalar_vector_conversions.ll =================================================================== --- llvm/test/CodeGen/PowerPC/p8-scalar_vector_conversions.ll +++ llvm/test/CodeGen/PowerPC/p8-scalar_vector_conversions.ll @@ -1,5 +1,9 @@ -; RUN: llc < %s -mtriple=powerpc64-unknown-linux-gnu -mcpu=pwr8 | FileCheck %s -; RUN: llc < %s -mtriple=powerpc64le-unknown-linux-gnu -mcpu=pwr8 | FileCheck %s -check-prefix=CHECK-LE +; RUN: llc < %s -ppc-vsr-nums-as-vr -mtriple=powerpc64-unknown-linux-gnu \ +; RUN: -verify-machineinstrs -ppc-asm-full-reg-names -mcpu=pwr8 \ +; RUN: | FileCheck %s +; RUN: llc < %s -ppc-vsr-nums-as-vr -mtriple=powerpc64le-unknown-linux-gnu \ +; RUN: -verify-machineinstrs -ppc-asm-full-reg-names -mcpu=pwr8 \ +; RUN: | FileCheck %s -check-prefix=CHECK-LE ; The build[csilf] functions simply test the scalar_to_vector handling with ; direct moves. This corresponds to the "insertelement" instruction. Subsequent @@ -13,10 +17,12 @@ %splat.splatinsert = insertelement <16 x i8> undef, i8 %a, i32 0 %splat.splat = shufflevector <16 x i8> %splat.splatinsert, <16 x i8> undef, <16 x i32> zeroinitializer ret <16 x i8> %splat.splat -; CHECK: sldi [[REG1:[0-9]+]], 3, 56 -; CHECK: mtvsrd {{[0-9]+}}, [[REG1]] -; CHECK-LE: mtvsrd [[REG1:[0-9]+]], 3 -; CHECK-LE: xxswapd {{[0-9]+}}, [[REG1]] +; CHECK-LABEL: buildc +; CHECK: sldi r3, r3, 56 +; CHECK: mtvsrd v2, r3 +; CHECK-LE-LABEL: buildc +; CHECK-LE: mtvsrd f0, r3 +; CHECK-LE: xxswapd v2, vs0 } ; Function Attrs: norecurse nounwind readnone @@ -25,10 +31,12 @@ %splat.splatinsert = insertelement <8 x i16> undef, i16 %a, i32 0 %splat.splat = shufflevector <8 x i16> %splat.splatinsert, <8 x i16> undef, <8 x i32> zeroinitializer ret <8 x i16> %splat.splat -; CHECK: sldi [[REG1:[0-9]+]], 3, 48 -; CHECK: mtvsrd {{[0-9]+}}, [[REG1]] -; CHECK-LE: mtvsrd [[REG1:[0-9]+]], 3 -; CHECK-LE: xxswapd {{[0-9]+}}, [[REG1]] +; CHECK-LABEL: builds +; CHECK: sldi r3, r3, 48 +; CHECK: mtvsrd v2, r3 +; CHECK-LE-LABEL: builds +; CHECK-LE: mtvsrd f0, r3 +; CHECK-LE: xxswapd v2, vs0 } ; Function Attrs: norecurse nounwind readnone @@ -37,10 +45,12 @@ %splat.splatinsert = insertelement <4 x i32> undef, i32 %a, i32 0 %splat.splat = shufflevector <4 x i32> %splat.splatinsert, <4 x i32> undef, <4 x i32> zeroinitializer ret <4 x i32> %splat.splat -; CHECK: mtvsrwz [[REG1:[0-9]+]], 3 -; CHECK: xxspltw 34, [[REG1]] -; CHECK-LE: mtvsrwz [[REG1:[0-9]+]], 3 -; CHECK-LE: xxspltw 34, [[REG1]] +; CHECK-LABEL: buildi +; CHECK: mtvsrwz f0, r3 +; CHECK: xxspltw v2, vs0, 1 +; CHECK-LE-LABEL: buildi +; CHECK-LE: mtvsrwz f0, r3 +; CHECK-LE: xxspltw v2, vs0, 1 } ; Function Attrs: norecurse nounwind readnone @@ -49,9 +59,11 @@ %splat.splatinsert = insertelement <2 x i64> undef, i64 %a, i32 0 %splat.splat = shufflevector <2 x i64> %splat.splatinsert, <2 x i64> undef, <2 x i32> zeroinitializer ret <2 x i64> %splat.splat -; CHECK: mtvsrd {{[0-9]+}}, 3 -; CHECK-LE: mtvsrd [[REG1:[0-9]+]], 3 -; CHECK-LE: xxspltd 34, [[REG1]], 0 +; CHECK-LABEL: buildl +; CHECK: mtvsrd f0, r3 +; CHECK-LE-LABEL: buildl +; CHECK-LE: mtvsrd f0, r3 +; CHECK-LE: xxspltd v2, vs0, 0 } ; Function Attrs: norecurse nounwind readnone @@ -60,10 +72,12 @@ %splat.splatinsert = insertelement <4 x float> undef, float %a, i32 0 %splat.splat = shufflevector <4 x float> %splat.splatinsert, <4 x float> undef, <4 x i32> zeroinitializer ret <4 x float> %splat.splat -; CHECK: xscvdpspn [[REG1:[0-9]+]], 1 -; CHECK: xxspltw 34, [[REG1]] -; CHECK-LE: xscvdpspn [[REG1:[0-9]+]], 1 -; CHECK-LE: xxspltw 34, [[REG1]] +; CHECK-LABEL: buildf +; CHECK: xscvdpspn vs0, f1 +; CHECK: xxspltw v2, vs0, 0 +; CHECK-LE-LABEL: buildf +; CHECK-LE: xscvdpspn vs0, f1 +; CHECK-LE: xxspltw v2, vs0, 0 } ; The optimization to remove stack operations from PPCDAGToDAGISel::Select @@ -75,10 +89,12 @@ %splat.splatinsert = insertelement <2 x double> undef, double %0, i32 0 %splat.splat = shufflevector <2 x double> %splat.splatinsert, <2 x double> undef, <2 x i32> zeroinitializer ret <2 x double> %splat.splat -; CHECK: ld [[REG1:[0-9]+]], .LC0@toc@l -; CHECK: lxvdsx 34, 0, [[REG1]] -; CHECK-LE: ld [[REG1:[0-9]+]], .LC0@toc@l -; CHECK-LE: lxvdsx 34, 0, [[REG1]] +; CHECK-LABEL: buildd +; CHECK: ld r3, .LC0@toc@l(r3) +; CHECK: lxvdsx v2, 0, r3 +; CHECK-LE-LABEL: buildd +; CHECK-LE: ld r3, .LC0@toc@l(r3) +; CHECK-LE: lxvdsx v2, 0, r3 } ; Function Attrs: norecurse nounwind readnone @@ -87,13 +103,13 @@ %vecext = extractelement <16 x i8> %vsc, i32 0 ret i8 %vecext ; CHECK-LABEL: @getsc0 -; CHECK: mfvsrd 3, 34 -; CHECK: rldicl 3, 3, 8, 56 -; CHECK: extsb 3, 3 +; CHECK: mfvsrd r3, v2 +; CHECK: rldicl r3, r3, 8, 56 +; CHECK: extsb r3, r3 ; CHECK-LE-LABEL: @getsc0 -; CHECK-LE: mfvsrd 3, -; CHECK-LE: clrldi 3, 3, 56 -; CHECK-LE: extsb 3, 3 +; CHECK-LE: mfvsrd r3, f0 +; CHECK-LE: clrldi r3, r3, 56 +; CHECK-LE: extsb r3, r3 } ; Function Attrs: norecurse nounwind readnone @@ -102,13 +118,13 @@ %vecext = extractelement <16 x i8> %vsc, i32 1 ret i8 %vecext ; CHECK-LABEL: @getsc1 -; CHECK: mfvsrd 3, 34 -; CHECK: rldicl 3, 3, 16, 56 -; CHECK: extsb 3, 3 +; CHECK: mfvsrd r3, v2 +; CHECK: rldicl r3, r3, 16, 56 +; CHECK: extsb r3, r3 ; CHECK-LE-LABEL: @getsc1 -; CHECK-LE: mfvsrd 3, -; CHECK-LE: rldicl 3, 3, 56, 56 -; CHECK-LE: extsb 3, 3 +; CHECK-LE: mfvsrd r3, f0 +; CHECK-LE: rldicl r3, r3, 56, 56 +; CHECK-LE: extsb r3, r3 } ; Function Attrs: norecurse nounwind readnone @@ -117,13 +133,13 @@ %vecext = extractelement <16 x i8> %vsc, i32 2 ret i8 %vecext ; CHECK-LABEL: @getsc2 -; CHECK: mfvsrd 3, 34 -; CHECK: rldicl 3, 3, 24, 56 -; CHECK: extsb 3, 3 +; CHECK: mfvsrd r3, v2 +; CHECK: rldicl r3, r3, 24, 56 +; CHECK: extsb r3, r3 ; CHECK-LE-LABEL: @getsc2 -; CHECK-LE: mfvsrd 3, -; CHECK-LE: rldicl 3, 3, 48, 56 -; CHECK-LE: extsb 3, 3 +; CHECK-LE: mfvsrd r3, f0 +; CHECK-LE: rldicl r3, r3, 48, 56 +; CHECK-LE: extsb r3, r3 } ; Function Attrs: norecurse nounwind readnone @@ -132,13 +148,13 @@ %vecext = extractelement <16 x i8> %vsc, i32 3 ret i8 %vecext ; CHECK-LABEL: @getsc3 -; CHECK: mfvsrd 3, 34 -; CHECK: rldicl 3, 3, 32, 56 -; CHECK: extsb 3, 3 +; CHECK: mfvsrd r3, v2 +; CHECK: rldicl r3, r3, 32, 56 +; CHECK: extsb r3, r3 ; CHECK-LE-LABEL: @getsc3 -; CHECK-LE: mfvsrd 3, -; CHECK-LE: rldicl 3, 3, 40, 56 -; CHECK-LE: extsb 3, 3 +; CHECK-LE: mfvsrd r3, f0 +; CHECK-LE: rldicl r3, r3, 40, 56 +; CHECK-LE: extsb r3, r3 } ; Function Attrs: norecurse nounwind readnone @@ -147,13 +163,13 @@ %vecext = extractelement <16 x i8> %vsc, i32 4 ret i8 %vecext ; CHECK-LABEL: @getsc4 -; CHECK: mfvsrd 3, 34 -; CHECK: rldicl 3, 3, 40, 56 -; CHECK: extsb 3, 3 +; CHECK: mfvsrd r3, v2 +; CHECK: rldicl r3, r3, 40, 56 +; CHECK: extsb r3, r3 ; CHECK-LE-LABEL: @getsc4 -; CHECK-LE: mfvsrd 3, -; CHECK-LE: rldicl 3, 3, 32, 56 -; CHECK-LE: extsb 3, 3 +; CHECK-LE: mfvsrd r3, f0 +; CHECK-LE: rldicl r3, r3, 32, 56 +; CHECK-LE: extsb r3, r3 } ; Function Attrs: norecurse nounwind readnone @@ -162,13 +178,13 @@ %vecext = extractelement <16 x i8> %vsc, i32 5 ret i8 %vecext ; CHECK-LABEL: @getsc5 -; CHECK: mfvsrd 3, 34 -; CHECK: rldicl 3, 3, 48, 56 -; CHECK: extsb 3, 3 +; CHECK: mfvsrd r3, v2 +; CHECK: rldicl r3, r3, 48, 56 +; CHECK: extsb r3, r3 ; CHECK-LE-LABEL: @getsc5 -; CHECK-LE: mfvsrd 3, -; CHECK-LE: rldicl 3, 3, 24, 56 -; CHECK-LE: extsb 3, 3 +; CHECK-LE: mfvsrd r3, f0 +; CHECK-LE: rldicl r3, r3, 24, 56 +; CHECK-LE: extsb r3, r3 } ; Function Attrs: norecurse nounwind readnone @@ -177,13 +193,13 @@ %vecext = extractelement <16 x i8> %vsc, i32 6 ret i8 %vecext ; CHECK-LABEL: @getsc6 -; CHECK: mfvsrd 3, 34 -; CHECK: rldicl 3, 3, 56, 56 -; CHECK: extsb 3, 3 +; CHECK: mfvsrd r3, v2 +; CHECK: rldicl r3, r3, 56, 56 +; CHECK: extsb r3, r3 ; CHECK-LE-LABEL: @getsc6 -; CHECK-LE: mfvsrd 3, -; CHECK-LE: rldicl 3, 3, 16, 56 -; CHECK-LE: extsb 3, 3 +; CHECK-LE: mfvsrd r3, f0 +; CHECK-LE: rldicl r3, r3, 16, 56 +; CHECK-LE: extsb r3, r3 } ; Function Attrs: norecurse nounwind readnone @@ -192,13 +208,13 @@ %vecext = extractelement <16 x i8> %vsc, i32 7 ret i8 %vecext ; CHECK-LABEL: @getsc7 -; CHECK: mfvsrd 3, 34 -; CHECK: clrldi 3, 3, 56 -; CHECK: extsb 3, 3 +; CHECK: mfvsrd r3, v2 +; CHECK: clrldi r3, r3, 56 +; CHECK: extsb r3, r3 ; CHECK-LE-LABEL: @getsc7 -; CHECK-LE: mfvsrd 3, -; CHECK-LE: rldicl 3, 3, 8, 56 -; CHECK-LE: extsb 3, 3 +; CHECK-LE: mfvsrd r3, f0 +; CHECK-LE: rldicl r3, r3, 8, 56 +; CHECK-LE: extsb r3, r3 } ; Function Attrs: norecurse nounwind readnone @@ -207,13 +223,13 @@ %vecext = extractelement <16 x i8> %vsc, i32 8 ret i8 %vecext ; CHECK-LABEL: @getsc8 -; CHECK: mfvsrd 3, -; CHECK: rldicl 3, 3, 8, 56 -; CHECK: extsb 3, 3 +; CHECK: mfvsrd r3, f0 +; CHECK: rldicl r3, r3, 8, 56 +; CHECK: extsb r3, r3 ; CHECK-LE-LABEL: @getsc8 -; CHECK-LE: mfvsrd 3, 34 -; CHECK-LE: clrldi 3, 3, 56 -; CHECK-LE: extsb 3, 3 +; CHECK-LE: mfvsrd r3, v2 +; CHECK-LE: clrldi r3, r3, 56 +; CHECK-LE: extsb r3, r3 } ; Function Attrs: norecurse nounwind readnone @@ -222,13 +238,13 @@ %vecext = extractelement <16 x i8> %vsc, i32 9 ret i8 %vecext ; CHECK-LABEL: @getsc9 -; CHECK: mfvsrd 3, -; CHECK: rldicl 3, 3, 16, 56 -; CHECK: extsb 3, 3 +; CHECK: mfvsrd r3, f0 +; CHECK: rldicl r3, r3, 16, 56 +; CHECK: extsb r3, r3 ; CHECK-LE-LABEL: @getsc9 -; CHECK-LE: mfvsrd 3, 34 -; CHECK-LE: rldicl 3, 3, 56, 56 -; CHECK-LE: extsb 3, 3 +; CHECK-LE: mfvsrd r3, v2 +; CHECK-LE: rldicl r3, r3, 56, 56 +; CHECK-LE: extsb r3, r3 } ; Function Attrs: norecurse nounwind readnone @@ -237,13 +253,13 @@ %vecext = extractelement <16 x i8> %vsc, i32 10 ret i8 %vecext ; CHECK-LABEL: @getsc10 -; CHECK: mfvsrd 3, -; CHECK: rldicl 3, 3, 24, 56 -; CHECK: extsb 3, 3 +; CHECK: mfvsrd r3, f0 +; CHECK: rldicl r3, r3, 24, 56 +; CHECK: extsb r3, r3 ; CHECK-LE-LABEL: @getsc10 -; CHECK-LE: mfvsrd 3, 34 -; CHECK-LE: rldicl 3, 3, 48, 56 -; CHECK-LE: extsb 3, 3 +; CHECK-LE: mfvsrd r3, v2 +; CHECK-LE: rldicl r3, r3, 48, 56 +; CHECK-LE: extsb r3, r3 } ; Function Attrs: norecurse nounwind readnone @@ -252,13 +268,13 @@ %vecext = extractelement <16 x i8> %vsc, i32 11 ret i8 %vecext ; CHECK-LABEL: @getsc11 -; CHECK: mfvsrd 3, -; CHECK: rldicl 3, 3, 32, 56 -; CHECK: extsb 3, 3 +; CHECK: mfvsrd r3, f0 +; CHECK: rldicl r3, r3, 32, 56 +; CHECK: extsb r3, r3 ; CHECK-LE-LABEL: @getsc11 -; CHECK-LE: mfvsrd 3, 34 -; CHECK-LE: rldicl 3, 3, 40, 56 -; CHECK-LE: extsb 3, 3 +; CHECK-LE: mfvsrd r3, v2 +; CHECK-LE: rldicl r3, r3, 40, 56 +; CHECK-LE: extsb r3, r3 } ; Function Attrs: norecurse nounwind readnone @@ -267,13 +283,13 @@ %vecext = extractelement <16 x i8> %vsc, i32 12 ret i8 %vecext ; CHECK-LABEL: @getsc12 -; CHECK: mfvsrd 3, -; CHECK: rldicl 3, 3, 40, 56 -; CHECK: extsb 3, 3 +; CHECK: mfvsrd r3, f0 +; CHECK: rldicl r3, r3, 40, 56 +; CHECK: extsb r3, r3 ; CHECK-LE-LABEL: @getsc12 -; CHECK-LE: mfvsrd 3, 34 -; CHECK-LE: rldicl 3, 3, 32, 56 -; CHECK-LE: extsb 3, 3 +; CHECK-LE: mfvsrd r3, v2 +; CHECK-LE: rldicl r3, r3, 32, 56 +; CHECK-LE: extsb r3, r3 } ; Function Attrs: norecurse nounwind readnone @@ -282,13 +298,13 @@ %vecext = extractelement <16 x i8> %vsc, i32 13 ret i8 %vecext ; CHECK-LABEL: @getsc13 -; CHECK: mfvsrd 3, -; CHECK: rldicl 3, 3, 48, 56 -; CHECK: extsb 3, 3 +; CHECK: mfvsrd r3, f0 +; CHECK: rldicl r3, r3, 48, 56 +; CHECK: extsb r3, r3 ; CHECK-LE-LABEL: @getsc13 -; CHECK-LE: mfvsrd 3, 34 -; CHECK-LE: rldicl 3, 3, 24, 56 -; CHECK-LE: extsb 3, 3 +; CHECK-LE: mfvsrd r3, v2 +; CHECK-LE: rldicl r3, r3, 24, 56 +; CHECK-LE: extsb r3, r3 } ; Function Attrs: norecurse nounwind readnone @@ -297,13 +313,13 @@ %vecext = extractelement <16 x i8> %vsc, i32 14 ret i8 %vecext ; CHECK-LABEL: @getsc14 -; CHECK: mfvsrd 3, -; CHECK: rldicl 3, 3, 56, 56 -; CHECK: extsb 3, 3 +; CHECK: mfvsrd r3, f0 +; CHECK: rldicl r3, r3, 56, 56 +; CHECK: extsb r3, r3 ; CHECK-LE-LABEL: @getsc14 -; CHECK-LE: mfvsrd 3, 34 -; CHECK-LE: rldicl 3, 3, 16, 56 -; CHECK-LE: extsb 3, 3 +; CHECK-LE: mfvsrd r3, v2 +; CHECK-LE: rldicl r3, r3, 16, 56 +; CHECK-LE: extsb r3, r3 } ; Function Attrs: norecurse nounwind readnone @@ -312,12 +328,13 @@ %vecext = extractelement <16 x i8> %vsc, i32 15 ret i8 %vecext ; CHECK-LABEL: @getsc15 -; CHECK: mfvsrd 3, -; CHECK: extsb 3, 3 +; CHECK: mfvsrd r3, f0 +; CHECK: clrldi r3, r3, 56 +; CHECK: extsb r3, r3 ; CHECK-LE-LABEL: @getsc15 -; CHECK-LE: mfvsrd 3, 34 -; CHECK-LE: rldicl 3, 3, 8, 56 -; CHECK-LE: extsb 3, 3 +; CHECK-LE: mfvsrd r3, v2 +; CHECK-LE: rldicl r3, r3, 8, 56 +; CHECK-LE: extsb r3, r3 } ; Function Attrs: norecurse nounwind readnone @@ -326,11 +343,11 @@ %vecext = extractelement <16 x i8> %vuc, i32 0 ret i8 %vecext ; CHECK-LABEL: @getuc0 -; CHECK: mfvsrd 3, 34 -; CHECK: rldicl 3, 3, 8, 56 +; CHECK: mfvsrd r3, v2 +; CHECK: rldicl r3, r3, 8, 56 ; CHECK-LE-LABEL: @getuc0 -; CHECK-LE: mfvsrd 3, -; CHECK-LE: clrldi 3, 3, 56 +; CHECK-LE: mfvsrd r3, f0 +; CHECK-LE: clrldi r3, r3, 56 } ; Function Attrs: norecurse nounwind readnone @@ -339,11 +356,11 @@ %vecext = extractelement <16 x i8> %vuc, i32 1 ret i8 %vecext ; CHECK-LABEL: @getuc1 -; CHECK: mfvsrd 3, 34 -; CHECK: rldicl 3, 3, 16, 56 +; CHECK: mfvsrd r3, v2 +; CHECK: rldicl r3, r3, 16, 56 ; CHECK-LE-LABEL: @getuc1 -; CHECK-LE: mfvsrd 3, -; CHECK-LE: rldicl 3, 3, 56, 56 +; CHECK-LE: mfvsrd r3, f0 +; CHECK-LE: rldicl r3, r3, 56, 56 } ; Function Attrs: norecurse nounwind readnone @@ -352,11 +369,11 @@ %vecext = extractelement <16 x i8> %vuc, i32 2 ret i8 %vecext ; CHECK-LABEL: @getuc2 -; CHECK: mfvsrd 3, 34 -; CHECK: rldicl 3, 3, 24, 56 +; CHECK: mfvsrd r3, v2 +; CHECK: rldicl r3, r3, 24, 56 ; CHECK-LE-LABEL: @getuc2 -; CHECK-LE: mfvsrd 3, -; CHECK-LE: rldicl 3, 3, 48, 56 +; CHECK-LE: mfvsrd r3, f0 +; CHECK-LE: rldicl r3, r3, 48, 56 } ; Function Attrs: norecurse nounwind readnone @@ -365,11 +382,11 @@ %vecext = extractelement <16 x i8> %vuc, i32 3 ret i8 %vecext ; CHECK-LABEL: @getuc3 -; CHECK: mfvsrd 3, 34 -; CHECK: rldicl 3, 3, 32, 56 +; CHECK: mfvsrd r3, v2 +; CHECK: rldicl r3, r3, 32, 56 ; CHECK-LE-LABEL: @getuc3 -; CHECK-LE: mfvsrd 3, -; CHECK-LE: rldicl 3, 3, 40, 56 +; CHECK-LE: mfvsrd r3, f0 +; CHECK-LE: rldicl r3, r3, 40, 56 } ; Function Attrs: norecurse nounwind readnone @@ -378,11 +395,11 @@ %vecext = extractelement <16 x i8> %vuc, i32 4 ret i8 %vecext ; CHECK-LABEL: @getuc4 -; CHECK: mfvsrd 3, 34 -; CHECK: rldicl 3, 3, 40, 56 +; CHECK: mfvsrd r3, v2 +; CHECK: rldicl r3, r3, 40, 56 ; CHECK-LE-LABEL: @getuc4 -; CHECK-LE: mfvsrd 3, -; CHECK-LE: rldicl 3, 3, 32, 56 +; CHECK-LE: mfvsrd r3, f0 +; CHECK-LE: rldicl r3, r3, 32, 56 } ; Function Attrs: norecurse nounwind readnone @@ -391,11 +408,11 @@ %vecext = extractelement <16 x i8> %vuc, i32 5 ret i8 %vecext ; CHECK-LABEL: @getuc5 -; CHECK: mfvsrd 3, 34 -; CHECK: rldicl 3, 3, 48, 56 +; CHECK: mfvsrd r3, v2 +; CHECK: rldicl r3, r3, 48, 56 ; CHECK-LE-LABEL: @getuc5 -; CHECK-LE: mfvsrd 3, -; CHECK-LE: rldicl 3, 3, 24, 56 +; CHECK-LE: mfvsrd r3, f0 +; CHECK-LE: rldicl r3, r3, 24, 56 } ; Function Attrs: norecurse nounwind readnone @@ -404,11 +421,11 @@ %vecext = extractelement <16 x i8> %vuc, i32 6 ret i8 %vecext ; CHECK-LABEL: @getuc6 -; CHECK: mfvsrd 3, 34 -; CHECK: rldicl 3, 3, 56, 56 +; CHECK: mfvsrd r3, v2 +; CHECK: rldicl r3, r3, 56, 56 ; CHECK-LE-LABEL: @getuc6 -; CHECK-LE: mfvsrd 3, -; CHECK-LE: rldicl 3, 3, 16, 56 +; CHECK-LE: mfvsrd r3, f0 +; CHECK-LE: rldicl r3, r3, 16, 56 } ; Function Attrs: norecurse nounwind readnone @@ -417,11 +434,11 @@ %vecext = extractelement <16 x i8> %vuc, i32 7 ret i8 %vecext ; CHECK-LABEL: @getuc7 -; CHECK: mfvsrd 3, 34 -; CHECK: clrldi 3, 3, 56 +; CHECK: mfvsrd r3, v2 +; CHECK: clrldi r3, r3, 56 ; CHECK-LE-LABEL: @getuc7 -; CHECK-LE: mfvsrd 3, -; CHECK-LE: rldicl 3, 3, 8, 56 +; CHECK-LE: mfvsrd r3, f0 +; CHECK-LE: rldicl r3, r3, 8, 56 } ; Function Attrs: norecurse nounwind readnone @@ -430,11 +447,11 @@ %vecext = extractelement <16 x i8> %vuc, i32 8 ret i8 %vecext ; CHECK-LABEL: @getuc8 -; CHECK: mfvsrd 3, -; CHECK: rldicl 3, 3, 8, 56 +; CHECK: mfvsrd r3, f0 +; CHECK: rldicl r3, r3, 8, 56 ; CHECK-LE-LABEL: @getuc8 -; CHECK-LE: mfvsrd 3, 34 -; CHECK-LE: clrldi 3, 3, 56 +; CHECK-LE: mfvsrd r3, v2 +; CHECK-LE: clrldi r3, r3, 56 } ; Function Attrs: norecurse nounwind readnone @@ -443,11 +460,11 @@ %vecext = extractelement <16 x i8> %vuc, i32 9 ret i8 %vecext ; CHECK-LABEL: @getuc9 -; CHECK: mfvsrd 3, -; CHECK: rldicl 3, 3, 16, 56 +; CHECK: mfvsrd r3, f0 +; CHECK: rldicl r3, r3, 16, 56 ; CHECK-LE-LABEL: @getuc9 -; CHECK-LE: mfvsrd 3, 34 -; CHECK-LE: rldicl 3, 3, 56, 56 +; CHECK-LE: mfvsrd r3, v2 +; CHECK-LE: rldicl r3, r3, 56, 56 } ; Function Attrs: norecurse nounwind readnone @@ -456,11 +473,11 @@ %vecext = extractelement <16 x i8> %vuc, i32 10 ret i8 %vecext ; CHECK-LABEL: @getuc10 -; CHECK: mfvsrd 3, -; CHECK: rldicl 3, 3, 24, 56 +; CHECK: mfvsrd r3, f0 +; CHECK: rldicl r3, r3, 24, 56 ; CHECK-LE-LABEL: @getuc10 -; CHECK-LE: mfvsrd 3, 34 -; CHECK-LE: rldicl 3, 3, 48, 56 +; CHECK-LE: mfvsrd r3, v2 +; CHECK-LE: rldicl r3, r3, 48, 56 } ; Function Attrs: norecurse nounwind readnone @@ -469,11 +486,11 @@ %vecext = extractelement <16 x i8> %vuc, i32 11 ret i8 %vecext ; CHECK-LABEL: @getuc11 -; CHECK: mfvsrd 3, -; CHECK: rldicl 3, 3, 32, 56 +; CHECK: mfvsrd r3, f0 +; CHECK: rldicl r3, r3, 32, 56 ; CHECK-LE-LABEL: @getuc11 -; CHECK-LE: mfvsrd 3, 34 -; CHECK-LE: rldicl 3, 3, 40, 56 +; CHECK-LE: mfvsrd r3, v2 +; CHECK-LE: rldicl r3, r3, 40, 56 } ; Function Attrs: norecurse nounwind readnone @@ -482,11 +499,11 @@ %vecext = extractelement <16 x i8> %vuc, i32 12 ret i8 %vecext ; CHECK-LABEL: @getuc12 -; CHECK: mfvsrd 3, -; CHECK: rldicl 3, 3, 40, 56 +; CHECK: mfvsrd r3, f0 +; CHECK: rldicl r3, r3, 40, 56 ; CHECK-LE-LABEL: @getuc12 -; CHECK-LE: mfvsrd 3, 34 -; CHECK-LE: rldicl 3, 3, 32, 56 +; CHECK-LE: mfvsrd r3, v2 +; CHECK-LE: rldicl r3, r3, 32, 56 } ; Function Attrs: norecurse nounwind readnone @@ -495,11 +512,11 @@ %vecext = extractelement <16 x i8> %vuc, i32 13 ret i8 %vecext ; CHECK-LABEL: @getuc13 -; CHECK: mfvsrd 3, -; CHECK: rldicl 3, 3, 48, 56 +; CHECK: mfvsrd r3, f0 +; CHECK: rldicl r3, r3, 48, 56 ; CHECK-LE-LABEL: @getuc13 -; CHECK-LE: mfvsrd 3, 34 -; CHECK-LE: rldicl 3, 3, 24, 56 +; CHECK-LE: mfvsrd r3, v2 +; CHECK-LE: rldicl r3, r3, 24, 56 } ; Function Attrs: norecurse nounwind readnone @@ -508,11 +525,11 @@ %vecext = extractelement <16 x i8> %vuc, i32 14 ret i8 %vecext ; CHECK-LABEL: @getuc14 -; CHECK: mfvsrd 3, -; CHECK: rldicl 3, 3, 56, 56 +; CHECK: mfvsrd r3, f0 +; CHECK: rldicl r3, r3, 56, 56 ; CHECK-LE-LABEL: @getuc14 -; CHECK-LE: mfvsrd 3, 34 -; CHECK-LE: rldicl 3, 3, 16, 56 +; CHECK-LE: mfvsrd r3, v2 +; CHECK-LE: rldicl r3, r3, 16, 56 } ; Function Attrs: norecurse nounwind readnone @@ -521,67 +538,67 @@ %vecext = extractelement <16 x i8> %vuc, i32 15 ret i8 %vecext ; CHECK-LABEL: @getuc15 -; CHECK: mfvsrd 3, -; CHECK: clrldi 3, 3, 56 +; CHECK: mfvsrd r3, f0 +; CHECK: clrldi r3, r3, 56 ; CHECK-LE-LABEL: @getuc15 -; CHECK-LE: mfvsrd 3, 34 -; CHECK-LE: rldicl 3, 3, 8, 56 +; CHECK-LE: mfvsrd r3, v2 +; CHECK-LE: rldicl r3, r3, 8, 56 } ; Function Attrs: norecurse nounwind readnone define signext i8 @getvelsc(<16 x i8> %vsc, i32 signext %i) { +; CHECK-LABEL: @getvelsc +; CHECK: andi. r4, r5, 8 +; CHECK: li r3, 7 +; CHECK: lvsl v3, 0, r4 +; CHECK: andc r3, r3, r5 +; CHECK: sldi r3, r3, 3 +; CHECK: vperm v2, v2, v2, v3 +; CHECK: mfvsrd r4, v2 +; CHECK: srd r3, r4, r3 +; CHECK: extsb r3, r3 +; CHECK-LE-LABEL: @getvelsc +; CHECK-LE: li r3, 8 +; CHECK-LE: andc r3, r3, r5 +; CHECK-LE: lvsl v3, 0, r3 +; CHECK-LE: li r3, 7 +; CHECK-LE: and r3, r3, r5 +; CHECK-LE: vperm v2, v2, v2, v3 +; CHECK-LE: sldi r3, r3, 3 +; CHECK-LE: mfvsrd r4, v2 +; CHECK-LE: srd r3, r4, r3 +; CHECK-LE: extsb r3, r3 entry: %vecext = extractelement <16 x i8> %vsc, i32 %i ret i8 %vecext -; CHECK-LABEL: @getvelsc -; CHECK-DAG: andi. [[ANDI:[0-9]+]], {{[0-9]+}}, 8 -; CHECK-DAG: lvsl [[SHMSK:[0-9]+]], 0, [[ANDI]] -; CHECK-DAG: vperm [[PERMD:[0-9]+]], {{[0-9]+}}, {{[0-9]+}}, [[SHMSK]] -; CHECK-DAG: mfvsrd [[MOV:[0-9]+]], -; CHECK-DAG: li [[IMM7:[0-9]+]], 7 -; CHECK-DAG: andc [[ANDC:[0-9]+]], [[IMM7]] -; CHECK-DAG: sldi [[SHL:[0-9]+]], [[ANDC]], 3 -; CHECK-DAG: srd 3, [[MOV]], [[SHL]] -; CHECK-DAG: extsb 3, 3 -; CHECK-LE-LABEL: @getvelsc -; CHECK-DAG-LE: li [[IMM8:[0-9]+]], 8 -; CHECK-DAG-LE: andc [[ANDC:[0-9]+]], [[IMM8]] -; CHECK-DAG-LE: lvsl [[SHMSK:[0-9]+]], 0, [[ANDC]] -; CHECK-DAG-LE: vperm [[PERMD:[0-9]+]], {{[0-9]+}}, {{[0-9]+}}, [[SHMSK]] -; CHECK-DAG-LE: mfvsrd [[MOV:[0-9]+]], -; CHECK-DAG-LE: li [[IMM7:[0-9]+]], 7 -; CHECK-DAG-LE: and [[AND:[0-9]+]], [[IMM7]] -; CHECK-DAG-LE: sldi [[SHL:[0-9]+]], [[AND]], 3 -; CHECK-DAG-LE: srd 3, [[MOV]], [[SHL]] -; CHECK-DAG-LE: extsb 3, 3 } ; Function Attrs: norecurse nounwind readnone define zeroext i8 @getveluc(<16 x i8> %vuc, i32 signext %i) { +; CHECK-LABEL: @getveluc +; CHECK: andi. r4, r5, 8 +; CHECK: li r3, 7 +; CHECK: lvsl v3, 0, r4 +; CHECK: andc r3, r3, r5 +; CHECK: sldi r3, r3, 3 +; CHECK: vperm v2, v2, v2, v3 +; CHECK: mfvsrd r4, v2 +; CHECK: srd r3, r4, r3 +; CHECK: clrldi r3, r3, 5 +; CHECK-LE-LABEL: @getveluc +; CHECK-LE: li r3, 8 +; CHECK-LE: andc r3, r3, r5 +; CHECK-LE: lvsl v3, 0, r3 +; CHECK-LE: li r3, 7 +; CHECK-LE: and r3, r3, r5 +; CHECK-LE: vperm v2, v2, v2, v3 +; CHECK-LE: sldi r3, r3, 3 +; CHECK-LE: mfvsrd r4, v2 +; CHECK-LE: srd r3, r4, r3 +; CHECK-LE: clrldi r3, r3, 56 entry: %vecext = extractelement <16 x i8> %vuc, i32 %i ret i8 %vecext -; CHECK-LABEL: @getveluc -; CHECK-DAG: andi. [[ANDI:[0-9]+]], {{[0-9]+}}, 8 -; CHECK-DAG: lvsl [[SHMSK:[0-9]+]], 0, [[ANDI]] -; CHECK-DAG: vperm [[PERMD:[0-9]+]], {{[0-9]+}}, {{[0-9]+}}, [[SHMSK]] -; CHECK-DAG: mfvsrd [[MOV:[0-9]+]], -; CHECK-DAG: li [[IMM7:[0-9]+]], 7 -; CHECK-DAG: andc [[ANDC:[0-9]+]], [[IMM7]] -; CHECK-DAG: sldi [[SHL:[0-9]+]], [[ANDC]], 3 -; CHECK-DAG: srd 3, [[MOV]], [[SHL]] -; CHECK-DAG: clrldi 3, 3, 56 -; CHECK-LE-LABEL: @getveluc -; CHECK-DAG-LE: li [[IMM8:[0-9]+]], 8 -; CHECK-DAG-LE: andc [[ANDC:[0-9]+]], [[IMM8]] -; CHECK-DAG-LE: lvsl [[SHMSK:[0-9]+]], 0, [[ANDC]] -; CHECK-DAG-LE: vperm [[PERMD:[0-9]+]], {{[0-9]+}}, {{[0-9]+}}, [[SHMSK]] -; CHECK-DAG-LE: mfvsrd [[MOV:[0-9]+]], -; CHECK-DAG-LE: li [[IMM7:[0-9]+]], 7 -; CHECK-DAG-LE: and [[AND:[0-9]+]], [[IMM7]] -; CHECK-DAG-LE: sldi [[SHL:[0-9]+]], [[AND]], 3 -; CHECK-DAG-LE: srd 3, [[MOV]], [[SHL]] -; CHECK-DAG-LE: clrldi 3, 3, 56 } ; Function Attrs: norecurse nounwind readnone @@ -590,13 +607,13 @@ %vecext = extractelement <8 x i16> %vss, i32 0 ret i16 %vecext ; CHECK-LABEL: @getss0 -; CHECK: mfvsrd 3, 34 -; CHECK: rldicl 3, 3, 16, 48 -; CHECK: extsh 3, 3 +; CHECK: mfvsrd r3, v2 +; CHECK: rldicl r3, r3, 16, 48 +; CHECK: extsh r3, r3 ; CHECK-LE-LABEL: @getss0 -; CHECK-LE: mfvsrd 3, -; CHECK-LE: clrldi 3, 3, 48 -; CHECK-LE: extsh 3, 3 +; CHECK-LE: mfvsrd r3, f0 +; CHECK-LE: clrldi r3, r3, 48 +; CHECK-LE: extsh r3, r3 } ; Function Attrs: norecurse nounwind readnone @@ -605,13 +622,13 @@ %vecext = extractelement <8 x i16> %vss, i32 1 ret i16 %vecext ; CHECK-LABEL: @getss1 -; CHECK: mfvsrd 3, 34 -; CHECK: rldicl 3, 3, 32, 48 -; CHECK: extsh 3, 3 +; CHECK: mfvsrd r3, v2 +; CHECK: rldicl r3, r3, 32, 48 +; CHECK: extsh r3, r3 ; CHECK-LE-LABEL: @getss1 -; CHECK-LE: mfvsrd 3, -; CHECK-LE: rldicl 3, 3, 48, 48 -; CHECK-LE: extsh 3, 3 +; CHECK-LE: mfvsrd r3, f0 +; CHECK-LE: rldicl r3, r3, 48, 48 +; CHECK-LE: extsh r3, r3 } ; Function Attrs: norecurse nounwind readnone @@ -620,13 +637,13 @@ %vecext = extractelement <8 x i16> %vss, i32 2 ret i16 %vecext ; CHECK-LABEL: @getss2 -; CHECK: mfvsrd 3, 34 -; CHECK: rldicl 3, 3, 48, 48 -; CHECK: extsh 3, 3 +; CHECK: mfvsrd r3, v2 +; CHECK: rldicl r3, r3, 48, 48 +; CHECK: extsh r3, r3 ; CHECK-LE-LABEL: @getss2 -; CHECK-LE: mfvsrd 3, -; CHECK-LE: rldicl 3, 3, 32, 48 -; CHECK-LE: extsh 3, 3 +; CHECK-LE: mfvsrd r3, f0 +; CHECK-LE: rldicl r3, r3, 32, 48 +; CHECK-LE: extsh r3, r3 } ; Function Attrs: norecurse nounwind readnone @@ -635,13 +652,13 @@ %vecext = extractelement <8 x i16> %vss, i32 3 ret i16 %vecext ; CHECK-LABEL: @getss3 -; CHECK: mfvsrd 3, 34 -; CHECK: clrldi 3, 3, 48 -; CHECK: extsh 3, 3 +; CHECK: mfvsrd r3, v2 +; CHECK: clrldi r3, r3, 48 +; CHECK: extsh r3, r3 ; CHECK-LE-LABEL: @getss3 -; CHECK-LE: mfvsrd 3, -; CHECK-LE: rldicl 3, 3, 16, 48 -; CHECK-LE: extsh 3, 3 +; CHECK-LE: mfvsrd r3, f0 +; CHECK-LE: rldicl r3, r3, 16, 48 +; CHECK-LE: extsh r3, r3 } ; Function Attrs: norecurse nounwind readnone @@ -650,13 +667,13 @@ %vecext = extractelement <8 x i16> %vss, i32 4 ret i16 %vecext ; CHECK-LABEL: @getss4 -; CHECK: mfvsrd 3, -; CHECK: rldicl 3, 3, 16, 48 -; CHECK: extsh 3, 3 +; CHECK: mfvsrd r3, f0 +; CHECK: rldicl r3, r3, 16, 48 +; CHECK: extsh r3, r3 ; CHECK-LE-LABEL: @getss4 -; CHECK-LE: mfvsrd 3, 34 -; CHECK-LE: clrldi 3, 3, 48 -; CHECK-LE: extsh 3, 3 +; CHECK-LE: mfvsrd r3, v2 +; CHECK-LE: clrldi r3, r3, 48 +; CHECK-LE: extsh r3, r3 } ; Function Attrs: norecurse nounwind readnone @@ -665,13 +682,13 @@ %vecext = extractelement <8 x i16> %vss, i32 5 ret i16 %vecext ; CHECK-LABEL: @getss5 -; CHECK: mfvsrd 3, -; CHECK: rldicl 3, 3, 32, 48 -; CHECK: extsh 3, 3 +; CHECK: mfvsrd r3, f0 +; CHECK: rldicl r3, r3, 32, 48 +; CHECK: extsh r3, r3 ; CHECK-LE-LABEL: @getss5 -; CHECK-LE: mfvsrd 3, 34 -; CHECK-LE: rldicl 3, 3, 48, 48 -; CHECK-LE: extsh 3, 3 +; CHECK-LE: mfvsrd r3, v2 +; CHECK-LE: rldicl r3, r3, 48, 48 +; CHECK-LE: extsh r3, r3 } ; Function Attrs: norecurse nounwind readnone @@ -680,13 +697,13 @@ %vecext = extractelement <8 x i16> %vss, i32 6 ret i16 %vecext ; CHECK-LABEL: @getss6 -; CHECK: mfvsrd 3, -; CHECK: rldicl 3, 3, 48, 48 -; CHECK: extsh 3, 3 +; CHECK: mfvsrd r3, f0 +; CHECK: rldicl r3, r3, 48, 48 +; CHECK: extsh r3, r3 ; CHECK-LE-LABEL: @getss6 -; CHECK-LE: mfvsrd 3, 34 -; CHECK-LE: rldicl 3, 3, 32, 48 -; CHECK-LE: extsh 3, 3 +; CHECK-LE: mfvsrd r3, v2 +; CHECK-LE: rldicl r3, r3, 32, 48 +; CHECK-LE: extsh r3, r3 } ; Function Attrs: norecurse nounwind readnone @@ -695,12 +712,13 @@ %vecext = extractelement <8 x i16> %vss, i32 7 ret i16 %vecext ; CHECK-LABEL: @getss7 -; CHECK: mfvsrd 3, -; CHECK: extsh 3, 3 +; CHECK: mfvsrd r3, f0 +; CHECK: clrldi r3, r3, 48 +; CHECK: extsh r3, r3 ; CHECK-LE-LABEL: @getss7 -; CHECK-LE: mfvsrd 3, 34 -; CHECK-LE: rldicl 3, 3, 16, 48 -; CHECK-LE: extsh 3, 3 +; CHECK-LE: mfvsrd r3, v2 +; CHECK-LE: rldicl r3, r3, 16, 48 +; CHECK-LE: extsh r3, r3 } ; Function Attrs: norecurse nounwind readnone @@ -709,11 +727,11 @@ %vecext = extractelement <8 x i16> %vus, i32 0 ret i16 %vecext ; CHECK-LABEL: @getus0 -; CHECK: mfvsrd 3, 34 -; CHECK: rldicl 3, 3, 16, 48 +; CHECK: mfvsrd r3, v2 +; CHECK: rldicl r3, r3, 16, 48 ; CHECK-LE-LABEL: @getus0 -; CHECK-LE: mfvsrd 3, -; CHECK-LE: clrldi 3, 3, 48 +; CHECK-LE: mfvsrd r3, f0 +; CHECK-LE: clrldi r3, r3, 48 } ; Function Attrs: norecurse nounwind readnone @@ -722,11 +740,11 @@ %vecext = extractelement <8 x i16> %vus, i32 1 ret i16 %vecext ; CHECK-LABEL: @getus1 -; CHECK: mfvsrd 3, 34 -; CHECK: rldicl 3, 3, 32, 48 +; CHECK: mfvsrd r3, v2 +; CHECK: rldicl r3, r3, 32, 48 ; CHECK-LE-LABEL: @getus1 -; CHECK-LE: mfvsrd 3, -; CHECK-LE: rldicl 3, 3, 48, 48 +; CHECK-LE: mfvsrd r3, f0 +; CHECK-LE: rldicl r3, r3, 48, 48 } ; Function Attrs: norecurse nounwind readnone @@ -735,11 +753,11 @@ %vecext = extractelement <8 x i16> %vus, i32 2 ret i16 %vecext ; CHECK-LABEL: @getus2 -; CHECK: mfvsrd 3, 34 -; CHECK: rldicl 3, 3, 48, 48 +; CHECK: mfvsrd r3, v2 +; CHECK: rldicl r3, r3, 48, 48 ; CHECK-LE-LABEL: @getus2 -; CHECK-LE: mfvsrd 3, -; CHECK-LE: rldicl 3, 3, 32, 48 +; CHECK-LE: mfvsrd r3, f0 +; CHECK-LE: rldicl r3, r3, 32, 48 } ; Function Attrs: norecurse nounwind readnone @@ -748,11 +766,11 @@ %vecext = extractelement <8 x i16> %vus, i32 3 ret i16 %vecext ; CHECK-LABEL: @getus3 -; CHECK: mfvsrd 3, 34 -; CHECK: clrldi 3, 3, 48 +; CHECK: mfvsrd r3, v2 +; CHECK: clrldi r3, r3, 48 ; CHECK-LE-LABEL: @getus3 -; CHECK-LE: mfvsrd 3, -; CHECK-LE: rldicl 3, 3, 16, 48 +; CHECK-LE: mfvsrd r3, f0 +; CHECK-LE: rldicl r3, r3, 16, 48 } ; Function Attrs: norecurse nounwind readnone @@ -761,11 +779,11 @@ %vecext = extractelement <8 x i16> %vus, i32 4 ret i16 %vecext ; CHECK-LABEL: @getus4 -; CHECK: mfvsrd 3, -; CHECK: rldicl 3, 3, 16, 48 +; CHECK: mfvsrd r3, f0 +; CHECK: rldicl r3, r3, 16, 48 ; CHECK-LE-LABEL: @getus4 -; CHECK-LE: mfvsrd 3, 34 -; CHECK-LE: clrldi 3, 3, 48 +; CHECK-LE: mfvsrd r3, v2 +; CHECK-LE: clrldi r3, r3, 48 } ; Function Attrs: norecurse nounwind readnone @@ -774,11 +792,11 @@ %vecext = extractelement <8 x i16> %vus, i32 5 ret i16 %vecext ; CHECK-LABEL: @getus5 -; CHECK: mfvsrd 3, -; CHECK: rldicl 3, 3, 32, 48 +; CHECK: mfvsrd r3, f0 +; CHECK: rldicl r3, r3, 32, 48 ; CHECK-LE-LABEL: @getus5 -; CHECK-LE: mfvsrd 3, 34 -; CHECK-LE: rldicl 3, 3, 48, 48 +; CHECK-LE: mfvsrd r3, v2 +; CHECK-LE: rldicl r3, r3, 48, 48 } ; Function Attrs: norecurse nounwind readnone @@ -787,11 +805,11 @@ %vecext = extractelement <8 x i16> %vus, i32 6 ret i16 %vecext ; CHECK-LABEL: @getus6 -; CHECK: mfvsrd 3, -; CHECK: rldicl 3, 3, 48, 48 +; CHECK: mfvsrd r3, f0 +; CHECK: rldicl r3, r3, 48, 48 ; CHECK-LE-LABEL: @getus6 -; CHECK-LE: mfvsrd 3, 34 -; CHECK-LE: rldicl 3, 3, 32, 48 +; CHECK-LE: mfvsrd r3, v2 +; CHECK-LE: rldicl r3, r3, 32, 48 } ; Function Attrs: norecurse nounwind readnone @@ -800,71 +818,71 @@ %vecext = extractelement <8 x i16> %vus, i32 7 ret i16 %vecext ; CHECK-LABEL: @getus7 -; CHECK: mfvsrd 3, -; CHECK: clrldi 3, 3, 48 +; CHECK: mfvsrd r3, f0 +; CHECK: clrldi r3, r3, 48 ; CHECK-LE-LABEL: @getus7 -; CHECK-LE: mfvsrd 3, 34 -; CHECK-LE: rldicl 3, 3, 16, 48 +; CHECK-LE: mfvsrd r3, v2 +; CHECK-LE: rldicl r3, r3, 16, 48 } ; Function Attrs: norecurse nounwind readnone define signext i16 @getvelss(<8 x i16> %vss, i32 signext %i) { +; CHECK-LABEL: @getvelss +; CHECK: andi. r4, r5, 4 +; CHECK: li r3, 3 +; CHECK: sldi r4, r4, 1 +; CHECK: andc r3, r3, r5 +; CHECK: lvsl v3, 0, r4 +; CHECK: sldi r3, r3, 4 +; CHECK: vperm v2, v2, v2, v3 +; CHECK: mfvsrd r4, v2 +; CHECK: srd r3, r4, r3 +; CHECK: extsh r3, r3 +; CHECK-LE-LABEL: @getvelss +; CHECK-LE: li r3, 4 +; CHECK-LE: andc r3, r3, r5 +; CHECK-LE: sldi r3, r3, 1 +; CHECK-LE: lvsl v3, 0, r3 +; CHECK-LE: li r3, 3 +; CHECK-LE: and r3, r3, r5 +; CHECK-LE: vperm v2, v2, v2, v3 +; CHECK-LE: sldi r3, r3, 4 +; CHECK-LE: mfvsrd r4, v2 +; CHECK-LE: srd r3, r4, r3 +; CHECK-LE: extsh r3, r3 entry: %vecext = extractelement <8 x i16> %vss, i32 %i ret i16 %vecext -; CHECK-LABEL: @getvelss -; CHECK-DAG: andi. [[ANDI:[0-9]+]], {{[0-9]+}}, 4 -; CHECK-DAG: sldi [[MUL2:[0-9]+]], [[ANDI]], 1 -; CHECK-DAG: lvsl [[SHMSK:[0-9]+]], 0, [[MUL2]] -; CHECK-DAG: vperm [[PERMD:[0-9]+]], {{[0-9]+}}, {{[0-9]+}}, [[SHMSK]] -; CHECK-DAG: mfvsrd [[MOV:[0-9]+]], -; CHECK-DAG: li [[IMM3:[0-9]+]], 3 -; CHECK-DAG: andc [[ANDC:[0-9]+]], [[IMM3]] -; CHECK-DAG: sldi [[SHL:[0-9]+]], [[ANDC]], 4 -; CHECK-DAG: srd 3, [[MOV]], [[SHL]] -; CHECK-DAG: extsh 3, 3 -; CHECK-LE-LABEL: @getvelss -; CHECK-DAG-LE: li [[IMM4:[0-9]+]], 4 -; CHECK-DAG-LE: andc [[ANDC:[0-9]+]], [[IMM4]] -; CHECK-DAG-LE: sldi [[MUL2:[0-9]+]], [[ANDC]], 1 -; CHECK-DAG-LE: lvsl [[SHMSK:[0-9]+]], 0, [[MUL2]] -; CHECK-DAG-LE: vperm [[PERMD:[0-9]+]], {{[0-9]+}}, {{[0-9]+}}, [[SHMSK]] -; CHECK-DAG-LE: mfvsrd [[MOV:[0-9]+]], -; CHECK-DAG-LE: li [[IMM3:[0-9]+]], 3 -; CHECK-DAG-LE: and [[AND:[0-9]+]], [[IMM3]] -; CHECK-DAG-LE: sldi [[SHL:[0-9]+]], [[AND]], 4 -; CHECK-DAG-LE: srd 3, [[MOV]], [[SHL]] -; CHECK-DAG-LE: extsh 3, 3 } ; Function Attrs: norecurse nounwind readnone define zeroext i16 @getvelus(<8 x i16> %vus, i32 signext %i) { +; CHECK-LABEL: @getvelus +; CHECK: andi. r4, r5, 4 +; CHECK: li r3, 3 +; CHECK: sldi r4, r4, 1 +; CHECK: andc r3, r3, r5 +; CHECK: lvsl v3, 0, r4 +; CHECK: sldi r3, r3, 4 +; CHECK: vperm v2, v2, v2, v3 +; CHECK: mfvsrd r4, v2 +; CHECK: srd r3, r4, r3 +; CHECK: clrldi r3, r3, 48 +; CHECK-LE-LABEL: @getvelus +; CHECK-LE: li r3, 4 +; CHECK-LE: andc r3, r3, r5 +; CHECK-LE: sldi r3, r3, 1 +; CHECK-LE: lvsl v3, 0, r3 +; CHECK-LE: li r3, 3 +; CHECK-LE: and r3, r3, r5 +; CHECK-LE: vperm v2, v2, v2, v3 +; CHECK-LE: sldi r3, r3, 4 +; CHECK-LE: mfvsrd r4, v2 +; CHECK-LE: srd r3, r4, r3 +; CHECK-LE: clrldi r3, r3, 48 entry: %vecext = extractelement <8 x i16> %vus, i32 %i ret i16 %vecext -; CHECK-LABEL: @getvelus -; CHECK-DAG: andi. [[ANDI:[0-9]+]], {{[0-9]+}}, 4 -; CHECK-DAG: sldi [[MUL2:[0-9]+]], [[ANDI]], 1 -; CHECK-DAG: lvsl [[SHMSK:[0-9]+]], 0, [[MUL2]] -; CHECK-DAG: vperm [[PERMD:[0-9]+]], {{[0-9]+}}, {{[0-9]+}}, [[SHMSK]] -; CHECK-DAG: mfvsrd [[MOV:[0-9]+]], -; CHECK-DAG: li [[IMM3:[0-9]+]], 3 -; CHECK-DAG: andc [[ANDC:[0-9]+]], [[IMM3]] -; CHECK-DAG: sldi [[SHL:[0-9]+]], [[ANDC]], 4 -; CHECK-DAG: srd 3, [[MOV]], [[SHL]] -; CHECK-DAG: clrldi 3, 3, 48 -; CHECK-LE-LABEL: @getvelus -; CHECK-DAG-LE: li [[IMM4:[0-9]+]], 4 -; CHECK-DAG-LE: andc [[ANDC:[0-9]+]], [[IMM4]] -; CHECK-DAG-LE: sldi [[MUL2:[0-9]+]], [[ANDC]], 1 -; CHECK-DAG-LE: lvsl [[SHMSK:[0-9]+]], 0, [[MUL2]] -; CHECK-DAG-LE: vperm [[PERMD:[0-9]+]], {{[0-9]+}}, {{[0-9]+}}, [[SHMSK]] -; CHECK-DAG-LE: mfvsrd [[MOV:[0-9]+]], -; CHECK-DAG-LE: li [[IMM3:[0-9]+]], 3 -; CHECK-DAG-LE: and [[AND:[0-9]+]], [[IMM3]] -; CHECK-DAG-LE: sldi [[SHL:[0-9]+]], [[AND]], 4 -; CHECK-DAG-LE: srd 3, [[MOV]], [[SHL]] -; CHECK-DAG-LE: clrldi 3, 3, 48 } ; Function Attrs: norecurse nounwind readnone @@ -873,13 +891,13 @@ %vecext = extractelement <4 x i32> %vsi, i32 0 ret i32 %vecext ; CHECK-LABEL: @getsi0 -; CHECK: xxsldwi [[SHL:[0-9]+]], 34, 34, 3 -; CHECK: mfvsrwz 3, [[SHL]] -; CHECK: extsw 3, 3 +; CHECK: xxsldwi vs0, v2, v2, 3 +; CHECK: mfvsrwz r3, f0 +; CHECK: extsw r3, r3 ; CHECK-LE-LABEL: @getsi0 -; CHECK-LE: xxswapd [[SHL:[0-9]+]], 34 -; CHECK-LE: mfvsrwz 3, [[SHL]] -; CHECK-LE: extsw 3, 3 +; CHECK-LE: xxswapd vs0, v2 +; CHECK-LE: mfvsrwz r3, f0 +; CHECK-LE: extsw r3, r3 } ; Function Attrs: norecurse nounwind readnone @@ -888,12 +906,12 @@ %vecext = extractelement <4 x i32> %vsi, i32 1 ret i32 %vecext ; CHECK-LABEL: @getsi1 -; CHECK: mfvsrwz 3, 34 -; CHECK: extsw 3, 3 +; CHECK: mfvsrwz r3, v2 +; CHECK: extsw r3, r3 ; CHECK-LE-LABEL: @getsi1 -; CHECK-LE: xxsldwi [[SHL:[0-9]+]], 34, 34, 1 -; CHECK-LE: mfvsrwz 3, [[SHL]] -; CHECK-LE: extsw 3, 3 +; CHECK-LE: xxsldwi vs0, v2, v2, 1 +; CHECK-LE: mfvsrwz r3, f0 +; CHECK-LE: extsw r3, r3 } ; Function Attrs: norecurse nounwind readnone @@ -902,12 +920,12 @@ %vecext = extractelement <4 x i32> %vsi, i32 2 ret i32 %vecext ; CHECK-LABEL: @getsi2 -; CHECK: xxsldwi [[SHL:[0-9]+]], 34, 34, 1 -; CHECK: mfvsrwz 3, [[SHL]] -; CHECK: extsw 3, 3 +; CHECK: xxsldwi vs0, v2, v2, 1 +; CHECK: mfvsrwz r3, f0 +; CHECK: extsw r3, r3 ; CHECK-LE-LABEL: @getsi2 -; CHECK-LE: mfvsrwz 3, 34 -; CHECK-LE: extsw 3, 3 +; CHECK-LE: mfvsrwz r3, v2 +; CHECK-LE: extsw r3, r3 } ; Function Attrs: norecurse nounwind readnone @@ -916,13 +934,13 @@ %vecext = extractelement <4 x i32> %vsi, i32 3 ret i32 %vecext ; CHECK-LABEL: @getsi3 -; CHECK: xxswapd [[SHL:[0-9]+]], 34 -; CHECK: mfvsrwz 3, [[SHL]] -; CHECK: extsw 3, 3 +; CHECK: xxswapd vs0, v2 +; CHECK: mfvsrwz r3, f0 +; CHECK: extsw r3, r3 ; CHECK-LE-LABEL: @getsi3 -; CHECK-LE: xxsldwi [[SHL:[0-9]+]], 34, 34, 3 -; CHECK-LE: mfvsrwz 3, [[SHL]] -; CHECK-LE: extsw 3, 3 +; CHECK-LE: xxsldwi vs0, v2, v2, 3 +; CHECK-LE: mfvsrwz r3, f0 +; CHECK-LE: extsw r3, r3 } ; Function Attrs: norecurse nounwind readnone @@ -931,11 +949,11 @@ %vecext = extractelement <4 x i32> %vui, i32 0 ret i32 %vecext ; CHECK-LABEL: @getui0 -; CHECK: xxsldwi [[SHL:[0-9]+]], 34, 34, 3 -; CHECK: mfvsrwz 3, [[SHL]] +; CHECK: xxsldwi vs0, v2, v2, 3 +; CHECK: mfvsrwz r3, f0 ; CHECK-LE-LABEL: @getui0 -; CHECK-LE: xxswapd [[SHL:[0-9]+]], 34 -; CHECK-LE: mfvsrwz 3, [[SHL]] +; CHECK-LE: xxswapd vs0, v2 +; CHECK-LE: mfvsrwz r3, f0 } ; Function Attrs: norecurse nounwind readnone @@ -944,10 +962,10 @@ %vecext = extractelement <4 x i32> %vui, i32 1 ret i32 %vecext ; CHECK-LABEL: @getui1 -; CHECK: mfvsrwz 3, 34 +; CHECK: mfvsrwz r3, v2 ; CHECK-LE-LABEL: @getui1 -; CHECK-LE: xxsldwi [[SHL:[0-9]+]], 34, 34, 1 -; CHECK-LE: mfvsrwz 3, [[SHL]] +; CHECK-LE: xxsldwi vs0, v2, v2, 1 +; CHECK-LE: mfvsrwz r3, f0 } ; Function Attrs: norecurse nounwind readnone @@ -956,10 +974,10 @@ %vecext = extractelement <4 x i32> %vui, i32 2 ret i32 %vecext ; CHECK-LABEL: @getui2 -; CHECK: xxsldwi [[SHL:[0-9]+]], 34, 34, 1 -; CHECK: mfvsrwz 3, [[SHL]] +; CHECK: xxsldwi vs0, v2, v2, 1 +; CHECK: mfvsrwz r3, f0 ; CHECK-LE-LABEL: @getui2 -; CHECK-LE: mfvsrwz 3, 34 +; CHECK-LE: mfvsrwz r3, v2 } ; Function Attrs: norecurse nounwind readnone @@ -968,11 +986,11 @@ %vecext = extractelement <4 x i32> %vui, i32 3 ret i32 %vecext ; CHECK-LABEL: @getui3 -; CHECK: xxswapd [[SHL:[0-9]+]], 34 -; CHECK: mfvsrwz 3, [[SHL]] +; CHECK: xxswapd vs0, v2 +; CHECK: mfvsrwz r3, f0 ; CHECK-LE-LABEL: @getui3 -; CHECK-LE: xxsldwi [[SHL:[0-9]+]], 34, 34, 3 -; CHECK-LE: mfvsrwz 3, [[SHL]] +; CHECK-LE: xxsldwi vs0, v2, v2, 3 +; CHECK-LE: mfvsrwz r3, f0 } ; Function Attrs: norecurse nounwind readnone @@ -1001,10 +1019,10 @@ %vecext = extractelement <2 x i64> %vsl, i32 0 ret i64 %vecext ; CHECK-LABEL: @getsl0 -; CHECK: mfvsrd 3, 34 +; CHECK: mfvsrd r3, v2 ; CHECK-LE-LABEL: @getsl0 -; CHECK-LE: xxswapd [[SWP:[0-9]+]], 34 -; CHECK-LE: mfvsrd 3, [[SWP]] +; CHECK-LE: xxswapd vs0, v2 +; CHECK-LE: mfvsrd r3, f0 } ; Function Attrs: norecurse nounwind readnone @@ -1013,10 +1031,10 @@ %vecext = extractelement <2 x i64> %vsl, i32 1 ret i64 %vecext ; CHECK-LABEL: @getsl1 -; CHECK: xxswapd [[SWP:[0-9]+]], 34 -; CHECK: mfvsrd 3, [[SWP]] +; CHECK: xxswapd vs0, v2 +; CHECK: mfvsrd r3, f0 ; CHECK-LE-LABEL: @getsl1 -; CHECK-LE: mfvsrd 3, 34 +; CHECK-LE: mfvsrd r3, v2 } ; Function Attrs: norecurse nounwind readnone @@ -1025,10 +1043,10 @@ %vecext = extractelement <2 x i64> %vul, i32 0 ret i64 %vecext ; CHECK-LABEL: @getul0 -; CHECK: mfvsrd 3, 34 +; CHECK: mfvsrd r3, v2 ; CHECK-LE-LABEL: @getul0 -; CHECK-LE: xxswapd [[SWP:[0-9]+]], 34 -; CHECK-LE: mfvsrd 3, [[SWP]] +; CHECK-LE: xxswapd vs0, v2 +; CHECK-LE: mfvsrd r3, f0 } ; Function Attrs: norecurse nounwind readnone @@ -1037,10 +1055,10 @@ %vecext = extractelement <2 x i64> %vul, i32 1 ret i64 %vecext ; CHECK-LABEL: @getul1 -; CHECK: xxswapd [[SWP:[0-9]+]], 34 -; CHECK: mfvsrd 3, [[SWP]] +; CHECK: xxswapd vs0, v2 +; CHECK: mfvsrd r3, f0 ; CHECK-LE-LABEL: @getul1 -; CHECK-LE: mfvsrd 3, 34 +; CHECK-LE: mfvsrd r3, v2 } ; Function Attrs: norecurse nounwind readnone @@ -1069,10 +1087,10 @@ %vecext = extractelement <4 x float> %vf, i32 0 ret float %vecext ; CHECK-LABEL: @getf0 -; CHECK: xscvspdpn 1, 34 +; CHECK: xscvspdpn f1, v2 ; CHECK-LE-LABEL: @getf0 -; CHECK-LE: xxsldwi [[SHL:[0-9]+]], 34, 34, 3 -; CHECK-LE: xscvspdpn 1, [[SHL]] +; CHECK-LE: xxsldwi vs0, v2, v2, 3 +; CHECK-LE: xscvspdpn f1, vs0 } ; Function Attrs: norecurse nounwind readnone @@ -1081,11 +1099,11 @@ %vecext = extractelement <4 x float> %vf, i32 1 ret float %vecext ; CHECK-LABEL: @getf1 -; CHECK: xxsldwi [[SHL:[0-9]+]], 34, 34, 1 -; CHECK: xscvspdpn 1, [[SHL]] +; CHECK: xxsldwi vs0, v2, v2, 1 +; CHECK: xscvspdpn f1, vs0 ; CHECK-LE-LABEL: @getf1 -; CHECK-LE: xxswapd [[SHL:[0-9]+]], 34 -; CHECK-LE: xscvspdpn 1, [[SHL]] +; CHECK-LE: xxswapd vs0, v2 +; CHECK-LE: xscvspdpn f1, vs0 } ; Function Attrs: norecurse nounwind readnone @@ -1094,11 +1112,11 @@ %vecext = extractelement <4 x float> %vf, i32 2 ret float %vecext ; CHECK-LABEL: @getf2 -; CHECK: xxswapd [[SHL:[0-9]+]], 34 -; CHECK: xscvspdpn 1, [[SHL]] +; CHECK: xxswapd vs0, v2 +; CHECK: xscvspdpn f1, vs0 ; CHECK-LE-LABEL: @getf2 -; CHECK-LE: xxsldwi [[SHL:[0-9]+]], 34, 34, 1 -; CHECK-LE: xscvspdpn 1, [[SHL]] +; CHECK-LE: xxsldwi vs0, v2, v2, 1 +; CHECK-LE: xscvspdpn f1, vs0 } ; Function Attrs: norecurse nounwind readnone @@ -1107,10 +1125,10 @@ %vecext = extractelement <4 x float> %vf, i32 3 ret float %vecext ; CHECK-LABEL: @getf3 -; CHECK: xxsldwi [[SHL:[0-9]+]], 34, 34, 3 -; CHECK: xscvspdpn 1, [[SHL]] +; CHECK: xxsldwi vs0, v2, v2, 3 +; CHECK: xscvspdpn f1, vs0 ; CHECK-LE-LABEL: @getf3 -; CHECK-LE: xscvspdpn 1, 34 +; CHECK-LE: xscvspdpn f1, v2 } ; Function Attrs: norecurse nounwind readnone @@ -1129,9 +1147,9 @@ %vecext = extractelement <2 x double> %vd, i32 0 ret double %vecext ; CHECK-LABEL: @getd0 -; CHECK: xxlor 1, 34, 34 +; CHECK: xxlor f1, v2, v2 ; CHECK-LE-LABEL: @getd0 -; CHECK-LE: xxswapd 1, 34 +; CHECK-LE: xxswapd vs1, v2 } ; Function Attrs: norecurse nounwind readnone @@ -1140,9 +1158,9 @@ %vecext = extractelement <2 x double> %vd, i32 1 ret double %vecext ; CHECK-LABEL: @getd1 -; CHECK: xxswapd 1, 34 +; CHECK: xxswapd vs1, v2 ; CHECK-LE-LABEL: @getd1 -; CHECK-LE: xxlor 1, 34, 34 +; CHECK-LE: xxlor f1, v2, v2 } ; Function Attrs: norecurse nounwind readnone Index: llvm/test/CodeGen/PowerPC/p9_copy_fp.ll =================================================================== --- /dev/null +++ llvm/test/CodeGen/PowerPC/p9_copy_fp.ll @@ -0,0 +1,49 @@ +; RUN: llc -verify-machineinstrs -mcpu=pwr9 -mattr=+vsx -ppc-vsr-nums-as-vr \ +; RUN: -mtriple=powerpc64le-unknown-linux-gnu -ppc-asm-full-reg-names < %s \ +; RUN: | FileCheck %s +; RUN: llc -verify-machineinstrs -mcpu=pwr9 -mattr=+vsx -ppc-vsr-nums-as-vr \ +; RUN: -mtriple=powerpc64-unknown-linux-gnu -ppc-asm-full-reg-names < %s \ +; RUN: | FileCheck -check-prefix=CHECK-BE %s + +; Function Attrs: norecurse nounwind readnone +define double @cp_fp1(<2 x double> %v) { +; CHECK-LABEL: cp_fp1: +; CHECK: xscpsgndp f1, v2, v2 +; CHECK: blr + +; CHECK-BE-LABEL: cp_fp1: +; CHECK-BE: xxswapd vs1, v2 +; CHECK-BE: blr +entry: + %vecext = extractelement <2 x double> %v, i32 1 + ret double %vecext +} + +; Function Attrs: norecurse nounwind readnone +define double @cp_fp2(<2 x double> %v) { +; CHECK-LABEL: cp_fp2: +; CHECK: xxswapd vs1, v2 +; CHECK: blr + +; CHECK-BE-LABEL: cp_fp2: +; CHECK-BE: xscpsgndp f1, v2, v2 +; CHECK-BE: blr +entry: + %vecext = extractelement <2 x double> %v, i32 0 + ret double %vecext +} + +; Function Attrs: norecurse nounwind readnone +define <2 x double> @cp_fp3(double %v) { +; CHECK-LABEL: cp_fp3: +; CHECK: xxspltd v2, vs1, 0 +; CHECK: blr + +; CHECK-BE-LABEL: cp_fp3: +; CHECK-BE: xscpsgndp v2, f1, f1 +; CHECK-BE: blr +entry: + %vecins = insertelement <2 x double> undef, double %v, i32 0 + ret <2 x double> %vecins +} + Index: llvm/test/CodeGen/PowerPC/vsx-spill.ll =================================================================== --- llvm/test/CodeGen/PowerPC/vsx-spill.ll +++ llvm/test/CodeGen/PowerPC/vsx-spill.ll @@ -1,14 +1,18 @@ -; RUN: llc -verify-machineinstrs -mcpu=pwr7 -mattr=+vsx < %s | FileCheck %s -; RUN: llc -verify-machineinstrs -mcpu=pwr7 -mattr=+vsx < %s | FileCheck \ -; RUN: -check-prefix=CHECK-REG %s -; RUN: llc -verify-machineinstrs -mcpu=pwr7 -mattr=+vsx -fast-isel -O0 < %s | \ -; RUN: FileCheck %s -; RUN: llc -verify-machineinstrs -mcpu=pwr7 -mattr=+vsx -fast-isel -O0 < %s | \ -; RUN: FileCheck -check-prefix=CHECK-FISL %s -; RUN: llc -verify-machineinstrs -mcpu=pwr9 < %s | FileCheck \ -; RUN: -check-prefix=CHECK-P9-REG %s -; RUN: llc -verify-machineinstrs -mcpu=pwr9 -fast-isel -O0 < %s | FileCheck \ -; RUN: -check-prefix=CHECK-P9-FISL %s +; RUN: llc -verify-machineinstrs -mcpu=pwr7 -mattr=+vsx \ +; RUN: -ppc-vsr-nums-as-vr -ppc-asm-full-reg-names < %s | FileCheck %s +; RUN: llc -verify-machineinstrs -mcpu=pwr7 -mattr=+vsx \ +; RUN: -ppc-vsr-nums-as-vr -ppc-asm-full-reg-names < %s | FileCheck \ +; RUN: -check-prefix=CHECK-REG %s +; RUN: llc -verify-machineinstrs -mcpu=pwr7 -mattr=+vsx -fast-isel -O0 \ +; RUN: -ppc-vsr-nums-as-vr -ppc-asm-full-reg-names < %s | FileCheck %s +; RUN: llc -verify-machineinstrs -mcpu=pwr7 -mattr=+vsx -fast-isel -O0 \ +; RUN: -ppc-vsr-nums-as-vr -ppc-asm-full-reg-names < %s | \ +; RUN: FileCheck -check-prefix=CHECK-FISL %s +; RUN: llc -verify-machineinstrs -mcpu=pwr9 -ppc-vsr-nums-as-vr \ +; RUN: -ppc-asm-full-reg-names < %s | FileCheck -check-prefix=CHECK-P9-REG %s +; RUN: llc -verify-machineinstrs -mcpu=pwr9 -fast-isel -O0 \ +; RUN: -ppc-vsr-nums-as-vr -ppc-asm-full-reg-names < %s | FileCheck \ +; RUN: -check-prefix=CHECK-P9-FISL %s target datalayout = "E-m:e-i64:64-n32:64" target triple = "powerpc64-unknown-linux-gnu" @@ -18,26 +22,26 @@ br label %return ; CHECK-REG: @foo1 -; CHECK-REG: xxlor [[R1:[0-9]+]], 1, 1 -; CHECK-REG: xxlor 1, [[R1]], [[R1]] +; CHECK-REG: xxlor v2, f1, f1 +; CHECK-REG: xxlor f1, v2, v2 ; CHECK-REG: blr ; CHECK-FISL: @foo1 ; CHECK-FISL-NOT: lis ; CHECK-FISL-NOT: ori -; CHECK-FISL: li 3, -152 +; CHECK-FISL: li r3, -152 ; CHECK-FISL-NOT: lis ; CHECK-FISL-NOT: ori -; CHECK-FISL: stxsdx 1, 1, 3 +; CHECK-FISL: stxsdx f1, r1, r3 ; CHECK-FISL: blr ; CHECK-P9-REG: @foo1 -; CHECK-P9-REG: xxlor [[R1:[0-9]+]], 1, 1 -; CHECK-P9-REG: xxlor 1, [[R1]], [[R1]] +; CHECK-P9-REG: xscpsgndp v2, f1, f1 +; CHECK-P9-REG: xscpsgndp f1, v2, v2 ; CHECK-P9-REG: blr ; CHECK-P9-FISL: @foo1 -; CHECK-P9-FISL: stfd 31, -8(1) +; CHECK-P9-FISL: stfd f31, -8(r1) ; CHECK-P9-FISL: blr return: ; preds = %entry @@ -51,25 +55,25 @@ br label %return ; CHECK-REG: @foo2 -; CHECK-REG: {{xxlor|xsadddp}} [[R1:[0-9]+]], 1, 1 -; CHECK-REG: {{xxlor|xsadddp}} 1, [[R1]], [[R1]] +; CHECK-REG: {{xxlor|xsadddp}} v2, f1, f1 +; CHECK-REG: {{xxlor|xsadddp}} f1, f0, f0 ; CHECK-REG: blr ; CHECK-FISL: @foo2 -; CHECK-FISL: xsadddp [[R1:[0-9]+]], 1, 1 -; CHECK-FISL: stxsdx [[R1]], [[R1]], 3 -; CHECK-FISL: lxsdx [[R1]], [[R1]], 3 +; CHECK-FISL: xsadddp f1, f1, f1 +; CHECK-FISL: stxsdx f1, r1, r3 +; CHECK-FISL: lxsdx f1, r1, r3 ; CHECK-FISL: blr ; CHECK-P9-REG: @foo2 -; CHECK-P9-REG: {{xxlor|xsadddp}} [[R1:[0-9]+]], 1, 1 -; CHECK-P9-REG: {{xxlor|xsadddp}} 1, [[R1]], [[R1]] +; CHECK-P9-REG: {{xscpsgndp|xsadddp}} v2, f1, f1 +; CHECK-P9-REG: {{xscpsgndp|xsadddp}} f1, v2, v2 ; CHECK-P9-REG: blr ; CHECK-P9-FISL: @foo2 -; CHECK-P9-FISL: xsadddp [[R1:[0-9]+]], 1, 1 -; CHECK-P9-FISL: stfd [[R1]], [[OFF:[0-9\-]+]](1) -; CHECK-P9-FISL: lfd [[R1]], [[OFF]](1) +; CHECK-P9-FISL: xsadddp f1, f1, f1 +; CHECK-P9-FISL: stfd f1, -152(r1) +; CHECK-P9-FISL: lfd f1, -152(r1) ; CHECK-P9-FISL: blr return: ; preds = %entry @@ -82,20 +86,20 @@ br label %return ; CHECK: @foo3 -; CHECK: stxsdx 1, -; CHECK: lxsdx [[R1:[0-9]+]], -; CHECK: xsadddp 1, [[R1]], [[R1]] +; CHECK: stxsdx f1, r1, r3 +; CHECK: lxsdx f0, r1, r3 +; CHECK: xsadddp f1, f0, f0 ; CHECK: blr ; CHECK-P9-REG-LABEL: foo3 -; CHECK-P9-REG: stfd 1, [[OFF:[0-9\-]+]](1) -; CHECK-P9-REG: lfd [[FPR:[0-9]+]], [[OFF]](1) -; CHECK-P9-REG: xsadddp 1, [[FPR]], [[FPR]] +; CHECK-P9-REG: stdu r1, -400(r1) +; CHECK-P9-REG: lfd f30, 384(r1) +; CHECK-P9-REG: xsadddp f1, f0, f0 ; CHECK-P9-FISL-LABEL: foo3 -; CHECK-P9-FISL: stfd 1, [[OFF:[0-9\-]+]](1) -; CHECK-P9-FISL: lfd [[FPR:[0-9]+]], [[OFF]](1) -; CHECK-P9-FISL: xsadddp 1, [[FPR]], [[FPR]] +; CHECK-P9-FISL: stdu r1, -400(r1) +; CHECK-P9-FISL: lfd f0, 56(r1) +; CHECK-P9-FISL: xsadddp f1, f0, f0 return: ; preds = %entry %b = fadd double %a, %a ret double %b Index: llvm/test/CodeGen/PowerPC/vsx.ll =================================================================== --- llvm/test/CodeGen/PowerPC/vsx.ll +++ llvm/test/CodeGen/PowerPC/vsx.ll @@ -1,8 +1,18 @@ -; RUN: llc -relocation-model=static -verify-machineinstrs -mcpu=pwr7 -mtriple=powerpc64-unknown-linux-gnu -mattr=+vsx < %s | FileCheck %s -; RUN: llc -relocation-model=static -verify-machineinstrs -mcpu=pwr7 -mtriple=powerpc64-unknown-linux-gnu -mattr=+vsx < %s | FileCheck -check-prefix=CHECK-REG %s -; RUN: llc -relocation-model=static -verify-machineinstrs -mcpu=pwr7 -mtriple=powerpc64-unknown-linux-gnu -mattr=+vsx -fast-isel -O0 < %s | FileCheck %s -; RUN: llc -relocation-model=static -verify-machineinstrs -mcpu=pwr7 -mtriple=powerpc64-unknown-linux-gnu -mattr=+vsx -fast-isel -O0 < %s | FileCheck -check-prefix=CHECK-FISL %s -; RUN: llc -relocation-model=static -verify-machineinstrs -mcpu=pwr8 -mtriple=powerpc64le-unknown-linux-gnu -mattr=+vsx < %s | FileCheck -check-prefix=CHECK-LE %s +; RUN: llc -relocation-model=static -verify-machineinstrs -mcpu=pwr7 \ +; RUN: -mtriple=powerpc64-unknown-linux-gnu -mattr=+vsx \ +; RUN: -ppc-vsr-nums-as-vr -ppc-asm-full-reg-names < %s | FileCheck %s +; RUN: llc -relocation-model=static -verify-machineinstrs -mcpu=pwr7 \ +; RUN: -mtriple=powerpc64-unknown-linux-gnu -mattr=+vsx \ +; RUN: -ppc-vsr-nums-as-vr -ppc-asm-full-reg-names < %s | FileCheck \ +; RUN: -check-prefix=CHECK-REG %s +; RUN: llc -relocation-model=static -verify-machineinstrs -mcpu=pwr7 \ +; RUN: -mtriple=powerpc64-unknown-linux-gnu -mattr=+vsx -fast-isel -O0 \ +; RUN: -ppc-vsr-nums-as-vr -ppc-asm-full-reg-names < %s | FileCheck \ +; RUN: -check-prefix=CHECK-FISL %s +; RUN: llc -relocation-model=static -verify-machineinstrs -mcpu=pwr8 \ +; RUN: -mtriple=powerpc64le-unknown-linux-gnu -mattr=+vsx \ +; RUN: -ppc-vsr-nums-as-vr -ppc-asm-full-reg-names < %s | FileCheck \ +; RUN: -check-prefix=CHECK-LE %s define double @test1(double %a, double %b) { entry: @@ -10,11 +20,11 @@ ret double %v ; CHECK-LABEL: @test1 -; CHECK: xsmuldp 1, 1, 2 +; CHECK: xsmuldp f1, f1, f2 ; CHECK: blr ; CHECK-LE-LABEL: @test1 -; CHECK-LE: xsmuldp 1, 1, 2 +; CHECK-LE: xsmuldp f1, f1, f2 ; CHECK-LE: blr } @@ -24,11 +34,11 @@ ret double %v ; CHECK-LABEL: @test2 -; CHECK: xsdivdp 1, 1, 2 +; CHECK: xsdivdp f1, f1, f2 ; CHECK: blr ; CHECK-LE-LABEL: @test2 -; CHECK-LE: xsdivdp 1, 1, 2 +; CHECK-LE: xsdivdp f1, f1, f2 ; CHECK-LE: blr } @@ -38,11 +48,11 @@ ret double %v ; CHECK-LABEL: @test3 -; CHECK: xsadddp 1, 1, 2 +; CHECK: xsadddp f1, f1, f2 ; CHECK: blr ; CHECK-LE-LABEL: @test3 -; CHECK-LE: xsadddp 1, 1, 2 +; CHECK-LE: xsadddp f1, f1, f2 ; CHECK-LE: blr } @@ -52,11 +62,11 @@ ret <2 x double> %v ; CHECK-LABEL: @test4 -; CHECK: xvadddp 34, 34, 35 +; CHECK: xvadddp v2, v2, v3 ; CHECK: blr ; CHECK-LE-LABEL: @test4 -; CHECK-LE: xvadddp 34, 34, 35 +; CHECK-LE: xvadddp v2, v2, v3 ; CHECK-LE: blr } @@ -66,15 +76,15 @@ ret <4 x i32> %v ; CHECK-REG-LABEL: @test5 -; CHECK-REG: xxlxor 34, 34, 35 +; CHECK-REG: xxlxor v2, v2, v3 ; CHECK-REG: blr ; CHECK-FISL-LABEL: @test5 -; CHECK-FISL: xxlxor 34, 34, 35 +; CHECK-FISL: xxlxor v2, v2, v3 ; CHECK-FISL: blr ; CHECK-LE-LABEL: @test5 -; CHECK-LE: xxlxor 34, 34, 35 +; CHECK-LE: xxlxor v2, v2, v3 ; CHECK-LE: blr } @@ -84,15 +94,15 @@ ret <8 x i16> %v ; CHECK-REG-LABEL: @test6 -; CHECK-REG: xxlxor 34, 34, 35 +; CHECK-REG: xxlxor v2, v2, v3 ; CHECK-REG: blr ; CHECK-FISL-LABEL: @test6 -; CHECK-FISL: xxlxor 34, 34, 35 +; CHECK-FISL: xxlxor v2, v2, v3 ; CHECK-FISL: blr ; CHECK-LE-LABEL: @test6 -; CHECK-LE: xxlxor 34, 34, 35 +; CHECK-LE: xxlxor v2, v2, v3 ; CHECK-LE: blr } @@ -102,15 +112,15 @@ ret <16 x i8> %v ; CHECK-REG-LABEL: @test7 -; CHECK-REG: xxlxor 34, 34, 35 +; CHECK-REG: xxlxor v2, v2, v3 ; CHECK-REG: blr ; CHECK-FISL-LABEL: @test7 -; CHECK-FISL: xxlxor 34, 34, 35 +; CHECK-FISL: xxlxor v2, v2, v3 ; CHECK-FISL: blr ; CHECK-LE-LABEL: @test7 -; CHECK-LE: xxlxor 34, 34, 35 +; CHECK-LE: xxlxor v2, v2, v3 ; CHECK-LE: blr } @@ -120,15 +130,15 @@ ret <4 x i32> %v ; CHECK-REG-LABEL: @test8 -; CHECK-REG: xxlor 34, 34, 35 +; CHECK-REG: xxlor v2, v2, v3 ; CHECK-REG: blr ; CHECK-FISL-LABEL: @test8 -; CHECK-FISL: xxlor 34, 34, 35 +; CHECK-FISL: xxlor v2, v2, v3 ; CHECK-FISL: blr ; CHECK-LE-LABEL: @test8 -; CHECK-LE: xxlor 34, 34, 35 +; CHECK-LE: xxlor v2, v2, v3 ; CHECK-LE: blr } @@ -138,15 +148,15 @@ ret <8 x i16> %v ; CHECK-REG-LABEL: @test9 -; CHECK-REG: xxlor 34, 34, 35 +; CHECK-REG: xxlor v2, v2, v3 ; CHECK-REG: blr ; CHECK-FISL-LABEL: @test9 -; CHECK-FISL: xxlor 34, 34, 35 +; CHECK-FISL: xxlor v2, v2, v3 ; CHECK-FISL: blr ; CHECK-LE-LABEL: @test9 -; CHECK-LE: xxlor 34, 34, 35 +; CHECK-LE: xxlor v2, v2, v3 ; CHECK-LE: blr } @@ -156,15 +166,15 @@ ret <16 x i8> %v ; CHECK-REG-LABEL: @test10 -; CHECK-REG: xxlor 34, 34, 35 +; CHECK-REG: xxlor v2, v2, v3 ; CHECK-REG: blr ; CHECK-FISL-LABEL: @test10 -; CHECK-FISL: xxlor 34, 34, 35 +; CHECK-FISL: xxlor v2, v2, v3 ; CHECK-FISL: blr ; CHECK-LE-LABEL: @test10 -; CHECK-LE: xxlor 34, 34, 35 +; CHECK-LE: xxlor v2, v2, v3 ; CHECK-LE: blr } @@ -174,15 +184,15 @@ ret <4 x i32> %v ; CHECK-REG-LABEL: @test11 -; CHECK-REG: xxland 34, 34, 35 +; CHECK-REG: xxland v2, v2, v3 ; CHECK-REG: blr ; CHECK-FISL-LABEL: @test11 -; CHECK-FISL: xxland 34, 34, 35 +; CHECK-FISL: xxland v2, v2, v3 ; CHECK-FISL: blr ; CHECK-LE-LABEL: @test11 -; CHECK-LE: xxland 34, 34, 35 +; CHECK-LE: xxland v2, v2, v3 ; CHECK-LE: blr } @@ -192,15 +202,15 @@ ret <8 x i16> %v ; CHECK-REG-LABEL: @test12 -; CHECK-REG: xxland 34, 34, 35 +; CHECK-REG: xxland v2, v2, v3 ; CHECK-REG: blr ; CHECK-FISL-LABEL: @test12 -; CHECK-FISL: xxland 34, 34, 35 +; CHECK-FISL: xxland v2, v2, v3 ; CHECK-FISL: blr ; CHECK-LE-LABEL: @test12 -; CHECK-LE: xxland 34, 34, 35 +; CHECK-LE: xxland v2, v2, v3 ; CHECK-LE: blr } @@ -210,15 +220,15 @@ ret <16 x i8> %v ; CHECK-REG-LABEL: @test13 -; CHECK-REG: xxland 34, 34, 35 +; CHECK-REG: xxland v2, v2, v3 ; CHECK-REG: blr ; CHECK-FISL-LABEL: @test13 -; CHECK-FISL: xxland 34, 34, 35 +; CHECK-FISL: xxland v2, v2, v3 ; CHECK-FISL: blr ; CHECK-LE-LABEL: @test13 -; CHECK-LE: xxland 34, 34, 35 +; CHECK-LE: xxland v2, v2, v3 ; CHECK-LE: blr } @@ -229,22 +239,22 @@ ret <4 x i32> %w ; CHECK-REG-LABEL: @test14 -; CHECK-REG: xxlnor 34, 34, 35 +; CHECK-REG: xxlnor v2, v2, v3 ; CHECK-REG: blr ; CHECK-FISL-LABEL: @test14 -; CHECK-FISL: xxlor 0, 34, 35 -; CHECK-FISL: xxlnor 34, 34, 35 +; CHECK-FISL: xxlor vs0, v2, v3 +; CHECK-FISL: xxlnor v2, v2, v3 ; CHECK-FISL-NOT: lis ; CHECK-FISL-NOT: ori -; CHECK-FISL: li 3, -16 +; CHECK-FISL: li r3, -16 ; CHECK-FISL-NOT: lis ; CHECK-FISL-NOT: ori -; CHECK-FISL: stxvd2x 0, 1, 3 +; CHECK-FISL: stxvd2x vs0, r1, r3 ; CHECK-FISL: blr ; CHECK-LE-LABEL: @test14 -; CHECK-LE: xxlnor 34, 34, 35 +; CHECK-LE: xxlnor v2, v2, v3 ; CHECK-LE: blr } @@ -255,24 +265,24 @@ ret <8 x i16> %w ; CHECK-REG-LABEL: @test15 -; CHECK-REG: xxlnor 34, 34, 35 +; CHECK-REG: xxlnor v2, v2, v3 ; CHECK-REG: blr ; CHECK-FISL-LABEL: @test15 -; CHECK-FISL: xxlor 0, 34, 35 -; CHECK-FISL: xxlor 36, 0, 0 -; CHECK-FISL: xxlnor 0, 34, 35 -; CHECK-FISL: xxlor 34, 0, 0 +; CHECK-FISL: xxlor vs0, v2, v3 +; CHECK-FISL: xxlor v4, vs0, vs0 +; CHECK-FISL: xxlnor vs0, v2, v3 +; CHECK-FISL: xxlor v2, vs0, vs0 ; CHECK-FISL-NOT: lis ; CHECK-FISL-NOT: ori -; CHECK-FISL: li 3, -16 +; CHECK-FISL: li r3, -16 ; CHECK-FISL-NOT: lis ; CHECK-FISL-NOT: ori -; CHECK-FISL: stxvd2x 36, 1, 3 +; CHECK-FISL: stxvd2x v4, r1, r3 ; CHECK-FISL: blr ; CHECK-LE-LABEL: @test15 -; CHECK-LE: xxlnor 34, 34, 35 +; CHECK-LE: xxlnor v2, v2, v3 ; CHECK-LE: blr } @@ -283,24 +293,24 @@ ret <16 x i8> %w ; CHECK-REG-LABEL: @test16 -; CHECK-REG: xxlnor 34, 34, 35 +; CHECK-REG: xxlnor v2, v2, v3 ; CHECK-REG: blr ; CHECK-FISL-LABEL: @test16 -; CHECK-FISL: xxlor 0, 34, 35 -; CHECK-FISL: xxlor 36, 0, 0 -; CHECK-FISL: xxlnor 0, 34, 35 -; CHECK-FISL: xxlor 34, 0, 0 +; CHECK-FISL: xxlor vs0, v2, v3 +; CHECK-FISL: xxlor v4, vs0, vs0 +; CHECK-FISL: xxlnor vs0, v2, v3 +; CHECK-FISL: xxlor v2, vs0, vs0 ; CHECK-FISL-NOT: lis ; CHECK-FISL-NOT: ori -; CHECK-FISL: li 3, -16 +; CHECK-FISL: li r3, -16 ; CHECK-FISL-NOT: lis ; CHECK-FISL-NOT: ori -; CHECK-FISL: stxvd2x 36, 1, 3 +; CHECK-FISL: stxvd2x v4, r1, r3 ; CHECK-FISL: blr ; CHECK-LE-LABEL: @test16 -; CHECK-LE: xxlnor 34, 34, 35 +; CHECK-LE: xxlnor v2, v2, v3 ; CHECK-LE: blr } @@ -311,16 +321,16 @@ ret <4 x i32> %v ; CHECK-REG-LABEL: @test17 -; CHECK-REG: xxlandc 34, 34, 35 +; CHECK-REG: xxlandc v2, v2, v3 ; CHECK-REG: blr ; CHECK-FISL-LABEL: @test17 -; CHECK-FISL: xxlnor 35, 35, 35 -; CHECK-FISL: xxland 34, 34, 35 +; CHECK-FISL: xxlnor v3, v3, v3 +; CHECK-FISL: xxland v2, v2, v3 ; CHECK-FISL: blr ; CHECK-LE-LABEL: @test17 -; CHECK-LE: xxlandc 34, 34, 35 +; CHECK-LE: xxlandc v2, v2, v3 ; CHECK-LE: blr } @@ -331,24 +341,24 @@ ret <8 x i16> %v ; CHECK-REG-LABEL: @test18 -; CHECK-REG: xxlandc 34, 34, 35 +; CHECK-REG: xxlandc v2, v2, v3 ; CHECK-REG: blr ; CHECK-FISL-LABEL: @test18 -; CHECK-FISL: xxlnor 0, 35, 35 -; CHECK-FISL: xxlor 36, 0, 0 -; CHECK-FISL: xxlandc 0, 34, 35 -; CHECK-FISL: xxlor 34, 0, 0 +; CHECK-FISL: xxlnor vs0, v3, v3 +; CHECK-FISL: xxlor v4, vs0, vs0 +; CHECK-FISL: xxlandc vs0, v2, v3 +; CHECK-FISL: xxlor v2, vs0, vs0 ; CHECK-FISL-NOT: lis ; CHECK-FISL-NOT: ori -; CHECK-FISL: li 3, -16 +; CHECK-FISL: li r3, -16 ; CHECK-FISL-NOT: lis ; CHECK-FISL-NOT: ori -; CHECK-FISL: stxvd2x 36, 1, 3 +; CHECK-FISL: stxvd2x v4, r1, r3 ; CHECK-FISL: blr ; CHECK-LE-LABEL: @test18 -; CHECK-LE: xxlandc 34, 34, 35 +; CHECK-LE: xxlandc v2, v2, v3 ; CHECK-LE: blr } @@ -359,24 +369,24 @@ ret <16 x i8> %v ; CHECK-REG-LABEL: @test19 -; CHECK-REG: xxlandc 34, 34, 35 +; CHECK-REG: xxlandc v2, v2, v3 ; CHECK-REG: blr ; CHECK-FISL-LABEL: @test19 -; CHECK-FISL: xxlnor 0, 35, 35 -; CHECK-FISL: xxlor 36, 0, 0 -; CHECK-FISL: xxlandc 0, 34, 35 -; CHECK-FISL: xxlor 34, 0, 0 +; CHECK-FISL: xxlnor vs0, v3, v3 +; CHECK-FISL: xxlor v4, vs0, vs0 +; CHECK-FISL: xxlandc vs0, v2, v3 +; CHECK-FISL: xxlor v2, vs0, vs0 ; CHECK-FISL-NOT: lis ; CHECK-FISL-NOT: ori -; CHECK-FISL: li 3, -16 +; CHECK-FISL: li r3, -16 ; CHECK-FISL-NOT: lis ; CHECK-FISL-NOT: ori -; CHECK-FISL: stxvd2x 36, 1, 3 +; CHECK-FISL: stxvd2x v4, r1, r3 ; CHECK-FISL: blr ; CHECK-LE-LABEL: @test19 -; CHECK-LE: xxlandc 34, 34, 35 +; CHECK-LE: xxlandc v2, v2, v3 ; CHECK-LE: blr } @@ -387,18 +397,18 @@ ret <4 x i32> %v ; CHECK-REG-LABEL: @test20 -; CHECK-REG: vcmpequw {{[0-9]+}}, 4, 5 -; CHECK-REG: xxsel 34, 35, 34, {{[0-9]+}} +; CHECK-REG: vcmpequw v4, v4, v5 +; CHECK-REG: xxsel v2, v3, v2, v4 ; CHECK-REG: blr ; CHECK-FISL-LABEL: @test20 -; CHECK-FISL: vcmpequw {{[0-9]+}}, 4, 5 -; CHECK-FISL: xxsel 34, 35, 34, {{[0-9]+}} +; CHECK-FISL: vcmpequw v4, v4, v5 +; CHECK-FISL: xxsel v2, v3, v2, v4 ; CHECK-FISL: blr ; CHECK-LE-LABEL: @test20 -; CHECK-LE: vcmpequw {{[0-9]+}}, 4, 5 -; CHECK-LE: xxsel 34, 35, 34, {{[0-9]+}} +; CHECK-LE: vcmpequw v4, v4, v5 +; CHECK-LE: xxsel v2, v3, v2, v4 ; CHECK-LE: blr } @@ -409,18 +419,18 @@ ret <4 x float> %v ; CHECK-REG-LABEL: @test21 -; CHECK-REG: xvcmpeqsp [[V1:[0-9]+]], 36, 37 -; CHECK-REG: xxsel 34, 35, 34, [[V1]] +; CHECK-REG: xvcmpeqsp vs0, v4, v5 +; CHECK-REG: xxsel v2, v3, v2, vs0 ; CHECK-REG: blr ; CHECK-FISL-LABEL: @test21 -; CHECK-FISL: xvcmpeqsp [[V1:[0-9]+]], 36, 37 -; CHECK-FISL: xxsel 34, 35, 34, [[V1]] +; CHECK-FISL: xvcmpeqsp v4, v4, v5 +; CHECK-FISL: xxsel v2, v3, v2, v4 ; CHECK-FISL: blr ; CHECK-LE-LABEL: @test21 -; CHECK-LE: xvcmpeqsp [[V1:[0-9]+]], 36, 37 -; CHECK-LE: xxsel 34, 35, 34, [[V1]] +; CHECK-LE: xvcmpeqsp vs0, v4, v5 +; CHECK-LE: xxsel v2, v3, v2, vs0 ; CHECK-LE: blr } @@ -431,36 +441,36 @@ ret <4 x float> %v ; CHECK-REG-LABEL: @test22 -; CHECK-REG-DAG: xvcmpeqsp {{[0-9]+}}, 37, 37 -; CHECK-REG-DAG: xvcmpeqsp {{[0-9]+}}, 36, 36 -; CHECK-REG-DAG: xvcmpeqsp {{[0-9]+}}, 36, 37 -; CHECK-REG-DAG: xxlnor -; CHECK-REG-DAG: xxlnor -; CHECK-REG-DAG: xxlor -; CHECK-REG-DAG: xxlor -; CHECK-REG: xxsel 34, 35, 34, {{[0-9]+}} +; CHECK-REG-DAG: xvcmpeqsp vs0, v5, v5 +; CHECK-REG-DAG: xvcmpeqsp vs1, v4, v4 +; CHECK-REG-DAG: xvcmpeqsp vs2, v4, v5 +; CHECK-REG-DAG: xxlnor vs0, vs0, vs0 +; CHECK-REG-DAG: xxlnor vs1, vs1, vs1 +; CHECK-REG-DAG: xxlor vs0, vs1, vs0 +; CHECK-REG-DAG: xxlor vs0, vs2, vs0 +; CHECK-REG: xxsel v2, v3, v2, vs0 ; CHECK-REG: blr ; CHECK-FISL-LABEL: @test22 -; CHECK-FISL-DAG: xvcmpeqsp {{[0-9]+}}, 37, 37 -; CHECK-FISL-DAG: xvcmpeqsp {{[0-9]+}}, 36, 36 -; CHECK-FISL-DAG: xvcmpeqsp {{[0-9]+}}, 36, 37 -; CHECK-FISL-DAG: xxlnor -; CHECK-FISL-DAG: xxlnor -; CHECK-FISL-DAG: xxlor -; CHECK-FISL-DAG: xxlor -; CHECK-FISL: xxsel 34, 35, 34, {{[0-9]+}} +; CHECK-FISL-DAG: xvcmpeqsp vs0, v4, v5 +; CHECK-FISL-DAG: xvcmpeqsp v5, v5, v5 +; CHECK-FISL-DAG: xvcmpeqsp v4, v4, v4 +; CHECK-FISL-DAG: xxlnor v5, v5, v5 +; CHECK-FISL-DAG: xxlnor v4, v4, v4 +; CHECK-FISL-DAG: xxlor v4, v4, v5 +; CHECK-FISL-DAG: xxlor vs0, vs0, v4 +; CHECK-FISL: xxsel v2, v3, v2, vs0 ; CHECK-FISL: blr ; CHECK-LE-LABEL: @test22 -; CHECK-LE-DAG: xvcmpeqsp {{[0-9]+}}, 37, 37 -; CHECK-LE-DAG: xvcmpeqsp {{[0-9]+}}, 36, 36 -; CHECK-LE-DAG: xvcmpeqsp {{[0-9]+}}, 36, 37 -; CHECK-LE-DAG: xxlnor -; CHECK-LE-DAG: xxlnor -; CHECK-LE-DAG: xxlor -; CHECK-LE-DAG: xxlor -; CHECK-LE: xxsel 34, 35, 34, {{[0-9]+}} +; CHECK-LE-DAG: xvcmpeqsp vs0, v5, v5 +; CHECK-LE-DAG: xvcmpeqsp vs1, v4, v4 +; CHECK-LE-DAG: xvcmpeqsp vs2, v4, v5 +; CHECK-LE-DAG: xxlnor vs0, vs0, vs0 +; CHECK-LE-DAG: xxlnor vs1, vs1, vs1 +; CHECK-LE-DAG: xxlor vs0, vs1, vs0 +; CHECK-LE-DAG: xxlor vs0, vs2, vs0 +; CHECK-LE: xxsel v2, v3, v2, vs0 ; CHECK-LE: blr } @@ -471,18 +481,18 @@ ret <8 x i16> %v ; CHECK-REG-LABEL: @test23 -; CHECK-REG: vcmpequh {{[0-9]+}}, 4, 5 -; CHECK-REG: xxsel 34, 35, 34, {{[0-9]+}} +; CHECK-REG: vcmpequh v4, v4, v5 +; CHECK-REG: xxsel v2, v3, v2, v4 ; CHECK-REG: blr ; CHECK-FISL-LABEL: @test23 -; CHECK-FISL: vcmpequh 4, 4, 5 -; CHECK-FISL: xxsel 34, 35, 34, 36 +; CHECK-FISL: vcmpequh v4, v4, v5 +; CHECK-FISL: xxsel v2, v3, v2, v4 ; CHECK-FISL: blr ; CHECK-LE-LABEL: @test23 -; CHECK-LE: vcmpequh {{[0-9]+}}, 4, 5 -; CHECK-LE: xxsel 34, 35, 34, {{[0-9]+}} +; CHECK-LE: vcmpequh v4, v4, v5 +; CHECK-LE: xxsel v2, v3, v2, v4 ; CHECK-LE: blr } @@ -493,18 +503,18 @@ ret <16 x i8> %v ; CHECK-REG-LABEL: @test24 -; CHECK-REG: vcmpequb {{[0-9]+}}, 4, 5 -; CHECK-REG: xxsel 34, 35, 34, {{[0-9]+}} +; CHECK-REG: vcmpequb v4, v4, v5 +; CHECK-REG: xxsel v2, v3, v2, v4 ; CHECK-REG: blr ; CHECK-FISL-LABEL: @test24 -; CHECK-FISL: vcmpequb 4, 4, 5 -; CHECK-FISL: xxsel 34, 35, 34, 36 +; CHECK-FISL: vcmpequb v4, v4, v5 +; CHECK-FISL: xxsel v2, v3, v2, v4 ; CHECK-FISL: blr ; CHECK-LE-LABEL: @test24 -; CHECK-LE: vcmpequb {{[0-9]+}}, 4, 5 -; CHECK-LE: xxsel 34, 35, 34, {{[0-9]+}} +; CHECK-LE: vcmpequb v4, v4, v5 +; CHECK-LE: xxsel v2, v3, v2, v4 ; CHECK-LE: blr } @@ -515,13 +525,13 @@ ret <2 x double> %v ; CHECK-LABEL: @test25 -; CHECK: xvcmpeqdp [[V1:[0-9]+]], 36, 37 -; CHECK: xxsel 34, 35, 34, [[V1]] +; CHECK: xvcmpeqdp v4, v4, v5 +; CHECK: xxsel v2, v3, v2, vs0 ; CHECK: blr ; CHECK-LE-LABEL: @test25 -; CHECK-LE: xvcmpeqdp [[V1:[0-9]+]], 36, 37 -; CHECK-LE: xxsel 34, 35, 34, [[V1]] +; CHECK-LE: xvcmpeqdp v4, v4, v5 +; CHECK-LE: xxsel v2, v3, v2, v4 ; CHECK-LE: blr } @@ -532,16 +542,16 @@ ; CHECK-LABEL: @test26 ; Make sure we use only two stores (one for each operand). -; CHECK: stxvd2x 35, -; CHECK: stxvd2x 34, +; CHECK: stxvd2x v3, 0, r3 +; CHECK: stxvd2x v2, 0, r4 ; CHECK-NOT: stxvd2x ; FIXME: The code quality here is not good; just make sure we do something for now. -; CHECK: add -; CHECK: add +; CHECK: add r3, r4, r3 +; CHECK: add r3, r4, r3 ; CHECK: blr -; CHECK-LE: vaddudm 2, 2, 3 +; CHECK-LE: vaddudm v2, v2, v3 ; CHECK-LE: blr } @@ -550,11 +560,11 @@ ret <2 x i64> %v ; CHECK-LABEL: @test27 -; CHECK: xxland 34, 34, 35 +; CHECK: xxland v2, v2, v3 ; CHECK: blr ; CHECK-LE-LABEL: @test27 -; CHECK-LE: xxland 34, 34, 35 +; CHECK-LE: xxland v2, v2, v3 ; CHECK-LE: blr } @@ -563,12 +573,12 @@ ret <2 x double> %v ; CHECK-LABEL: @test28 -; CHECK: lxvd2x 34, 0, 3 +; CHECK: lxvd2x v2, 0, r3 ; CHECK: blr ; CHECK-LE-LABEL: @test28 -; CHECK-LE: lxvd2x [[V1:[0-9]+]], 0, 3 -; CHECK-LE: xxswapd 34, [[V1]] +; CHECK-LE: lxvd2x vs0, 0, r3 +; CHECK-LE: xxswapd v2, vs0 ; CHECK-LE: blr } @@ -577,12 +587,12 @@ ret void ; CHECK-LABEL: @test29 -; CHECK: stxvd2x 34, 0, 3 +; CHECK: stxvd2x v2, 0, r3 ; CHECK: blr ; CHECK-LE-LABEL: @test29 -; CHECK-LE: xxswapd [[V1:[0-9]+]], 34 -; CHECK-LE: stxvd2x [[V1]], 0, 3 +; CHECK-LE: xxswapd vs0, v2 +; CHECK-LE: stxvd2x vs0, 0, r3 ; CHECK-LE: blr } @@ -591,12 +601,12 @@ ret <2 x double> %v ; CHECK-LABEL: @test28u -; CHECK: lxvd2x 34, 0, 3 +; CHECK: lxvd2x v2, 0, r3 ; CHECK: blr ; CHECK-LE-LABEL: @test28u -; CHECK-LE: lxvd2x [[V1:[0-9]+]], 0, 3 -; CHECK-LE: xxswapd 34, [[V1]] +; CHECK-LE: lxvd2x vs0, 0, r3 +; CHECK-LE: xxswapd v2, vs0 ; CHECK-LE: blr } @@ -605,12 +615,12 @@ ret void ; CHECK-LABEL: @test29u -; CHECK: stxvd2x 34, 0, 3 +; CHECK: stxvd2x v2, 0, r3 ; CHECK: blr ; CHECK-LE-LABEL: @test29u -; CHECK-LE: xxswapd [[V1:[0-9]+]], 34 -; CHECK-LE: stxvd2x [[V1]], 0, 3 +; CHECK-LE: xxswapd vs0, v2 +; CHECK-LE: stxvd2x vs0, 0, r3 ; CHECK-LE: blr } @@ -619,17 +629,17 @@ ret <2 x i64> %v ; CHECK-REG-LABEL: @test30 -; CHECK-REG: lxvd2x 34, 0, 3 +; CHECK-REG: lxvd2x v2, 0, r3 ; CHECK-REG: blr ; CHECK-FISL-LABEL: @test30 -; CHECK-FISL: lxvd2x 0, 0, 3 -; CHECK-FISL: xxlor 34, 0, 0 +; CHECK-FISL: lxvd2x vs0, 0, r3 +; CHECK-FISL: xxlor v2, vs0, vs0 ; CHECK-FISL: blr ; CHECK-LE-LABEL: @test30 -; CHECK-LE: lxvd2x [[V1:[0-9]+]], 0, 3 -; CHECK-LE: xxswapd 34, [[V1]] +; CHECK-LE: lxvd2x vs0, 0, r3 +; CHECK-LE: xxswapd v2, vs0 ; CHECK-LE: blr } @@ -638,12 +648,12 @@ ret void ; CHECK-LABEL: @test31 -; CHECK: stxvd2x 34, 0, 3 +; CHECK: stxvd2x v2, 0, r3 ; CHECK: blr ; CHECK-LE-LABEL: @test31 -; CHECK-LE: xxswapd [[V1:[0-9]+]], 34 -; CHECK-LE: stxvd2x [[V1]], 0, 3 +; CHECK-LE: xxswapd vs0, v2 +; CHECK-LE: stxvd2x vs0, 0, r3 ; CHECK-LE: blr } @@ -652,15 +662,15 @@ ret <4 x float> %v ; CHECK-REG-LABEL: @test32 -; CHECK-REG: lxvw4x 34, 0, 3 +; CHECK-REG: lxvw4x v2, 0, r3 ; CHECK-REG: blr ; CHECK-FISL-LABEL: @test32 -; CHECK-FISL: lxvw4x 34, 0, 3 +; CHECK-FISL: lxvw4x v2, 0, r3 ; CHECK-FISL: blr ; CHECK-LE-LABEL: @test32 -; CHECK-LE: lvx 2, 0, 3 +; CHECK-LE: lvx v2, 0, r3 ; CHECK-LE-NOT: xxswapd ; CHECK-LE: blr } @@ -670,16 +680,16 @@ ret void ; CHECK-REG-LABEL: @test33 -; CHECK-REG: stxvw4x 34, 0, 3 +; CHECK-REG: stxvw4x v2, 0, r3 ; CHECK-REG: blr ; CHECK-FISL-LABEL: @test33 -; CHECK-FISL: stxvw4x 34, 0, 3 +; CHECK-FISL: stxvw4x v2, 0, r3 ; CHECK-FISL: blr ; CHECK-LE-LABEL: @test33 ; CHECK-LE-NOT: xxswapd -; CHECK-LE: stvx 2, 0, 3 +; CHECK-LE: stvx v2, 0, r3 ; CHECK-LE: blr } @@ -688,15 +698,15 @@ ret <4 x float> %v ; CHECK-LABEL: @test32u -; CHECK-DAG: lvsl -; CHECK-DAG: lvx -; CHECK-DAG: lvx -; CHECK: vperm 2, +; CHECK-DAG: lvsl v3, 0, r3 +; CHECK-DAG: lvx v2, r3, r4 +; CHECK-DAG: lvx v4, 0, r3 +; CHECK: vperm v2, v4, v2, v3 ; CHECK: blr ; CHECK-LE-LABEL: @test32u -; CHECK-LE: lxvd2x [[V1:[0-9]+]], 0, 3 -; CHECK-LE: xxswapd 34, [[V1]] +; CHECK-LE: lxvd2x vs0, 0, r3 +; CHECK-LE: xxswapd v2, vs0 ; CHECK-LE: blr } @@ -705,16 +715,16 @@ ret void ; CHECK-REG-LABEL: @test33u -; CHECK-REG: stxvw4x 34, 0, 3 +; CHECK-REG: stxvw4x v2, 0, r3 ; CHECK-REG: blr ; CHECK-FISL-LABEL: @test33u -; CHECK-FISL: stxvw4x 34, 0, 3 +; CHECK-FISL: stxvw4x v2, 0, r3 ; CHECK-FISL: blr ; CHECK-LE-LABEL: @test33u -; CHECK-LE: xxswapd [[V1:[0-9]+]], 34 -; CHECK-LE: stxvd2x [[V1]], 0, 3 +; CHECK-LE: xxswapd vs0, v2 +; CHECK-LE: stxvd2x vs0, 0, r3 ; CHECK-LE: blr } @@ -723,15 +733,15 @@ ret <4 x i32> %v ; CHECK-REG-LABEL: @test34 -; CHECK-REG: lxvw4x 34, 0, 3 +; CHECK-REG: lxvw4x v2, 0, r3 ; CHECK-REG: blr ; CHECK-FISL-LABEL: @test34 -; CHECK-FISL: lxvw4x 34, 0, 3 +; CHECK-FISL: lxvw4x v2, 0, r3 ; CHECK-FISL: blr ; CHECK-LE-LABEL: @test34 -; CHECK-LE: lvx 2, 0, 3 +; CHECK-LE: lvx v2, 0, r3 ; CHECK-LE-NOT: xxswapd ; CHECK-LE: blr } @@ -741,16 +751,16 @@ ret void ; CHECK-REG-LABEL: @test35 -; CHECK-REG: stxvw4x 34, 0, 3 +; CHECK-REG: stxvw4x v2, 0, r3 ; CHECK-REG: blr ; CHECK-FISL-LABEL: @test35 -; CHECK-FISL: stxvw4x 34, 0, 3 +; CHECK-FISL: stxvw4x v2, 0, r3 ; CHECK-FISL: blr ; CHECK-LE-LABEL: @test35 ; CHECK-LE-NOT: xxswapd -; CHECK-LE: stvx 2, 0, 3 +; CHECK-LE: stvx v2, 0, r3 ; CHECK-LE: blr } @@ -759,11 +769,11 @@ ret <2 x double> %v ; CHECK-LABEL: @test40 -; CHECK: xvcvuxddp 34, 34 +; CHECK: xvcvuxddp v2, v2 ; CHECK: blr ; CHECK-LE-LABEL: @test40 -; CHECK-LE: xvcvuxddp 34, 34 +; CHECK-LE: xvcvuxddp v2, v2 ; CHECK-LE: blr } @@ -772,11 +782,11 @@ ret <2 x double> %v ; CHECK-LABEL: @test41 -; CHECK: xvcvsxddp 34, 34 +; CHECK: xvcvsxddp v2, v2 ; CHECK: blr ; CHECK-LE-LABEL: @test41 -; CHECK-LE: xvcvsxddp 34, 34 +; CHECK-LE: xvcvsxddp v2, v2 ; CHECK-LE: blr } @@ -785,11 +795,11 @@ ret <2 x i64> %v ; CHECK-LABEL: @test42 -; CHECK: xvcvdpuxds 34, 34 +; CHECK: xvcvdpuxds v2, v2 ; CHECK: blr ; CHECK-LE-LABEL: @test42 -; CHECK-LE: xvcvdpuxds 34, 34 +; CHECK-LE: xvcvdpuxds v2, v2 ; CHECK-LE: blr } @@ -798,11 +808,11 @@ ret <2 x i64> %v ; CHECK-LABEL: @test43 -; CHECK: xvcvdpsxds 34, 34 +; CHECK: xvcvdpsxds v2, v2 ; CHECK: blr ; CHECK-LE-LABEL: @test43 -; CHECK-LE: xvcvdpsxds 34, 34 +; CHECK-LE: xvcvdpsxds v2, v2 ; CHECK-LE: blr } @@ -813,6 +823,17 @@ ; CHECK-LABEL: @test44 ; FIXME: The code quality here looks pretty bad. ; CHECK: blr +; CHECK-LE-LABEL: @test44 +; CHECK-LE: xxswapd vs0, v2 +; CHECK-LE: xxlor vs1, v2, v2 +; CHECK-LE: xscvuxdsp f1, f1 +; CHECK-LE: xscvuxdsp f0, f0 +; CHECK-LE: xscvdpspn vs1, f1 +; CHECK-LE: xscvdpspn vs0, f0 +; CHECK-LE: xxsldwi v3, vs1, vs1, 1 +; CHECK-LE: xxsldwi v2, vs0, vs0, 1 +; CHECK-LE: vmrglw v2, v3, v2 +; CHECK-LE: blr } define <2 x float> @test45(<2 x i64> %a) { @@ -822,6 +843,8 @@ ; CHECK-LABEL: @test45 ; FIXME: The code quality here looks pretty bad. ; CHECK: blr +; CHECK-LE-LABEL: @test45 +; CHECK-LE: blr } define <2 x i64> @test46(<2 x float> %a) { @@ -849,11 +872,11 @@ ret <2 x double> %x ; CHECK-LABEL: @test50 -; CHECK: lxvdsx 34, 0, 3 +; CHECK: lxvdsx v2, 0, r3 ; CHECK: blr ; CHECK-LE-LABEL: @test50 -; CHECK-LE: lxvdsx 34, 0, 3 +; CHECK-LE: lxvdsx v2, 0, r3 ; CHECK-LE: blr } @@ -862,11 +885,11 @@ ret <2 x double> %v ; CHECK-LABEL: @test51 -; CHECK: xxspltd 34, 34, 0 +; CHECK: xxspltd v2, v2, 0 ; CHECK: blr ; CHECK-LE-LABEL: @test51 -; CHECK-LE: xxspltd 34, 34, 1 +; CHECK-LE: xxspltd v2, v2, 1 ; CHECK-LE: blr } @@ -875,11 +898,11 @@ ret <2 x double> %v ; CHECK-LABEL: @test52 -; CHECK: xxmrghd 34, 34, 35 +; CHECK: xxmrghd v2, v2, v3 ; CHECK: blr ; CHECK-LE-LABEL: @test52 -; CHECK-LE: xxmrgld 34, 35, 34 +; CHECK-LE: xxmrgld v2, v3, v2 ; CHECK-LE: blr } @@ -888,11 +911,11 @@ ret <2 x double> %v ; CHECK-LABEL: @test53 -; CHECK: xxmrghd 34, 35, 34 +; CHECK: xxmrghd v2, v3, v2 ; CHECK: blr ; CHECK-LE-LABEL: @test53 -; CHECK-LE: xxmrgld 34, 34, 35 +; CHECK-LE: xxmrgld v2, v2, v3 ; CHECK-LE: blr } @@ -901,11 +924,11 @@ ret <2 x double> %v ; CHECK-LABEL: @test54 -; CHECK: xxpermdi 34, 34, 35, 2 +; CHECK: xxpermdi v2, v2, v3, 2 ; CHECK: blr ; CHECK-LE-LABEL: @test54 -; CHECK-LE: xxpermdi 34, 35, 34, 2 +; CHECK-LE: xxpermdi v2, v3, v2, 2 ; CHECK-LE: blr } @@ -914,11 +937,11 @@ ret <2 x double> %v ; CHECK-LABEL: @test55 -; CHECK: xxmrgld 34, 34, 35 +; CHECK: xxmrgld v2, v2, v3 ; CHECK: blr ; CHECK-LE-LABEL: @test55 -; CHECK-LE: xxmrghd 34, 35, 34 +; CHECK-LE: xxmrghd v2, v3, v2 ; CHECK-LE: blr } @@ -927,11 +950,11 @@ ret <2 x i64> %v ; CHECK-LABEL: @test56 -; CHECK: xxmrgld 34, 34, 35 +; CHECK: xxmrgld v2, v2, v3 ; CHECK: blr ; CHECK-LE-LABEL: @test56 -; CHECK-LE: xxmrghd 34, 35, 34 +; CHECK-LE: xxmrghd v2, v3, v2 ; CHECK-LE: blr } @@ -941,11 +964,11 @@ ; CHECK-LABEL: @test60 ; This should scalarize, and the current code quality is not good. -; CHECK: stxvd2x -; CHECK: stxvd2x -; CHECK: sld -; CHECK: sld -; CHECK: lxvd2x +; CHECK: stxvd2x v3, 0, r3 +; CHECK: stxvd2x v2, 0, r4 +; CHECK: sld r3, r4, r3 +; CHECK: sld r3, r4, r3 +; CHECK: lxvd2x v2, 0, r3 ; CHECK: blr } @@ -955,11 +978,11 @@ ; CHECK-LABEL: @test61 ; This should scalarize, and the current code quality is not good. -; CHECK: stxvd2x -; CHECK: stxvd2x -; CHECK: srd -; CHECK: srd -; CHECK: lxvd2x +; CHECK: stxvd2x v3, 0, r3 +; CHECK: stxvd2x v2, 0, r4 +; CHECK: srd r3, r4, r3 +; CHECK: srd r3, r4, r3 +; CHECK: lxvd2x v2, 0, r3 ; CHECK: blr } @@ -969,11 +992,11 @@ ; CHECK-LABEL: @test62 ; This should scalarize, and the current code quality is not good. -; CHECK: stxvd2x -; CHECK: stxvd2x -; CHECK: srad -; CHECK: srad -; CHECK: lxvd2x +; CHECK: stxvd2x v3, 0, r3 +; CHECK: stxvd2x v2, 0, r4 +; CHECK: srad r3, r4, r3 +; CHECK: srad r3, r4, r3 +; CHECK: lxvd2x v2, 0, r3 ; CHECK: blr } @@ -982,16 +1005,16 @@ ret double %v ; CHECK-REG-LABEL: @test63 -; CHECK-REG: xxlor 1, 34, 34 +; CHECK-REG: xxlor f1, v2, v2 ; CHECK-REG: blr ; CHECK-FISL-LABEL: @test63 -; CHECK-FISL: xxlor 0, 34, 34 -; CHECK-FISL: fmr 1, 0 +; CHECK-FISL: xxlor f0, v2, v2 +; CHECK-FISL: fmr f1, f0 ; CHECK-FISL: blr ; CHECK-LE-LABEL: @test63 -; CHECK-LE: xxswapd 1, 34 +; CHECK-LE: xxswapd vs1, v2 ; CHECK-LE: blr } @@ -1000,17 +1023,18 @@ ret double %v ; CHECK-REG-LABEL: @test64 -; CHECK-REG: xxswapd 1, 34 +; CHECK-REG: xxswapd vs1, v2 ; CHECK-REG: blr ; CHECK-FISL-LABEL: @test64 -; CHECK-FISL: xxswapd 34, 34 -; CHECK-FISL: xxlor 0, 34, 34 -; CHECK-FISL: fmr 1, 0 +; CHECK-FISL: xxswapd v2, v2 +; CHECK-FISL: xxlor f0, v2, v2 +; CHECK-FISL: fmr f1, f0 ; CHECK-FISL: blr ; CHECK-LE-LABEL: @test64 -; CHECK-LE: xxlor 1, 34, 34 +; CHECK-LE: xxlor f1, v2, v2 +; CHECK-LE: blr } define <2 x i1> @test65(<2 x i64> %a, <2 x i64> %b) { @@ -1018,15 +1042,15 @@ ret <2 x i1> %w ; CHECK-REG-LABEL: @test65 -; CHECK-REG: vcmpequw 2, 2, 3 +; CHECK-REG: vcmpequw v2, v2, v3 ; CHECK-REG: blr ; CHECK-FISL-LABEL: @test65 -; CHECK-FISL: vcmpequw 2, 2, 3 +; CHECK-FISL: vcmpequw v2, v2, v3 ; CHECK-FISL: blr ; CHECK-LE-LABEL: @test65 -; CHECK-LE: vcmpequd 2, 2, 3 +; CHECK-LE: vcmpequd v2, v2, v3 ; CHECK-LE: blr } @@ -1035,18 +1059,18 @@ ret <2 x i1> %w ; CHECK-REG-LABEL: @test66 -; CHECK-REG: vcmpequw {{[0-9]+}}, 2, 3 -; CHECK-REG: xxlnor 34, {{[0-9]+}}, {{[0-9]+}} +; CHECK-REG: vcmpequw v2, v2, v3 +; CHECK-REG: xxlnor v2, v2, v2 ; CHECK-REG: blr ; CHECK-FISL-LABEL: @test66 -; CHECK-FISL: vcmpequw 2, 2, 3 -; CHECK-FISL: xxlnor 34, 34, 34 +; CHECK-FISL: vcmpequw v2, v2, v3 +; CHECK-FISL: xxlnor v2, v2, v2 ; CHECK-FISL: blr ; CHECK-LE-LABEL: @test66 -; CHECK-LE: vcmpequd {{[0-9]+}}, 2, 3 -; CHECK-LE: xxlnor 34, {{[0-9]+}}, {{[0-9]+}} +; CHECK-LE: vcmpequd v2, v2, v3 +; CHECK-LE: xxlnor v2, v2, v2 ; CHECK-LE: blr } @@ -1056,15 +1080,15 @@ ; CHECK-LABEL: @test67 ; This should scalarize, and the current code quality is not good. -; CHECK: stxvd2x -; CHECK: stxvd2x -; CHECK: cmpld -; CHECK: cmpld -; CHECK: lxvd2x +; CHECK: stxvd2x v3, 0, r3 +; CHECK: stxvd2x v2, 0, r4 +; CHECK: cmpld r4, r3 +; CHECK: cmpld r6, r5 +; CHECK: lxvd2x v2, 0, r3 ; CHECK: blr ; CHECK-LE-LABEL: @test67 -; CHECK-LE: vcmpgtud 2, 3, 2 +; CHECK-LE: vcmpgtud v2, v3, v2 ; CHECK-LE: blr } @@ -1073,13 +1097,13 @@ ret <2 x double> %w ; CHECK-LABEL: @test68 -; CHECK: xxmrghw [[V1:[0-9]+]] -; CHECK: xvcvsxwdp 34, [[V1]] +; CHECK: xxmrghw vs0, v2, v2 +; CHECK: xvcvsxwdp v2, vs0 ; CHECK: blr ; CHECK-LE-LABEL: @test68 -; CHECK-LE: xxmrglw [[V1:[0-9]+]], 34, 34 -; CHECK-LE: xvcvsxwdp 34, [[V1]] +; CHECK-LE: xxmrglw v2, v2, v2 +; CHECK-LE: xvcvsxwdp v2, v2 ; CHECK-LE: blr } @@ -1089,11 +1113,11 @@ ret <2 x double> %w ; CHECK-LABEL: @test69 -; CHECK-DAG: lfiwax -; CHECK-DAG: lfiwax -; CHECK-DAG: xscvsxddp -; CHECK-DAG: xscvsxddp -; CHECK: xxmrghd +; CHECK-DAG: lfiwax f0, 0, r3 +; CHECK-DAG: lfiwax f1, 0, r3 +; CHECK-DAG: xscvsxddp f0, f0 +; CHECK-DAG: xscvsxddp f1, f1 +; CHECK: xxmrghd v2, vs1, vs0 ; CHECK: blr ; CHECK-LE-LABEL: @test69 @@ -1112,11 +1136,11 @@ ret <2 x double> %w ; CHECK-LABEL: @test70 -; CHECK-DAG: lfiwax -; CHECK-DAG: lfiwax -; CHECK-DAG: xscvsxddp -; CHECK-DAG: xscvsxddp -; CHECK: xxmrghd +; CHECK-DAG: lfiwax f0, 0, r3 +; CHECK-DAG: lfiwax f1, 0, r3 +; CHECK-DAG: xscvsxddp f0, f0 +; CHECK-DAG: xscvsxddp f1, f1 +; CHECK: xxmrghd v2, vs1, vs0 ; CHECK: blr ; CHECK-LE-LABEL: @test70 @@ -1137,38 +1161,38 @@ ret <2 x i32> %i ; CHECK-REG-LABEL: @test80 -; CHECK-REG-DAG: stw 3, -16(1) -; CHECK-REG-DAG: addi [[R1:[0-9]+]], 1, -16 -; CHECK-REG: addis [[R2:[0-9]+]] -; CHECK-REG-DAG: addi [[R2]], [[R2]] -; CHECK-REG-DAG: lxvw4x [[VS1:[0-9]+]], 0, [[R1]] -; CHECK-REG-DAG: lxvw4x 35, 0, [[R2]] -; CHECK-REG: xxspltw 34, [[VS1]], 0 -; CHECK-REG: vadduwm 2, 2, 3 +; CHECK-REG-DAG: stw r3, -16(r1) +; CHECK-REG-DAG: addi r4, r1, -16 +; CHECK-REG: addis r3, r2, .LCPI65_0@toc@ha +; CHECK-REG-DAG: addi r3, r3, .LCPI65_0@toc@l +; CHECK-REG-DAG: lxvw4x vs0, 0, r4 +; CHECK-REG-DAG: lxvw4x v3, 0, r3 +; CHECK-REG: xxspltw v2, vs0, 0 +; CHECK-REG: vadduwm v2, v2, v3 ; CHECK-REG-NOT: stxvw4x ; CHECK-REG: blr ; CHECK-FISL-LABEL: @test80 -; CHECK-FISL: mr 4, 3 -; CHECK-FISL: stw 4, -16(1) -; CHECK-FISL: addi [[R1:[0-9]+]], 1, -16 -; CHECK-FISL-DAG: lxvw4x [[VS1:[0-9]+]], 0, [[R1]] -; CHECK-FISL-DAG: xxspltw {{[0-9]+}}, [[VS1]], 0 -; CHECK-FISL: addis [[R2:[0-9]+]] -; CHECK-FISL: addi [[R2]], [[R2]] -; CHECK-FISL-DAG: lxvw4x {{[0-9]+}}, 0, [[R2]] +; CHECK-FISL: mr r4, r3 +; CHECK-FISL: stw r4, -16(r1) +; CHECK-FISL: addi r3, r1, -16 +; CHECK-FISL-DAG: lxvw4x vs0, 0, r3 +; CHECK-FISL-DAG: xxspltw v2, vs0, 0 +; CHECK-FISL: addis r3, r2, .LCPI65_0@toc@ha +; CHECK-FISL: addi r3, r3, .LCPI65_0@toc@l +; CHECK-FISL-DAG: lxvw4x v3, 0, r3 ; CHECK-FISL: vadduwm ; CHECK-FISL-NOT: stxvw4x ; CHECK-FISL: blr ; CHECK-LE-LABEL: @test80 -; CHECK-LE-DAG: mtvsrd [[R1:[0-9]+]], 3 -; CHECK-LE-DAG: xxswapd [[V1:[0-9]+]], [[R1]] -; CHECK-LE-DAG: addi [[R2:[0-9]+]], {{[0-9]+}}, .LCPI -; CHECK-LE-DAG: lvx 3, 0, [[R2]] -; CHECK-LE-DAG: xxspltw 34, [[V1]] -; CHECK-LE-NOT: xxswapd 35, [[V2]] -; CHECK-LE: vadduwm 2, 2, 3 +; CHECK-LE-DAG: mtvsrd f0, r3 +; CHECK-LE-DAG: xxswapd vs0, vs0 +; CHECK-LE-DAG: addi r3, r4, .LCPI65_0@toc@l +; CHECK-LE-DAG: lvx v3, 0, r3 +; CHECK-LE-DAG: xxspltw v2, vs0, 3 +; CHECK-LE-NOT: xxswapd v3, +; CHECK-LE: vadduwm v2, v2, v3 ; CHECK-LE: blr } @@ -1190,26 +1214,26 @@ ret double %v ; CHECK-REG-LABEL: @test82 -; CHECK-REG: xscmpudp [[REG:[0-9]+]], 3, 4 -; CHECK-REG: beqlr [[REG]] +; CHECK-REG: xscmpudp cr0, f3, f4 +; CHECK-REG: beqlr cr0 ; CHECK-FISL-LABEL: @test82 -; CHECK-FISL: xscmpudp [[REG:[0-9]+]], 3, 4 -; CHECK-FISL: beq [[REG]], {{.*}} +; CHECK-FISL: xscmpudp cr0, f3, f4 +; CHECK-FISL: beq cr0 ; CHECK-LE-LABEL: @test82 -; CHECK-LE: xscmpudp [[REG:[0-9]+]], 3, 4 -; CHECK-LE: beqlr [[REG]] +; CHECK-LE: xscmpudp cr0, f3, f4 +; CHECK-LE: beqlr cr0 } ; Function Attrs: nounwind readnone define <4 x i32> @test83(i8* %a) { entry: %0 = tail call <4 x i32> @llvm.ppc.vsx.lxvw4x.be(i8* %a) - ret <4 x i32> %0 - ; CHECK-LABEL: test83 - ; CHECK: lxvw4x 34, 0, 3 - ; CHECK: blr + ret <4 x i32> %0 +; CHECK-LABEL: test83 +; CHECK: lxvw4x v2, 0, r3 +; CHECK: blr } ; Function Attrs: nounwind readnone declare <4 x i32> @llvm.ppc.vsx.lxvw4x.be(i8*) @@ -1218,10 +1242,10 @@ define <2 x double> @test84(i8* %a) { entry: %0 = tail call <2 x double> @llvm.ppc.vsx.lxvd2x.be(i8* %a) - ret <2 x double> %0 - ; CHECK-LABEL: test84 - ; CHECK: lxvd2x 34, 0, 3 - ; CHECK: blr + ret <2 x double> %0 +; CHECK-LABEL: test84 +; CHECK: lxvd2x v2, 0, r3 +; CHECK: blr } ; Function Attrs: nounwind readnone declare <2 x double> @llvm.ppc.vsx.lxvd2x.be(i8*) @@ -1231,10 +1255,11 @@ entry: tail call void @llvm.ppc.vsx.stxvw4x.be(<4 x i32> %a, i8* %b) ret void - ; CHECK-LABEL: test85 - ; CHECK: stxvw4x 34, 0, 5 - ; CHECK: blr +; CHECK-LABEL: test85 +; CHECK: stxvw4x v2, 0, r5 +; CHECK: blr } + ; Function Attrs: nounwind readnone declare void @llvm.ppc.vsx.stxvw4x.be(<4 x i32>, i8*) @@ -1243,9 +1268,9 @@ entry: tail call void @llvm.ppc.vsx.stxvd2x.be(<2 x double> %a, i8* %b) ret void - ; CHECK-LABEL: test86 - ; CHECK: stxvd2x 34, 0, 5 - ; CHECK: blr +; CHECK-LABEL: test86 +; CHECK: stxvd2x v2, 0, r5 +; CHECK: blr } ; Function Attrs: nounwind readnone declare void @llvm.ppc.vsx.stxvd2x.be(<2 x double>, i8*)