Index: lib/Target/AMDGPU/AMDGPUISelLowering.cpp =================================================================== --- lib/Target/AMDGPU/AMDGPUISelLowering.cpp +++ lib/Target/AMDGPU/AMDGPUISelLowering.cpp @@ -945,11 +945,7 @@ unsigned NumRegs = getNumRegistersForCallingConv(Ctx, ArgVT); - if (!Subtarget->isAmdHsaOS() && - (ArgVT == MVT::i16 || ArgVT == MVT::i8 || ArgVT == MVT::f16)) { - // The ABI says the caller will extend these values to 32-bits. - MemVT = ArgVT.isInteger() ? MVT::i32 : MVT::f32; - } else if (NumRegs == 1) { + if (NumRegs == 1) { // This argument is not split, so the IR type is the memory type. if (ArgVT.isExtended()) { // We have an extended type, like i24, so we should just use the Index: lib/Target/AMDGPU/AMDGPULowerKernelArguments.cpp =================================================================== --- lib/Target/AMDGPU/AMDGPULowerKernelArguments.cpp +++ lib/Target/AMDGPU/AMDGPULowerKernelArguments.cpp @@ -100,16 +100,6 @@ unsigned Size = DL.getTypeSizeInBits(ArgTy); unsigned AllocSize = DL.getTypeAllocSize(ArgTy); - - // Clover seems to always pad i8/i16 to i32, but doesn't properly align - // them? - // Make sure the struct elements have correct size and alignment for ext - // args. These seem to be padded up to 4-bytes but not correctly aligned. - bool IsExtArg = AllocSize < 32 && (Arg.hasZExtAttr() || Arg.hasSExtAttr()) && - !ST.isAmdHsaOS(); - if (IsExtArg) - AllocSize = 4; - uint64_t EltOffset = alignTo(ExplicitArgOffset, Align) + BaseOffset; ExplicitArgOffset = alignTo(ExplicitArgOffset, Align) + AllocSize; @@ -164,8 +154,6 @@ ArgPtr->getName() + ".cast"); } - assert((!IsExtArg || !IsV3) && "incompatible situation"); - if (IsV3 && Size >= 32) { V4Ty = VectorType::get(VT->getVectorElementType(), 4); // Use the hack that clang uses to avoid SelectionDAG ruining v3 loads @@ -212,20 +200,6 @@ // TODO: Convert noalias arg to !noalias if (Size < 32 && !ArgTy->isAggregateType()) { - if (IsExtArg && OffsetDiff == 0) { - Type *I32Ty = Builder.getInt32Ty(); - bool IsSext = Arg.hasSExtAttr(); - Metadata *LowAndHigh[] = { - ConstantAsMetadata::get( - ConstantInt::get(I32Ty, IsSext ? minIntN(Size) : 0)), - ConstantAsMetadata::get( - ConstantInt::get(I32Ty, - IsSext ? maxIntN(Size) + 1 : maxUIntN(Size) + 1)) - }; - - Load->setMetadata(LLVMContext::MD_range, MDNode::get(Ctx, LowAndHigh)); - } - Value *ExtractBits = OffsetDiff == 0 ? Load : Builder.CreateLShr(Load, OffsetDiff * 8); Index: test/CodeGen/AMDGPU/kernel-args.ll =================================================================== --- test/CodeGen/AMDGPU/kernel-args.ll +++ test/CodeGen/AMDGPU/kernel-args.ll @@ -1,19 +1,28 @@ ; RUN: llc < %s -march=amdgcn -verify-machineinstrs | FileCheck -allow-deprecated-dag-overlap -enable-var-scope --check-prefixes=SI,GCN,MESA-GCN,FUNC %s ; RUN: llc < %s -march=amdgcn -mcpu=tonga -mattr=-flat-for-global -verify-machineinstrs | FileCheck -allow-deprecated-dag-overlap -enable-var-scope -check-prefixes=VI,GCN,MESA-VI,MESA-GCN,FUNC %s ; RUN: llc < %s -mtriple=amdgcn--amdhsa -mcpu=fiji -verify-machineinstrs | FileCheck -allow-deprecated-dag-overlap -enable-var-scope -check-prefixes=VI,GCN,HSA-VI,FUNC %s -; RUN: llc < %s -march=r600 -mcpu=redwood -verify-machineinstrs | FileCheck -allow-deprecated-dag-overlap -enable-var-scope -check-prefix=EG --check-prefix=FUNC %s -; RUN: llc < %s -march=r600 -mcpu=cayman -verify-machineinstrs | FileCheck -allow-deprecated-dag-overlap -enable-var-scope --check-prefix=EG --check-prefix=FUNC %s +; RUN: llc < %s -march=r600 -mcpu=redwood -verify-machineinstrs | FileCheck -allow-deprecated-dag-overlap -enable-var-scope -check-prefixes=EG,EGCM,FUNC %s +; RUN: llc < %s -march=r600 -mcpu=cayman -verify-machineinstrs | FileCheck -allow-deprecated-dag-overlap -enable-var-scope --check-prefixes=CM,EGCM,FUNC %s ; FUNC-LABEL: {{^}}i8_arg: ; HSA-VI: kernarg_segment_byte_size = 12 ; HSA-VI: kernarg_segment_alignment = 4 -; EG: AND_INT {{[ *]*}}T{{[0-9]+\.[XYZW]}}, KC0[2].Z + ; SI: s_load_dword [[VAL:s[0-9]+]], s[{{[0-9]+:[0-9]+}}], 0xb ; MESA-VI: s_load_dword [[VAL:s[0-9]+]], s[{{[0-9]+:[0-9]+}}], 0x2c ; MESA-GCN: s_and_b32 s{{[0-9]+}}, [[VAL]], 0xff ; HSA-VI: s_load_dword [[VAL:s[0-9]+]], s[{{[0-9]+:[0-9]+}}], 0x8 ; HSA-VI: s_and_b32 s{{[0-9]+}}, [[VAL]], 0xff + + +; EG: LSHR T0.X, KC0[2].Y, literal.x, +; EG-NEXT: MOV * T1.X, KC0[2].Z, +; EG-NEXT: 2(2.802597e-45), 0(0.000000e+00) + +; CM: LSHR * T0.X, KC0[2].Y, literal.x, +; CM-NEXT: 2(2.802597e-45), 0(0.000000e+00) +; CM-NEXT: MOV * T1.X, KC0[2].Z, define amdgpu_kernel void @i8_arg(i32 addrspace(1)* nocapture %out, i8 %in) nounwind { %ext = zext i8 %in to i32 store i32 %ext, i32 addrspace(1)* %out, align 4 @@ -23,12 +32,21 @@ ; FUNC-LABEL: {{^}}i8_zext_arg: ; HSA-VI: kernarg_segment_byte_size = 12 ; HSA-VI: kernarg_segment_alignment = 4 -; EG: MOV {{[ *]*}}T{{[0-9]+\.[XYZW]}}, KC0[2].Z ; SI: s_load_dword s{{[0-9]}}, s[0:1], 0xb ; MESA-VI: s_load_dword s{{[0-9]}}, s[0:1], 0x2c ; HSA-VI: s_load_dword [[VAL:s[0-9]+]], s[{{[0-9]+:[0-9]+}}], 0x8 ; HSA-VI: s_and_b32 s{{[0-9]+}}, [[VAL]], 0xff + + +; EG: BFE_INT T0.X, T0.X, 0.0, literal.x, +; EG-NEXT: LSHR * T1.X, KC0[2].Y, literal.y, +; EG-NEXT: 8(1.121039e-44), 2(2.802597e-45) + +; CM: BFE_INT * T0.X, T0.X, 0.0, literal.x, +; CM-NEXT: 8(1.121039e-44), 0(0.000000e+00) +; CM-NEXT: LSHR * T1.X, KC0[2].Y, literal.x, +; CM-NEXT: 2(2.802597e-45), 0(0.000000e+00) define amdgpu_kernel void @i8_zext_arg(i32 addrspace(1)* nocapture %out, i8 zeroext %in) nounwind { %ext = zext i8 %in to i32 store i32 %ext, i32 addrspace(1)* %out, align 4 @@ -38,7 +56,6 @@ ; FUNC-LABEL: {{^}}i8_sext_arg: ; HSA-VI: kernarg_segment_byte_size = 12 ; HSA-VI: kernarg_segment_alignment = 4 -; EG: MOV {{[ *]*}}T{{[0-9]+\.[XYZW]}}, KC0[2].Z ; SI: s_load_dword s{{[0-9]}}, s[0:1], 0xb ; MESA-VI: s_load_dword s{{[0-9]}}, s[0:1], 0x2c @@ -46,6 +63,16 @@ ; HSA-VI: s_load_dword [[VAL:s[0-9]+]], s[{{[0-9]+:[0-9]+}}], 0x8 ; HSA-VI: s_sext_i32_i8 s{{[0-9]+}}, [[VAL]] ; HSA-VI: flat_store_dword + + +; EG: BFE_INT T0.X, T0.X, 0.0, literal.x, +; EG-NEXT: LSHR * T1.X, KC0[2].Y, literal.y, +; EG-NEXT: 8(1.121039e-44), 2(2.802597e-45) + +; CM: BFE_INT * T0.X, T0.X, 0.0, literal.x, +; CM-NEXT: 8(1.121039e-44), 0(0.000000e+00) +; CM-NEXT: LSHR * T1.X, KC0[2].Y, literal.x, +; CM-NEXT: 2(2.802597e-45), 0(0.000000e+00) define amdgpu_kernel void @i8_sext_arg(i32 addrspace(1)* nocapture %out, i8 signext %in) nounwind { %ext = sext i8 %in to i32 store i32 %ext, i32 addrspace(1)* %out, align 4 @@ -56,7 +83,6 @@ ; HSA-VI: kernarg_segment_byte_size = 12 ; HSA-VI: kernarg_segment_alignment = 4 -; EG: AND_INT {{[ *]*}}T{{[0-9]+\.[XYZW]}}, KC0[2].Z ; SI: s_load_dword [[VAL:s[0-9]+]], s[{{[0-9]+:[0-9]+}}], 0xb ; MESA-VI: s_load_dword [[VAL:s[0-9]+]], s[{{[0-9]+:[0-9]+}}], 0x2c @@ -65,6 +91,15 @@ ; HSA-VI: s_load_dword [[VAL:s[0-9]+]], s[{{[0-9]+:[0-9]+}}], 0x8 ; HSA-VI: s_and_b32 s{{[0-9]+}}, [[VAL]], 0xffff{{$}} ; HSA-VI: flat_store_dword + + +; EG: LSHR T0.X, KC0[2].Y, literal.x, +; EG-NEXT: MOV * T1.X, KC0[2].Z, +; EG-NEXT: 2(2.802597e-45), 0(0.000000e+00) + +; CM: LSHR * T0.X, KC0[2].Y, literal.x, +; CM-NEXT: 2(2.802597e-45), 0(0.000000e+00) +; CM-NEXT: MOV * T1.X, KC0[2].Z, define amdgpu_kernel void @i16_arg(i32 addrspace(1)* nocapture %out, i16 %in) nounwind { %ext = zext i16 %in to i32 store i32 %ext, i32 addrspace(1)* %out, align 4 @@ -75,13 +110,21 @@ ; HSA-VI: kernarg_segment_byte_size = 12 ; HSA-VI: kernarg_segment_alignment = 4 -; EG: MOV {{[ *]*}}T{{[0-9]+\.[XYZW]}}, KC0[2].Z ; SI: s_load_dword s{{[0-9]}}, s[0:1], 0xb ; MESA-VI: s_load_dword s{{[0-9]}}, s[0:1], 0x2c ; HSA-VI: s_load_dword [[VAL:s[0-9]+]], s[{{[0-9]+:[0-9]+}}], 0x8 ; HSA-VI: s_and_b32 s{{[0-9]+}}, [[VAL]], 0xffff{{$}} ; HSA-VI: flat_store_dword + +; EG: BFE_INT T0.X, T0.X, 0.0, literal.x, +; EG-NEXT: LSHR * T1.X, KC0[2].Y, literal.y, +; EG-NEXT: 16(2.242078e-44), 2(2.802597e-45) + +; CM: BFE_INT * T0.X, T0.X, 0.0, literal.x, +; CM-NEXT: 16(2.242078e-44), 0(0.000000e+00) +; CM-NEXT: LSHR * T1.X, KC0[2].Y, literal.x, +; CM-NEXT: 2(2.802597e-45), 0(0.000000e+00) define amdgpu_kernel void @i16_zext_arg(i32 addrspace(1)* nocapture %out, i16 zeroext %in) nounwind { %ext = zext i16 %in to i32 store i32 %ext, i32 addrspace(1)* %out, align 4 @@ -92,7 +135,6 @@ ; HSA-VI: kernarg_segment_byte_size = 12 ; HSA-VI: kernarg_segment_alignment = 4 -; EG: MOV {{[ *]*}}T{{[0-9]+\.[XYZW]}}, KC0[2].Z ; SI: s_load_dword s{{[0-9]}}, s[0:1], 0xb ; MESA-VI: s_load_dword s{{[0-9]}}, s[0:1], 0x2c @@ -100,6 +142,15 @@ ; HSA-VI: s_load_dword [[VAL:s[0-9]+]], s[{{[0-9]+:[0-9]+}}], 0x8 ; HSA-VI: s_sext_i32_i16 s{{[0-9]+}}, [[VAL]] ; HSA-VI: flat_store_dword + +; EG: BFE_INT T0.X, T0.X, 0.0, literal.x, +; EG-NEXT: LSHR * T1.X, KC0[2].Y, literal.y, +; EG-NEXT: 16(2.242078e-44), 2(2.802597e-45) + +; CM: BFE_INT * T0.X, T0.X, 0.0, literal.x, +; CM-NEXT: 16(2.242078e-44), 0(0.000000e+00) +; CM-NEXT: LSHR * T1.X, KC0[2].Y, literal.x, +; CM-NEXT: 2(2.802597e-45), 0(0.000000e+00) define amdgpu_kernel void @i16_sext_arg(i32 addrspace(1)* nocapture %out, i16 signext %in) nounwind { %ext = sext i16 %in to i32 store i32 %ext, i32 addrspace(1)* %out, align 4 @@ -110,7 +161,7 @@ ; HSA-VI: kernarg_segment_byte_size = 12 ; HSA-VI: kernarg_segment_alignment = 4 -; EG: T{{[0-9]\.[XYZW]}}, KC0[2].Z +; EGCM: T{{[0-9]\.[XYZW]}}, KC0[2].Z ; SI: s_load_dword s{{[0-9]}}, s[0:1], 0xb ; MESA-VI: s_load_dword s{{[0-9]}}, s[0:1], 0x2c ; HSA-VI: s_load_dword s{{[0-9]}}, s[4:5], 0x8 @@ -123,7 +174,7 @@ ; FUNC-LABEL: {{^}}f32_arg: ; HSA-VI: kernarg_segment_byte_size = 12 ; HSA-VI: kernarg_segment_alignment = 4 -; EG: T{{[0-9]\.[XYZW]}}, KC0[2].Z +; EGCM: T{{[0-9]\.[XYZW]}}, KC0[2].Z ; SI: s_load_dword s{{[0-9]}}, s[0:1], 0xb ; MESA-VI: s_load_dword s{{[0-9]}}, s[0:1], 0x2c ; HSA-VI: s_load_dword s{{[0-9]+}}, s[4:5], 0x8 @@ -137,8 +188,8 @@ ; HSA-VI: kernarg_segment_byte_size = 12 ; HSA-VI: kernarg_segment_alignment = 4 -; EG: VTX_READ_8 -; EG: VTX_READ_8 +; EGCM: VTX_READ_8 +; EGCM: VTX_READ_8 ; GCN: s_load_dword s ; GCN-NOT: {{buffer|flat|global}}_load_ @@ -152,8 +203,8 @@ ; HSA-VI: kernarg_segment_byte_size = 12 ; HSA-VI: kernarg_segment_alignment = 4 -; EG: VTX_READ_16 -; EG: VTX_READ_16 +; EGCM: VTX_READ_16 +; EGCM: VTX_READ_16 ; SI: s_load_dword s{{[0-9]+}}, s[0:1], 0xb ; MESA-VI: s_load_dword s{{[0-9]+}}, s{{\[[0-9]+:[0-9]+\]}}, 0x2c @@ -168,8 +219,8 @@ ; HSA-VI: kernarg_segment_byte_size = 16 ; HSA-VI: kernarg_segment_alignment = 4 -; EG-DAG: T{{[0-9]\.[XYZW]}}, KC0[3].X -; EG-DAG: T{{[0-9]\.[XYZW]}}, KC0[2].W +; EGCM-DAG: T{{[0-9]\.[XYZW]}}, KC0[3].X +; EGCM-DAG: T{{[0-9]\.[XYZW]}}, KC0[2].W ; SI: s_load_dwordx2 s{{\[[0-9]:[0-9]\]}}, s[0:1], 0xb ; MESA-VI: s_load_dwordx2 s{{\[[0-9]:[0-9]\]}}, s[0:1], 0x2c ; HSA-VI: s_load_dwordx2 s[{{[0-9]+:[0-9]+}}], s[4:5], 0x8 @@ -183,8 +234,8 @@ ; HSA-VI: kernarg_segment_byte_size = 16 ; HSA-VI: kernarg_segment_alignment = 4 -; EG-DAG: T{{[0-9]\.[XYZW]}}, KC0[3].X -; EG-DAG: T{{[0-9]\.[XYZW]}}, KC0[2].W +; EGCM-DAG: T{{[0-9]\.[XYZW]}}, KC0[3].X +; EGCM-DAG: T{{[0-9]\.[XYZW]}}, KC0[2].W ; SI: s_load_dwordx2 s{{\[[0-9]:[0-9]\]}}, s[0:1], 0xb ; MESA-VI: s_load_dwordx2 s{{\[[0-9]:[0-9]\]}}, s[0:1], 0x2c ; HSA-VI: s_load_dwordx2 s{{\[[0-9]:[0-9]\]}}, s[4:5], 0x8 @@ -198,9 +249,9 @@ ; HSA-VI: kernarg_segment_byte_size = 12 ; HSA-VI: kernarg_segment_alignment = 4 -; EG-DAG: VTX_READ_8 T{{[0-9]}}.X, T{{[0-9]}}.X, 40 -; EG-DAG: VTX_READ_8 T{{[0-9]}}.X, T{{[0-9]}}.X, 41 -; EG-DAG: VTX_READ_8 T{{[0-9]}}.X, T{{[0-9]}}.X, 42 +; EGCM-DAG: VTX_READ_8 T{{[0-9]}}.X, T{{[0-9]}}.X, 40 +; EGCM-DAG: VTX_READ_8 T{{[0-9]}}.X, T{{[0-9]}}.X, 41 +; EGCM-DAG: VTX_READ_8 T{{[0-9]}}.X, T{{[0-9]}}.X, 42 ; SI: s_load_dword s{{[0-9]+}}, s{{\[[0-9]+:[0-9]+\]}}, 0xb @@ -216,9 +267,9 @@ ; HSA-VI: kernarg_segment_byte_size = 16 ; HSA-VI: kernarg_segment_alignment = 4 -; EG-DAG: VTX_READ_16 T{{[0-9]}}.X, T{{[0-9]}}.X, 44 -; EG-DAG: VTX_READ_16 T{{[0-9]}}.X, T{{[0-9]}}.X, 46 -; EG-DAG: VTX_READ_16 T{{[0-9]}}.X, T{{[0-9]}}.X, 48 +; EGCM-DAG: VTX_READ_16 T{{[0-9]}}.X, T{{[0-9]}}.X, 44 +; EGCM-DAG: VTX_READ_16 T{{[0-9]}}.X, T{{[0-9]}}.X, 46 +; EGCM-DAG: VTX_READ_16 T{{[0-9]}}.X, T{{[0-9]}}.X, 48 ; SI: s_load_dwordx2 s{{\[[0-9]+:[0-9]+\]}}, s{{\[[0-9]+:[0-9]+\]}}, 0xb @@ -233,9 +284,9 @@ ; FUNC-LABEL: {{^}}v3i32_arg: ; HSA-VI: kernarg_segment_byte_size = 32 ; HSA-VI: kernarg_segment_alignment = 4 -; EG-DAG: T{{[0-9]\.[XYZW]}}, KC0[3].Y -; EG-DAG: T{{[0-9]\.[XYZW]}}, KC0[3].Z -; EG-DAG: T{{[0-9]\.[XYZW]}}, KC0[3].W +; EGCM-DAG: T{{[0-9]\.[XYZW]}}, KC0[3].Y +; EGCM-DAG: T{{[0-9]\.[XYZW]}}, KC0[3].Z +; EGCM-DAG: T{{[0-9]\.[XYZW]}}, KC0[3].W ; SI: s_load_dwordx4 s{{\[[0-9]:[0-9]+\]}}, s[0:1], 0xd ; MESA-VI: s_load_dwordx4 s{{\[[0-9]:[0-9]+\]}}, s[0:1], 0x34 ; HSA-VI: s_load_dwordx4 s[{{[0-9]+:[0-9]+}}], s[4:5], 0x10 @@ -248,9 +299,9 @@ ; FUNC-LABEL: {{^}}v3f32_arg: ; HSA-VI: kernarg_segment_byte_size = 32 ; HSA-VI: kernarg_segment_alignment = 4 -; EG-DAG: T{{[0-9]\.[XYZW]}}, KC0[3].Y -; EG-DAG: T{{[0-9]\.[XYZW]}}, KC0[3].Z -; EG-DAG: T{{[0-9]\.[XYZW]}}, KC0[3].W +; EGCM-DAG: T{{[0-9]\.[XYZW]}}, KC0[3].Y +; EGCM-DAG: T{{[0-9]\.[XYZW]}}, KC0[3].Z +; EGCM-DAG: T{{[0-9]\.[XYZW]}}, KC0[3].W ; SI: s_load_dwordx4 s{{\[[0-9]:[0-9]+\]}}, s[0:1], 0xd ; MESA-VI: s_load_dwordx4 s{{\[[0-9]:[0-9]+\]}}, s[0:1], 0x34 ; HSA-VI: s_load_dwordx4 s[{{[0-9]+:[0-9]+}}], s[4:5], 0x10 @@ -263,10 +314,10 @@ ; FUNC-LABEL: {{^}}v4i8_arg: ; HSA-VI: kernarg_segment_byte_size = 12 ; HSA-VI: kernarg_segment_alignment = 4 -; EG: VTX_READ_8 -; EG: VTX_READ_8 -; EG: VTX_READ_8 -; EG: VTX_READ_8 +; EGCM: VTX_READ_8 +; EGCM: VTX_READ_8 +; EGCM: VTX_READ_8 +; EGCM: VTX_READ_8 ; GCN-DAG: s_load_dwordx2 s ; GCN-DAG: s_load_dword s @@ -279,10 +330,10 @@ ; FUNC-LABEL: {{^}}v4i16_arg: ; HSA-VI: kernarg_segment_byte_size = 16 ; HSA-VI: kernarg_segment_alignment = 4 -; EG: VTX_READ_16 -; EG: VTX_READ_16 -; EG: VTX_READ_16 -; EG: VTX_READ_16 +; EGCM: VTX_READ_16 +; EGCM: VTX_READ_16 +; EGCM: VTX_READ_16 +; EGCM: VTX_READ_16 ; SI-DAG: s_load_dwordx2 s{{\[[0-9]+:[0-9]+\]}}, s[0:1], 0xb ; SI-DAG: s_load_dwordx2 s{{\[[0-9]+:[0-9]+\]}}, s[0:1], 0x9 @@ -305,10 +356,10 @@ ; FUNC-LABEL: {{^}}v4i32_arg: ; HSA-VI: kernarg_segment_byte_size = 32 ; HSA-VI: kernarg_segment_alignment = 4 -; EG-DAG: T{{[0-9]\.[XYZW]}}, KC0[3].Y -; EG-DAG: T{{[0-9]\.[XYZW]}}, KC0[3].Z -; EG-DAG: T{{[0-9]\.[XYZW]}}, KC0[3].W -; EG-DAG: T{{[0-9]\.[XYZW]}}, KC0[4].X +; EGCM-DAG: T{{[0-9]\.[XYZW]}}, KC0[3].Y +; EGCM-DAG: T{{[0-9]\.[XYZW]}}, KC0[3].Z +; EGCM-DAG: T{{[0-9]\.[XYZW]}}, KC0[3].W +; EGCM-DAG: T{{[0-9]\.[XYZW]}}, KC0[4].X ; SI: s_load_dwordx4 s{{\[[0-9]:[0-9]\]}}, s[0:1], 0xd ; MESA-VI: s_load_dwordx4 s{{\[[0-9]:[0-9]\]}}, s[0:1], 0x34 @@ -322,10 +373,10 @@ ; FUNC-LABEL: {{^}}v4f32_arg: ; HSA-VI: kernarg_segment_byte_size = 32 ; HSA-VI: kernarg_segment_alignment = 4 -; EG-DAG: T{{[0-9]\.[XYZW]}}, KC0[3].Y -; EG-DAG: T{{[0-9]\.[XYZW]}}, KC0[3].Z -; EG-DAG: T{{[0-9]\.[XYZW]}}, KC0[3].W -; EG-DAG: T{{[0-9]\.[XYZW]}}, KC0[4].X +; EGCM-DAG: T{{[0-9]\.[XYZW]}}, KC0[3].Y +; EGCM-DAG: T{{[0-9]\.[XYZW]}}, KC0[3].Z +; EGCM-DAG: T{{[0-9]\.[XYZW]}}, KC0[3].W +; EGCM-DAG: T{{[0-9]\.[XYZW]}}, KC0[4].X ; SI: s_load_dwordx4 s{{\[[0-9]:[0-9]\]}}, s[0:1], 0xd ; MESA-VI: s_load_dwordx4 s{{\[[0-9]:[0-9]\]}}, s[0:1], 0x34 ; HSA-VI: s_load_dwordx4 s[{{[0-9]+:[0-9]+}}], s[4:5], 0x10 @@ -339,14 +390,14 @@ ; FUNC-LABEL: {{^}}v8i8_arg: ; HSA-VI: kernarg_segment_byte_size = 16 ; HSA-VI: kernarg_segment_alignment = 4 -; EG: VTX_READ_8 -; EG: VTX_READ_8 -; EG: VTX_READ_8 -; EG: VTX_READ_8 -; EG: VTX_READ_8 -; EG: VTX_READ_8 -; EG: VTX_READ_8 -; EG: VTX_READ_8 +; EGCM: VTX_READ_8 +; EGCM: VTX_READ_8 +; EGCM: VTX_READ_8 +; EGCM: VTX_READ_8 +; EGCM: VTX_READ_8 +; EGCM: VTX_READ_8 +; EGCM: VTX_READ_8 +; EGCM: VTX_READ_8 ; SI-NOT: {{buffer|flat|global}}_load ; SI: s_load_dwordx2 s @@ -367,14 +418,14 @@ ; FUNC-LABEL: {{^}}v8i16_arg: ; HSA-VI: kernarg_segment_byte_size = 32 ; HSA-VI: kernarg_segment_alignment = 4 -; EG: VTX_READ_16 -; EG: VTX_READ_16 -; EG: VTX_READ_16 -; EG: VTX_READ_16 -; EG: VTX_READ_16 -; EG: VTX_READ_16 -; EG: VTX_READ_16 -; EG: VTX_READ_16 +; EGCM: VTX_READ_16 +; EGCM: VTX_READ_16 +; EGCM: VTX_READ_16 +; EGCM: VTX_READ_16 +; EGCM: VTX_READ_16 +; EGCM: VTX_READ_16 +; EGCM: VTX_READ_16 +; EGCM: VTX_READ_16 ; SI: s_load_dwordx4 ; SI-NEXT: s_load_dwordx2 @@ -393,14 +444,14 @@ ; FUNC-LABEL: {{^}}v8i32_arg: ; HSA-VI: kernarg_segment_byte_size = 64 ; HSA-VI: kernarg_segment_alignment = 5 -; EG-DAG: T{{[0-9]\.[XYZW]}}, KC0[4].Y -; EG-DAG: T{{[0-9]\.[XYZW]}}, KC0[4].Z -; EG-DAG: T{{[0-9]\.[XYZW]}}, KC0[4].W -; EG-DAG: T{{[0-9]\.[XYZW]}}, KC0[5].X -; EG-DAG: T{{[0-9]\.[XYZW]}}, KC0[5].Y -; EG-DAG: T{{[0-9]\.[XYZW]}}, KC0[5].Z -; EG-DAG: T{{[0-9]\.[XYZW]}}, KC0[5].W -; EG-DAG: T{{[0-9]\.[XYZW]}}, KC0[6].X +; EGCM-DAG: T{{[0-9]\.[XYZW]}}, KC0[4].Y +; EGCM-DAG: T{{[0-9]\.[XYZW]}}, KC0[4].Z +; EGCM-DAG: T{{[0-9]\.[XYZW]}}, KC0[4].W +; EGCM-DAG: T{{[0-9]\.[XYZW]}}, KC0[5].X +; EGCM-DAG: T{{[0-9]\.[XYZW]}}, KC0[5].Y +; EGCM-DAG: T{{[0-9]\.[XYZW]}}, KC0[5].Z +; EGCM-DAG: T{{[0-9]\.[XYZW]}}, KC0[5].W +; EGCM-DAG: T{{[0-9]\.[XYZW]}}, KC0[6].X ; SI: s_load_dwordx8 s{{\[[0-9]+:[0-9]+\]}}, s[0:1], 0x11 ; MESA-VI: s_load_dwordx8 s{{\[[0-9]+:[0-9]+\]}}, s[0:1], 0x44 @@ -414,14 +465,14 @@ ; FUNC-LABEL: {{^}}v8f32_arg: ; HSA-VI: kernarg_segment_byte_size = 64 ; HSA-VI: kernarg_segment_alignment = 5 -; EG-DAG: T{{[0-9]\.[XYZW]}}, KC0[4].Y -; EG-DAG: T{{[0-9]\.[XYZW]}}, KC0[4].Z -; EG-DAG: T{{[0-9]\.[XYZW]}}, KC0[4].W -; EG-DAG: T{{[0-9]\.[XYZW]}}, KC0[5].X -; EG-DAG: T{{[0-9]\.[XYZW]}}, KC0[5].Y -; EG-DAG: T{{[0-9]\.[XYZW]}}, KC0[5].Z -; EG-DAG: T{{[0-9]\.[XYZW]}}, KC0[5].W -; EG-DAG: T{{[0-9]\.[XYZW]}}, KC0[6].X +; EGCM-DAG: T{{[0-9]\.[XYZW]}}, KC0[4].Y +; EGCM-DAG: T{{[0-9]\.[XYZW]}}, KC0[4].Z +; EGCM-DAG: T{{[0-9]\.[XYZW]}}, KC0[4].W +; EGCM-DAG: T{{[0-9]\.[XYZW]}}, KC0[5].X +; EGCM-DAG: T{{[0-9]\.[XYZW]}}, KC0[5].Y +; EGCM-DAG: T{{[0-9]\.[XYZW]}}, KC0[5].Z +; EGCM-DAG: T{{[0-9]\.[XYZW]}}, KC0[5].W +; EGCM-DAG: T{{[0-9]\.[XYZW]}}, KC0[6].X ; SI: s_load_dwordx8 s{{\[[0-9]+:[0-9]+\]}}, s[0:1], 0x11 define amdgpu_kernel void @v8f32_arg(<8 x float> addrspace(1)* nocapture %out, <8 x float> %in) nounwind { entry: @@ -434,22 +485,22 @@ ; FUNC-LABEL: {{^}}v16i8_arg: ; HSA-VI: kernarg_segment_byte_size = 32 ; HSA-VI: kernarg_segment_alignment = 4 -; EG: VTX_READ_8 -; EG: VTX_READ_8 -; EG: VTX_READ_8 -; EG: VTX_READ_8 -; EG: VTX_READ_8 -; EG: VTX_READ_8 -; EG: VTX_READ_8 -; EG: VTX_READ_8 -; EG: VTX_READ_8 -; EG: VTX_READ_8 -; EG: VTX_READ_8 -; EG: VTX_READ_8 -; EG: VTX_READ_8 -; EG: VTX_READ_8 -; EG: VTX_READ_8 -; EG: VTX_READ_8 +; EGCM: VTX_READ_8 +; EGCM: VTX_READ_8 +; EGCM: VTX_READ_8 +; EGCM: VTX_READ_8 +; EGCM: VTX_READ_8 +; EGCM: VTX_READ_8 +; EGCM: VTX_READ_8 +; EGCM: VTX_READ_8 +; EGCM: VTX_READ_8 +; EGCM: VTX_READ_8 +; EGCM: VTX_READ_8 +; EGCM: VTX_READ_8 +; EGCM: VTX_READ_8 +; EGCM: VTX_READ_8 +; EGCM: VTX_READ_8 +; EGCM: VTX_READ_8 ; SI: s_load_dwordx4 s ; SI-NEXT: s_load_dwordx2 s @@ -470,23 +521,23 @@ ; FUNC-LABEL: {{^}}v16i16_arg: ; HSA-VI: kernarg_segment_byte_size = 64 ; HSA-VI: kernarg_segment_alignment = 5 -; EG: VTX_READ_16 -; EG: VTX_READ_16 -; EG: VTX_READ_16 -; EG: VTX_READ_16 -; EG: VTX_READ_16 - -; EG: VTX_READ_16 -; EG: VTX_READ_16 -; EG: VTX_READ_16 -; EG: VTX_READ_16 -; EG: VTX_READ_16 -; EG: VTX_READ_16 -; EG: VTX_READ_16 -; EG: VTX_READ_16 -; EG: VTX_READ_16 -; EG: VTX_READ_16 -; EG: VTX_READ_16 +; EGCM: VTX_READ_16 +; EGCM: VTX_READ_16 +; EGCM: VTX_READ_16 +; EGCM: VTX_READ_16 +; EGCM: VTX_READ_16 + +; EGCM: VTX_READ_16 +; EGCM: VTX_READ_16 +; EGCM: VTX_READ_16 +; EGCM: VTX_READ_16 +; EGCM: VTX_READ_16 +; EGCM: VTX_READ_16 +; EGCM: VTX_READ_16 +; EGCM: VTX_READ_16 +; EGCM: VTX_READ_16 +; EGCM: VTX_READ_16 +; EGCM: VTX_READ_16 ; SI: s_load_dwordx8 s ; SI-NEXT: s_load_dwordx2 s @@ -505,22 +556,22 @@ ; FUNC-LABEL: {{^}}v16i32_arg: ; HSA-VI: kernarg_segment_byte_size = 128 ; HSA-VI: kernarg_segment_alignment = 6 -; EG-DAG: T{{[0-9]\.[XYZW]}}, KC0[6].Y -; EG-DAG: T{{[0-9]\.[XYZW]}}, KC0[6].Z -; EG-DAG: T{{[0-9]\.[XYZW]}}, KC0[6].W -; EG-DAG: T{{[0-9]\.[XYZW]}}, KC0[7].X -; EG-DAG: T{{[0-9]\.[XYZW]}}, KC0[7].Y -; EG-DAG: T{{[0-9]\.[XYZW]}}, KC0[7].Z -; EG-DAG: T{{[0-9]\.[XYZW]}}, KC0[7].W -; EG-DAG: T{{[0-9]\.[XYZW]}}, KC0[8].X -; EG-DAG: T{{[0-9]\.[XYZW]}}, KC0[8].Y -; EG-DAG: T{{[0-9]\.[XYZW]}}, KC0[8].Z -; EG-DAG: T{{[0-9]\.[XYZW]}}, KC0[8].W -; EG-DAG: T{{[0-9]\.[XYZW]}}, KC0[9].X -; EG-DAG: T{{[0-9]\.[XYZW]}}, KC0[9].Y -; EG-DAG: T{{[0-9]\.[XYZW]}}, KC0[9].Z -; EG-DAG: T{{[0-9]\.[XYZW]}}, KC0[9].W -; EG-DAG: T{{[0-9]\.[XYZW]}}, KC0[10].X +; EGCM-DAG: T{{[0-9]\.[XYZW]}}, KC0[6].Y +; EGCM-DAG: T{{[0-9]\.[XYZW]}}, KC0[6].Z +; EGCM-DAG: T{{[0-9]\.[XYZW]}}, KC0[6].W +; EGCM-DAG: T{{[0-9]\.[XYZW]}}, KC0[7].X +; EGCM-DAG: T{{[0-9]\.[XYZW]}}, KC0[7].Y +; EGCM-DAG: T{{[0-9]\.[XYZW]}}, KC0[7].Z +; EGCM-DAG: T{{[0-9]\.[XYZW]}}, KC0[7].W +; EGCM-DAG: T{{[0-9]\.[XYZW]}}, KC0[8].X +; EGCM-DAG: T{{[0-9]\.[XYZW]}}, KC0[8].Y +; EGCM-DAG: T{{[0-9]\.[XYZW]}}, KC0[8].Z +; EGCM-DAG: T{{[0-9]\.[XYZW]}}, KC0[8].W +; EGCM-DAG: T{{[0-9]\.[XYZW]}}, KC0[9].X +; EGCM-DAG: T{{[0-9]\.[XYZW]}}, KC0[9].Y +; EGCM-DAG: T{{[0-9]\.[XYZW]}}, KC0[9].Z +; EGCM-DAG: T{{[0-9]\.[XYZW]}}, KC0[9].W +; EGCM-DAG: T{{[0-9]\.[XYZW]}}, KC0[10].X ; SI: s_load_dwordx16 s{{\[[0-9]+:[0-9]+\]}}, s[0:1], 0x19 ; MESA-VI: s_load_dwordx16 s{{\[[0-9]+:[0-9]+\]}}, s[0:1], 0x64 ; HSA-VI: s_load_dwordx16 s[{{[0-9]+:[0-9]+}}], s[4:5], 0x40 @@ -533,22 +584,22 @@ ; FUNC-LABEL: {{^}}v16f32_arg: ; HSA-VI: kernarg_segment_byte_size = 128 ; HSA-VI: kernarg_segment_alignment = 6 -; EG-DAG: T{{[0-9]\.[XYZW]}}, KC0[6].Y -; EG-DAG: T{{[0-9]\.[XYZW]}}, KC0[6].Z -; EG-DAG: T{{[0-9]\.[XYZW]}}, KC0[6].W -; EG-DAG: T{{[0-9]\.[XYZW]}}, KC0[7].X -; EG-DAG: T{{[0-9]\.[XYZW]}}, KC0[7].Y -; EG-DAG: T{{[0-9]\.[XYZW]}}, KC0[7].Z -; EG-DAG: T{{[0-9]\.[XYZW]}}, KC0[7].W -; EG-DAG: T{{[0-9]\.[XYZW]}}, KC0[8].X -; EG-DAG: T{{[0-9]\.[XYZW]}}, KC0[8].Y -; EG-DAG: T{{[0-9]\.[XYZW]}}, KC0[8].Z -; EG-DAG: T{{[0-9]\.[XYZW]}}, KC0[8].W -; EG-DAG: T{{[0-9]\.[XYZW]}}, KC0[9].X -; EG-DAG: T{{[0-9]\.[XYZW]}}, KC0[9].Y -; EG-DAG: T{{[0-9]\.[XYZW]}}, KC0[9].Z -; EG-DAG: T{{[0-9]\.[XYZW]}}, KC0[9].W -; EG-DAG: T{{[0-9]\.[XYZW]}}, KC0[10].X +; EGCM-DAG: T{{[0-9]\.[XYZW]}}, KC0[6].Y +; EGCM-DAG: T{{[0-9]\.[XYZW]}}, KC0[6].Z +; EGCM-DAG: T{{[0-9]\.[XYZW]}}, KC0[6].W +; EGCM-DAG: T{{[0-9]\.[XYZW]}}, KC0[7].X +; EGCM-DAG: T{{[0-9]\.[XYZW]}}, KC0[7].Y +; EGCM-DAG: T{{[0-9]\.[XYZW]}}, KC0[7].Z +; EGCM-DAG: T{{[0-9]\.[XYZW]}}, KC0[7].W +; EGCM-DAG: T{{[0-9]\.[XYZW]}}, KC0[8].X +; EGCM-DAG: T{{[0-9]\.[XYZW]}}, KC0[8].Y +; EGCM-DAG: T{{[0-9]\.[XYZW]}}, KC0[8].Z +; EGCM-DAG: T{{[0-9]\.[XYZW]}}, KC0[8].W +; EGCM-DAG: T{{[0-9]\.[XYZW]}}, KC0[9].X +; EGCM-DAG: T{{[0-9]\.[XYZW]}}, KC0[9].Y +; EGCM-DAG: T{{[0-9]\.[XYZW]}}, KC0[9].Z +; EGCM-DAG: T{{[0-9]\.[XYZW]}}, KC0[9].W +; EGCM-DAG: T{{[0-9]\.[XYZW]}}, KC0[10].X ; SI: s_load_dwordx16 s{{\[[0-9]+:[0-9]+\]}}, s[0:1], 0x19 ; MESA-VI: s_load_dwordx16 s{{\[[0-9]+:[0-9]+\]}}, s[0:1], 0x64 ; HSA-VI: s_load_dwordx16 s[{{[0-9]+:[0-9]+}}], s[4:5], 0x40 Index: test/CodeGen/AMDGPU/lower-kernargs.ll =================================================================== --- test/CodeGen/AMDGPU/lower-kernargs.ll +++ test/CodeGen/AMDGPU/lower-kernargs.ll @@ -98,7 +98,7 @@ ; MESA-NEXT: [[KERN_ZEROEXT_I8_KERNARG_SEGMENT:%.*]] = call nonnull align 16 dereferenceable(40) i8 addrspace(4)* @llvm.amdgcn.kernarg.segment.ptr() ; MESA-NEXT: [[ARG_KERNARG_OFFSET_ALIGN_DOWN:%.*]] = getelementptr inbounds i8, i8 addrspace(4)* [[KERN_ZEROEXT_I8_KERNARG_SEGMENT]], i64 36 ; MESA-NEXT: [[ARG_KERNARG_OFFSET_ALIGN_DOWN_CAST:%.*]] = bitcast i8 addrspace(4)* [[ARG_KERNARG_OFFSET_ALIGN_DOWN]] to i32 addrspace(4)* -; MESA-NEXT: [[TMP1:%.*]] = load i32, i32 addrspace(4)* [[ARG_KERNARG_OFFSET_ALIGN_DOWN_CAST]], align 4, !range !1, !invariant.load !0 +; MESA-NEXT: [[TMP1:%.*]] = load i32, i32 addrspace(4)* [[ARG_KERNARG_OFFSET_ALIGN_DOWN_CAST]], align 4, !invariant.load !0 ; MESA-NEXT: [[TMP2:%.*]] = trunc i32 [[TMP1]] to i8 ; MESA-NEXT: store i8 [[TMP2]], i8 addrspace(1)* undef, align 1 ; MESA-NEXT: ret void @@ -121,7 +121,7 @@ ; MESA-NEXT: [[KERN_ZEROEXT_I16_KERNARG_SEGMENT:%.*]] = call nonnull align 16 dereferenceable(40) i8 addrspace(4)* @llvm.amdgcn.kernarg.segment.ptr() ; MESA-NEXT: [[ARG_KERNARG_OFFSET_ALIGN_DOWN:%.*]] = getelementptr inbounds i8, i8 addrspace(4)* [[KERN_ZEROEXT_I16_KERNARG_SEGMENT]], i64 36 ; MESA-NEXT: [[ARG_KERNARG_OFFSET_ALIGN_DOWN_CAST:%.*]] = bitcast i8 addrspace(4)* [[ARG_KERNARG_OFFSET_ALIGN_DOWN]] to i32 addrspace(4)* -; MESA-NEXT: [[TMP1:%.*]] = load i32, i32 addrspace(4)* [[ARG_KERNARG_OFFSET_ALIGN_DOWN_CAST]], align 4, !range !2, !invariant.load !0 +; MESA-NEXT: [[TMP1:%.*]] = load i32, i32 addrspace(4)* [[ARG_KERNARG_OFFSET_ALIGN_DOWN_CAST]], align 4, !invariant.load !0 ; MESA-NEXT: [[TMP2:%.*]] = trunc i32 [[TMP1]] to i16 ; MESA-NEXT: store i16 [[TMP2]], i16 addrspace(1)* undef, align 1 ; MESA-NEXT: ret void @@ -144,7 +144,7 @@ ; MESA-NEXT: [[KERN_SIGNEXT_I8_KERNARG_SEGMENT:%.*]] = call nonnull align 16 dereferenceable(40) i8 addrspace(4)* @llvm.amdgcn.kernarg.segment.ptr() ; MESA-NEXT: [[ARG_KERNARG_OFFSET_ALIGN_DOWN:%.*]] = getelementptr inbounds i8, i8 addrspace(4)* [[KERN_SIGNEXT_I8_KERNARG_SEGMENT]], i64 36 ; MESA-NEXT: [[ARG_KERNARG_OFFSET_ALIGN_DOWN_CAST:%.*]] = bitcast i8 addrspace(4)* [[ARG_KERNARG_OFFSET_ALIGN_DOWN]] to i32 addrspace(4)* -; MESA-NEXT: [[TMP1:%.*]] = load i32, i32 addrspace(4)* [[ARG_KERNARG_OFFSET_ALIGN_DOWN_CAST]], align 4, !range !3, !invariant.load !0 +; MESA-NEXT: [[TMP1:%.*]] = load i32, i32 addrspace(4)* [[ARG_KERNARG_OFFSET_ALIGN_DOWN_CAST]], align 4, !invariant.load !0 ; MESA-NEXT: [[TMP2:%.*]] = trunc i32 [[TMP1]] to i8 ; MESA-NEXT: store i8 [[TMP2]], i8 addrspace(1)* undef, align 1 ; MESA-NEXT: ret void @@ -167,7 +167,7 @@ ; MESA-NEXT: [[KERN_SIGNEXT_I16_KERNARG_SEGMENT:%.*]] = call nonnull align 16 dereferenceable(40) i8 addrspace(4)* @llvm.amdgcn.kernarg.segment.ptr() ; MESA-NEXT: [[ARG_KERNARG_OFFSET_ALIGN_DOWN:%.*]] = getelementptr inbounds i8, i8 addrspace(4)* [[KERN_SIGNEXT_I16_KERNARG_SEGMENT]], i64 36 ; MESA-NEXT: [[ARG_KERNARG_OFFSET_ALIGN_DOWN_CAST:%.*]] = bitcast i8 addrspace(4)* [[ARG_KERNARG_OFFSET_ALIGN_DOWN]] to i32 addrspace(4)* -; MESA-NEXT: [[TMP1:%.*]] = load i32, i32 addrspace(4)* [[ARG_KERNARG_OFFSET_ALIGN_DOWN_CAST]], align 4, !range !4, !invariant.load !0 +; MESA-NEXT: [[TMP1:%.*]] = load i32, i32 addrspace(4)* [[ARG_KERNARG_OFFSET_ALIGN_DOWN_CAST]], align 4, !invariant.load !0 ; MESA-NEXT: [[TMP2:%.*]] = trunc i32 [[TMP1]] to i16 ; MESA-NEXT: store i16 [[TMP2]], i16 addrspace(1)* undef, align 1 ; MESA-NEXT: ret void @@ -1160,7 +1160,7 @@ ; MESA-NEXT: [[KERN_GLOBAL_PTR_DEREFERENCABLE_KERNARG_SEGMENT:%.*]] = call nonnull align 16 dereferenceable(44) i8 addrspace(4)* @llvm.amdgcn.kernarg.segment.ptr() ; MESA-NEXT: [[PTR_KERNARG_OFFSET:%.*]] = getelementptr inbounds i8, i8 addrspace(4)* [[KERN_GLOBAL_PTR_DEREFERENCABLE_KERNARG_SEGMENT]], i64 36 ; MESA-NEXT: [[PTR_KERNARG_OFFSET_CAST:%.*]] = bitcast i8 addrspace(4)* [[PTR_KERNARG_OFFSET]] to i8 addrspace(1)* addrspace(4)* -; MESA-NEXT: [[PTR_LOAD:%.*]] = load i8 addrspace(1)*, i8 addrspace(1)* addrspace(4)* [[PTR_KERNARG_OFFSET_CAST]], align 4, !invariant.load !0, !dereferenceable !5 +; MESA-NEXT: [[PTR_LOAD:%.*]] = load i8 addrspace(1)*, i8 addrspace(1)* addrspace(4)* [[PTR_KERNARG_OFFSET_CAST]], align 4, !invariant.load !0, !dereferenceable !1 ; MESA-NEXT: store volatile i8 addrspace(1)* [[PTR_LOAD]], i8 addrspace(1)* addrspace(1)* undef ; MESA-NEXT: ret void ; @@ -1181,7 +1181,7 @@ ; MESA-NEXT: [[KERN_GLOBAL_PTR_DEREFERENCABLE_OR_NULL_KERNARG_SEGMENT:%.*]] = call nonnull align 16 dereferenceable(44) i8 addrspace(4)* @llvm.amdgcn.kernarg.segment.ptr() ; MESA-NEXT: [[PTR_KERNARG_OFFSET:%.*]] = getelementptr inbounds i8, i8 addrspace(4)* [[KERN_GLOBAL_PTR_DEREFERENCABLE_OR_NULL_KERNARG_SEGMENT]], i64 36 ; MESA-NEXT: [[PTR_KERNARG_OFFSET_CAST:%.*]] = bitcast i8 addrspace(4)* [[PTR_KERNARG_OFFSET]] to i8 addrspace(1)* addrspace(4)* -; MESA-NEXT: [[PTR_LOAD:%.*]] = load i8 addrspace(1)*, i8 addrspace(1)* addrspace(4)* [[PTR_KERNARG_OFFSET_CAST]], align 4, !invariant.load !0, !dereferenceable_or_null !6 +; MESA-NEXT: [[PTR_LOAD:%.*]] = load i8 addrspace(1)*, i8 addrspace(1)* addrspace(4)* [[PTR_KERNARG_OFFSET_CAST]], align 4, !invariant.load !0, !dereferenceable_or_null !2 ; MESA-NEXT: store volatile i8 addrspace(1)* [[PTR_LOAD]], i8 addrspace(1)* addrspace(1)* undef ; MESA-NEXT: ret void ; @@ -1223,7 +1223,7 @@ ; MESA-NEXT: [[KERN_ALIGN32_GLOBAL_PTR_KERNARG_SEGMENT:%.*]] = call nonnull align 16 dereferenceable(44) i8 addrspace(4)* @llvm.amdgcn.kernarg.segment.ptr() ; MESA-NEXT: [[PTR_KERNARG_OFFSET:%.*]] = getelementptr inbounds i8, i8 addrspace(4)* [[KERN_ALIGN32_GLOBAL_PTR_KERNARG_SEGMENT]], i64 36 ; MESA-NEXT: [[PTR_KERNARG_OFFSET_CAST:%.*]] = bitcast i8 addrspace(4)* [[PTR_KERNARG_OFFSET]] to i8 addrspace(1)* addrspace(4)* -; MESA-NEXT: [[PTR_LOAD:%.*]] = load i8 addrspace(1)*, i8 addrspace(1)* addrspace(4)* [[PTR_KERNARG_OFFSET_CAST]], align 4, !invariant.load !0, !align !7 +; MESA-NEXT: [[PTR_LOAD:%.*]] = load i8 addrspace(1)*, i8 addrspace(1)* addrspace(4)* [[PTR_KERNARG_OFFSET_CAST]], align 4, !invariant.load !0, !align !3 ; MESA-NEXT: store volatile i8 addrspace(1)* [[PTR_LOAD]], i8 addrspace(1)* addrspace(1)* undef ; MESA-NEXT: ret void ; @@ -1432,17 +1432,7 @@ attributes #1 = { nounwind "target-cpu"="kaveri" "amdgpu-implicitarg-num-bytes"="40" } attributes #2 = { nounwind "target-cpu"="tahiti" } -; HSA: 0 = !{} -; HSA: !1 = !{i64 42} -; HSA: !2 = !{i64 128} -; HSA: !3 = !{i64 1024} - - -; MESA: !0 = !{} -; MESA: !1 = !{i32 0, i32 256} -; MESA: !2 = !{i32 0, i32 65536} -; MESA: !3 = !{i32 -128, i32 128} -; MESA: !4 = !{i32 -32768, i32 32768} -; MESA: !5 = !{i64 42} -; MESA: !6 = !{i64 128} -; MESA: !7 = !{i64 1024} +; GCN: 0 = !{} +; GCN: !1 = !{i64 42} +; GCN: !2 = !{i64 128} +; GCN: !3 = !{i64 1024} Index: test/CodeGen/AMDGPU/store-global.ll =================================================================== --- test/CodeGen/AMDGPU/store-global.ll +++ test/CodeGen/AMDGPU/store-global.ll @@ -24,23 +24,12 @@ ; EG: MEM_RAT MSKOR T[[RW_GPR:[0-9]]].XW, T{{[0-9]}}.X ; EG-NOT: MEM_RAT MSKOR -; IG 0: Get the byte index and truncate the value -; EG: AND_INT * T{{[0-9]}}.[[BI_CHAN:[XYZW]]], KC0[2].Y, literal.x -; EG: LSHL T{{[0-9]}}.[[SHIFT_CHAN:[XYZW]]], PV.[[BI_CHAN]], literal.x -; EG: AND_INT * T{{[0-9]}}.[[TRUNC_CHAN:[XYZW]]], KC0[2].Z, literal.y -; EG-NEXT: 3(4.203895e-45), 255(3.573311e-43) - - -; IG 1: Truncate the calculated the shift amount for the mask - -; IG 2: Shift the value and the mask -; EG: LSHL T[[RW_GPR]].X, PS, PV.[[SHIFT_CHAN]] -; EG: LSHL * T[[RW_GPR]].W, literal.x, PV.[[SHIFT_CHAN]] -; EG-NEXT: 255 -; IG 3: Initialize the Y and Z channels to zero -; XXX: An optimal scheduler should merge this into one of the prevous IGs. -; EG: MOV T[[RW_GPR]].Y, 0.0 -; EG: MOV * T[[RW_GPR]].Z, 0.0 +; EG: VTX_READ_8 +; EG: AND_INT +; EG: AND_INT +; EG: LSHL +; EG: LSHL +; EG: LSHL ; SIVI: buffer_store_byte ; GFX9: global_store_byte @@ -55,26 +44,13 @@ ; EG: MEM_RAT MSKOR T[[RW_GPR:[0-9]]].XW, T{{[0-9]}}.X ; EG-NOT: MEM_RAT MSKOR -; IG 0: Get the byte index and truncate the value - - -; EG: AND_INT * T{{[0-9]}}.[[BI_CHAN:[XYZW]]], KC0[2].Y, literal.x -; EG-NEXT: 3(4.203895e-45), - -; EG: LSHL T{{[0-9]}}.[[SHIFT_CHAN:[XYZW]]], PV.[[BI_CHAN]], literal.x -; EG: AND_INT * T{{[0-9]}}.[[TRUNC_CHAN:[XYZW]]], KC0[2].Z, literal.y - -; EG-NEXT: 3(4.203895e-45), 65535(9.183409e-41) -; IG 1: Truncate the calculated the shift amount for the mask +; EG: VTX_READ_16 +; EG: AND_INT +; EG: AND_INT +; EG: LSHL +; EG: LSHL +; EG: LSHL -; IG 2: Shift the value and the mask -; EG: LSHL T[[RW_GPR]].X, PS, PV.[[SHIFT_CHAN]] -; EG: LSHL * T[[RW_GPR]].W, literal.x, PV.[[SHIFT_CHAN]] -; EG-NEXT: 65535 -; IG 3: Initialize the Y and Z channels to zero -; XXX: An optimal scheduler should merge this into one of the prevous IGs. -; EG: MOV T[[RW_GPR]].Y, 0.0 -; EG: MOV * T[[RW_GPR]].Z, 0.0 ; SIVI: buffer_store_short ; GFX9: global_store_short Index: test/CodeGen/AMDGPU/store-private.ll =================================================================== --- test/CodeGen/AMDGPU/store-private.ll +++ test/CodeGen/AMDGPU/store-private.ll @@ -32,7 +32,9 @@ ; EG: AND_INT * T{{[0-9]}}.[[BI_CHAN:[XYZW]]], KC0[2].Y, literal.x ; EG: LSHL * T{{[0-9]}}.[[SHIFT_CHAN:[XYZW]]], PV.[[BI_CHAN]], literal.x ; EG-NEXT: 3(4.203895e-45) -; EG: AND_INT * T{{[0-9]}}.[[TRUNC_CHAN:[XYZW]]], KC0[2].Z, literal.x + + +; EG: LSHL * T{{[0-9]}}.[[TRUNC_CHAN:[XYZW]]], literal.x, PV.W ; EG-NEXT: 255(3.573311e-43) ; EG: NOT_INT @@ -57,12 +59,12 @@ ; EG: MOVA_INT * AR.x (MASKED) ; EG: MOV [[OLD:T[0-9]\.[XYZW]]], {{.*}}AR.x +; EG: VTX_READ_16 + ; IG 0: Get the byte index and truncate the value ; EG: AND_INT * T{{[0-9]}}.[[BI_CHAN:[XYZW]]], KC0[2].Y, literal.x ; EG: LSHL * T{{[0-9]}}.[[SHIFT_CHAN:[XYZW]]], PV.[[BI_CHAN]], literal.x ; EG-NEXT: 3(4.203895e-45) -; EG: AND_INT * T{{[0-9]}}.[[TRUNC_CHAN:[XYZW]]], KC0[2].Z, literal.x -; EG-NEXT: 65535(9.183409e-41) ; EG: NOT_INT ; EG: AND_INT {{[\* ]*}}[[CLR_CHAN:T[0-9]\.[XYZW]]], {{.*}}[[OLD]] Index: test/CodeGen/AMDGPU/zero_extend.ll =================================================================== --- test/CodeGen/AMDGPU/zero_extend.ll +++ test/CodeGen/AMDGPU/zero_extend.ll @@ -51,11 +51,11 @@ ; GCN: s_load_dword [[A:s[0-9]+]] ; GCN: s_load_dword [[B:s[0-9]+]] -; SI: v_mov_b32_e32 [[V_A:v[0-9]+]], [[A]] -; SI: v_cmp_eq_u32_e32 vcc, [[B]], [[V_A]] - -; VI: v_mov_b32_e32 [[V_B:v[0-9]+]], [[B]] -; VI: v_cmp_eq_u32_e32 vcc, [[A]], [[V_B]] +; GCN: s_mov_b32 [[MASK:s[0-9]+]], 0xffff{{$}} +; GCN-DAG: s_and_b32 [[MASK_A:s[0-9]+]], [[A]], [[MASK]] +; GCN-DAG: s_and_b32 [[MASK_B:s[0-9]+]], [[B]], [[MASK]] +; GCN: v_mov_b32_e32 [[V_B:v[0-9]+]], [[B]] +; GCN: v_cmp_eq_u32_e32 vcc, [[MASK_A]], [[V_B]] ; GCN: v_cndmask_b32_e64 [[RESULT:v[0-9]+]], 0, 1, vcc ; GCN: buffer_store_short [[RESULT]]