Index: lib/Target/AArch64/AArch64InstrFormats.td =================================================================== --- lib/Target/AArch64/AArch64InstrFormats.td +++ lib/Target/AArch64/AArch64InstrFormats.td @@ -4773,6 +4773,14 @@ let Inst{4-0} = Rd; } +let Predicates = [HasV8_2a, HasNEON, HasFullFP16] in +class BaseSIMDThreeSameMult size, string asm, string kind1, + string kind2> : + BaseSIMDThreeSameVector { + let AsmString = !strconcat(asm, "{\t$Rd" # kind1 # ", $Rn" # kind2 # ", $Rm" # kind2 # "}"); + let Inst{13} = b13; +} + class BaseSIMDThreeSameVectorDot opc, string asm, + string dst_kind, string lhs_kind, + string rhs_kind> : + BaseSIMDIndexedTied { + //idx = H:L:M + bits<3> idx; + let Inst{11} = idx{2}; // H + let Inst{21} = idx{1}; // L + let Inst{20} = idx{0}; // M +} + multiclass SIMDThreeSameVectorDotIndex { def v8i8 : BaseSIMDThreeSameVectorDotIndex<0, U, asm, ".2s", ".8b", ".4b", V64, Index: lib/Target/AArch64/AArch64InstrInfo.td =================================================================== --- lib/Target/AArch64/AArch64InstrInfo.td +++ lib/Target/AArch64/AArch64InstrInfo.td @@ -3296,6 +3296,24 @@ defm SQRDMLSH : SIMDThreeSameVectorSQRDMLxHTiedHS<1,0b10001,"sqrdmlsh", int_aarch64_neon_sqsub>; +// Armv8.2-A Floating Point Multiplication Variants +def FMLAL_2S : BaseSIMDThreeSameMult<0, 0, 1, 0b001, "fmlal", ".2s", ".2h">; +def FMLSL_2S : BaseSIMDThreeSameMult<0, 0, 1, 0b101, "fmlsl", ".2s", ".2h">; +def FMLAL_4S : BaseSIMDThreeSameMult<1, 0, 1, 0b001, "fmlal", ".4s", ".4h">; +def FMLSL_4S : BaseSIMDThreeSameMult<1, 0, 1, 0b101, "fmlsl", ".4s", ".4h">; +def FMLAL2_2S : BaseSIMDThreeSameMult<0, 1, 0, 0b001, "fmlal2", ".2s", ".2h">; +def FMLSL2_2S : BaseSIMDThreeSameMult<0, 1, 0, 0b101, "fmlsl2", ".2s", ".2h">; +def FMLAL2_4S : BaseSIMDThreeSameMult<1, 1, 0, 0b001, "fmlal2", ".4s", ".4h">; +def FMLSL2_4S : BaseSIMDThreeSameMult<1, 1, 0, 0b101, "fmlsl2", ".4s", ".4h">; +def FMLALI_2s : BaseSIMDThreeSameMultIndex<0, 0, 0b0000, "fmlal", ".2s", ".2h", ".h">; +def FMLSLI_2s : BaseSIMDThreeSameMultIndex<0, 0, 0b0100, "fmlsl", ".2s", ".2h", ".h">; +def FMLALI_4s : BaseSIMDThreeSameMultIndex<1, 0, 0b0000, "fmlal", ".4s", ".4h", ".h">; +def FMLSLI_4s : BaseSIMDThreeSameMultIndex<1, 0, 0b0100, "fmlsl", ".4s", ".4h", ".h">; +def FMLALI2_2s : BaseSIMDThreeSameMultIndex<0, 1, 0b1000, "fmlal2", ".2s", ".2h", ".h">; +def FMLSLI2_2s : BaseSIMDThreeSameMultIndex<0, 1, 0b1100, "fmlsl2", ".2s", ".2h", ".h">; +def FMLALI2_4s : BaseSIMDThreeSameMultIndex<1, 1, 0b1000, "fmlal2", ".4s", ".4h", ".h">; +def FMLSLI2_4s : BaseSIMDThreeSameMultIndex<1, 1, 0b1100, "fmlsl2", ".4s", ".4h", ".h">; + defm AND : SIMDLogicalThreeVector<0, 0b00, "and", and>; defm BIC : SIMDLogicalThreeVector<0, 0b01, "bic", BinOpFrag<(and node:$LHS, (vnot node:$RHS))> >; Index: lib/Target/ARM/ARMInstrFormats.td =================================================================== --- lib/Target/ARM/ARMInstrFormats.td +++ lib/Target/ARM/ARMInstrFormats.td @@ -2579,6 +2579,37 @@ let Inst{3-0} = Vm{3-0}; } +// In Armv8.2-A, some NEON instructions are added that encode Vn and Vm +// differently: +// if Q == ‘1’ then UInt(N:Vn) else UInt(Vn:N); +// if Q == ‘1’ then UInt(M:Vm) else UInt(Vm:M); +// Class N3VCP8 above describes the Q=1 case, and this class the Q=0 case. +class N3VCP8Q0 op24_23, bits<2> op21_20, bit op6, bit op4, + dag oops, dag iops, InstrItinClass itin, + string opc, string dt, string asm, string cstr, list pattern> + : NeonInp { + bits<5> Vd; + bits<5> Vn; + bits<5> Vm; + + let DecoderNamespace = "VFPV8"; + // These have the same encodings in ARM and Thumb2 + let PostEncoderMethod = ""; + + let Inst{31-25} = 0b1111110; + let Inst{24-23} = op24_23; + let Inst{22} = Vd{4}; + let Inst{21-20} = op21_20; + let Inst{19-16} = Vn{4-1}; + let Inst{15-12} = Vd{3-0}; + let Inst{11-8} = 0b1000; + let Inst{7} = Vn{0}; + let Inst{6} = op6; + let Inst{5} = Vm{0}; + let Inst{4} = op4; + let Inst{3-0} = Vm{4-1}; +} + // Operand types for complex instructions class ComplexRotationOperand : AsmOperandClass { Index: lib/Target/ARM/ARMInstrNEON.td =================================================================== --- lib/Target/ARM/ARMInstrNEON.td +++ lib/Target/ARM/ARMInstrNEON.td @@ -5091,6 +5091,54 @@ (VACGEhq QPR:$Vd, QPR:$Vm, QPR:$Vn, pred:$p)>; } +// Armv8.2-A Floating Point Multiplication Variants +let Predicates = [HasNEON, HasV8_2a, HasFullFP16], DecoderNamespace= "VFPV8" in { + +class N3VCP8F16Q1 op1, bits<2> op2, bit op3> + : N3VCP8; + +class N3VCP8F16Q0 op1, bits<2> op2, bit op3> + : N3VCP8Q0; + +class VFMQ0 S> + : N3VLaneCP8<0, S, 0, 1, (outs DPR:$Vd), + (ins SPR:$Vn, SPR:$Vm, VectorIndex32:$idx), + IIC_VMACD, opc, "f16", "$Vd, $Vn, $Vm$idx", "", []> { + bit idx; + let Inst{3} = idx; + let Inst{19-16} = Vn{4-1}; + let Inst{7} = Vn{0}; + let Inst{5} = Vm{0}; + let Inst{2-0} = Vm{3-1}; +} + +class VFMQ1 S> + : N3VLaneCP8<0, S, 1, 1, (outs QPR:$Vd), + (ins DPR:$Vn, DPR:$Vm, VectorIndex16:$idx), + IIC_VMACD, opc, "f16", "$Vd, $Vn, $Vm$idx", "", []> { + bits<2> idx; + let Inst{5} = idx{1}; + let Inst{3} = idx{0}; +} + +let hasNoSchedulingInfo = 1 in { +// op1 op2 op3 +def VFMALD : N3VCP8F16Q0<"vfmal", DPR, SPR, SPR, 0b00, 0b10, 1>; +def VFMSLD : N3VCP8F16Q0<"vfmsl", DPR, SPR, SPR, 0b01, 0b10, 1>; +def VFMALQ : N3VCP8F16Q1<"vfmal", QPR, DPR, DPR, 0b00, 0b10, 1>; +def VFMSLQ : N3VCP8F16Q1<"vfmsl", QPR, DPR, DPR, 0b01, 0b10, 1>; +def VFMALDI : VFMQ0<"vfmal", 0b00>; +def VFMSLDI : VFMQ0<"vfmsl", 0b01>; +def VFMALQI : VFMQ1<"vfmal", 0b00>; +def VFMSLQI : VFMQ1<"vfmsl", 0b01>; +} +} // HasNEON, HasV8_2a, HasFullFP16 + + def: NEONInstAlias<"vaclt${p}.f32 $Vd, $Vm", (VACGTfd DPR:$Vd, DPR:$Vm, DPR:$Vd, pred:$p)>; def: NEONInstAlias<"vaclt${p}.f32 $Vd, $Vm", Index: lib/Target/ARM/AsmParser/ARMAsmParser.cpp =================================================================== --- lib/Target/ARM/AsmParser/ARMAsmParser.cpp +++ lib/Target/ARM/AsmParser/ARMAsmParser.cpp @@ -5626,7 +5626,8 @@ Mnemonic.startswith("vsel") || Mnemonic == "vins" || Mnemonic == "vmovx" || Mnemonic == "bxns" || Mnemonic == "blxns" || Mnemonic == "vudot" || Mnemonic == "vsdot" || - Mnemonic == "vcmla" || Mnemonic == "vcadd") + Mnemonic == "vcmla" || Mnemonic == "vcadd" || + Mnemonic == "vfmal" || Mnemonic == "vfmsl") return Mnemonic; // First, split out any predication code. Ignore mnemonics we know aren't @@ -5716,7 +5717,8 @@ (FullInst.startswith("vmull") && FullInst.endswith(".p64")) || Mnemonic == "vmovx" || Mnemonic == "vins" || Mnemonic == "vudot" || Mnemonic == "vsdot" || - Mnemonic == "vcmla" || Mnemonic == "vcadd") { + Mnemonic == "vcmla" || Mnemonic == "vcadd" || + Mnemonic == "vfmal" || Mnemonic == "vfmsl") { // These mnemonics are never predicable CanAcceptPredicationCode = false; } else if (!isThumb()) { Index: test/MC/AArch64/armv8.2a-fpmul-error.s =================================================================== --- /dev/null +++ test/MC/AArch64/armv8.2a-fpmul-error.s @@ -0,0 +1,51 @@ +// RUN: not llvm-mc -triple aarch64-none-linux-gnu -show-encoding -mattr=+v8.2a,+fullfp16 < %s 2>&1 | FileCheck %s --check-prefix=CHECK + +//------------------------------------------------------------------------------ +// Armv8.2-A Floating Point Multiplication Variants +//------------------------------------------------------------------------------ + +fmlal V0.2s, v1.2h, v2.h[8] +fmlsl V0.2s, v1.2h, v2.h[8] +fmlal V0.4s, v1.4h, v2.h[8] +fmlsl V0.4s, v1.4h, v2.h[8] + +fmlal2 V0.2s, v1.2h, v2.h[8] +fmlsl2 V0.2s, v1.2h, v2.h[8] +fmlal2 V0.4s, v1.4h, v2.h[8] +fmlsl2 V0.4s, v1.4h, v2.h[8] + +fmlal V0.2s, v1.2h, v2.h[-1] +fmlsl2 V0.2s, v1.2h, v2.h[-1] + +//CHECK: error: vector lane must be an integer in range [0, 7]. +//CHECK-NEXT: fmlal V0.2s, v1.2h, v2.h[8] +//CHECK-NEXT: ^ +//CHECK-NEXT: error: vector lane must be an integer in range [0, 7]. +//CHECK-NEXT: fmlsl V0.2s, v1.2h, v2.h[8] +//CHECK-NEXT: ^ +//CHECK-NEXT: error: vector lane must be an integer in range [0, 7]. +//CHECK-NEXT: fmlal V0.4s, v1.4h, v2.h[8] +//CHECK-NEXT: ^ +//CHECK-NEXT: error: vector lane must be an integer in range [0, 7]. +//CHECK-NEXT: fmlsl V0.4s, v1.4h, v2.h[8] +//CHECK-NEXT: ^ + +//CHECK-NEXT: error: vector lane must be an integer in range [0, 7]. +//CHECK-NEXT: fmlal2 V0.2s, v1.2h, v2.h[8] +//CHECK-NEXT: ^ +//CHECK-NEXT: error: vector lane must be an integer in range [0, 7]. +//CHECK-NEXT: fmlsl2 V0.2s, v1.2h, v2.h[8] +//CHECK-NEXT: ^ +//CHECK-NEXT: error: vector lane must be an integer in range [0, 7]. +//CHECK-NEXT: fmlal2 V0.4s, v1.4h, v2.h[8] +//CHECK-NEXT: ^ +//CHECK-NEXT: error: vector lane must be an integer in range [0, 7]. +//CHECK-NEXT: fmlsl2 V0.4s, v1.4h, v2.h[8] +//CHECK-NEXT: ^ + +//CHECK-NEXT: error: vector lane must be an integer in range [0, 7]. +//CHECK-NEXT: fmlal V0.2s, v1.2h, v2.h[-1] +//CHECK-NEXT: ^ +//CHECK-NEXT: error: vector lane must be an integer in range [0, 7]. +//CHECK-NEXT: fmlsl2 V0.2s, v1.2h, v2.h[-1] +//CHECK-NEXT: ^ Index: test/MC/AArch64/armv8.2a-fpmul.s =================================================================== --- /dev/null +++ test/MC/AArch64/armv8.2a-fpmul.s @@ -0,0 +1,116 @@ +// RUN: llvm-mc -triple aarch64-none-linux-gnu -show-encoding -mattr=+v8.2a,+fullfp16 < %s | FileCheck %s --check-prefix=CHECK +// RUN: not llvm-mc -triple aarch64-none-linux-gnu -show-encoding -mattr=+v8.2a,-fullfp16 < %s 2>&1 | FileCheck %s --check-prefix=CHECK-ERROR +// RUN: not llvm-mc -triple aarch64-none-linux-gnu -show-encoding -mattr=-v8.2a,+fullfp16 < %s 2>&1 | FileCheck %s --check-prefix=CHECK-ERROR-NOV82 + +//------------------------------------------------------------------------------ +// Armv8.2-A Floating Point Multiplication +//------------------------------------------------------------------------------ + +FMLAL V0.2S, V1.2H, V2.2H +FMLSL V0.2S, V1.2H, V2.2H +FMLAL V0.4S, V1.4H, V2.4H +FMLSL V0.4S, V1.4H, V2.4H +FMLAL2 V0.2S, V1.2H, V2.2H +FMLSL2 V0.2S, V1.2H, V2.2H +FMLAL2 V0.4S, V1.4H, V2.4H +FMLSL2 V0.4S, V1.4H, V2.4H + +//CHECK: fmlal v0.2s, v1.2h, v2.2h // encoding: [0x20,0xec,0x22,0x0e] +//CHECK: fmlsl v0.2s, v1.2h, v2.2h // encoding: [0x20,0xec,0xa2,0x0e] +//CHECK: fmlal v0.4s, v1.4h, v2.4h // encoding: [0x20,0xec,0x22,0x4e] +//CHECK: fmlsl v0.4s, v1.4h, v2.4h // encoding: [0x20,0xec,0xa2,0x4e] +//CHECK: fmlal2 v0.2s, v1.2h, v2.2h // encoding: [0x20,0xcc,0x22,0x2e] +//CHECK: fmlsl2 v0.2s, v1.2h, v2.2h // encoding: [0x20,0xcc,0xa2,0x2e] +//CHECK: fmlal2 v0.4s, v1.4h, v2.4h // encoding: [0x20,0xcc,0x22,0x6e] +//CHECK: fmlsl2 v0.4s, v1.4h, v2.4h // encoding: [0x20,0xcc,0xa2,0x6e] + +//CHECK-ERROR: error: instruction requires: fullfp16 +//CHECK-ERROR: error: instruction requires: fullfp16 +//CHECK-ERROR: error: instruction requires: fullfp16 +//CHECK-ERROR: error: instruction requires: fullfp16 +//CHECK-ERROR: error: instruction requires: fullfp16 +//CHECK-ERROR: error: instruction requires: fullfp16 +//CHECK-ERROR: error: instruction requires: fullfp16 +//CHECK-ERROR: error: instruction requires: fullfp16 + +//CHECK-ERROR-NOV82: error: instruction requires: armv8.2a +//CHECK-ERROR-NOV82: error: instruction requires: armv8.2a +//CHECK-ERROR-NOV82: error: instruction requires: armv8.2a +//CHECK-ERROR-NOV82: error: instruction requires: armv8.2a +//CHECK-ERROR-NOV82: error: instruction requires: armv8.2a +//CHECK-ERROR-NOV82: error: instruction requires: armv8.2a +//CHECK-ERROR-NOV82: error: instruction requires: armv8.2a +//CHECK-ERROR-NOV82: error: instruction requires: armv8.2a + +# Checks with the maximum index value 7: +fmlal V0.2s, v1.2h, v2.h[7] +fmlsl V0.2s, v1.2h, v2.h[7] +fmlal V0.4s, v1.4h, v2.h[7] +fmlsl V0.4s, v1.4h, v2.h[7] +fmlal2 V0.2s, v1.2h, v2.h[7] +fmlsl2 V0.2s, v1.2h, v2.h[7] +fmlal2 V0.4s, v1.4h, v2.h[7] +fmlsl2 V0.4s, v1.4h, v2.h[7] + +# Some more checks with a different index bit pattern to catch +# incorrect permutations of the index (decimal 7 is 0b111): +fmlal V0.2s, v1.2h, v2.h[5] +fmlsl V0.2s, v1.2h, v2.h[5] +fmlal V0.4s, v1.4h, v2.h[5] +fmlsl V0.4s, v1.4h, v2.h[5] +fmlal2 V0.2s, v1.2h, v2.h[5] +fmlsl2 V0.2s, v1.2h, v2.h[5] +fmlal2 V0.4s, v1.4h, v2.h[5] +fmlsl2 V0.4s, v1.4h, v2.h[5] + +//CHECK: fmlal v0.2s, v1.2h, v2.h[7] // encoding: [0x20,0x08,0xb2,0x0f] +//CHECK: fmlsl v0.2s, v1.2h, v2.h[7] // encoding: [0x20,0x48,0xb2,0x0f] +//CHECK: fmlal v0.4s, v1.4h, v2.h[7] // encoding: [0x20,0x08,0xb2,0x4f] +//CHECK: fmlsl v0.4s, v1.4h, v2.h[7] // encoding: [0x20,0x48,0xb2,0x4f] +//CHECK: fmlal2 v0.2s, v1.2h, v2.h[7] // encoding: [0x20,0x88,0xb2,0x2f] +//CHECK: fmlsl2 v0.2s, v1.2h, v2.h[7] // encoding: [0x20,0xc8,0xb2,0x2f] +//CHECK: fmlal2 v0.4s, v1.4h, v2.h[7] // encoding: [0x20,0x88,0xb2,0x6f] +//CHECK: fmlsl2 v0.4s, v1.4h, v2.h[7] // encoding: [0x20,0xc8,0xb2,0x6f] + +//CHECK: fmlal v0.2s, v1.2h, v2.h[5] // encoding: [0x20,0x08,0x92,0x0f] +//CHECK: fmlsl v0.2s, v1.2h, v2.h[5] // encoding: [0x20,0x48,0x92,0x0f] +//CHECK: fmlal v0.4s, v1.4h, v2.h[5] // encoding: [0x20,0x08,0x92,0x4f] +//CHECK: fmlsl v0.4s, v1.4h, v2.h[5] // encoding: [0x20,0x48,0x92,0x4f] +//CHECK: fmlal2 v0.2s, v1.2h, v2.h[5] // encoding: [0x20,0x88,0x92,0x2f] +//CHECK: fmlsl2 v0.2s, v1.2h, v2.h[5] // encoding: [0x20,0xc8,0x92,0x2f] +//CHECK: fmlal2 v0.4s, v1.4h, v2.h[5] // encoding: [0x20,0x88,0x92,0x6f] +//CHECK: fmlsl2 v0.4s, v1.4h, v2.h[5] // encoding: [0x20,0xc8,0x92,0x6f] + +//CHECK-ERROR: error: instruction requires: fullfp16 +//CHECK-ERROR: error: instruction requires: fullfp16 +//CHECK-ERROR: error: instruction requires: fullfp16 +//CHECK-ERROR: error: instruction requires: fullfp16 +//CHECK-ERROR: error: instruction requires: fullfp16 +//CHECK-ERROR: error: instruction requires: fullfp16 +//CHECK-ERROR: error: instruction requires: fullfp16 +//CHECK-ERROR: error: instruction requires: fullfp16 +//CHECK-ERROR: error: instruction requires: fullfp16 +//CHECK-ERROR: error: instruction requires: fullfp16 +//CHECK-ERROR: error: instruction requires: fullfp16 +//CHECK-ERROR: error: instruction requires: fullfp16 +//CHECK-ERROR: error: instruction requires: fullfp16 +//CHECK-ERROR: error: instruction requires: fullfp16 +//CHECK-ERROR: error: instruction requires: fullfp16 +//CHECK-ERROR: error: instruction requires: fullfp16 + +//CHECK-ERROR-NOV82: error: instruction requires: armv8.2a +//CHECK-ERROR-NOV82: error: instruction requires: armv8.2a +//CHECK-ERROR-NOV82: error: instruction requires: armv8.2a +//CHECK-ERROR-NOV82: error: instruction requires: armv8.2a +//CHECK-ERROR-NOV82: error: instruction requires: armv8.2a +//CHECK-ERROR-NOV82: error: instruction requires: armv8.2a +//CHECK-ERROR-NOV82: error: instruction requires: armv8.2a +//CHECK-ERROR-NOV82: error: instruction requires: armv8.2a +//CHECK-ERROR-NOV82: error: instruction requires: armv8.2a +//CHECK-ERROR-NOV82: error: instruction requires: armv8.2a +//CHECK-ERROR-NOV82: error: instruction requires: armv8.2a +//CHECK-ERROR-NOV82: error: instruction requires: armv8.2a +//CHECK-ERROR-NOV82: error: instruction requires: armv8.2a +//CHECK-ERROR-NOV82: error: instruction requires: armv8.2a +//CHECK-ERROR-NOV82: error: instruction requires: armv8.2a +//CHECK-ERROR-NOV82: error: instruction requires: armv8.2a Index: test/MC/ARM/armv8.2a-fpmul-error.s =================================================================== --- /dev/null +++ test/MC/ARM/armv8.2a-fpmul-error.s @@ -0,0 +1,27 @@ +// RUN: not llvm-mc -triple arm -mattr=+v8.2a,+fullfp16,+neon -show-encoding < %s 2>&1 | FileCheck %s --check-prefix=CHECK-ERROR + +VFMAL.F16 D0, S1, S2[2] +vfmsl.f16 d0, s1, s2[2] +vfmsl.f16 d0, s1, s2[-1] +vfmal.f16 q0, d1, d2[4] +VFMSL.F16 Q0, D1, D2[4] +vfmal.f16 q0, d1, d2[-1] + +//CHECK-ERROR: error: invalid operand for instruction +//CHECK-ERROR-NEXT: VFMAL.F16 D0, S1, S2[2] +//CHECK-ERROR-NEXT: ^ +//CHECK-ERROR-NEXT: error: invalid operand for instruction +//CHECK-ERROR-NEXT: vfmsl.f16 d0, s1, s2[2] +//CHECK-ERROR-NEXT: ^ +//CHECK-ERROR-NEXT: error: invalid operand for instruction +//CHECK-ERROR-NEXT: vfmsl.f16 d0, s1, s2[-1] +//CHECK-ERROR-NEXT: ^ +//CHECK-ERROR-NEXT: error: invalid operand for instruction +//CHECK-ERROR-NEXT: vfmal.f16 q0, d1, d2[4] +//CHECK-ERROR-NEXT: ^ +//CHECK-ERROR-NEXT: error: invalid operand for instruction +//CHECK-ERROR-NEXT: VFMSL.F16 Q0, D1, D2[4] +//CHECK-ERROR-NEXT: ^ +//CHECK-ERROR-NEXT: error: invalid operand for instruction +//CHECK-ERROR-NEXT: vfmal.f16 q0, d1, d2[-1] +//CHECK-ERROR-NEXT: ^ Index: test/MC/ARM/armv8.2a-fpmul.s =================================================================== --- /dev/null +++ test/MC/ARM/armv8.2a-fpmul.s @@ -0,0 +1,68 @@ +// RUN: llvm-mc -triple arm -mattr=+v8.2a,+fullfp16,+neon -show-encoding < %s | FileCheck %s --check-prefix=CHECK +// RUN: llvm-mc -triple thumb -mattr=+v8.2a,+fullfp16,+neon -show-encoding < %s | FileCheck %s --check-prefix=CHECK-T32 + +// RUN: not llvm-mc -triple arm -mattr=-v8.2a,+fullfp16,+neon -show-encoding < %s 2> %t +// RUN: FileCheck --check-prefix=CHECK-NO-84 < %t %s + +// RUN: not llvm-mc -triple arm -mattr=+v8.2a,-fullfp16,+neon -show-encoding < %s 2> %t +// RUN: FileCheck --check-prefix=CHECK-NO-FP16 < %t %s + +// RUN: not llvm-mc -triple arm -mattr=+v8.2a,+fullfp16,-neon -show-encoding < %s 2> %t +// RUN: FileCheck --check-prefix=CHECK-NO-NEON < %t %s + +VFMAL.F16 D0, S1, S2 +vfmsl.f16 d0, s1, s2 +vfmal.f16 q0, d1, d2 +VFMSL.F16 Q0, D1, D2 + +VFMAL.F16 D0, S1, S2[1] +vfmsl.f16 d0, s1, s2[1] +vfmal.f16 q0, d1, d2[3] +VFMSL.F16 Q0, D1, D2[3] + +//CHECK: vfmal.f16 d0, s1, s2 @ encoding: [0x91,0x08,0x20,0xfc] +//CHECK: vfmsl.f16 d0, s1, s2 @ encoding: [0x91,0x08,0xa0,0xfc] +//CHECK: vfmal.f16 q0, d1, d2 @ encoding: [0x52,0x08,0x21,0xfc] +//CHECK: vfmsl.f16 q0, d1, d2 @ encoding: [0x52,0x08,0xa1,0xfc] + +//CHECK: vfmal.f16 d0, s1, s2[1] @ encoding: [0x99,0x08,0x00,0xfe] +//CHECK: vfmsl.f16 d0, s1, s2[1] @ encoding: [0x99,0x08,0x10,0xfe] +//CHECK: vfmal.f16 q0, d1, d2[3] @ encoding: [0x7a,0x08,0x01,0xfe] +//CHECK: vfmsl.f16 q0, d1, d2[3] @ encoding: [0x7a,0x08,0x11,0xfe] + +//CHECK-T32: vfmal.f16 d0, s1, s2 @ encoding: [0x20,0xfc,0x91,0x08] +//CHECK-T32: vfmsl.f16 d0, s1, s2 @ encoding: [0xa0,0xfc,0x91,0x08] +//CHECK-T32: vfmal.f16 q0, d1, d2 @ encoding: [0x21,0xfc,0x52,0x08] +//CHECK-T32: vfmsl.f16 q0, d1, d2 @ encoding: [0xa1,0xfc,0x52,0x08] + +//CHECK-T32: vfmal.f16 d0, s1, s2[1] @ encoding: [0x00,0xfe,0x99,0x08] +//CHECK-T32: vfmsl.f16 d0, s1, s2[1] @ encoding: [0x10,0xfe,0x99,0x08] +//CHECK-T32: vfmal.f16 q0, d1, d2[3] @ encoding: [0x01,0xfe,0x7a,0x08] +//CHECK-T32: vfmsl.f16 q0, d1, d2[3] @ encoding: [0x11,0xfe,0x7a,0x08] + +//CHECK-NO-84: error: instruction requires: armv8.2a +//CHECK-NO-84: error: instruction requires: armv8.2a +//CHECK-NO-84: error: instruction requires: armv8.2a +//CHECK-NO-84: error: instruction requires: armv8.2a +//CHECK-NO-84: error: instruction requires: armv8.2a +//CHECK-NO-84: error: instruction requires: armv8.2a +//CHECK-NO-84: error: instruction requires: armv8.2a +//CHECK-NO-84: error: instruction requires: armv8.2a + +//CHECK-NO-FP16: instruction requires: full half-float +//CHECK-NO-FP16: instruction requires: full half-float +//CHECK-NO-FP16: instruction requires: full half-float +//CHECK-NO-FP16: instruction requires: full half-float +//CHECK-NO-FP16: instruction requires: full half-float +//CHECK-NO-FP16: instruction requires: full half-float +//CHECK-NO-FP16: instruction requires: full half-float +//CHECK-NO-FP16: instruction requires: full half-float + +//CHECK-NO-NEON: instruction requires: NEON +//CHECK-NO-NEON: instruction requires: NEON +//CHECK-NO-NEON: instruction requires: NEON +//CHECK-NO-NEON: instruction requires: NEON +//CHECK-NO-NEON: instruction requires: NEON +//CHECK-NO-NEON: instruction requires: NEON +//CHECK-NO-NEON: instruction requires: NEON +//CHECK-NO-NEON: instruction requires: NEON Index: test/MC/Disassembler/AArch64/armv8.2a-fpmul.txt =================================================================== --- /dev/null +++ test/MC/Disassembler/AArch64/armv8.2a-fpmul.txt @@ -0,0 +1,132 @@ +# RUN: llvm-mc -triple aarch64-none-linux-gnu -mattr=+v8.2a,+fullfp16 --disassemble < %s | FileCheck %s +# RUN: not llvm-mc -triple aarch64-none-linux-gnu -mattr=-v8.2a,+fullfp16 --disassemble < %s 2>&1 | FileCheck %s --check-prefix=CHECK-ERROR +# RUN: not llvm-mc -triple aarch64-none-linux-gnu -mattr=+v8.2a,-fullfp16 --disassemble < %s 2>&1 | FileCheck %s --check-prefix=CHECK-ERROR + +[0x20,0xec,0x22,0x0e] +[0x20,0xec,0xa2,0x0e] +[0x20,0xec,0x22,0x4e] +[0x20,0xec,0xa2,0x4e] +[0x20,0xcc,0x22,0x2e] +[0x20,0xcc,0xa2,0x2e] +[0x20,0xcc,0x22,0x6e] +[0x20,0xcc,0xa2,0x6e] + +#indexed variants: + +[0x20,0x08,0xb2,0x0f] +[0x20,0x48,0xb2,0x0f] +[0x20,0x08,0xb2,0x4f] +[0x20,0x48,0xb2,0x4f] +[0x20,0x88,0xb2,0x2f] +[0x20,0xc8,0xb2,0x2f] +[0x20,0x88,0xb2,0x6f] +[0x20,0xc8,0xb2,0x6f] + +[0x20,0x08,0x92,0x0f] +[0x20,0x48,0x92,0x0f] +[0x20,0x08,0x92,0x4f] +[0x20,0x48,0x92,0x4f] +[0x20,0x88,0x92,0x2f] +[0x20,0xc8,0x92,0x2f] +[0x20,0x88,0x92,0x6f] +[0x20,0xc8,0x92,0x6f] + +#CHECK: fmlal v0.2s, v1.2h, v2.2h +#CHECK: fmlsl v0.2s, v1.2h, v2.2h +#CHECK: fmlal v0.4s, v1.4h, v2.4h +#CHECK: fmlsl v0.4s, v1.4h, v2.4h +#CHECK: fmlal2 v0.2s, v1.2h, v2.2h +#CHECK: fmlsl2 v0.2s, v1.2h, v2.2h +#CHECK: fmlal2 v0.4s, v1.4h, v2.4h +#CHECK: fmlsl2 v0.4s, v1.4h, v2.4h + +#CHECK: fmlal v0.2s, v1.2h, v2.h[7] +#CHECK: fmlsl v0.2s, v1.2h, v2.h[7] +#CHECK: fmlal v0.4s, v1.4h, v2.h[7] +#CHECK: fmlsl v0.4s, v1.4h, v2.h[7] +#CHECK: fmlal2 v0.2s, v1.2h, v2.h[7] +#CHECK: fmlsl2 v0.2s, v1.2h, v2.h[7] +#CHECK: fmlal2 v0.4s, v1.4h, v2.h[7] +#CHECK: fmlsl2 v0.4s, v1.4h, v2.h[7] + +#CHECK: fmlal v0.2s, v1.2h, v2.h[5] +#CHECK: fmlsl v0.2s, v1.2h, v2.h[5] +#CHECK: fmlal v0.4s, v1.4h, v2.h[5] +#CHECK: fmlsl v0.4s, v1.4h, v2.h[5] +#CHECK: fmlal2 v0.2s, v1.2h, v2.h[5] +#CHECK: fmlsl2 v0.2s, v1.2h, v2.h[5] +#CHECK: fmlal2 v0.4s, v1.4h, v2.h[5] +#CHECK: fmlsl2 v0.4s, v1.4h, v2.h[5] + +#CHECK-ERROR: warning: invalid instruction encoding +#CHECK-ERROR: [0x20,0xec,0x22,0x0e] +#CHECK-ERROR: ^ +#CHECK-ERROR: warning: invalid instruction encoding +#CHECK-ERROR: [0x20,0xec,0xa2,0x0e] +#CHECK-ERROR: ^ +#CHECK-ERROR: warning: invalid instruction encoding +#CHECK-ERROR: [0x20,0xec,0x22,0x4e] +#CHECK-ERROR: ^ +#CHECK-ERROR: warning: invalid instruction encoding +#CHECK-ERROR: [0x20,0xec,0xa2,0x4e] +#CHECK-ERROR: ^ +#CHECK-ERROR: warning: invalid instruction encoding +#CHECK-ERROR: [0x20,0xcc,0x22,0x2e] +#CHECK-ERROR: ^ +#CHECK-ERROR: warning: invalid instruction encoding +#CHECK-ERROR: [0x20,0xcc,0xa2,0x2e] +#CHECK-ERROR: ^ +#CHECK-ERROR: warning: invalid instruction encoding +#CHECK-ERROR: [0x20,0xcc,0x22,0x6e] +#CHECK-ERROR: ^ +#CHECK-ERROR: warning: invalid instruction encoding +#CHECK-ERROR: [0x20,0xcc,0xa2,0x6e] +#CHECK-ERROR: ^ +#CHECK-ERROR: warning: invalid instruction encoding +#CHECK-ERROR: [0x20,0x08,0xb2,0x0f] +#CHECK-ERROR: ^ +#CHECK-ERROR: warning: invalid instruction encoding +#CHECK-ERROR: [0x20,0x48,0xb2,0x0f] +#CHECK-ERROR: ^ +#CHECK-ERROR: warning: invalid instruction encoding +#CHECK-ERROR: [0x20,0x08,0xb2,0x4f] +#CHECK-ERROR: ^ +#CHECK-ERROR: warning: invalid instruction encoding +#CHECK-ERROR: [0x20,0x48,0xb2,0x4f] +#CHECK-ERROR: ^ +#CHECK-ERROR: warning: invalid instruction encoding +#CHECK-ERROR: [0x20,0x88,0xb2,0x2f] +#CHECK-ERROR: ^ +#CHECK-ERROR: warning: invalid instruction encoding +#CHECK-ERROR: [0x20,0xc8,0xb2,0x2f] +#CHECK-ERROR: ^ +#CHECK-ERROR: warning: invalid instruction encoding +#CHECK-ERROR: [0x20,0x88,0xb2,0x6f] +#CHECK-ERROR: ^ +#CHECK-ERROR: warning: invalid instruction encoding +#CHECK-ERROR: [0x20,0xc8,0xb2,0x6f] +#CHECK-ERROR: ^ +#CHECK-ERROR: warning: invalid instruction encoding +#CHECK-ERROR: [0x20,0x08,0x92,0x0f] +#CHECK-ERROR: ^ +#CHECK-ERROR: warning: invalid instruction encoding +#CHECK-ERROR: [0x20,0x48,0x92,0x0f] +#CHECK-ERROR: ^ +#CHECK-ERROR: warning: invalid instruction encoding +#CHECK-ERROR: [0x20,0x08,0x92,0x4f] +#CHECK-ERROR: ^ +#CHECK-ERROR: warning: invalid instruction encoding +#CHECK-ERROR: [0x20,0x48,0x92,0x4f] +#CHECK-ERROR: ^ +#CHECK-ERROR: warning: invalid instruction encoding +#CHECK-ERROR: [0x20,0x88,0x92,0x2f] +#CHECK-ERROR: ^ +#CHECK-ERROR: warning: invalid instruction encoding +#CHECK-ERROR: [0x20,0xc8,0x92,0x2f] +#CHECK-ERROR: ^ +#CHECK-ERROR: warning: invalid instruction encoding +#CHECK-ERROR: [0x20,0x88,0x92,0x6f] +#CHECK-ERROR: ^ +#CHECK-ERROR: warning: invalid instruction encoding +#CHECK-ERROR: [0x20,0xc8,0x92,0x6f] +#CHECK-ERROR: ^ Index: test/MC/Disassembler/ARM/armv8.2a-fpmul-a32.txt =================================================================== --- /dev/null +++ test/MC/Disassembler/ARM/armv8.2a-fpmul-a32.txt @@ -0,0 +1,56 @@ +# RUN: llvm-mc -triple arm-none-linux-gnu -mattr=+v8.2a,+fullfp16,+neon --disassemble < %s | FileCheck %s +# RUN: llvm-mc -triple arm-none-linux-gnu -mattr=-v8.2a,+fullfp16,+neon --disassemble < %s 2>&1 | FileCheck %s --check-prefix=CHECK-NO-82 +# RUN: not llvm-mc -triple arm-none-linux-gnu -mattr=+v8.2a,-fullfp16,+neon --disassemble < %s 2>&1 | FileCheck %s --check-prefix=CHECK-INVALID +# RUN: not llvm-mc -triple arm-none-linux-gnu -mattr=+v8.2a,+fullfp16,-neon --disassemble < %s 2>&1 | FileCheck %s --check-prefix=CHECK-INVALID + +[0x91,0x08,0x20,0xfc] +[0x91,0x08,0xa0,0xfc] +[0x52,0x08,0x21,0xfc] +[0x52,0x08,0xa1,0xfc] +[0x99,0x08,0x00,0xfe] +[0x99,0x08,0x10,0xfe] +[0x7a,0x08,0x01,0xfe] +[0x7a,0x08,0x11,0xfe] + +#CHECK: vfmal.f16 d0, s1, s2 +#CHECK: vfmsl.f16 d0, s1, s2 +#CHECK: vfmal.f16 q0, d1, d2 +#CHECK: vfmsl.f16 q0, d1, d2 +#CHECK: vfmal.f16 d0, s1, s2[1] +#CHECK: vfmsl.f16 d0, s1, s2[1] +#CHECK: vfmal.f16 q0, d1, d2[3] +#CHECK: vfmsl.f16 q0, d1, d2[3] + +#CHECK-NO-82: stc2 p8, c0, [r0], #-580 +#CHECK-NO-82: stc2 p8, c0, [r0], #580 +#CHECK-NO-82: stc2 p8, c0, [r1], #-328 +#CHECK-NO-82: stc2 p8, c0, [r1], #328 +#CHECK-NO-82: mcr2 p8, #0, r0, c0, c9, #4 +#CHECK-NO-82: mrc2 p8, #0, r0, c0, c9, #4 +#CHECK-NO-82: mcr2 p8, #0, r0, c1, c10, #3 +#CHECK-NO-82: mrc2 p8, #0, r0, c1, c10, #3 + +#CHECK-INVALID: warning: invalid instruction encoding +#CHECK-INVALID: [0x91,0x08,0x20,0xfc] +#CHECK-INVALID: ^ +#CHECK-INVALID: warning: invalid instruction encoding +#CHECK-INVALID: [0x91,0x08,0xa0,0xfc] +#CHECK-INVALID: ^ +#CHECK-INVALID: warning: invalid instruction encoding +#CHECK-INVALID: [0x52,0x08,0x21,0xfc] +#CHECK-INVALID: ^ +#CHECK-INVALID: warning: invalid instruction encoding +#CHECK-INVALID: [0x52,0x08,0xa1,0xfc] +#CHECK-INVALID: ^ +#CHECK-INVALID: warning: invalid instruction encoding +#CHECK-INVALID: [0x99,0x08,0x00,0xfe] +#CHECK-INVALID: ^ +#CHECK-INVALID: warning: invalid instruction encoding +#CHECK-INVALID: [0x99,0x08,0x10,0xfe] +#CHECK-INVALID: ^ +#CHECK-INVALID: warning: invalid instruction encoding +#CHECK-INVALID: [0x7a,0x08,0x01,0xfe] +#CHECK-INVALID: ^ +#CHECK-INVALID: warning: invalid instruction encoding +#CHECK-INVALID: [0x7a,0x08,0x11,0xfe] +#CHECK-INVALID: ^ Index: test/MC/Disassembler/ARM/armv8.2a-fpmul-t32.txt =================================================================== --- /dev/null +++ test/MC/Disassembler/ARM/armv8.2a-fpmul-t32.txt @@ -0,0 +1,47 @@ +# RUN: llvm-mc -triple thumb -mattr=+v8.2a,+fullfp16,+neon --disassemble < %s | FileCheck %s +# RUN: not llvm-mc -triple thumb -mattr=-v8.2a,+fullfp16,+neon --disassemble < %s 2>&1 | FileCheck %s --check-prefix=CHECK-INVALID +# RUN: not llvm-mc -triple thumb -mattr=+v8.2a,-fullfp16,+neon --disassemble < %s 2>&1 | FileCheck %s --check-prefix=CHECK-INVALID +# RUN: not llvm-mc -triple thumb -mattr=+v8.2a,+fullfp16,-neon --disassemble < %s 2>&1 | FileCheck %s --check-prefix=CHECK-INVALID + +[0x20,0xfc,0x91,0x08] +[0xa0,0xfc,0x91,0x08] +[0x21,0xfc,0x52,0x08] +[0xa1,0xfc,0x52,0x08] +[0x00,0xfe,0x99,0x08] +[0x10,0xfe,0x99,0x08] +[0x01,0xfe,0x7a,0x08] +[0x11,0xfe,0x7a,0x08] + +#CHECK: vfmal.f16 d0, s1, s2 +#CHECK: vfmsl.f16 d0, s1, s2 +#CHECK: vfmal.f16 q0, d1, d2 +#CHECK: vfmsl.f16 q0, d1, d2 +#CHECK: vfmal.f16 d0, s1, s2[1] +#CHECK: vfmsl.f16 d0, s1, s2[1] +#CHECK: vfmal.f16 q0, d1, d2[3] +#CHECK: vfmsl.f16 q0, d1, d2[3] + +#CHECK-INVALID: warning: invalid instruction encoding +#CHECK-INVALID: [0x20,0xfc,0x91,0x08] +#CHECK-INVALID: ^ +#CHECK-INVALID: warning: invalid instruction encoding +#CHECK-INVALID: [0xa0,0xfc,0x91,0x08] +#CHECK-INVALID: ^ +#CHECK-INVALID: warning: invalid instruction encoding +#CHECK-INVALID: [0x21,0xfc,0x52,0x08] +#CHECK-INVALID: ^ +#CHECK-INVALID: warning: invalid instruction encoding +#CHECK-INVALID: [0xa1,0xfc,0x52,0x08] +#CHECK-INVALID: ^ +#CHECK-INVALID: warning: invalid instruction encoding +#CHECK-INVALID: [0x00,0xfe,0x99,0x08] +#CHECK-INVALID: ^ +#CHECK-INVALID: warning: invalid instruction encoding +#CHECK-INVALID: [0x10,0xfe,0x99,0x08] +#CHECK-INVALID: ^ +#CHECK-INVALID: warning: invalid instruction encoding +#CHECK-INVALID: [0x01,0xfe,0x7a,0x08] +#CHECK-INVALID: ^ +#CHECK-INVALID: warning: invalid instruction encoding +#CHECK-INVALID: [0x11,0xfe,0x7a,0x08] +#CHECK-INVALID: ^