Index: bindings/go/llvm/target.go =================================================================== --- bindings/go/llvm/target.go +++ bindings/go/llvm/target.go @@ -62,6 +62,7 @@ const ( CodeModelDefault CodeModel = C.LLVMCodeModelDefault CodeModelJITDefault CodeModel = C.LLVMCodeModelJITDefault + CodeModelTiny CodeModel = C.LLVMCodeModelTiny CodeModelSmall CodeModel = C.LLVMCodeModelSmall CodeModelKernel CodeModel = C.LLVMCodeModelKernel CodeModelMedium CodeModel = C.LLVMCodeModelMedium Index: include/llvm-c/TargetMachine.h =================================================================== --- include/llvm-c/TargetMachine.h +++ include/llvm-c/TargetMachine.h @@ -45,6 +45,7 @@ typedef enum { LLVMCodeModelDefault, LLVMCodeModelJITDefault, + LLVMCodeModelTiny, LLVMCodeModelSmall, LLVMCodeModelKernel, LLVMCodeModelMedium, Index: include/llvm/CodeGen/CommandFlags.inc =================================================================== --- include/llvm/CodeGen/CommandFlags.inc +++ include/llvm/CodeGen/CommandFlags.inc @@ -74,7 +74,8 @@ static cl::opt CMModel( "code-model", cl::desc("Choose code model"), - cl::values(clEnumValN(CodeModel::Small, "small", "Small code model"), + cl::values(clEnumValN(CodeModel::Tiny, "tiny", "Tiny code model"), + clEnumValN(CodeModel::Small, "small", "Small code model"), clEnumValN(CodeModel::Kernel, "kernel", "Kernel code model"), clEnumValN(CodeModel::Medium, "medium", "Medium code model"), clEnumValN(CodeModel::Large, "large", "Large code model"))); Index: include/llvm/Support/CodeGen.h =================================================================== --- include/llvm/Support/CodeGen.h +++ include/llvm/Support/CodeGen.h @@ -25,7 +25,7 @@ // Code model types. namespace CodeModel { // Sync changes with CodeGenCWrappers.h. - enum Model { Small, Kernel, Medium, Large }; + enum Model { Tiny, Small, Kernel, Medium, Large }; } namespace PICLevel { Index: include/llvm/Target/CodeGenCWrappers.h =================================================================== --- include/llvm/Target/CodeGenCWrappers.h +++ include/llvm/Target/CodeGenCWrappers.h @@ -31,6 +31,8 @@ LLVM_FALLTHROUGH; case LLVMCodeModelDefault: return None; + case LLVMCodeModelTiny: + return CodeModel::Tiny; case LLVMCodeModelSmall: return CodeModel::Small; case LLVMCodeModelKernel: @@ -45,6 +47,8 @@ inline LLVMCodeModel wrap(CodeModel::Model Model) { switch (Model) { + case CodeModel::Tiny: + return LLVMCodeModelTiny; case CodeModel::Small: return LLVMCodeModelSmall; case CodeModel::Kernel: Index: lib/Target/AArch64/AArch64FrameLowering.cpp =================================================================== --- lib/Target/AArch64/AArch64FrameLowering.cpp +++ lib/Target/AArch64/AArch64FrameLowering.cpp @@ -655,6 +655,7 @@ .setMIFlags(MachineInstr::FrameSetup); switch (MF.getTarget().getCodeModel()) { + case CodeModel::Tiny: case CodeModel::Small: case CodeModel::Medium: case CodeModel::Kernel: Index: lib/Target/AArch64/AArch64ISelLowering.h =================================================================== --- lib/Target/AArch64/AArch64ISelLowering.h +++ lib/Target/AArch64/AArch64ISelLowering.h @@ -35,6 +35,7 @@ // offset of a variable into X0, using the TLSDesc model. TLSDESC_CALLSEQ, ADRP, // Page address of a TargetGlobalAddress operand. + ADR, // ADR ADDlow, // Add the low 12 bits of a TargetGlobalAddress operand. LOADgot, // Load from automatically generated descriptor (e.g. Global // Offset Table, TLS record). @@ -586,6 +587,8 @@ SDValue getAddrLarge(NodeTy *N, SelectionDAG &DAG, unsigned Flags = 0) const; template SDValue getAddr(NodeTy *N, SelectionDAG &DAG, unsigned Flags = 0) const; + template + SDValue getAddrTiny(NodeTy *N, SelectionDAG &DAG, unsigned Flags = 0) const; SDValue LowerADDROFRETURNADDR(SDValue Op, SelectionDAG &DAG) const; SDValue LowerGlobalAddress(SDValue Op, SelectionDAG &DAG) const; SDValue LowerGlobalTLSAddress(SDValue Op, SelectionDAG &DAG) const; Index: lib/Target/AArch64/AArch64ISelLowering.cpp =================================================================== --- lib/Target/AArch64/AArch64ISelLowering.cpp +++ lib/Target/AArch64/AArch64ISelLowering.cpp @@ -1086,6 +1086,7 @@ case AArch64ISD::FIRST_NUMBER: break; case AArch64ISD::CALL: return "AArch64ISD::CALL"; case AArch64ISD::ADRP: return "AArch64ISD::ADRP"; + case AArch64ISD::ADR: return "AArch64ISD::ADR"; case AArch64ISD::ADDlow: return "AArch64ISD::ADDlow"; case AArch64ISD::LOADgot: return "AArch64ISD::LOADgot"; case AArch64ISD::RET_FLAG: return "AArch64ISD::RET_FLAG"; @@ -3912,6 +3913,17 @@ return DAG.getNode(AArch64ISD::ADDlow, DL, Ty, ADRP, Lo); } +// (adr sym) +template +SDValue AArch64TargetLowering::getAddrTiny(NodeTy *N, SelectionDAG &DAG, + unsigned Flags) const { + LLVM_DEBUG(dbgs() << "AArch64TargetLowering::getAddrTiny\n"); + SDLoc DL(N); + EVT Ty = getPointerTy(DAG.getDataLayout()); + SDValue Sym = getTargetNode(N, Ty, DAG, Flags); + return DAG.getNode(AArch64ISD::ADR, DL, Ty, Sym); +} + SDValue AArch64TargetLowering::LowerGlobalAddress(SDValue Op, SelectionDAG &DAG) const { GlobalAddressSDNode *GN = cast(Op); @@ -3926,17 +3938,19 @@ assert(cast(Op)->getOffset() == 0 && "unexpected offset in global node"); - // This also catches the large code model case for Darwin. - if ((OpFlags & AArch64II::MO_GOT) != 0) { + // This also catches the large code model case for Darwin, and tiny code + // model with git relocations. + if ((OpFlags & AArch64II::MO_GOT) != 0) return getGOT(GN, DAG, TargetFlags); - } SDValue Result; - if (getTargetMachine().getCodeModel() == CodeModel::Large) { + if (getTargetMachine().getCodeModel() == CodeModel::Large) Result = getAddrLarge(GN, DAG, TargetFlags); - } else { + else if (getTargetMachine().getCodeModel() == CodeModel::Tiny) + Result = getAddrTiny(GN, DAG, TargetFlags); + else Result = getAddr(GN, DAG, TargetFlags); - } + EVT PtrVT = getPointerTy(DAG.getDataLayout()); SDLoc DL(GN); if (GV->hasDLLImportStorageClass()) @@ -4776,9 +4790,11 @@ // is necessary here. Just get the address of the jump table. JumpTableSDNode *JT = cast(Op); - if (getTargetMachine().getCodeModel() == CodeModel::Large && - !Subtarget->isTargetMachO()) { - return getAddrLarge(JT, DAG); + if (!Subtarget->isTargetMachO()) { + if (getTargetMachine().getCodeModel() == CodeModel::Large) + return getAddrLarge(JT, DAG); + else if (getTargetMachine().getCodeModel() == CodeModel::Tiny) + return getAddrTiny(JT, DAG); } return getAddr(JT, DAG); } @@ -4793,6 +4809,9 @@ return getGOT(CP, DAG); } return getAddrLarge(CP, DAG); + } else if (getTargetMachine().getCodeModel() == CodeModel::Tiny && + !Subtarget->isTargetMachO()) { + return getAddrTiny(CP, DAG); } else { return getAddr(CP, DAG); } @@ -4801,12 +4820,13 @@ SDValue AArch64TargetLowering::LowerBlockAddress(SDValue Op, SelectionDAG &DAG) const { BlockAddressSDNode *BA = cast(Op); - if (getTargetMachine().getCodeModel() == CodeModel::Large && - !Subtarget->isTargetMachO()) { - return getAddrLarge(BA, DAG); - } else { - return getAddr(BA, DAG); + if (!Subtarget->isTargetMachO()) { + if (getTargetMachine().getCodeModel() == CodeModel::Large) + return getAddrLarge(BA, DAG); + else if (getTargetMachine().getCodeModel() == CodeModel::Tiny) + return getAddrTiny(BA, DAG); } + return getAddr(BA, DAG); } SDValue AArch64TargetLowering::LowerDarwin_VASTART(SDValue Op, Index: lib/Target/AArch64/AArch64InstrInfo.td =================================================================== --- lib/Target/AArch64/AArch64InstrInfo.td +++ lib/Target/AArch64/AArch64InstrInfo.td @@ -166,6 +166,7 @@ // Node definitions. def AArch64adrp : SDNode<"AArch64ISD::ADRP", SDTIntUnaryOp, []>; +def AArch64adr : SDNode<"AArch64ISD::ADR", SDTIntUnaryOp, []>; def AArch64addlow : SDNode<"AArch64ISD::ADDlow", SDTIntBinOp, []>; def AArch64LOADgot : SDNode<"AArch64ISD::LOADgot", SDTIntUnaryOp>; def AArch64callseq_start : SDNode<"ISD::CALLSEQ_START", @@ -1348,7 +1349,8 @@ //===----------------------------------------------------------------------===// let isReMaterializable = 1 in { let hasSideEffects = 0, mayStore = 0, mayLoad = 0 in { -def ADR : ADRI<0, "adr", adrlabel, []>; +def ADR : ADRI<0, "adr", adrlabel, + [(set GPR64:$Xd, (AArch64adr tglobaladdr:$label))]>; } // hasSideEffects = 0 def ADRP : ADRI<1, "adrp", adrplabel, @@ -1356,6 +1358,10 @@ } // isReMaterializable = 1 // page address of a constant pool entry, block address +def : Pat<(AArch64adr tconstpool:$cp), (ADR tconstpool:$cp)>; +def : Pat<(AArch64adr tblockaddress:$cp), (ADR tblockaddress:$cp)>; +def : Pat<(AArch64adr texternalsym:$sym), (ADR texternalsym:$sym)>; +def : Pat<(AArch64adr tjumptable:$sym), (ADR tjumptable:$sym)>; def : Pat<(AArch64adrp tconstpool:$cp), (ADRP tconstpool:$cp)>; def : Pat<(AArch64adrp tblockaddress:$cp), (ADRP tblockaddress:$cp)>; def : Pat<(AArch64adrp texternalsym:$sym), (ADRP texternalsym:$sym)>; Index: lib/Target/AArch64/AArch64InstructionSelector.cpp =================================================================== --- lib/Target/AArch64/AArch64InstructionSelector.cpp +++ lib/Target/AArch64/AArch64InstructionSelector.cpp @@ -968,6 +968,9 @@ BuildMovK(DstReg, AArch64II::MO_G3, 48, I.getOperand(0).getReg()); I.eraseFromParent(); return true; + } else if (TM.getCodeModel() == CodeModel::Tiny) { + I.setDesc(TII.get(AArch64::ADR)); + I.getOperand(1).setTargetFlags(OpFlags); } else { I.setDesc(TII.get(AArch64::MOVaddr)); I.getOperand(1).setTargetFlags(OpFlags | AArch64II::MO_PAGE); Index: lib/Target/AArch64/AArch64Subtarget.h =================================================================== --- lib/Target/AArch64/AArch64Subtarget.h +++ lib/Target/AArch64/AArch64Subtarget.h @@ -312,13 +312,15 @@ bool useAA() const override { return UseAA; } - bool useSmallAddressing() const { + bool useSmallAddressing(bool OrTiny = false) const { switch (TLInfo.getTargetMachine().getCodeModel()) { case CodeModel::Kernel: // Kernel is currently allowed only for Fuchsia targets, // where it is the same as Small for almost all purposes. case CodeModel::Small: return true; + case CodeModel::Tiny: + return OrTiny; default: return false; } Index: lib/Target/AArch64/AArch64Subtarget.cpp =================================================================== --- lib/Target/AArch64/AArch64Subtarget.cpp +++ lib/Target/AArch64/AArch64Subtarget.cpp @@ -204,7 +204,8 @@ // The small code model's direct accesses use ADRP, which cannot // necessarily produce the value 0 (if the code is above 4GB). - if (useSmallAddressing() && GV->hasExternalWeakLinkage()) + // Same for the tiny code model, where we have an ADR. + if (useSmallAddressing(true) && GV->hasExternalWeakLinkage()) return AArch64II::MO_GOT | Flags; return Flags; Index: lib/Target/AArch64/AArch64TargetMachine.cpp =================================================================== --- lib/Target/AArch64/AArch64TargetMachine.cpp +++ lib/Target/AArch64/AArch64TargetMachine.cpp @@ -210,13 +210,14 @@ Optional CM, bool JIT) { if (CM) { - if (*CM != CodeModel::Small && *CM != CodeModel::Large) { + if (*CM != CodeModel::Small && *CM != CodeModel::Tiny && + *CM != CodeModel::Large) { if (!TT.isOSFuchsia()) report_fatal_error( - "Only small and large code models are allowed on AArch64"); - else if (CM != CodeModel::Kernel) - report_fatal_error( - "Only small, kernel, and large code models are allowed on AArch64"); + "Only small, tiny and large code models are allowed on AArch64"); + else if (*CM != CodeModel::Kernel) + report_fatal_error("Only small, tiny, kernel, and large code models " + "are allowed on AArch64"); } return *CM; } Index: lib/Target/AArch64/MCTargetDesc/AArch64ELFObjectWriter.cpp =================================================================== --- lib/Target/AArch64/MCTargetDesc/AArch64ELFObjectWriter.cpp +++ lib/Target/AArch64/MCTargetDesc/AArch64ELFObjectWriter.cpp @@ -138,7 +138,9 @@ } else return ELF::R_AARCH64_PREL64; case AArch64::fixup_aarch64_pcrel_adr_imm21: - assert(SymLoc == AArch64MCExpr::VK_NONE && "unexpected ADR relocation"); + assert((SymLoc == AArch64MCExpr::VK_NONE || + (SymLoc == AArch64MCExpr::VK_ABS && !IsNC)) && + "unexpected ADR relocation"); return R_CLS(ADR_PREL_LO21); case AArch64::fixup_aarch64_pcrel_adrp_imm21: if (SymLoc == AArch64MCExpr::VK_ABS && !IsNC) Index: lib/Target/ARM/ARMFrameLowering.cpp =================================================================== --- lib/Target/ARM/ARMFrameLowering.cpp +++ lib/Target/ARM/ARMFrameLowering.cpp @@ -526,6 +526,7 @@ .setMIFlags(MachineInstr::FrameSetup); switch (TM.getCodeModel()) { + case CodeModel::Tiny: case CodeModel::Small: case CodeModel::Medium: case CodeModel::Kernel: Index: lib/Target/ARM/ARMISelLowering.cpp =================================================================== --- lib/Target/ARM/ARMISelLowering.cpp +++ lib/Target/ARM/ARMISelLowering.cpp @@ -9169,6 +9169,7 @@ // IP. switch (TM.getCodeModel()) { + case CodeModel::Tiny: case CodeModel::Small: case CodeModel::Medium: case CodeModel::Kernel: Index: test/CodeGen/AArch64/GlobalISel/select-gv-cmodel-tiny.mir =================================================================== --- /dev/null +++ test/CodeGen/AArch64/GlobalISel/select-gv-cmodel-tiny.mir @@ -0,0 +1,56 @@ +# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py +# RUN: llc -mtriple=aarch64-none-eabi -code-model=tiny -run-pass=instruction-select -verify-machineinstrs -O0 %s -o - | FileCheck %s +--- | + target datalayout = "e-m:e-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128" + + @foo1 = common global [1073741824 x i32] zeroinitializer, align 4 + @foo2 = common global [1073741824 x i32] zeroinitializer, align 4 + + define i32 @gv_tiny() { + entry: + %retval = alloca i32, align 4 + store i32 0, i32* %retval, align 4 + %0 = load i32, i32* getelementptr inbounds ([1073741824 x i32], [1073741824 x i32]* @foo1, i64 0, i64 0), align 4 + %1 = load i32, i32* getelementptr inbounds ([1073741824 x i32], [1073741824 x i32]* @foo2, i64 0, i64 0), align 4 + %add = add nsw i32 %0, %1 + ret i32 %add + } + +... +--- +name: gv_tiny +legalized: true +regBankSelected: true +stack: + - { id: 0, name: retval, type: default, offset: 0, size: 4, alignment: 4, + stack-id: 0, callee-saved-register: '', callee-saved-restored: true, + debug-info-variable: '', debug-info-expression: '', + debug-info-location: '' } +constants: +body: | + bb.1: + ; CHECK-LABEL: name: gv_tiny + ; CHECK: [[ADR:%[0-9]+]]:gpr64 = ADR @foo1 + ; CHECK: [[COPY:%[0-9]+]]:gpr64sp = COPY [[ADR]] + ; CHECK: [[ADR1:%[0-9]+]]:gpr64 = ADR @foo2 + ; CHECK: [[COPY1:%[0-9]+]]:gpr64sp = COPY [[ADR1]] + ; CHECK: STRWui $wzr, %stack.0.retval, 0 :: (store 4 into %ir.retval) + ; CHECK: [[LDRWui:%[0-9]+]]:gpr32 = LDRWui [[COPY]], 0 :: (load 4 from `i32* getelementptr inbounds ([1073741824 x i32], [1073741824 x i32]* @foo1, i64 0, i64 0)`) + ; CHECK: [[LDRWui1:%[0-9]+]]:gpr32 = LDRWui [[COPY1]], 0 :: (load 4 from `i32* getelementptr inbounds ([1073741824 x i32], [1073741824 x i32]* @foo2, i64 0, i64 0)`) + ; CHECK: [[ADDWrr:%[0-9]+]]:gpr32 = ADDWrr [[LDRWui]], [[LDRWui1]] + ; CHECK: $w0 = COPY [[ADDWrr]] + ; CHECK: RET_ReallyLR implicit $w0 + %1:gpr(s32) = G_CONSTANT i32 0 + %4:gpr(p0) = G_GLOBAL_VALUE @foo1 + %3:gpr(p0) = COPY %4(p0) + %7:gpr(p0) = G_GLOBAL_VALUE @foo2 + %6:gpr(p0) = COPY %7(p0) + %0:gpr(p0) = G_FRAME_INDEX %stack.0.retval + G_STORE %1(s32), %0(p0) :: (store 4 into %ir.retval) + %2:gpr(s32) = G_LOAD %3(p0) :: (load 4 from `i32* getelementptr inbounds ([1073741824 x i32], [1073741824 x i32]* @foo1, i64 0, i64 0)`) + %5:gpr(s32) = G_LOAD %6(p0) :: (load 4 from `i32* getelementptr inbounds ([1073741824 x i32], [1073741824 x i32]* @foo2, i64 0, i64 0)`) + %8:gpr(s32) = G_ADD %2, %5 + $w0 = COPY %8(s32) + RET_ReallyLR implicit $w0 + +... Index: test/CodeGen/AArch64/blockaddress.ll =================================================================== --- test/CodeGen/AArch64/blockaddress.ll +++ test/CodeGen/AArch64/blockaddress.ll @@ -1,5 +1,6 @@ ; RUN: llc -mtriple=aarch64-none-linux-gnu -aarch64-enable-atomic-cfg-tidy=0 -verify-machineinstrs < %s | FileCheck %s ; RUN: llc -code-model=large -mtriple=aarch64-none-linux-gnu -aarch64-enable-atomic-cfg-tidy=0 -verify-machineinstrs < %s | FileCheck --check-prefix=CHECK-LARGE %s +; RUN: llc -code-model=tiny -mtriple=aarch64-none-none-eabi -aarch64-enable-atomic-cfg-tidy=0 -verify-machineinstrs < %s | FileCheck --check-prefix=CHECK-TINY %s @addr = global i8* null @@ -22,6 +23,11 @@ ; CHECK-LARGE: ldr [[NEWDEST:x[0-9]+]] ; CHECK-LARGE: br [[NEWDEST]] +; CHECK-TINY: adr [[DEST:x[0-9]+]], {{.Ltmp[0-9]+}} +; CHECK-TINY: str [[DEST]], +; CHECK-TINY: ldr [[NEWDEST:x[0-9]+]] +; CHECK-TINY: br [[NEWDEST]] + block: ret void } Index: test/CodeGen/AArch64/code-model-tiny-abs.ll =================================================================== --- /dev/null +++ test/CodeGen/AArch64/code-model-tiny-abs.ll @@ -0,0 +1,54 @@ +; RUN: llc -mtriple=aarch64-none-eabi -code-model=tiny < %s | FileCheck %s + +@var8 = global i8 0 +@var16 = global i16 0 +@var32 = global i32 0 +@var64 = global i64 0 + +define i8* @global_addr() { +; CHECK-LABEL: global_addr: + ret i8* @var8 + ; The adr calculation should end up returned directly in x0. +; CHECK: adr x0, var8 +; CHECK-NEXT: ret +} + +define i8 @global_i8() { +; CHECK-LABEL: global_i8: + %val = load i8, i8* @var8 + ret i8 %val +; CHECK: adr x[[ADDR_REG:[0-9]+]], var8 +; CHECK: ldrb w0, [x[[ADDR_REG]]] +} + +define i16 @global_i16() { +; CHECK-LABEL: global_i16: + %val = load i16, i16* @var16 + ret i16 %val +; CHECK: adr x[[ADDR_REG:[0-9]+]], var16 +; CHECK: ldrh w0, [x[[ADDR_REG]]] +} + +define i32 @global_i32() { +; CHECK-LABEL: global_i32: + %val = load i32, i32* @var32 + ret i32 %val +; CHECK: adr x[[ADDR_REG:[0-9]+]], var32 +; CHECK: ldr w0, [x[[ADDR_REG]]] +} + +define i64 @global_i64() { +; CHECK-LABEL: global_i64: + %val = load i64, i64* @var64 + ret i64 %val +; CHECK: adr x[[ADDR_REG:[0-9]+]], var64 +; CHECK: ldr x0, [x[[ADDR_REG]]] +} + +define <2 x i64> @constpool() { +; CHECK-LABEL: constpool: + ret <2 x i64> + +; CHECK: adr x[[ADDR_REG:[0-9]+]], {{.LCPI[0-9]+_[0-9]+}} +; CHECK: ldr q0, [x[[ADDR_REG]]] +} Index: test/CodeGen/AArch64/extern-weak.ll =================================================================== --- test/CodeGen/AArch64/extern-weak.ll +++ test/CodeGen/AArch64/extern-weak.ll @@ -1,6 +1,7 @@ ; RUN: llc -mtriple=aarch64-none-linux-gnu -relocation-model=pic -o - %s | FileCheck %s ; RUN: llc -mtriple=aarch64-none-linux-gnu -relocation-model=static -o - < %s | FileCheck %s ; RUN: llc -mtriple=aarch64-none-linux-gnu -code-model=large -o - %s | FileCheck --check-prefix=CHECK-LARGE %s +; RUN: llc -mtriple=aarch64-none-none-eabi -code-model=tiny -o - %s | FileCheck --check-prefix=CHECK-TINY %s declare extern_weak i32 @var() @@ -20,6 +21,11 @@ ; CHECK-LARGE: movk x0, #:abs_g1_nc:var ; CHECK-LARGE: movk x0, #:abs_g2_nc:var ; CHECK-LARGE: movk x0, #:abs_g3:var + + ; In the tiny codemodel there is no ADR GOT relocation, so we + ; fall-back to a ADRP/ADD pair, same as small. +; CHECK-TINY: adrp x[[ADDRHI:[0-9]+]], :got:var +; CHECK-TINY: ldr x0, [x[[ADDRHI]], :got_lo12:var] } @@ -41,6 +47,10 @@ ; CHECK-LARGE: movk [[ADDR]], #:abs_g1_nc:arr_var ; CHECK-LARGE: movk [[ADDR]], #:abs_g2_nc:arr_var ; CHECK-LARGE: movk [[ADDR]], #:abs_g3:arr_var + +; CHECK-TINY: adrp x[[ADDRHI:[0-9]+]], :got:arr_var +; CHECK-TINY: ldr [[BASE:x[0-9]+]], [x[[ADDRHI]], :got_lo12:arr_var] +; CHECK-TINY: add x0, [[BASE]], #20 } @defined_weak_var = internal unnamed_addr global i32 0 @@ -55,4 +65,6 @@ ; CHECK-LARGE: movk x0, #:abs_g1_nc:defined_weak_var ; CHECK-LARGE: movk x0, #:abs_g2_nc:defined_weak_var ; CHECK-LARGE: movk x0, #:abs_g3:defined_weak_var + +; CHECK-TINY: adr x0, defined_weak_var } Index: test/CodeGen/AArch64/fpimm.ll =================================================================== --- test/CodeGen/AArch64/fpimm.ll +++ test/CodeGen/AArch64/fpimm.ll @@ -1,39 +1,48 @@ ; RUN: llc -mtriple=aarch64-linux-gnu -verify-machineinstrs < %s | FileCheck %s ; RUN: llc -mtriple=aarch64-apple-darwin -code-model=large -verify-machineinstrs < %s | FileCheck %s --check-prefix=LARGE ; RUN: llc -mtriple=aarch64-apple-darwin -code-model=large -fast-isel -fast-isel-abort=1 -verify-machineinstrs < %s | FileCheck %s --check-prefix=LARGE +; RUN: llc -mtriple=aarch64-none-eabi -code-model=tiny -verify-machineinstrs < %s | FileCheck %s --check-prefix=TINY @varf32 = global float 0.0 @varf64 = global double 0.0 define void @check_float() { ; CHECK-LABEL: check_float: +; TINY-LABEL: check_float: %val = load float, float* @varf32 %newval1 = fadd float %val, 8.5 store volatile float %newval1, float* @varf32 -; CHECK-DAG: fmov [[EIGHT5:s[0-9]+]], #8.5 +; CHECK-DAG: fmov {{s[0-9]+}}, #8.5 +; TINY-DAG: fmov {{s[0-9]+}}, #8.5 %newval2 = fadd float %val, 128.0 store volatile float %newval2, float* @varf32 -; CHECK-DAG: ldr [[HARD:s[0-9]+]], [{{x[0-9]+}}, {{#?}}:lo12:.LCPI0_0 +; CHECK-DAG: ldr {{s[0-9]+}}, [{{x[0-9]+}}, {{#?}}:lo12:.LCPI0_0 +; TINY-DAG: ldr {{s[0-9]+}}, [{{x[0-9]+}}] ; CHECK: ret +; TINY: ret ret void } define void @check_double() { ; CHECK-LABEL: check_double: +; TINY-LABEL: check_double: %val = load double, double* @varf64 %newval1 = fadd double %val, 8.5 store volatile double %newval1, double* @varf64 ; CHECK-DAG: fmov {{d[0-9]+}}, #8.5 +; TINY-DAG: fmov {{d[0-9]+}}, #8.5 %newval2 = fadd double %val, 128.0 store volatile double %newval2, double* @varf64 ; CHECK-DAG: ldr {{d[0-9]+}}, [{{x[0-9]+}}, {{#?}}:lo12:.LCPI1_0 +; TINY-DAG: ldr {{d[0-9]+}}, [{{x[0-9]+}}] ; CHECK: ret +; TINY: ret ret void } @@ -41,6 +50,9 @@ ; LARGE: mov [[REG:w[0-9]+]], #4059 ; LARGE-NEXT: movk [[REG]], #16457, lsl #16 ; LARGE-NEXT: fmov s0, [[REG]] +; TINY-LABEL: check_float2 +; TINY: adr x[[REG:[0-9]+]], .LCPI2_0 +; TINY-NEXT: ldr s0, [x[[REG]]] define float @check_float2() { ret float 3.14159274101257324218750 } @@ -51,6 +63,9 @@ ; LARGE-NEXT: movk [[REG]], #8699, lsl #32 ; LARGE-NEXT: movk [[REG]], #16393, lsl #48 ; LARGE-NEXT: fmov d0, [[REG]] +; TINY-LABEL: check_double2 +; TINY: adr x[[REG:[0-9]+]], .LCPI3_0 +; TINY-NEXT: ldr d0, [x[[REG]]] define double @check_double2() { ret double 3.1415926535897931159979634685441851615905761718750 } Index: test/CodeGen/AArch64/jump-table.ll =================================================================== --- test/CodeGen/AArch64/jump-table.ll +++ test/CodeGen/AArch64/jump-table.ll @@ -1,6 +1,7 @@ ; RUN: llc -verify-machineinstrs -o - %s -mtriple=aarch64-none-linux-gnu -aarch64-enable-atomic-cfg-tidy=0 | FileCheck %s ; RUN: llc -code-model=large -verify-machineinstrs -o - %s -mtriple=aarch64-none-linux-gnu -aarch64-enable-atomic-cfg-tidy=0 | FileCheck --check-prefix=CHECK-LARGE %s ; RUN: llc -mtriple=aarch64-none-linux-gnu -verify-machineinstrs -relocation-model=pic -aarch64-enable-atomic-cfg-tidy=0 -o - %s | FileCheck --check-prefix=CHECK-PIC %s +; RUN: llc -code-model=tiny -verify-machineinstrs -o - %s -mtriple=aarch64-none-linux-gnu -aarch64-enable-atomic-cfg-tidy=0 | FileCheck --check-prefix=CHECK-TINY %s define i32 @test_jumptable(i32 %in) { ; CHECK: test_jumptable @@ -29,6 +30,10 @@ ; CHECK-PIC: add [[TABLE:x[0-9]+]], [[DEST]], x[[JT]] ; CHECK-PIC: br [[TABLE]] +; CHECK-TINY: adr x[[JT:[0-9]+]], .LJTI0_0 +; CHECK-TINY: ldr [[DEST:x[0-9]+]], [x[[JT]], {{x[0-9]+}}, lsl #3] +; CHECK-TINY: br [[DEST]] + def: ret i32 0 Index: test/CodeGen/AArch64/literal_pools_float.ll =================================================================== --- test/CodeGen/AArch64/literal_pools_float.ll +++ test/CodeGen/AArch64/literal_pools_float.ll @@ -1,7 +1,9 @@ ; RUN: llc -verify-machineinstrs -o - %s -mtriple=aarch64-none-linux-gnu -mcpu=cyclone | FileCheck %s ; RUN: llc -verify-machineinstrs -o - %s -mtriple=aarch64-none-linux-gnu -code-model=large -mcpu=cyclone | FileCheck --check-prefix=CHECK-LARGE %s +; RUN: llc -verify-machineinstrs -o - %s -mtriple=aarch64-none-none-eabi -code-model=tiny -mcpu=cyclone | FileCheck --check-prefix=CHECK-TINY %s ; RUN: llc -verify-machineinstrs < %s -mtriple=aarch64-none-linux-gnu -mattr=-fp-armv8 | FileCheck --check-prefix=CHECK-NOFP %s ; RUN: llc -verify-machineinstrs < %s -mtriple=aarch64-none-linux-gnu -code-model=large -mattr=-fp-armv8 | FileCheck --check-prefix=CHECK-NOFP-LARGE %s +; RUN: llc -verify-machineinstrs < %s -mtriple=aarch64-none-none-eabi -code-model=tiny -mattr=-fp-armv8 | FileCheck --check-prefix=CHECK-NOFP-TINY %s @varfloat = global float 0.0 @vardouble = global double 0.0 @@ -15,6 +17,10 @@ ; CHECK: ldr [[LIT128:s[0-9]+]], [x[[LITBASE]], {{#?}}:lo12:[[CURLIT]]] ; CHECK-NOFP-NOT: ldr {{s[0-9]+}}, +; CHECK-TINY: adr x[[LITBASE:[0-9]+]], [[CURLIT:.LCPI[0-9]+_[0-9]+]] +; CHECK-TINY: ldr [[LIT128:s[0-9]+]], [x[[LITBASE]]] +; CHECK-NOFP-TINY-NOT: ldr {{s[0-9]+}}, + ; CHECK-LARGE: movz x[[LITADDR:[0-9]+]], #:abs_g0_nc:[[CURLIT:.LCPI[0-9]+_[0-9]+]] ; CHECK-LARGE: movk x[[LITADDR]], #:abs_g1_nc:[[CURLIT]] ; CHECK-LARGE: movk x[[LITADDR]], #:abs_g2_nc:[[CURLIT]] @@ -33,6 +39,11 @@ ; CHECK-NOFP-NOT: ldr {{d[0-9]+}}, ; CHECK-NOFP-NOT: fadd +; CHECK-TINY: adr x[[LITBASE:[0-9]+]], [[CURLIT:.LCPI[0-9]+_[0-9]+]] +; CHECK-TINY: ldr [[LIT129:d[0-9]+]], [x[[LITBASE]]] +; CHECK-NOFP-TINY-NOT: ldr {{d[0-9]+}}, +; CHECK-NOFP-TINY-NOT: fadd + ; CHECK-LARGE: movz x[[LITADDR:[0-9]+]], #:abs_g0_nc:[[CURLIT:.LCPI[0-9]+_[0-9]+]] ; CHECK-LARGE: movk x[[LITADDR]], #:abs_g1_nc:[[CURLIT]] ; CHECK-LARGE: movk x[[LITADDR]], #:abs_g2_nc:[[CURLIT]]