Index: lib/CodeGen/ScheduleDAGInstrs.cpp =================================================================== --- lib/CodeGen/ScheduleDAGInstrs.cpp +++ lib/CodeGen/ScheduleDAGInstrs.cpp @@ -234,6 +234,11 @@ // Ask the target if address-backscheduling is desirable, and if so how much. const TargetSubtargetInfo &ST = MF.getSubtarget(); + // Only use any non-zero latency for real defs/uses, in contrast to + // "fake" operands added by regalloc. + const MCInstrDesc *DefMIDesc = &SU->getInstr()->getDesc(); + bool ImplicitPseudoDef = (OperIdx >= DefMIDesc->getNumOperands() && + !DefMIDesc->hasImplicitDefOfPhysReg(MO.getReg())); for (MCRegAliasIterator Alias(MO.getReg(), TRI, true); Alias.isValid(); ++Alias) { if (!Uses.contains(*Alias)) @@ -257,11 +262,18 @@ Dep = SDep(SU, SDep::Data, *Alias); RegUse = UseSU->getInstr(); } - Dep.setLatency( - SchedModel.computeOperandLatency(SU->getInstr(), OperIdx, RegUse, - UseOp)); + const MCInstrDesc *UseMIDesc = + (RegUse ? &UseSU->getInstr()->getDesc() : nullptr); + bool ImplicitPseudoUse = + (UseMIDesc && UseOp >= ((int)UseMIDesc->getNumOperands()) && + !UseMIDesc->hasImplicitUseOfPhysReg(*Alias)); + if (!ImplicitPseudoDef && !ImplicitPseudoUse) { + Dep.setLatency(SchedModel.computeOperandLatency(SU->getInstr(), OperIdx, + RegUse, UseOp)); + ST.adjustSchedDependency(SU, UseSU, Dep); + } else + Dep.setLatency(0); - ST.adjustSchedDependency(SU, UseSU, Dep); UseSU->addPred(Dep); } } Index: test/CodeGen/SystemZ/misched-readadvances.mir =================================================================== --- /dev/null +++ test/CodeGen/SystemZ/misched-readadvances.mir @@ -0,0 +1,31 @@ +# Check that the extra operand for the full register added by RegAlloc does +# not have a latency that interferes with the latency adjustment +# (ReadAdvance) for the MSY register operand. + +# RUN: llc %s -mtriple=s390x-linux-gnu -mcpu=z13 -start-before=machine-scheduler \ +# RUN: -debug-only=machine-scheduler -o - 2>&1 | FileCheck %s +# REQUIRES: asserts + +# CHECK: ScheduleDAGMI::schedule starting +# CHECK: SU(4): renamable $r2l = MSR renamable $r2l(tied-def 0), renamable $r2l +# CHECK: Latency : 6 +# CHECK: SU(5): renamable $r2l = MSY renamable $r2l(tied-def 0), renamable $r1d, -4, $noreg, implicit $r2d +# CHECK: Predecessors: +# CHECK: SU(4): Data Latency=2 Reg=$r2l +# CHECK: SU(4): Data Latency=0 Reg=$r2d + +--- +name: Perl_do_sv_dump +alignment: 4 +tracksRegLiveness: true +body: | + bb.0 : + %1:addr64bit = IMPLICIT_DEF + %2:addr64bit = IMPLICIT_DEF + %3:vr64bit = IMPLICIT_DEF + + bb.1 : + %2:addr64bit = ALGFI %2, 4294967291, implicit-def dead $cc + %2.subreg_l32:addr64bit = MSR %2.subreg_l32, %2.subreg_l32 + %2.subreg_l32:addr64bit = MSY %2.subreg_l32, %1, -4, $noreg +... Index: test/CodeGen/X86/lsr-loop-exit-cond.ll =================================================================== --- test/CodeGen/X86/lsr-loop-exit-cond.ll +++ test/CodeGen/X86/lsr-loop-exit-cond.ll @@ -97,8 +97,8 @@ ; ATOM-NEXT: pushq %r14 ; ATOM-NEXT: pushq %rbx ; ATOM-NEXT: ## kill: def $ecx killed $ecx def $rcx -; ATOM-NEXT: movl 4(%rdx), %eax ; ATOM-NEXT: movl (%rdx), %r15d +; ATOM-NEXT: movl 4(%rdx), %eax ; ATOM-NEXT: leaq 20(%rdx), %r14 ; ATOM-NEXT: movq _Te0@{{.*}}(%rip), %r9 ; ATOM-NEXT: movq _Te1@{{.*}}(%rip), %r8 @@ -116,8 +116,8 @@ ; ATOM-NEXT: movzbl %bl, %eax ; ATOM-NEXT: movl (%r10,%rax,4), %eax ; ATOM-NEXT: xorl (%r8,%rbp,4), %r15d -; ATOM-NEXT: xorl -4(%r14), %r15d ; ATOM-NEXT: xorl (%r9,%rdi,4), %eax +; ATOM-NEXT: xorl -4(%r14), %r15d ; ATOM-NEXT: xorl (%r14), %eax ; ATOM-NEXT: addq $16, %r14 ; ATOM-NEXT: LBB0_1: ## %bb @@ -130,14 +130,14 @@ ; ATOM-NEXT: movzbl %dil, %edi ; ATOM-NEXT: movl (%r8,%rdi,4), %ebx ; ATOM-NEXT: movzbl %r15b, %edi -; ATOM-NEXT: movl (%r10,%rdi,4), %edi ; ATOM-NEXT: xorl (%r9,%rbp,4), %ebx +; ATOM-NEXT: movl (%r10,%rdi,4), %edi ; ATOM-NEXT: xorl -12(%r14), %ebx ; ATOM-NEXT: xorl (%r9,%rax,4), %edi ; ATOM-NEXT: movl %ebx, %eax +; ATOM-NEXT: xorl -8(%r14), %edi ; ATOM-NEXT: shrl $24, %eax ; ATOM-NEXT: movl (%r9,%rax,4), %r15d -; ATOM-NEXT: xorl -8(%r14), %edi ; ATOM-NEXT: testq %r11, %r11 ; ATOM-NEXT: movl %edi, %eax ; ATOM-NEXT: jne LBB0_2 Index: test/CodeGen/X86/phys-reg-local-regalloc.ll =================================================================== --- test/CodeGen/X86/phys-reg-local-regalloc.ll +++ test/CodeGen/X86/phys-reg-local-regalloc.ll @@ -20,9 +20,9 @@ ; On Intel Atom the scheduler moves a movl instruction ; used for the printf call to follow movl 24(%esp), %eax ; ATOM: movl 24(%esp), %eax -; ATOM: movl -; ATOM: movl %eax, 36(%esp) ; ATOM-NOT: movl +; ATOM: movl %eax, 36(%esp) +; ATOM: movl ; ATOM: movl 28(%esp), %ebx ; ATOM-NOT: movl ; ATOM: movl %ebx, 40(%esp) Index: test/CodeGen/X86/schedule-x86-64-shld.ll =================================================================== --- test/CodeGen/X86/schedule-x86-64-shld.ll +++ test/CodeGen/X86/schedule-x86-64-shld.ll @@ -134,8 +134,8 @@ ; ; BTVER2-LABEL: lshift_cl_optsize: ; BTVER2: # %bb.0: # %entry -; BTVER2-NEXT: movq %rdx, %rcx # sched: [1:0.50] ; BTVER2-NEXT: movq %rdi, %rax # sched: [1:0.50] +; BTVER2-NEXT: movq %rdx, %rcx # sched: [1:0.50] ; BTVER2-NEXT: # kill: def $cl killed $cl killed $rcx ; BTVER2-NEXT: shldq %cl, %rsi, %rax # sched: [4:4.00] ; BTVER2-NEXT: retq # sched: [4:1.00] @@ -210,8 +210,8 @@ ; ; BTVER2-LABEL: rshift_cl_optsize: ; BTVER2: # %bb.0: # %entry -; BTVER2-NEXT: movq %rdx, %rcx # sched: [1:0.50] ; BTVER2-NEXT: movq %rdi, %rax # sched: [1:0.50] +; BTVER2-NEXT: movq %rdx, %rcx # sched: [1:0.50] ; BTVER2-NEXT: # kill: def $cl killed $cl killed $rcx ; BTVER2-NEXT: shrdq %cl, %rsi, %rax # sched: [4:4.00] ; BTVER2-NEXT: retq # sched: [4:1.00] Index: test/CodeGen/X86/schedule-x86_32.ll =================================================================== --- test/CodeGen/X86/schedule-x86_32.ll +++ test/CodeGen/X86/schedule-x86_32.ll @@ -451,8 +451,8 @@ ; ; ZNVER1-LABEL: test_arpl: ; ZNVER1: # %bb.0: -; ZNVER1-NEXT: movl {{[0-9]+}}(%esp), %ecx # sched: [8:0.50] ; ZNVER1-NEXT: movzwl {{[0-9]+}}(%esp), %eax # sched: [8:0.50] +; ZNVER1-NEXT: movl {{[0-9]+}}(%esp), %ecx # sched: [8:0.50] ; ZNVER1-NEXT: #APP ; ZNVER1-NEXT: arpl %ax, (%ecx) # sched: [100:0.25] ; ZNVER1-NEXT: #NO_APP @@ -620,10 +620,10 @@ ; ZNVER1-NEXT: pushl %esi # sched: [1:0.50] ; ZNVER1-NEXT: .cfi_def_cfa_offset 8 ; ZNVER1-NEXT: .cfi_offset %esi, -8 +; ZNVER1-NEXT: movzwl {{[0-9]+}}(%esp), %eax # sched: [8:0.50] ; ZNVER1-NEXT: movl {{[0-9]+}}(%esp), %ecx # sched: [8:0.50] ; ZNVER1-NEXT: movl {{[0-9]+}}(%esp), %edx # sched: [8:0.50] ; ZNVER1-NEXT: movl {{[0-9]+}}(%esp), %esi # sched: [8:0.50] -; ZNVER1-NEXT: movzwl {{[0-9]+}}(%esp), %eax # sched: [8:0.50] ; ZNVER1-NEXT: #APP ; ZNVER1-NEXT: bound %ax, (%esi) # sched: [100:0.25] ; ZNVER1-NEXT: bound %ecx, (%edx) # sched: [100:0.25] @@ -898,8 +898,8 @@ ; ; ZNVER1-LABEL: test_dec16: ; ZNVER1: # %bb.0: -; ZNVER1-NEXT: movl {{[0-9]+}}(%esp), %ecx # sched: [8:0.50] ; ZNVER1-NEXT: movzwl {{[0-9]+}}(%esp), %eax # sched: [8:0.50] +; ZNVER1-NEXT: movl {{[0-9]+}}(%esp), %ecx # sched: [8:0.50] ; ZNVER1-NEXT: #APP ; ZNVER1-NEXT: decw %ax # sched: [1:0.25] ; ZNVER1-NEXT: decw (%ecx) # sched: [5:0.50] @@ -1105,8 +1105,8 @@ ; ; ZNVER1-LABEL: test_inc16: ; ZNVER1: # %bb.0: -; ZNVER1-NEXT: movl {{[0-9]+}}(%esp), %ecx # sched: [8:0.50] ; ZNVER1-NEXT: movzwl {{[0-9]+}}(%esp), %eax # sched: [8:0.50] +; ZNVER1-NEXT: movl {{[0-9]+}}(%esp), %ecx # sched: [8:0.50] ; ZNVER1-NEXT: #APP ; ZNVER1-NEXT: incw %ax # sched: [1:0.25] ; ZNVER1-NEXT: incw (%ecx) # sched: [5:0.50] @@ -1777,8 +1777,8 @@ ; ; ZNVER1-LABEL: test_pop_push_16: ; ZNVER1: # %bb.0: -; ZNVER1-NEXT: movl {{[0-9]+}}(%esp), %ecx # sched: [8:0.50] ; ZNVER1-NEXT: movzwl {{[0-9]+}}(%esp), %eax # sched: [8:0.50] +; ZNVER1-NEXT: movl {{[0-9]+}}(%esp), %ecx # sched: [8:0.50] ; ZNVER1-NEXT: #APP ; ZNVER1-NEXT: popw %ax # sched: [8:0.50] ; ZNVER1-NEXT: popw (%ecx) # sched: [5:0.50]