Index: lib/Target/ARM/ARMISelLowering.h
===================================================================
--- lib/Target/ARM/ARMISelLowering.h
+++ lib/Target/ARM/ARMISelLowering.h
@@ -397,6 +397,11 @@
     Value *emitStoreConditional(IRBuilder<> &Builder, Value *Val,
                                 Value *Addr, AtomicOrdering Ord) const override;
 
+    void emitLeadingFence(IRBuilder<> &Builder, AtomicOrdering Ord,
+                            bool IsStore, bool IsLoad) const override;
+    void emitTrailingFence(IRBuilder<> &Builder, AtomicOrdering Ord,
+                            bool IsStore, bool IsLoad) const override;
+
     bool shouldExpandAtomicInIR(Instruction *Inst) const override;
 
     bool useLoadStackGuardNode() const override;
@@ -415,7 +420,6 @@
     const InstrItineraryData *Itins;
 
     /// ARMPCLabelIndex - Keep track of the number of ARM PC labels created.
-    ///
     unsigned ARMPCLabelIndex;
 
     void addTypeForNEON(MVT VT, MVT PromotedLdStVT, MVT PromotedBitwiseVT);
Index: lib/Target/ARM/ARMISelLowering.cpp
===================================================================
--- lib/Target/ARM/ARMISelLowering.cpp
+++ lib/Target/ARM/ARMISelLowering.cpp
@@ -2737,7 +2737,7 @@
 
   ConstantSDNode *OrdN = cast<ConstantSDNode>(Op.getOperand(1));
   AtomicOrdering Ord = static_cast<AtomicOrdering>(OrdN->getZExtValue());
-  unsigned Domain = ARM_MB::ISH;
+  ARM_MB::MemBOpt Domain = ARM_MB::ISH;
   if (Subtarget->isMClass()) {
     // Only a full system barrier exists in the M-class architectures.
     Domain = ARM_MB::SY;
@@ -10998,6 +10998,67 @@
   return true;
 }
 
+static void MakeDMB(IRBuilder<> &Builder, ARM_MB::MemBOpt Domain) {
+  Module *M = Builder.GetInsertBlock()->getParent()->getParent();
+  Function *DMB = llvm::Intrinsic::getDeclaration(M, Intrinsic::arm_dmb);
+  Constant *CDomain = Builder.getInt32(Domain);
+  Builder.CreateCall(DMB, CDomain);
+}
+
+// Based on http://ww.cl.cam.ac.uk/~pes20/cpp/cpp0xmappings.html
+void ARMTargetLowering::emitLeadingFence(IRBuilder<> &Builder,
+                                    AtomicOrdering Ord,
+                                    bool IsStore, bool IsLoad) const {
+  if (!getInsertFencesForAtomic())
+    return;
+
+  switch (Ord) {
+    case NotAtomic:
+    case Unordered:
+      llvm_unreachable("An unordered/not-atomic fence makes no sense");
+    case Monotonic:
+    case Acquire:
+      return; // Nothing to do
+    case SequentiallyConsistent:
+      if (!IsStore)
+        return; // Nothing to do
+      MakeDMB(Builder, ARM_MB::ISH);
+      return;
+    case Release:
+    case AcquireRelease:
+      if (Subtarget->isSwift())
+        MakeDMB(Builder, ARM_MB::ISHST);
+      else
+        MakeDMB(Builder, ARM_MB::ISH);
+      return;
+  }
+}
+
+void ARMTargetLowering::emitTrailingFence(IRBuilder<> &Builder,
+                                    AtomicOrdering Ord,
+                                    bool IsStore, bool IsLoad) const {
+  if (!getInsertFencesForAtomic())
+    return;
+
+  switch (Ord) {
+    case NotAtomic:
+    case Unordered:
+      llvm_unreachable("An unordered/not-atomic fence makes no sense");
+    case Monotonic:
+    case Release:
+      return; // Nothing to do
+    case Acquire:
+    case AcquireRelease:
+      // FIXME: Too conservative, an isb after a dependent branch is enough
+      // See http://www.cl.cam.ac.uk/~pes20/cpp/cpp0xmappings.html, confirmed in
+      // http://www0.cs.ucl.ac.uk/staff/j.alglave/papers/toplas14.pdf page 36,
+      // and hinted at by the ARM documentation section A3.8.3.
+    case SequentiallyConsistent:
+      MakeDMB(Builder, ARM_MB::ISH);
+      return;
+  }
+}
+
 bool ARMTargetLowering::shouldExpandAtomicInIR(Instruction *Inst) const {
   // Loads and stores less than 64-bits are already atomic; ones above that
   // are doomed anyway, so defer to the default libcall and blame the OS when