Index: llvm/lib/Target/PowerPC/P9InstrResources.td
===================================================================
--- llvm/lib/Target/PowerPC/P9InstrResources.td
+++ llvm/lib/Target/PowerPC/P9InstrResources.td
@@ -531,6 +531,7 @@
     (instregex "VEXTRACTU(B|H|W)$"),
     (instregex "VINSERT(B|H|W|D)$"),
     MFVSRLD,
+    MFVRLD,
     MTVSRWS,
     VBPERMQ,
     VCLZLSBB,
Index: llvm/lib/Target/PowerPC/PPCISelLowering.h
===================================================================
--- llvm/lib/Target/PowerPC/PPCISelLowering.h
+++ llvm/lib/Target/PowerPC/PPCISelLowering.h
@@ -192,6 +192,9 @@
       /// Direct move of 2 consective GPR to a VSX register.
       BUILD_FP128,
 
+      /// Extract bits from a float128
+      EXTRACT_FP128,
+
       /// Extract a subvector from signed integer vector and convert to FP.
       /// It is primarily used to convert a (widened) illegal integer vector
       /// type to a legal floating point vector type.
@@ -1086,6 +1089,7 @@
     SDValue combineSHL(SDNode *N, DAGCombinerInfo &DCI) const;
     SDValue combineSRA(SDNode *N, DAGCombinerInfo &DCI) const;
     SDValue combineSRL(SDNode *N, DAGCombinerInfo &DCI) const;
+    SDValue combineTRUNCATE(SDNode *N, DAGCombinerInfo &DCI) const;
 
     /// ConvertSETCCToSubtract - looks at SETCC that compares ints. It replaces
     /// SETCC with integer subtraction when (1) there is a legal way of doing it
Index: llvm/lib/Target/PowerPC/PPCISelLowering.cpp
===================================================================
--- llvm/lib/Target/PowerPC/PPCISelLowering.cpp
+++ llvm/lib/Target/PowerPC/PPCISelLowering.cpp
@@ -1076,8 +1076,9 @@
   setTargetDAGCombine(ISD::ZERO_EXTEND);
   setTargetDAGCombine(ISD::ANY_EXTEND);
 
+  setTargetDAGCombine(ISD::TRUNCATE);
+
   if (Subtarget.useCRBits()) {
-    setTargetDAGCombine(ISD::TRUNCATE);
     setTargetDAGCombine(ISD::SETCC);
     setTargetDAGCombine(ISD::SELECT_CC);
   }
@@ -1353,6 +1354,7 @@
   case PPCISD::QBFLT:           return "PPCISD::QBFLT";
   case PPCISD::QVLFSb:          return "PPCISD::QVLFSb";
   case PPCISD::BUILD_FP128:     return "PPCISD::BUILD_FP128";
+  case PPCISD::EXTRACT_FP128:   return "PPCISD::EXTRACT_FP128";
   }
   return nullptr;
 }
@@ -9633,6 +9635,9 @@
       return;
     Results.push_back(LowerFP_TO_INT(SDValue(N, 0), DAG, dl));
     return;
+  case ISD::BITCAST:
+    // Don't handle bitcast here.
+    return;
   }
 }
 
@@ -12462,6 +12467,7 @@
   case ISD::ANY_EXTEND:
     return DAGCombineExtBoolTrunc(N, DCI);
   case ISD::TRUNCATE:
+    return combineTRUNCATE(N, DCI);
   case ISD::SETCC:
   case ISD::SELECT_CC:
     return DAGCombineTruncBoolExt(N, DCI);
@@ -14121,6 +14127,51 @@
   return SDValue();
 }
 
+SDValue PPCTargetLowering::combineTRUNCATE(SDNode *N,
+                                           DAGCombinerInfo &DCI) const {
+  // If we are using CRBits then try that first.
+  if (Subtarget.useCRBits()) {
+    SDValue CRTruncValue = DAGCombineTruncBoolExt(N, DCI);
+
+    // Check if CRBits did anything and return that if it did.
+    if (CRTruncValue.getNode())
+      return CRTruncValue;
+  }
+
+  SDLoc dl(N);
+  const SDValue &Op0 = N->getOperand(0);
+  if (Op0.getValueType() == MVT::i128 && N->getValueType(0) == MVT::i64) {
+
+    EVT TCVT = MVT::i32;
+    // BITCAST feeding a TRUNCATE
+    if (Op0.getNode()->getOpcode() == ISD::BITCAST &&
+        Op0.getNode()->getOperand(0).getValueType() == MVT::f128) {
+
+      // Have a truncate fed by a bitcast of an f128.
+      return DCI.DAG.getNode(PPCISD::EXTRACT_FP128, dl, MVT::i64,
+                             Op0.getNode()->getOperand(0),
+                             DCI.DAG.getTargetConstant(0, dl, TCVT));
+    }
+
+    // BITCAST feeding SRL feeding TRUNCATE
+    if (Op0.getNode()->getOpcode() == ISD::SRL &&
+        Op0.getNode()->getOperand(0).getValueType() == MVT::i128 &&
+        Op0.getNode()->getConstantOperandVal(1) == 64 &&
+        Op0.getNode()->getOperand(0).getNode()->getOpcode() == ISD::BITCAST) {
+      SDNode *BitcastNode = Op0.getNode()->getOperand(0).getNode();
+
+      // Check if we are bitcasting from an f128
+      if (BitcastNode->getOperand(0).getValueType() == MVT::f128) {
+        return DCI.DAG.getNode(PPCISD::EXTRACT_FP128, dl, MVT::i64,
+                               BitcastNode->getOperand(0),
+                               DCI.DAG.getTargetConstant(64, dl, TCVT));
+      }
+    }
+  }
+
+  return SDValue();
+}
+
 bool PPCTargetLowering::mayBeEmittedAsTailCall(const CallInst *CI) const {
   // Only duplicate to increase tail-calls for the 64bit SysV ABIs.
   if (!Subtarget.isSVR4ABI() || !Subtarget.isPPC64())
Index: llvm/lib/Target/PowerPC/PPCInstrInfo.td
===================================================================
--- llvm/lib/Target/PowerPC/PPCInstrInfo.td
+++ llvm/lib/Target/PowerPC/PPCInstrInfo.td
@@ -225,6 +225,12 @@
                               SDTCisSameAs<1,2>]>,
                            []>;
 
+// Extract bits from a float128
+def PPCextract_fp128: SDNode<"PPCISD::EXTRACT_FP128",
+                             SDTypeProfile<1, 2,
+                               [SDTCisInt<0>, SDTCisFP<1>, SDTCisPtrTy<2>]>,
+                             []>;
+
 // These are target-independent nodes, but have target-specific formats.
 def callseq_start : SDNode<"ISD::CALLSEQ_START", SDT_PPCCallSeqStart,
                            [SDNPHasChain, SDNPOutGlue]>;
Index: llvm/lib/Target/PowerPC/PPCInstrVSX.td
===================================================================
--- llvm/lib/Target/PowerPC/PPCInstrVSX.td
+++ llvm/lib/Target/PowerPC/PPCInstrVSX.td
@@ -1528,6 +1528,10 @@
   def MFVSRLD: XX1_RS6_RD5_XO<31, 307, (outs g8rc:$rA), (ins vsrc:$XT),
                               "mfvsrld $rA, $XT", IIC_VecGeneral,
                               []>, Requires<[In64BitMode]>;
+  let isCodeGenOnly = 1 in
+  def MFVRLD: XX1_RS6_RD5_XO<31, 307, (outs g8rc:$rA), (ins vrrc:$XT),
+                              "mfvsrld $rA, $XT", IIC_VecGeneral,
+                              []>, Requires<[In64BitMode]>;
 
 } // IsISA3_0, HasDirectMove
 } // UseVSXReg = 1
@@ -3460,6 +3464,13 @@
   }
 }
 
+let Predicates = [IsISA3_0, HasP9Vector, HasDirectMove, IsLittleEndian] in {
+  def : Pat<(i64 (PPCextract_fp128 f128:$rA, 0)),
+            (i64 (MFVRD $rA))>;
+  def : Pat<(i64 (PPCextract_fp128 f128:$rA, 64)),
+            (i64 (MFVRLD $rA))>;
+}
+
 let Predicates = [HasP9Vector] in {
   let isPseudo = 1 in {
     let mayStore = 1 in {