Index: lib/Target/X86/X86InstrInfo.td
===================================================================
--- lib/Target/X86/X86InstrInfo.td
+++ lib/Target/X86/X86InstrInfo.td
@@ -1352,7 +1352,7 @@
                OpSize16, Requires<[Not64BitMode]>;
 }
 
-let Constraints = "$src = $dst", SchedRW = [WriteALU] in {
+let Constraints = "$src = $dst", SchedRW = [WriteBSWAP32] in {
 // This instruction is a consequence of BSWAP32r observing operand size. The
 // encoding is valid, but the behavior is undefined.
 let isCodeGenOnly = 1, ForceDisassemble = 1, hasSideEffects = 0 in
@@ -1363,6 +1363,7 @@
                  "bswap{l}\t$dst",
                  [(set GR32:$dst, (bswap GR32:$src))]>, OpSize32, TB;
 
+let SchedRW = [WriteBSWAP64] in
 def BSWAP64r : RI<0xC8, AddRegFrm, (outs GR64:$dst), (ins GR64:$src),
                   "bswap{q}\t$dst",
                   [(set GR64:$dst, (bswap GR64:$src))]>, TB;
Index: lib/Target/X86/X86SchedBroadwell.td
===================================================================
--- lib/Target/X86/X86SchedBroadwell.td
+++ lib/Target/X86/X86SchedBroadwell.td
@@ -110,7 +110,6 @@
 defm : BWWriteResPair<WriteADC,    [BWPort06], 1>; // Integer ALU + flags op.
 defm : BWWriteResPair<WriteIMul,   [BWPort1], 3>; // Integer multiplication.
 defm : BWWriteResPair<WriteIMul64, [BWPort1], 3>; // Integer 64-bit multiplication.
-
 defm : BWWriteResPair<WriteDiv8,   [BWPort0, BWDivider], 25, [1, 10]>;
 defm : BWWriteResPair<WriteDiv16,  [BWPort0, BWDivider], 25, [1, 10]>;
 defm : BWWriteResPair<WriteDiv32,  [BWPort0, BWDivider], 25, [1, 10]>;
@@ -120,6 +119,9 @@
 defm : BWWriteResPair<WriteIDiv32, [BWPort0, BWDivider], 25, [1, 10]>;
 defm : BWWriteResPair<WriteIDiv64, [BWPort0, BWDivider], 25, [1, 10]>;
 
+defm : BWWriteResPair<WriteBSWAP32,[BWPort15], 1>; //
+defm : BWWriteResPair<WriteBSWAP64,[BWPort06, BWPort15], 2, [1, 1], 2>; //
+
 defm : BWWriteResPair<WriteCRC32, [BWPort1],   3>;
 def : WriteRes<WriteIMulH, []> { let Latency = 3; } // Integer multiplication, high part.
 
@@ -699,20 +701,6 @@
 }
 def: InstRW<[BWWriteResGroup18], (instrs SFENCE)>;
 
-def BWWriteResGroup19 : SchedWriteRes<[BWPort06,BWPort15]> {
-  let Latency = 2;
-  let NumMicroOps = 2;
-  let ResourceCycles = [1,1];
-}
-def: InstRW<[BWWriteResGroup19], (instrs BSWAP64r)>;
-
-def BWWriteResGroup19_1 : SchedWriteRes<[BWPort15]> {
-  let Latency = 1;
-  let NumMicroOps = 1;
-  let ResourceCycles = [1];
-}
-def: InstRW<[BWWriteResGroup19_1], (instrs BSWAP32r)>;
-
 def BWWriteResGroup20 : SchedWriteRes<[BWPort06,BWPort0156]> {
   let Latency = 2;
   let NumMicroOps = 2;
Index: lib/Target/X86/X86SchedHaswell.td
===================================================================
--- lib/Target/X86/X86SchedHaswell.td
+++ lib/Target/X86/X86SchedHaswell.td
@@ -122,6 +122,10 @@
 defm : HWWriteResPair<WriteADC,    [HWPort06,HWPort0156], 2, [1,1], 2>;
 defm : HWWriteResPair<WriteIMul,   [HWPort1],   3>;
 defm : HWWriteResPair<WriteIMul64, [HWPort1],   3>;
+
+defm : HWWriteResPair<WriteBSWAP32,[HWPort15],   1>;
+defm : HWWriteResPair<WriteBSWAP64,[HWPort06, HWPort15], 2, [1,1], 2>;
+
 def  : WriteRes<WriteIMulH, []> { let Latency = 3; }
 defm : HWWriteResPair<WriteShift,  [HWPort06],  1>;
 defm : HWWriteResPair<WriteShiftDouble,  [HWPort06],  1>;
@@ -1149,20 +1153,6 @@
 }
 def: InstRW<[HWWriteResGroup33], (instregex "MMX_MOVDQ2Qrr")>;
 
-def HWWriteResGroup34 : SchedWriteRes<[HWPort06,HWPort15]> {
-  let Latency = 2;
-  let NumMicroOps = 2;
-  let ResourceCycles = [1,1];
-}
-def: InstRW<[HWWriteResGroup34], (instrs BSWAP64r)>;
-
-def HWWriteResGroup34_1 : SchedWriteRes<[HWPort15]> {
-  let Latency = 1;
-  let NumMicroOps = 1;
-  let ResourceCycles = [1];
-}
-def: InstRW<[HWWriteResGroup34_1], (instrs BSWAP32r)>;
-
 def HWWriteResGroup35 : SchedWriteRes<[HWPort06,HWPort0156]> {
   let Latency = 2;
   let NumMicroOps = 2;
Index: lib/Target/X86/X86SchedSandyBridge.td
===================================================================
--- lib/Target/X86/X86SchedSandyBridge.td
+++ lib/Target/X86/X86SchedSandyBridge.td
@@ -111,6 +111,9 @@
 defm : SBWriteResPair<WriteIMul,   [SBPort1],   3>;
 defm : SBWriteResPair<WriteIMul64, [SBPort1],   3>;
 
+defm : SBWriteResPair<WriteBSWAP32,[SBPort1], 1>;
+defm : SBWriteResPair<WriteBSWAP64,[SBPort1,SBPort05], 2, [1,1], 2>;
+
 defm : SBWriteResPair<WriteDiv8,   [SBPort0, SBDivider], 25, [1, 10]>;
 defm : SBWriteResPair<WriteDiv16,  [SBPort0, SBDivider], 25, [1, 10]>;
 defm : SBWriteResPair<WriteDiv32,  [SBPort0, SBDivider], 25, [1, 10]>;
@@ -619,20 +622,6 @@
 def: InstRW<[SBWriteResGroup15], (instrs CWD,
                                          FNSTSW16r)>;
 
-def SBWriteResGroup16 : SchedWriteRes<[SBPort1,SBPort05]> {
-  let Latency = 2;
-  let NumMicroOps = 2;
-  let ResourceCycles = [1,1];
-}
-def: InstRW<[SBWriteResGroup16], (instrs BSWAP64r)>;
-
-def SBWriteResGroup16_1 : SchedWriteRes<[SBPort1]> {
-  let Latency = 1;
-  let NumMicroOps = 1;
-  let ResourceCycles = [1];
-}
-def: InstRW<[SBWriteResGroup16_1], (instrs BSWAP32r)>;
-
 def SBWriteResGroup18 : SchedWriteRes<[SBPort5,SBPort015]> {
   let Latency = 2;
   let NumMicroOps = 2;
Index: lib/Target/X86/X86SchedSkylakeClient.td
===================================================================
--- lib/Target/X86/X86SchedSkylakeClient.td
+++ lib/Target/X86/X86SchedSkylakeClient.td
@@ -110,6 +110,9 @@
 defm : SKLWriteResPair<WriteIMul,   [SKLPort1],    3>; // Integer multiplication.
 defm : SKLWriteResPair<WriteIMul64, [SKLPort1],    3>; // Integer 64-bit multiplication.
 
+defm : SKLWriteResPair<WriteBSWAP32,[SKLPort15],   1>; //
+defm : SKLWriteResPair<WriteBSWAP64,[SKLPort06, SKLPort15], 2, [1,1], 2>; //
+
 defm : SKLWriteResPair<WriteDiv8,   [SKLPort0, SKLDivider], 25, [1,10], 1, 4>;
 defm : SKLWriteResPair<WriteDiv16,  [SKLPort0, SKLDivider], 25, [1,10], 1, 4>;
 defm : SKLWriteResPair<WriteDiv32,  [SKLPort0, SKLDivider], 25, [1,10], 1, 4>;
@@ -698,20 +701,6 @@
 }
 def: InstRW<[SKLWriteResGroup21], (instrs SFENCE)>;
 
-def SKLWriteResGroup22 : SchedWriteRes<[SKLPort06,SKLPort15]> {
-  let Latency = 2;
-  let NumMicroOps = 2;
-  let ResourceCycles = [1,1];
-}
-def: InstRW<[SKLWriteResGroup22], (instrs BSWAP64r)>;
-
-def SKLWriteResGroup22_1 : SchedWriteRes<[SKLPort15]> {
-  let Latency = 1;
-  let NumMicroOps = 1;
-  let ResourceCycles = [1];
-}
-def: InstRW<[SKLWriteResGroup22_1], (instrs BSWAP32r)>;
-
 def SKLWriteResGroup23 : SchedWriteRes<[SKLPort06,SKLPort0156]> {
   let Latency = 2;
   let NumMicroOps = 2;
Index: lib/Target/X86/X86SchedSkylakeServer.td
===================================================================
--- lib/Target/X86/X86SchedSkylakeServer.td
+++ lib/Target/X86/X86SchedSkylakeServer.td
@@ -110,6 +110,9 @@
 defm : SKXWriteResPair<WriteIMul,   [SKXPort1],    3>; // Integer multiplication.
 defm : SKXWriteResPair<WriteIMul64, [SKXPort1],    3>; // Integer 64-bit multiplication.
 
+defm : SKXWriteResPair<WriteBSWAP32,[SKXPort15],   1>; //
+defm : SKXWriteResPair<WriteBSWAP64,[SKXPort06, SKXPort15], 2, [1,1], 2>; //
+
 defm : SKXWriteResPair<WriteDiv8,   [SKXPort0, SKXDivider], 25, [1,10], 1, 4>;
 defm : SKXWriteResPair<WriteDiv16,  [SKXPort0, SKXDivider], 25, [1,10], 1, 4>;
 defm : SKXWriteResPair<WriteDiv32,  [SKXPort0, SKXDivider], 25, [1,10], 1, 4>;
@@ -722,20 +725,6 @@
 }
 def: InstRW<[SKXWriteResGroup21], (instrs SFENCE)>;
 
-def SKXWriteResGroup22 : SchedWriteRes<[SKXPort06,SKXPort15]> {
-  let Latency = 2;
-  let NumMicroOps = 2;
-  let ResourceCycles = [1,1];
-}
-def: InstRW<[SKXWriteResGroup22], (instrs BSWAP64r)>;
-
-def SKXWriteResGroup22_1 : SchedWriteRes<[SKXPort15]> {
-  let Latency = 1;
-  let NumMicroOps = 1;
-  let ResourceCycles = [1];
-}
-def: InstRW<[SKXWriteResGroup22_1], (instrs BSWAP32r)>;
-
 def SKXWriteResGroup23 : SchedWriteRes<[SKXPort06,SKXPort0156]> {
   let Latency = 2;
   let NumMicroOps = 2;
Index: lib/Target/X86/X86Schedule.td
===================================================================
--- lib/Target/X86/X86Schedule.td
+++ lib/Target/X86/X86Schedule.td
@@ -118,6 +118,9 @@
 def  WriteIMulH  : SchedWrite;        // Integer multiplication, high part.
 def  WriteLEA    : SchedWrite;        // LEA instructions can't fold loads.
 
+defm WriteBSWAP32: X86SchedWritePair; // Byte Order (Endiannes) Swap
+defm WriteBSWAP64: X86SchedWritePair; // Byte Order (Endiannes) Swap
+
 // Integer division.
 defm WriteDiv8   : X86SchedWritePair;
 defm WriteDiv16  : X86SchedWritePair;
Index: lib/Target/X86/X86ScheduleAtom.td
===================================================================
--- lib/Target/X86/X86ScheduleAtom.td
+++ lib/Target/X86/X86ScheduleAtom.td
@@ -81,6 +81,9 @@
 defm : AtomWriteResPair<WriteIMul,   [AtomPort01], [AtomPort01],  7,  7,  [7],  [7]>;
 defm : AtomWriteResPair<WriteIMul64, [AtomPort01], [AtomPort01], 12, 12, [12], [12]>;
 
+defm : AtomWriteResPair<WriteBSWAP32,    [AtomPort0], [AtomPort0]>;
+defm : AtomWriteResPair<WriteBSWAP64,    [AtomPort0], [AtomPort0]>;
+
 defm : AtomWriteResPair<WriteDiv8,   [AtomPort01], [AtomPort01], 50, 68, [50], [68]>;
 defm : AtomWriteResPair<WriteDiv16,  [AtomPort01], [AtomPort01], 50, 50, [50], [50]>;
 defm : AtomWriteResPair<WriteDiv32,  [AtomPort01], [AtomPort01], 50, 50, [50], [50]>;
@@ -489,7 +492,6 @@
   let ResourceCycles = [1];
 }
 def : InstRW<[AtomWrite0_1], (instrs FXAM, LD_Frr,
-                                     BSWAP32r, BSWAP64r,
                                      MOVSX64rr32)>;
 def : SchedAlias<WriteALURMW, AtomWrite0_1>;
 def : SchedAlias<WriteADCRMW, AtomWrite0_1>;
Index: lib/Target/X86/X86ScheduleBtVer2.td
===================================================================
--- lib/Target/X86/X86ScheduleBtVer2.td
+++ lib/Target/X86/X86ScheduleBtVer2.td
@@ -168,6 +168,9 @@
 defm : JWriteResIntPair<WriteIMul64, [JALU1, JMul], 6, [1, 4], 2>; // i64 multiplication
 defm : X86WriteRes<WriteIMulH,       [JALU1], 6, [4], 1>;
 
+defm : JWriteResIntPair<WriteBSWAP32,[JALU01], 1>;
+defm : JWriteResIntPair<WriteBSWAP64,[JALU01], 1>;
+
 defm : JWriteResIntPair<WriteDiv8,   [JALU1, JDiv], 12, [1, 12], 1>;
 defm : JWriteResIntPair<WriteDiv16,  [JALU1, JDiv], 17, [1, 17], 2>;
 defm : JWriteResIntPair<WriteDiv32,  [JALU1, JDiv], 25, [1, 25], 2>;
Index: lib/Target/X86/X86ScheduleSLM.td
===================================================================
--- lib/Target/X86/X86ScheduleSLM.td
+++ lib/Target/X86/X86ScheduleSLM.td
@@ -97,6 +97,10 @@
 defm : SLMWriteResPair<WriteADC,    [SLM_IEC_RSV01], 1>;
 defm : SLMWriteResPair<WriteIMul,   [SLM_IEC_RSV1],  3>;
 defm : SLMWriteResPair<WriteIMul64, [SLM_IEC_RSV1],  3>;
+
+defm : SLMWriteResPair<WriteBSWAP32,[SLM_IEC_RSV01], 1>;
+defm : SLMWriteResPair<WriteBSWAP64,[SLM_IEC_RSV01], 1>;
+
 defm : SLMWriteResPair<WriteShift,  [SLM_IEC_RSV0],  1>;
 defm : SLMWriteResPair<WriteShiftDouble,  [SLM_IEC_RSV0],  1>;
 defm : SLMWriteResPair<WriteJump,   [SLM_IEC_RSV1],  1>;
Index: lib/Target/X86/X86ScheduleZnver1.td
===================================================================
--- lib/Target/X86/X86ScheduleZnver1.td
+++ lib/Target/X86/X86ScheduleZnver1.td
@@ -179,6 +179,10 @@
 defm : ZnWriteResPair<WriteADC,   [ZnALU], 1>;
 defm : ZnWriteResPair<WriteIMul,   [ZnALU1, ZnMultiplier], 4>;
 defm : ZnWriteResPair<WriteIMul64, [ZnALU1, ZnMultiplier], 4, [1,1], 2>;
+
+defm : ZnWriteResPair<WriteBSWAP32,[ZnALU], 1, [4]>;
+defm : ZnWriteResPair<WriteBSWAP64,[ZnALU], 1, [4]>;
+
 defm : ZnWriteResPair<WriteShift, [ZnALU], 1>;
 defm : ZnWriteResPair<WriteShiftDouble, [ZnALU], 1>;
 defm : ZnWriteResPair<WriteJump,  [ZnALU], 1>;
@@ -537,12 +541,6 @@
 //LAHF
 def : InstRW<[WriteMicrocoded], (instrs LAHF)>;
 
-// BSWAP.
-def ZnWriteBSwap : SchedWriteRes<[ZnALU]> {
-  let ResourceCycles = [4];
-}
-def : InstRW<[ZnWriteBSwap], (instregex "BSWAP")>;
-
 // MOVBE.
 // r,m.
 def ZnWriteMOVBE : SchedWriteRes<[ZnAGU, ZnALU]> {
Index: utils/TableGen/CodeGenSchedule.h
===================================================================
--- utils/TableGen/CodeGenSchedule.h
+++ utils/TableGen/CodeGenSchedule.h
@@ -443,6 +443,8 @@
 
   void collectSchedClasses();
 
+  void checkSchedClasses();
+
   void collectRetireControlUnits();
 
   void collectRegisterFiles();
Index: utils/TableGen/CodeGenSchedule.cpp
===================================================================
--- utils/TableGen/CodeGenSchedule.cpp
+++ utils/TableGen/CodeGenSchedule.cpp
@@ -21,6 +21,7 @@
 #include "llvm/ADT/SmallSet.h"
 #include "llvm/ADT/SmallVector.h"
 #include "llvm/Support/Casting.h"
+#include "llvm/Support/CommandLine.h"
 #include "llvm/Support/Debug.h"
 #include "llvm/Support/Regex.h"
 #include "llvm/Support/raw_ostream.h"
@@ -33,6 +34,16 @@
 
 #define DEBUG_TYPE "subtarget-emitter"
 
+#ifdef EXPENSIVE_CHECKS
+// FIXME: TableGen is failed iff EXPENSIVE_CHECKS defined
+static constexpr bool OptCheckSchedClasses = true;
+#else
+// FIXME: the default value should be false
+static cl::opt<bool> OptCheckSchedClasses(
+    "check-sched-class-table", cl::init(true), cl::Hidden,
+    cl::desc("Check sched class table on different types of inconsistencies"));
+#endif
+
 #ifndef NDEBUG
 static void dumpIdxVec(ArrayRef<unsigned> V) {
   for (unsigned Idx : V)
@@ -223,6 +234,7 @@
   collectOptionalProcessorInfo();
 
   checkCompleteness();
+  checkSchedClasses();
 }
 
 void CodeGenSchedModels::collectRetireControlUnits() {
@@ -699,6 +711,89 @@
   }
 }
 
+void CodeGenSchedModels::checkSchedClasses() {
+  if (!OptCheckSchedClasses)
+    return;
+
+  std::string str;
+  raw_string_ostream OS(str);
+
+  // Check each instruction for each model to see if its overridden.
+  // Iff YES it's a candidate for separate Sched Class
+  for (const CodeGenInstruction *Inst : Target.getInstructionsByEnumValue()) {
+    StringRef InstName = Inst->TheDef->getName();
+    unsigned SCIdx = getSchedClassIdx(*Inst);
+    if (!SCIdx)
+      continue;
+    CodeGenSchedClass &SC = getSchedClass(SCIdx);
+    if (SC.Writes.empty())
+      continue;
+    const RecVec &RWDefs = SchedClasses[SCIdx].InstRWs;
+    if (RWDefs.empty())
+      continue;
+    // FIXME: what should be threshold here?
+    if (RWDefs.size() > (ProcModels.size() / 2)) {
+      // FIXME: this dump hangs the execution !!!
+      // SC.dump(&Target.getSchedModels());
+      OS << "SchedRW machine model for inst '" << InstName << "' (";
+      for (auto I : SC.Writes)
+        OS << " " << SchedWrites[I].Name;
+      for (auto I : SC.Reads)
+        OS << " " << SchedReads[I].Name;
+      OS << " ) should be removed because it's overriden " << RWDefs.size()
+         << " times out of " << ProcModels.size() << " models:\n\t";
+      for (Record *RWDef : RWDefs)
+        OS << " " << getProcModel(RWDef->getValueAsDef("SchedModel")).ModelName;
+      PrintWarning(OS.str());
+      str.clear();
+    }
+
+    // TODO: here we should check latency/uop in SC vs. RWDef. Maybe we
+    // should do it iff RWDefs.size() == 1 only.
+    // Iff latnecy/uop are the same then warn about unnecessary redefine.
+    if (RWDefs.size()) {
+      for (Record *RWDef : RWDefs) {
+        IdxVec Writes;
+        IdxVec Reads;
+        findRWs(RWDef->getValueAsListOfDefs("OperandReadWrites"), Writes,
+                Reads);
+
+        if ((Writes.size() == SC.Writes.size()) &&
+            (Reads.size() == SC.Reads.size())) {
+          // TODO: do we need sorting Write & Reads?
+          for (unsigned I = 0; I < SC.Writes.size(); I++) {
+            if (!SchedWrites[SC.Writes[I]].TheDef ||
+                !SchedWrites[Writes[I]].TheDef)
+              continue;
+            const RecordVal *R =
+                SchedWrites[SC.Writes[I]].TheDef->getValue("Latency");
+            // FIXME: We should deal with default Latency here
+            if (!R || !R->getValue())
+              continue;
+            auto SCLat =
+                SchedWrites[SC.Writes[I]].TheDef->getValueAsInt("Latency");
+            auto SCuOp =
+                SchedWrites[SC.Writes[I]].TheDef->getValueAsInt("NumMicroOps");
+            auto Lat = SchedWrites[Writes[I]].TheDef->getValueAsInt("Latency");
+            auto uOp =
+                SchedWrites[Writes[I]].TheDef->getValueAsInt("NumMicroOps");
+            if ((SCLat == Lat) && (SCuOp == uOp))
+              OS << "Overridden verion of inst '" << InstName
+                 << "' has the same latency & uOp values as the original one "
+                    "for model '"
+                 << getProcModel(RWDef->getValueAsDef("SchedModel")).ModelName
+                 << "'\n";
+          }
+          if (!str.empty()) {
+            PrintWarning(OS.str());
+            str.clear();
+          }
+        }
+      }
+    }
+  }
+}
+
 // Get the SchedClass index for an instruction.
 unsigned
 CodeGenSchedModels::getSchedClassIdx(const CodeGenInstruction &Inst) const {