[Mips][FastISel] Fix handling of icmp with i1 type.

[draganm]

Summary

The Mips FastISel back-end does not extend i1 values while lowering icmp. Ensure that we bail into DAG ISel when handling this case.

[atanasyan]

LGTM

[petarj]

test/CodeGen/Mips/Fast-ISel/sel1.ll will fail with this change. Double check.

[draganm]

Replaced the usage of icmp i1 with xor i1 within test/CodeGen/Mips/Fast-ISel/sel1.ll . Now the test won't trigger fast-isel-abort.

llvm/trunk/lib/Target/Mips/MipsFastISel.cpp

 }
 
 unsigned MipsFastISel::getRegEnsuringSimpleIntegerWidening(const Value *V,
                                                            bool IsUnsigned) {
   unsigned VReg = getRegForValue(V);
   if (VReg == 0)
     return 0;
   MVT VMVT = TLI.getValueType(DL, V->getType(), true).getSimpleVT();
+
+  if (VMVT == MVT::i1)
+    return 0;
+
   if ((VMVT == MVT::i8) || (VMVT == MVT::i16)) {
     unsigned TempReg = createResultReg(&Mips::GPR32RegClass);
     if (!emitIntExt(VMVT, VReg, MVT::i32, TempReg, IsUnsigned))
       return 0;
     VReg = TempReg;
   }
   return VReg;
 }

llvm/trunk/test/CodeGen/Mips/Fast-ISel/icmpi1.ll

+; RUN: llc -march=mipsel -relocation-model=pic -O0 -fast-isel=true -mcpu=mips32r2 \
+; RUN:     < %s -verify-machineinstrs | FileCheck %s
+
+
+define zeroext i1 @foo(i8* nocapture readonly) {
+; CHECK-LABEL: foo
+; CHECK:         lbu $[[REG0:[0-9]+]], 0($4)
+; CHECK-NEXT:    xori $[[REG1:[0-9]+]], $[[REG0]], 1
+; CHECK-NEXT:    andi $2, $[[REG1]], 1
+  %2 = load i8, i8* %0, align 1
+  %3 = trunc i8 %2 to i1
+  %4 = icmp ne i1 %3, true
+  ret i1 %4
+}

llvm/trunk/test/CodeGen/Mips/Fast-ISel/sel1.ll

 ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
 ; RUN: llc < %s -mtriple=mipsel-linux-gnu -mcpu=mips32r2 -O2 -relocation-model=pic \
 ; RUN:          -fast-isel -fast-isel-abort=1 | FileCheck %s
 
 ; FIXME: The first xor instruction is redundant.
 define i1 @sel_i1(i1 %j, i1 %k, i1 %l) {
 ; CHECK-LABEL: sel_i1:
 ; CHECK:       # %bb.0: # %entry
 ; CHECK-NEXT:    xor $1, $4, $zero
-; CHECK-NEXT:    sltu $1, $zero, $1
 ; CHECK-NEXT:    andi $1, $1, 1
 ; CHECK-NEXT:    movn $6, $5, $1
 ; CHECK-NEXT:    jr $ra
 ; CHECK-NEXT:    move $2, $6
 entry:
-  %cond = icmp ne i1 %j, 0
+  %cond = xor i1 %j, false
   %res = select i1 %cond, i1 %k, i1 %l
   ret i1 %res
 }
 
 ; FIXME: The seb $X, $zero and xor .., .., $x   instructions are redundant.
 define i8 @sel_i8(i8 %j, i8 %k, i8 %l) {
 ; CHECK-LABEL: sel_i8:
 ; CHECK:       # %bb.0: # %entry