Index: include/llvm/CodeGen/MachineInstr.h =================================================================== --- include/llvm/CodeGen/MachineInstr.h +++ include/llvm/CodeGen/MachineInstr.h @@ -244,7 +244,15 @@ /// DebugLoc getDebugLoc() const { return debugLoc; } - /// getDebugVariable() - Return the debug variable referenced by + /// \brief Return the complex address expression referenced by + /// this DBG_VALUE instruction. + DIExpression getDebugExpression() const { + assert(isDebugValue() && "not a DBG_VALUE"); + const MDNode *Expr = getOperand(getNumOperands() - 2).getMetadata(); + return DIExpression(Expr); + } + + /// \brief Return the debug variable referenced by /// this DBG_VALUE instruction. DIVariable getDebugVariable() const { assert(isDebugValue() && "not a DBG_VALUE"); Index: include/llvm/CodeGen/MachineInstrBuilder.h =================================================================== --- include/llvm/CodeGen/MachineInstrBuilder.h +++ include/llvm/CodeGen/MachineInstrBuilder.h @@ -351,18 +351,21 @@ bool IsIndirect, unsigned Reg, unsigned Offset, - const MDNode *MD) { + const MDNode *Expr, + const MDNode *Variable) { if (IsIndirect) return BuildMI(MF, DL, MCID) .addReg(Reg, RegState::Debug) .addImm(Offset) - .addMetadata(MD); + .addMetadata(Expr) + .addMetadata(Variable); else { assert(Offset == 0 && "A direct address cannot have an offset."); return BuildMI(MF, DL, MCID) .addReg(Reg, RegState::Debug) .addReg(0U, RegState::Debug) - .addMetadata(MD); + .addMetadata(Expr) + .addMetadata(Variable); } } @@ -377,9 +380,12 @@ bool IsIndirect, unsigned Reg, unsigned Offset, - const MDNode *MD) { + const MDNode *Expr, + const MDNode *Variable) { + MachineFunction &MF = *BB.getParent(); - MachineInstr *MI = BuildMI(MF, DL, MCID, IsIndirect, Reg, Offset, MD); + MachineInstr *MI = + BuildMI(MF, DL, MCID, IsIndirect, Reg, Offset, Expr, Variable); BB.insert(I, MI); return MachineInstrBuilder(MF, MI); } Index: include/llvm/CodeGen/MachineModuleInfo.h =================================================================== --- include/llvm/CodeGen/MachineModuleInfo.h +++ include/llvm/CodeGen/MachineModuleInfo.h @@ -165,6 +165,7 @@ static char ID; // Pass identification, replacement for typeid struct VariableDbgInfo { + TrackingVH Expr; TrackingVH Var; unsigned Slot; DebugLoc Loc; @@ -390,8 +391,9 @@ /// setVariableDbgInfo - Collect information used to emit debugging /// information of a variable. - void setVariableDbgInfo(MDNode *N, unsigned Slot, DebugLoc Loc) { - VariableDbgInfo Info = { N, Slot, Loc }; + void setVariableDbgInfo(MDNode *Expr, MDNode *Var, + unsigned Slot, DebugLoc Loc) { + VariableDbgInfo Info = { Expr, Var, Slot, Loc }; VariableDbgInfos.push_back(std::move(Info)); } Index: include/llvm/CodeGen/SelectionDAG.h =================================================================== --- include/llvm/CodeGen/SelectionDAG.h +++ include/llvm/CodeGen/SelectionDAG.h @@ -984,15 +984,19 @@ /// getDbgValue - Creates a SDDbgValue node. /// - SDDbgValue *getDbgValue(MDNode *MDPtr, SDNode *N, unsigned R, + /// SDNode + SDDbgValue *getDbgValue(MDNode *Expr, MDNode *Var, SDNode *N, unsigned R, bool IsIndirect, uint64_t Off, DebugLoc DL, unsigned O); - /// Constant. - SDDbgValue *getConstantDbgValue(MDNode *MDPtr, const Value *C, uint64_t Off, - DebugLoc DL, unsigned O); - /// Frame index. - SDDbgValue *getFrameIndexDbgValue(MDNode *MDPtr, unsigned FI, uint64_t Off, - DebugLoc DL, unsigned O); + + /// Constant + SDDbgValue *getConstantDbgValue(MDNode *Expr, MDNode *Var, const Value *C, + uint64_t Off, DebugLoc DL, unsigned O); + + /// FrameIndex + SDDbgValue *getFrameIndexDbgValue(MDNode *Expr, MDNode *Var, + unsigned FI, uint64_t Off, + DebugLoc DL, unsigned O); /// RemoveDeadNode - Remove the specified node from the system. If any of its /// operands then becomes dead, remove them as well. Inform UpdateListener Index: include/llvm/IR/DIBuilder.h =================================================================== --- include/llvm/IR/DIBuilder.h +++ include/llvm/IR/DIBuilder.h @@ -544,32 +544,22 @@ unsigned ArgNo = 0); - /// createComplexVariable - Create a new descriptor for the specified + /// createExpression - Create an empty DIExpression. + DIExpression createExpression(); + + /// createExpression - Create a new descriptor for the specified /// variable which has a complex address expression for its address. - /// @param Tag Dwarf TAG. Usually DW_TAG_auto_variable or - /// DW_TAG_arg_variable. - /// @param Scope Variable scope. - /// @param Name Variable name. - /// @param F File where this variable is defined. - /// @param LineNo Line number. - /// @param Ty Variable Type /// @param Addr An array of complex address operations. - /// @param ArgNo If this variable is an argument then this argument's - /// number. 1 indicates 1st argument. - DIVariable createComplexVariable(unsigned Tag, DIDescriptor Scope, - StringRef Name, DIFile F, unsigned LineNo, - DITypeRef Ty, ArrayRef Addr, - unsigned ArgNo = 0); + DIExpression createExpression(ArrayRef Addr); - /// createVariablePiece - Create a descriptor to describe one part + + /// createPieceExpression - Create a descriptor to describe one part /// of aggregate variable that is fragmented across multiple Values. /// - /// @param Variable Variable that is partially represented by this. /// @param OffsetInBytes Offset of the piece in bytes. /// @param SizeInBytes Size of the piece in bytes. - DIVariable createVariablePiece(DIVariable Variable, - unsigned OffsetInBytes, - unsigned SizeInBytes); + DIExpression createPieceExpression(unsigned OffsetInBytes, + unsigned SizeInBytes); /// createFunction - Create a new descriptor for the specified subprogram. /// See comments in DISubprogram for descriptions of these fields. @@ -702,34 +692,42 @@ /// insertDeclare - Insert a new llvm.dbg.declare intrinsic call. /// @param Storage llvm::Value of the variable + /// @param Expr A complex location expression. /// @param VarInfo Variable's debug info descriptor. /// @param InsertAtEnd Location for the new intrinsic. - Instruction *insertDeclare(llvm::Value *Storage, DIVariable VarInfo, + Instruction *insertDeclare(llvm::Value *Storage, + DIExpression Expr, DIVariable VarInfo, BasicBlock *InsertAtEnd); /// insertDeclare - Insert a new llvm.dbg.declare intrinsic call. /// @param Storage llvm::Value of the variable + /// @param Expr A complex location expression. /// @param VarInfo Variable's debug info descriptor. /// @param InsertBefore Location for the new intrinsic. - Instruction *insertDeclare(llvm::Value *Storage, DIVariable VarInfo, + Instruction *insertDeclare(llvm::Value *Storage, + DIExpression Expr, DIVariable VarInfo, Instruction *InsertBefore); /// insertDbgValueIntrinsic - Insert a new llvm.dbg.value intrinsic call. /// @param Val llvm::Value of the variable /// @param Offset Offset + /// @param Expr A complex location expression. /// @param VarInfo Variable's debug info descriptor. /// @param InsertAtEnd Location for the new intrinsic. Instruction *insertDbgValueIntrinsic(llvm::Value *Val, uint64_t Offset, + DIExpression Expr, DIVariable VarInfo, BasicBlock *InsertAtEnd); /// insertDbgValueIntrinsic - Insert a new llvm.dbg.value intrinsic call. /// @param Val llvm::Value of the variable /// @param Offset Offset + /// @param Expr A complex location expression. /// @param VarInfo Variable's debug info descriptor. /// @param InsertBefore Location for the new intrinsic. Instruction *insertDbgValueIntrinsic(llvm::Value *Val, uint64_t Offset, + DIExpression Expr, DIVariable VarInfo, Instruction *InsertBefore); Index: include/llvm/IR/DebugInfo.h =================================================================== --- include/llvm/IR/DebugInfo.h +++ include/llvm/IR/DebugInfo.h @@ -701,20 +701,6 @@ /// Verify - Verify that a variable descriptor is well formed. bool Verify() const; - /// HasComplexAddr - Return true if the variable has a complex address. - bool hasComplexAddress() const { return getNumAddrElements() > 0; } - - /// \brief Return the size of this variable's complex address or - /// zero if there is none. - unsigned getNumAddrElements() const { - if (DbgNode->getNumOperands() < 9) - return 0; - return getDescriptorField(8)->getNumOperands(); - } - - /// \brief return the Idx'th complex address element. - uint64_t getAddrElement(unsigned Idx) const; - /// isBlockByrefVariable - Return true if the variable was declared as /// a "__block" variable (Apple Blocks). bool isBlockByrefVariable(const DITypeIdentifierMap &Map) const { @@ -725,6 +711,32 @@ /// information for an inlined function arguments. bool isInlinedFnArgument(const Function *CurFn); + /// Return the size reported by the variable's type. + unsigned getSizeInBits(const DITypeIdentifierMap &Map); + + void printExtendedName(raw_ostream &OS) const; +}; + +/// DIExpression - A complex location expression. +class DIExpression : public DIDescriptor { + friend class DIDescriptor; + void printInternal(raw_ostream &OS) const; + +public: + explicit DIExpression(const MDNode *N = nullptr) : DIDescriptor(N) {} + + /// Verify - Verify that a variable descriptor is well formed. + bool Verify() const; + + /// \brief Return the size of this variable's complex address or + /// zero if there is none. + unsigned getNumElements() const { + return DbgNode ? DbgNode->getNumOperands() : 0; + } + + /// \brief return the Idx'th complex address element. + uint64_t getElement(unsigned Idx) const; + /// isVariablePiece - Return whether this is a piece of an aggregate /// variable. bool isVariablePiece() const; @@ -732,11 +744,6 @@ uint64_t getPieceOffset() const; /// getPieceSize - Return the size of this piece in bytes. uint64_t getPieceSize() const; - - /// Return the size reported by the variable's type. - unsigned getSizeInBits(const DITypeIdentifierMap &Map); - - void printExtendedName(raw_ostream &OS) const; }; /// DILocation - This object holds location information. This object @@ -853,9 +860,6 @@ /// cleanseInlinedVariable - Remove inlined scope from the variable. DIVariable cleanseInlinedVariable(MDNode *DV, LLVMContext &VMContext); -/// getEntireVariable - Remove OpPiece exprs from the variable. -DIVariable getEntireVariable(DIVariable DV); - /// Construct DITypeIdentifierMap by going through retained types of each CU. DITypeIdentifierMap generateDITypeIdentifierMap(const NamedMDNode *CU_Nodes); Index: include/llvm/IR/IntrinsicInst.h =================================================================== --- include/llvm/IR/IntrinsicInst.h +++ include/llvm/IR/IntrinsicInst.h @@ -81,7 +81,8 @@ class DbgDeclareInst : public DbgInfoIntrinsic { public: Value *getAddress() const; - MDNode *getVariable() const { return cast(getArgOperand(1)); } + MDNode *getExpression() const { return cast(getArgOperand(1)); } + MDNode *getVariable() const { return cast(getArgOperand(2)); } // Methods for support type inquiry through isa, cast, and dyn_cast: static inline bool classof(const IntrinsicInst *I) { @@ -102,7 +103,8 @@ return cast( const_cast(getArgOperand(1)))->getZExtValue(); } - MDNode *getVariable() const { return cast(getArgOperand(2)); } + MDNode *getExpression() const { return cast(getArgOperand(2)); } + MDNode *getVariable() const { return cast(getArgOperand(3)); } // Methods for support type inquiry through isa, cast, and dyn_cast: static inline bool classof(const IntrinsicInst *I) { Index: include/llvm/IR/Intrinsics.td =================================================================== --- include/llvm/IR/Intrinsics.td +++ include/llvm/IR/Intrinsics.td @@ -373,9 +373,12 @@ // places. let Properties = [IntrNoMem] in { def int_dbg_declare : Intrinsic<[], - [llvm_metadata_ty, llvm_metadata_ty]>; + [llvm_metadata_ty, + llvm_metadata_ty, + llvm_metadata_ty]>; def int_dbg_value : Intrinsic<[], [llvm_metadata_ty, llvm_i64_ty, + llvm_metadata_ty, llvm_metadata_ty]>; } Index: lib/CodeGen/AsmPrinter/AsmPrinter.cpp =================================================================== --- lib/CodeGen/AsmPrinter/AsmPrinter.cpp +++ lib/CodeGen/AsmPrinter/AsmPrinter.cpp @@ -608,24 +608,26 @@ /// of DBG_VALUE, returning true if it was able to do so. A false return /// means the target will need to handle MI in EmitInstruction. static bool emitDebugValueComment(const MachineInstr *MI, AsmPrinter &AP) { - // This code handles only the 3-operand target-independent form. - if (MI->getNumOperands() != 3) + // This code handles only the 4-operand target-independent form. + if (MI->getNumOperands() != 4) return false; SmallString<128> Str; raw_svector_ostream OS(Str); OS << "DEBUG_VALUE: "; - DIVariable V(MI->getOperand(2).getMetadata()); + DIVariable V = MI->getDebugVariable(); if (V.getContext().isSubprogram()) { StringRef Name = DISubprogram(V.getContext()).getDisplayName(); if (!Name.empty()) OS << Name << ":"; } OS << V.getName(); - if (V.isVariablePiece()) - OS << " [piece offset=" << V.getPieceOffset() - << " size="<getDebugExpression(); + if (Expr.isVariablePiece()) + OS << " [piece offset=" << Expr.getPieceOffset() + << " size="<isIdenticalTo(&MI)) { @@ -193,7 +193,7 @@ // Use the base variable (without any DW_OP_piece expressions) // as index into History. The full variables including the // piece expressions are attached to the MI. - DIVariable Var = getEntireVariable(MI.getDebugVariable()); + DIVariable Var = MI.getDebugVariable(); if (unsigned PrevReg = Result.getRegisterForVar(Var)) dropRegDescribedVar(RegVars, PrevReg, Var); Index: lib/CodeGen/AsmPrinter/DebugLocEntry.h =================================================================== --- lib/CodeGen/AsmPrinter/DebugLocEntry.h +++ lib/CodeGen/AsmPrinter/DebugLocEntry.h @@ -26,22 +26,25 @@ public: /// A single location or constant. struct Value { - Value(const MDNode *Var, int64_t i) - : Variable(Var), EntryKind(E_Integer) { + Value(const MDNode *Expr, const MDNode *Var, int64_t i) + : Expression(Expr), Variable(Var), EntryKind(E_Integer) { Constant.Int = i; } - Value(const MDNode *Var, const ConstantFP *CFP) - : Variable(Var), EntryKind(E_ConstantFP) { + Value(const MDNode *Expr, const MDNode *Var, const ConstantFP *CFP) + : Expression(Expr), Variable(Var), EntryKind(E_ConstantFP) { Constant.CFP = CFP; } - Value(const MDNode *Var, const ConstantInt *CIP) - : Variable(Var), EntryKind(E_ConstantInt) { + Value(const MDNode *Expr, const MDNode *Var, const ConstantInt *CIP) + : Expression(Expr), Variable(Var), EntryKind(E_ConstantInt) { Constant.CIP = CIP; } - Value(const MDNode *Var, MachineLocation Loc) - : Variable(Var), EntryKind(E_Location), Loc(Loc) { + Value(const MDNode *Expr, const MDNode *Var, MachineLocation Loc) + : Expression(Expr), Variable(Var), EntryKind(E_Location), Loc(Loc) { } + // Any complex address location expression for this Value. + const MDNode *Expression; + // The variable to which this location entry corresponds. const MDNode *Variable; @@ -69,7 +72,8 @@ MachineLocation getLoc() const { return Loc; } const MDNode *getVariableNode() const { return Variable; } DIVariable getVariable() const { return DIVariable(Variable); } - bool isVariablePiece() const { return getVariable().isVariablePiece(); } + DIExpression getExpression() const { return DIExpression(Expression); } + bool isVariablePiece() const { return getExpression().isVariablePiece(); } friend bool operator==(const Value &, const Value &); friend bool operator<(const Value &, const Value &); }; @@ -90,11 +94,13 @@ // list of values. // Return true if the merge was successful. bool MergeValues(const DebugLocEntry &Next) { - if (Begin == Next.Begin && Values.size() > 0 && Next.Values.size() > 0) { + if (Begin == Next.Begin) { + DIExpression Expr(Values[0].Expression); DIVariable Var(Values[0].Variable); + DIExpression NextExpr(Next.Values[0].Expression); DIVariable NextVar(Next.Values[0].Variable); - if (Var.getName() == NextVar.getName() && - Var.isVariablePiece() && NextVar.isVariablePiece()) { + if (Var == NextVar && + Expr.isVariablePiece() && NextExpr.isVariablePiece()) { addValues(Next.Values); End = Next.End; return true; @@ -133,7 +139,8 @@ std::sort(Values.begin(), Values.end()); Values.erase(std::unique(Values.begin(), Values.end(), [](const Value &A, const Value &B) { - return A.getVariable() == B.getVariable(); + return A.getVariable() == B.getVariable() + && A.getExpression() == B.getExpression(); }), Values.end()); } }; @@ -144,7 +151,10 @@ if (A.EntryKind != B.EntryKind) return false; - if (A.getVariable() != B.getVariable()) + if (A.Expression != B.Expression) + return false; + + if (A.Variable != B.Variable) return false; switch (A.EntryKind) { @@ -163,7 +173,7 @@ /// Compare two pieces based on their offset. inline bool operator<(const DebugLocEntry::Value &A, const DebugLocEntry::Value &B) { - return A.getVariable().getPieceOffset() < B.getVariable().getPieceOffset(); + return A.getExpression().getPieceOffset() < B.getExpression().getPieceOffset(); } } Index: lib/CodeGen/AsmPrinter/DwarfDebug.h =================================================================== --- lib/CodeGen/AsmPrinter/DwarfDebug.h +++ lib/CodeGen/AsmPrinter/DwarfDebug.h @@ -69,6 +69,7 @@ //===----------------------------------------------------------------------===// /// \brief This class is used to track local variable information. class DbgVariable { + DIExpression Expr; // Complex address location expression. DIVariable Var; // Variable Descriptor. DIE *TheDIE; // Variable DIE. unsigned DotDebugLocOffset; // Offset in DotDebugLocEntries. @@ -78,18 +79,20 @@ public: /// Construct a DbgVariable from a DIVariable. - DbgVariable(DIVariable V, DwarfDebug *DD) - : Var(V), TheDIE(nullptr), DotDebugLocOffset(~0U), MInsn(nullptr), + DbgVariable(DIExpression E, DIVariable V, DwarfDebug *DD) + : Expr(E), Var(V), TheDIE(nullptr), DotDebugLocOffset(~0U), MInsn(nullptr), FrameIndex(~0), DD(DD) {} /// Construct a DbgVariable from a DEBUG_VALUE. /// AbstractVar may be NULL. DbgVariable(const MachineInstr *DbgValue, DwarfDebug *DD) - : Var(DbgValue->getDebugVariable()), TheDIE(nullptr), + : Expr(DbgValue->getDebugExpression()), + Var(DbgValue->getDebugVariable()), TheDIE(nullptr), DotDebugLocOffset(~0U), MInsn(DbgValue), FrameIndex(~0), DD(DD) {} // Accessors. DIVariable getVariable() const { return Var; } + DIExpression getExpression() const { return Expr; } void setDIE(DIE &D) { TheDIE = &D; } DIE *getDIE() const { return TheDIE; } void setDotDebugLocOffset(unsigned O) { DotDebugLocOffset = O; } @@ -124,14 +127,14 @@ bool variableHasComplexAddress() const { assert(Var.isVariable() && "Invalid complex DbgVariable!"); - return Var.hasComplexAddress(); + return Expr; } bool isBlockByrefVariable() const; unsigned getNumAddrElements() const { assert(Var.isVariable() && "Invalid complex DbgVariable!"); - return Var.getNumAddrElements(); + return Expr.getNumElements(); } - uint64_t getAddrElement(unsigned i) const { return Var.getAddrElement(i); } + uint64_t getAddrElement(unsigned i) const { return Expr.getElement(i); } DIType getType() const; private: Index: lib/CodeGen/AsmPrinter/DwarfDebug.cpp =================================================================== --- lib/CodeGen/AsmPrinter/DwarfDebug.cpp +++ lib/CodeGen/AsmPrinter/DwarfDebug.cpp @@ -876,7 +876,7 @@ for (unsigned vi = 0, ve = Variables.getNumElements(); vi != ve; ++vi) { DIVariable DV(Variables.getElement(vi)); assert(DV.isVariable()); - DbgVariable NewVar(DV, this); + DbgVariable NewVar(DIExpression(nullptr), DV, this); auto VariableDie = SPCU->constructVariableDIE(NewVar); SPCU->applyVariableAttributes(NewVar, *VariableDie); SPDIE->addChild(std::move(VariableDie)); @@ -1099,7 +1099,7 @@ void DwarfDebug::createAbstractVariable(const DIVariable &Var, LexicalScope *Scope) { - auto AbsDbgVariable = make_unique(Var, this); + auto AbsDbgVariable = make_unique(DIExpression(), Var, this); addScopeVariable(Scope, AbsDbgVariable.get()); AbstractVariables[Var] = std::move(AbsDbgVariable); } @@ -1154,6 +1154,7 @@ if (!VI.Var) continue; Processed.insert(VI.Var); + DIExpression Expr(VI.Expr); DIVariable DV(VI.Var); LexicalScope *Scope = LScopes.findLexicalScope(VI.Loc); @@ -1162,7 +1163,7 @@ continue; ensureAbstractVariableIsCreatedIfScoped(DV, Scope->getScopeNode()); - ConcreteVariables.push_back(make_unique(DV, this)); + ConcreteVariables.push_back(make_unique(Expr, DV, this)); DbgVariable *RegVar = ConcreteVariables.back().get(); RegVar->setFrameIndex(VI.Slot); addScopeVariable(Scope, RegVar); @@ -1171,9 +1172,10 @@ // Get .debug_loc entry for the instruction range starting at MI. static DebugLocEntry::Value getDebugLocValue(const MachineInstr *MI) { + const MDNode *Expr = MI->getDebugExpression(); const MDNode *Var = MI->getDebugVariable(); - assert(MI->getNumOperands() == 3); + assert(MI->getNumOperands() == 4); if (MI->getOperand(0).isReg()) { MachineLocation MLoc; // If the second operand is an immediate, this is a @@ -1182,20 +1184,20 @@ MLoc.set(MI->getOperand(0).getReg()); else MLoc.set(MI->getOperand(0).getReg(), MI->getOperand(1).getImm()); - return DebugLocEntry::Value(Var, MLoc); + return DebugLocEntry::Value(Expr, Var, MLoc); } if (MI->getOperand(0).isImm()) - return DebugLocEntry::Value(Var, MI->getOperand(0).getImm()); + return DebugLocEntry::Value(Expr, Var, MI->getOperand(0).getImm()); if (MI->getOperand(0).isFPImm()) - return DebugLocEntry::Value(Var, MI->getOperand(0).getFPImm()); + return DebugLocEntry::Value(Expr, Var, MI->getOperand(0).getFPImm()); if (MI->getOperand(0).isCImm()) - return DebugLocEntry::Value(Var, MI->getOperand(0).getCImm()); + return DebugLocEntry::Value(Expr, Var, MI->getOperand(0).getCImm()); - llvm_unreachable("Unexpected 3 operand DBG_VALUE instruction!"); + llvm_unreachable("Unexpected 4-operand DBG_VALUE instruction!"); } /// Determine whether two variable pieces overlap. -static bool piecesOverlap(DIVariable P1, DIVariable P2) { +static bool piecesOverlap(DIExpression P1, DIExpression P2) { if (!P1.isVariablePiece() || !P2.isVariablePiece()) return true; unsigned l1 = P1.getPieceOffset(); @@ -1246,10 +1248,10 @@ } // If this piece overlaps with any open ranges, truncate them. - DIVariable DIVar = Begin->getDebugVariable(); + DIExpression DIExpr = Begin->getDebugExpression(); auto Last = std::remove_if(OpenRanges.begin(), OpenRanges.end(), [&](DebugLocEntry::Value R) { - return piecesOverlap(DIVar, R.getVariable()); + return piecesOverlap(DIExpr, R.getExpression()); }); OpenRanges.erase(Last, OpenRanges.end()); @@ -1272,7 +1274,7 @@ bool couldMerge = false; // If this is a piece, it may belong to the current DebugLocEntry. - if (DIVar.isVariablePiece()) { + if (DIExpr.isVariablePiece()) { // Add this value to the list of open ranges. OpenRanges.push_back(Value); @@ -1298,9 +1300,11 @@ if (PrevEntry != DebugLoc.rend() && PrevEntry->MergeRanges(*CurEntry)) DebugLoc.pop_back(); - DEBUG(dbgs() << "Values:\n"; - for (auto Value : CurEntry->getValues()) + DEBUG(dbgs() << CurEntry->getValues().size() << " Values:\n"; + for (auto Value : CurEntry->getValues()) { Value.getVariable()->dump(); + Value.getExpression()->dump(); + } dbgs() << "-----\n"); } } @@ -1336,7 +1340,7 @@ if (!Scope) continue; - Processed.insert(getEntireVariable(DV)); + Processed.insert(DV); const MachineInstr *MInsn = Ranges.front().first; assert(MInsn->isDebugValue() && "History must begin with debug value"); ensureAbstractVariableIsCreatedIfScoped(DV, Scope->getScopeNode()); @@ -1370,7 +1374,8 @@ continue; if (LexicalScope *Scope = LScopes.findLexicalScope(DV.getContext())) { ensureAbstractVariableIsCreatedIfScoped(DV, Scope->getScopeNode()); - ConcreteVariables.push_back(make_unique(DV, this)); + DIExpression NoExpr; + ConcreteVariables.push_back(make_unique(NoExpr, DV, this)); addScopeVariable(Scope, ConcreteVariables.back().get()); } } @@ -1558,18 +1563,17 @@ // The first mention of a function argument gets the FunctionBeginSym // label, so arguments are visible when breaking at function entry. - DIVariable DV(Ranges.front().first->getDebugVariable()); - if (DV.isVariable() && DV.getTag() == dwarf::DW_TAG_arg_variable && - getDISubprogram(DV.getContext()).describes(MF->getFunction())) { - if (!DV.isVariablePiece()) - LabelsBeforeInsn[Ranges.front().first] = FunctionBeginSym; - else { + DIVariable DIVar(Ranges.front().first->getDebugVariable()); + if (DIVar.isVariable() && DIVar.getTag() == dwarf::DW_TAG_arg_variable && + getDISubprogram(DIVar.getContext()).describes(MF->getFunction())) { + LabelsBeforeInsn[Ranges.front().first] = FunctionBeginSym; + if (Ranges.front().first->getDebugExpression().isVariablePiece()) { // Mark all non-overlapping initial pieces. for (auto I = Ranges.begin(); I != Ranges.end(); ++I) { - DIVariable Piece = I->first->getDebugVariable(); + DIExpression Piece = I->first->getDebugExpression(); if (std::all_of(Ranges.begin(), I, [&](DbgValueHistoryMap::InstrRange Pred){ - return !piecesOverlap(Piece, Pred.first->getDebugVariable()); + return !piecesOverlap(Piece, Pred.first->getDebugExpression()); })) LabelsBeforeInsn[I->first] = FunctionBeginSym; else @@ -2071,9 +2075,9 @@ unsigned Offset = 0; for (auto Piece : Values) { - DIVariable Var = Piece.getVariable(); - unsigned PieceOffset = Var.getPieceOffset(); - unsigned PieceSize = Var.getPieceSize(); + DIExpression Expr = Piece.getExpression(); + unsigned PieceOffset = Expr.getPieceOffset(); + unsigned PieceSize = Expr.getPieceSize(); assert(Offset <= PieceOffset && "overlapping or duplicate pieces"); if (Offset < PieceOffset) { // The DWARF spec seriously mandates pieces with no locations for gaps. @@ -2084,8 +2088,9 @@ Offset += PieceSize; const unsigned SizeOfByte = 8; - assert(!Var.isIndirect() && "indirect address for piece"); #ifndef NDEBUG + DIVariable Var = Piece.getVariable(); + assert(!Var.isIndirect() && "indirect address for piece"); unsigned VarSize = Var.getSizeInBits(Map); assert(PieceSize+PieceOffset <= VarSize/SizeOfByte && "piece is larger than or outside of variable"); @@ -2131,24 +2136,25 @@ } } else if (Value.isLocation()) { MachineLocation Loc = Value.getLoc(); - if (!DV.hasComplexAddress()) + DIExpression Expr = Value.getExpression(); + if (!Expr) // Regular entry. Asm->EmitDwarfRegOp(Streamer, Loc, DV.isIndirect()); else { // Complex address entry. - unsigned N = DV.getNumAddrElements(); + unsigned N = Expr.getNumElements(); unsigned i = 0; - if (N >= 2 && DV.getAddrElement(0) == DIBuilder::OpPlus) { + if (N >= 2 && Expr.getElement(0) == DIBuilder::OpPlus) { if (Loc.getOffset()) { i = 2; Asm->EmitDwarfRegOp(Streamer, Loc, DV.isIndirect()); Streamer.EmitInt8(dwarf::DW_OP_deref, "DW_OP_deref"); Streamer.EmitInt8(dwarf::DW_OP_plus_uconst, "DW_OP_plus_uconst"); - Streamer.EmitSLEB128(DV.getAddrElement(1)); + Streamer.EmitSLEB128(Expr.getElement(1)); } else { // If first address element is OpPlus then emit // DW_OP_breg + Offset instead of DW_OP_reg + Offset. - MachineLocation TLoc(Loc.getReg(), DV.getAddrElement(1)); + MachineLocation TLoc(Loc.getReg(), Expr.getElement(1)); Asm->EmitDwarfRegOp(Streamer, TLoc, DV.isIndirect()); i = 2; } @@ -2158,10 +2164,10 @@ // Emit remaining complex address elements. for (; i < N; ++i) { - uint64_t Element = DV.getAddrElement(i); + uint64_t Element = Expr.getElement(i); if (Element == DIBuilder::OpPlus) { Streamer.EmitInt8(dwarf::DW_OP_plus_uconst, "DW_OP_plus_uconst"); - Streamer.EmitULEB128(DV.getAddrElement(++i)); + Streamer.EmitULEB128(Expr.getElement(++i)); } else if (Element == DIBuilder::OpDeref) { if (!Loc.isReg()) Streamer.EmitInt8(dwarf::DW_OP_deref, "DW_OP_deref"); Index: lib/CodeGen/AsmPrinter/DwarfUnit.cpp =================================================================== --- lib/CodeGen/AsmPrinter/DwarfUnit.cpp +++ lib/CodeGen/AsmPrinter/DwarfUnit.cpp @@ -605,16 +605,20 @@ unsigned i = 0; if (Location.isReg()) { if (N >= 2 && DV.getAddrElement(0) == DIBuilder::OpPlus) { + assert(!DV.getVariable().isIndirect() && "double indirection not handled"); // If first address element is OpPlus then emit // DW_OP_breg + Offset instead of DW_OP_reg + Offset. addRegisterOffset(*Loc, Location.getReg(), DV.getAddrElement(1)); i = 2; } else if (N >= 2 && DV.getAddrElement(0) == DIBuilder::OpDeref) { - addRegisterOpPiece(*Loc, Location.getReg(), - DV.getVariable().getPieceSize(), - DV.getVariable().getPieceOffset()); - i = 3; - } else + assert(!DV.getVariable().isIndirect() && "double indirection not handled"); + addRegisterOpPiece(*Loc, Location.getReg(), + DV.getExpression().getPieceSize(), + DV.getExpression().getPieceOffset()); + i = 3; + } else if (DV.getVariable().isIndirect()) + addRegisterOffset(*Loc, Location.getReg(), 0); + else addRegisterOpPiece(*Loc, Location.getReg()); } else addRegisterOffset(*Loc, Location.getReg(), Location.getOffset()); @@ -1853,7 +1857,7 @@ // Check if variable is described by a DBG_VALUE instruction. if (const MachineInstr *DVInsn = DV.getMInsn()) { - assert(DVInsn->getNumOperands() == 3); + assert(DVInsn->getNumOperands() == 4); if (DVInsn->getOperand(0).isReg()) { const MachineOperand RegOp = DVInsn->getOperand(0); // If the second operand is an immediate, this is an indirect value. Index: lib/CodeGen/InlineSpiller.cpp =================================================================== --- lib/CodeGen/InlineSpiller.cpp +++ lib/CodeGen/InlineSpiller.cpp @@ -1213,12 +1213,14 @@ // Modify DBG_VALUE now that the value is in a spill slot. bool IsIndirect = MI->isIndirectDebugValue(); uint64_t Offset = IsIndirect ? MI->getOperand(1).getImm() : 0; - const MDNode *MDPtr = MI->getOperand(2).getMetadata(); + const MDNode *Expr = MI->getDebugExpression(); + const MDNode *Var = MI->getDebugVariable(); DebugLoc DL = MI->getDebugLoc(); DEBUG(dbgs() << "Modifying debug info due to spill:" << "\t" << *MI); MachineBasicBlock *MBB = MI->getParent(); BuildMI(*MBB, MBB->erase(MI), DL, TII.get(TargetOpcode::DBG_VALUE)) - .addFrameIndex(StackSlot).addImm(Offset).addMetadata(MDPtr); + .addFrameIndex(StackSlot).addImm(Offset) + .addMetadata(Expr).addMetadata(Var); continue; } Index: lib/CodeGen/LiveDebugVariables.cpp =================================================================== --- lib/CodeGen/LiveDebugVariables.cpp +++ lib/CodeGen/LiveDebugVariables.cpp @@ -111,6 +111,7 @@ class LDVImpl; class UserValue { const MDNode *variable; ///< The debug info variable we are part of. + const MDNode *expr; ///< Any complex address expression. unsigned offset; ///< Byte offset into variable. bool IsIndirect; ///< true if this is a register-indirect+offset value. DebugLoc dl; ///< The debug location for the variable. This is @@ -140,9 +141,10 @@ public: /// UserValue - Create a new UserValue. - UserValue(const MDNode *var, unsigned o, bool i, DebugLoc L, + UserValue(const MDNode *var, const MDNode *expr, + unsigned o, bool i, DebugLoc L, LocMap::Allocator &alloc) - : variable(var), offset(o), IsIndirect(i), dl(L), leader(this), + : variable(var), expr(expr), offset(o), IsIndirect(i), dl(L), leader(this), next(nullptr), locInts(alloc) {} @@ -158,8 +160,10 @@ UserValue *getNext() const { return next; } /// match - Does this UserValue match the parameters? - bool match(const MDNode *Var, unsigned Offset, bool indirect) const { - return Var == variable && Offset == offset && indirect == IsIndirect; + bool match(const MDNode *Var, const MDNode *Expr, + unsigned Offset, bool indirect) const { + return Var == variable && Expr == expr + && Offset == offset && indirect == IsIndirect; } /// merge - Merge equivalence classes. @@ -307,8 +311,8 @@ UVMap userVarMap; /// getUserValue - Find or create a UserValue. - UserValue *getUserValue(const MDNode *Var, unsigned Offset, - bool IsIndirect, DebugLoc DL); + UserValue *getUserValue(const MDNode *Var, const MDNode *Expr, + unsigned Offset, bool IsIndirect, DebugLoc DL); /// lookupVirtReg - Find the EC leader for VirtReg or null. UserValue *lookupVirtReg(unsigned VirtReg); @@ -422,19 +426,19 @@ LDV->mapVirtReg(locations[i].getReg(), this); } -UserValue *LDVImpl::getUserValue(const MDNode *Var, unsigned Offset, - bool IsIndirect, DebugLoc DL) { +UserValue *LDVImpl::getUserValue(const MDNode *Var, const MDNode *Expr, + unsigned Offset, bool IsIndirect, DebugLoc DL) { UserValue *&Leader = userVarMap[Var]; if (Leader) { UserValue *UV = Leader->getLeader(); Leader = UV; for (; UV; UV = UV->getNext()) - if (UV->match(Var, Offset, IsIndirect)) + if (UV->match(Var, Expr, Offset, IsIndirect)) return UV; } userValues.push_back( - make_unique(Var, Offset, IsIndirect, DL, allocator)); + make_unique(Var, Expr, Offset, IsIndirect, DL, allocator)); UserValue *UV = userValues.back().get(); Leader = UserValue::merge(Leader, UV); return UV; @@ -454,7 +458,7 @@ bool LDVImpl::handleDebugValue(MachineInstr *MI, SlotIndex Idx) { // DBG_VALUE loc, offset, variable - if (MI->getNumOperands() != 3 || + if (MI->getNumOperands() != 4 || !(MI->getOperand(1).isReg() || MI->getOperand(1).isImm()) || !MI->getOperand(2).isMetadata()) { DEBUG(dbgs() << "Can't handle " << *MI); @@ -464,9 +468,10 @@ // Get or create the UserValue for (variable,offset). bool IsIndirect = MI->isIndirectDebugValue(); unsigned Offset = IsIndirect ? MI->getOperand(1).getImm() : 0; - const MDNode *Var = MI->getOperand(2).getMetadata(); + const MDNode *Expr = MI->getOperand(2).getMetadata(); + const MDNode *Var = MI->getOperand(3).getMetadata(); //here. - UserValue *UV = getUserValue(Var, Offset, IsIndirect, MI->getDebugLoc()); + UserValue *UV = getUserValue(Var, Expr, Offset, IsIndirect, MI->getDebugLoc()); UV->addDef(Idx, MI->getOperand(0)); return true; } @@ -951,10 +956,10 @@ if (Loc.isReg()) BuildMI(*MBB, I, findDebugLoc(), TII.get(TargetOpcode::DBG_VALUE), - IsIndirect, Loc.getReg(), offset, variable); + IsIndirect, Loc.getReg(), offset, expr, variable); else BuildMI(*MBB, I, findDebugLoc(), TII.get(TargetOpcode::DBG_VALUE)) - .addOperand(Loc).addImm(offset).addMetadata(variable); + .addOperand(Loc).addImm(offset).addMetadata(expr).addMetadata(variable); } void UserValue::emitDebugValues(VirtRegMap *VRM, LiveIntervals &LIS, Index: lib/CodeGen/MachineInstr.cpp =================================================================== --- lib/CodeGen/MachineInstr.cpp +++ lib/CodeGen/MachineInstr.cpp @@ -1625,8 +1625,11 @@ if (isDebugValue() && MO.isMetadata()) { // Pretty print DBG_VALUE instructions. const MDNode *MD = MO.getMetadata(); - if (const MDString *MDS = dyn_cast(MD->getOperand(2))) - OS << "!\"" << MDS->getString() << '\"'; + if (MD->getNumOperands() >= 2) + if (const MDString *MDS = dyn_cast(MD->getOperand(2))) + OS << "!\"" << MDS->getString() << '\"'; + else + MO.print(OS, TM); else MO.print(OS, TM); } else if (TM && (isInsertSubreg() || isRegSequence()) && MO.isImm()) { @@ -1729,6 +1732,8 @@ OS << " ]"; } } + if (isIndirectDebugValue()) + OS << " indirect"; } else if (!debugLoc.isUnknown() && MF) { if (!HaveSemi) OS << ";"; OS << " dbg:"; Index: lib/CodeGen/RegAllocFast.cpp =================================================================== --- lib/CodeGen/RegAllocFast.cpp +++ lib/CodeGen/RegAllocFast.cpp @@ -299,7 +299,8 @@ LiveDbgValueMap[LRI->VirtReg]; for (unsigned li = 0, le = LRIDbgValues.size(); li != le; ++li) { MachineInstr *DBG = LRIDbgValues[li]; - const MDNode *MDPtr = DBG->getOperand(2).getMetadata(); + const MDNode *Expr = DBG->getDebugExpression(); + const MDNode *Var = DBG->getDebugVariable(); bool IsIndirect = DBG->isIndirectDebugValue(); uint64_t Offset = IsIndirect ? DBG->getOperand(1).getImm() : 0; DebugLoc DL; @@ -312,7 +313,7 @@ MachineBasicBlock *MBB = DBG->getParent(); MachineInstr *NewDV = BuildMI(*MBB, MI, DL, TII->get(TargetOpcode::DBG_VALUE)) - .addFrameIndex(FI).addImm(Offset).addMetadata(MDPtr); + .addFrameIndex(FI).addImm(Offset).addMetadata(Expr).addMetadata(Var); (void)NewDV; DEBUG(dbgs() << "Inserting debug info due to spill:" << "\n" << *NewDV); } @@ -863,13 +864,14 @@ // Modify DBG_VALUE now that the value is in a spill slot. bool IsIndirect = MI->isIndirectDebugValue(); uint64_t Offset = IsIndirect ? MI->getOperand(1).getImm() : 0; - const MDNode *MDPtr = - MI->getOperand(MI->getNumOperands()-1).getMetadata(); + const MDNode *Expr = MI->getDebugExpression(); + const MDNode *Var = MI->getDebugVariable(); DebugLoc DL = MI->getDebugLoc(); MachineBasicBlock *MBB = MI->getParent(); MachineInstr *NewDV = BuildMI(*MBB, MBB->erase(MI), DL, TII->get(TargetOpcode::DBG_VALUE)) - .addFrameIndex(SS).addImm(Offset).addMetadata(MDPtr); + .addFrameIndex(SS).addImm(Offset) + .addMetadata(Expr).addMetadata(Var); DEBUG(dbgs() << "Modifying debug info due to spill:" << "\t" << *NewDV); // Scan NewDV operands from the beginning. Index: lib/CodeGen/SelectionDAG/FastISel.cpp =================================================================== --- lib/CodeGen/SelectionDAG/FastISel.cpp +++ lib/CodeGen/SelectionDAG/FastISel.cpp @@ -1144,12 +1144,13 @@ Op->setIsDebug(true); BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, TII.get(TargetOpcode::DBG_VALUE), false, Op->getReg(), 0, - DI->getVariable()); + DI->getExpression(), DI->getVariable()); } else BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, TII.get(TargetOpcode::DBG_VALUE)) .addOperand(*Op) .addImm(0) + .addMetadata(DI->getExpression()) .addMetadata(DI->getVariable()); } else { // We can't yet handle anything else here because it would require @@ -1168,25 +1169,29 @@ // help debugging. Probably the optimizer should not do this. BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, II) .addReg(0U).addImm(DI->getOffset()) + .addMetadata(DI->getExpression()) .addMetadata(DI->getVariable()); } else if (const ConstantInt *CI = dyn_cast(V)) { if (CI->getBitWidth() > 64) BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, II) .addCImm(CI).addImm(DI->getOffset()) + .addMetadata(DI->getExpression()) .addMetadata(DI->getVariable()); else BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, II) .addImm(CI->getZExtValue()).addImm(DI->getOffset()) + .addMetadata(DI->getExpression()) .addMetadata(DI->getVariable()); } else if (const ConstantFP *CF = dyn_cast(V)) { BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, II) .addFPImm(CF).addImm(DI->getOffset()) + .addMetadata(DI->getExpression()) .addMetadata(DI->getVariable()); } else if (unsigned Reg = lookUpRegForValue(V)) { // FIXME: This does not handle register-indirect values at offset 0. bool IsIndirect = DI->getOffset() != 0; BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, II, IsIndirect, - Reg, DI->getOffset(), DI->getVariable()); + Reg, DI->getOffset(), DI->getExpression(), DI->getVariable()); } else { // We can't yet handle anything else here because it would require // generating code, thus altering codegen because of debug info. Index: lib/CodeGen/SelectionDAG/FunctionLoweringInfo.cpp =================================================================== --- lib/CodeGen/SelectionDAG/FunctionLoweringInfo.cpp +++ lib/CodeGen/SelectionDAG/FunctionLoweringInfo.cpp @@ -168,7 +168,8 @@ StaticAllocaMap.find(AI); if (SI != StaticAllocaMap.end()) { // Check for VLAs. int FI = SI->second; - MMI.setVariableDbgInfo(DI->getVariable(), + MMI.setVariableDbgInfo(DI->getExpression(), + DI->getVariable(), FI, DI->getDebugLoc()); } } Index: lib/CodeGen/SelectionDAG/InstrEmitter.cpp =================================================================== --- lib/CodeGen/SelectionDAG/InstrEmitter.cpp +++ lib/CodeGen/SelectionDAG/InstrEmitter.cpp @@ -649,14 +649,16 @@ InstrEmitter::EmitDbgValue(SDDbgValue *SD, DenseMap &VRBaseMap) { uint64_t Offset = SD->getOffset(); - MDNode* MDPtr = SD->getMDPtr(); + MDNode* Expr = SD->getExpression(); + MDNode* Var = SD->getVariable(); DebugLoc DL = SD->getDebugLoc(); if (SD->getKind() == SDDbgValue::FRAMEIX) { // Stack address; this needs to be lowered in target-dependent fashion. // EmitTargetCodeForFrameDebugValue is responsible for allocation. return BuildMI(*MF, DL, TII->get(TargetOpcode::DBG_VALUE)) - .addFrameIndex(SD->getFrameIx()).addImm(Offset).addMetadata(MDPtr); + .addFrameIndex(SD->getFrameIx()).addImm(Offset) + .addMetadata(Expr).addMetadata(Var); } // Otherwise, we're going to create an instruction here. const MCInstrDesc &II = TII->get(TargetOpcode::DBG_VALUE); @@ -702,7 +704,8 @@ MIB.addReg(0U, RegState::Debug); } - MIB.addMetadata(MDPtr); + MIB.addMetadata(Expr); + MIB.addMetadata(Var); return &*MIB; } Index: lib/CodeGen/SelectionDAG/SDNodeDbgValue.h =================================================================== --- lib/CodeGen/SelectionDAG/SDNodeDbgValue.h +++ lib/CodeGen/SelectionDAG/SDNodeDbgValue.h @@ -44,7 +44,8 @@ const Value *Const; // valid for constants unsigned FrameIx; // valid for stack objects } u; - MDNode *mdPtr; + MDNode *Expr; + MDNode *Var; bool IsIndirect; uint64_t Offset; DebugLoc DL; @@ -52,9 +53,9 @@ bool Invalid; public: // Constructor for non-constants. - SDDbgValue(MDNode *mdP, SDNode *N, unsigned R, + SDDbgValue(MDNode *Expr, MDNode *Var, SDNode *N, unsigned R, bool indir, uint64_t off, DebugLoc dl, - unsigned O) : mdPtr(mdP), IsIndirect(indir), + unsigned O) : Expr(Expr), Var(Var), IsIndirect(indir), Offset(off), DL(dl), Order(O), Invalid(false) { kind = SDNODE; @@ -63,17 +64,18 @@ } // Constructor for constants. - SDDbgValue(MDNode *mdP, const Value *C, uint64_t off, DebugLoc dl, + SDDbgValue(MDNode *Expr, MDNode *Var, const Value *C, uint64_t off, DebugLoc dl, unsigned O) : - mdPtr(mdP), IsIndirect(false), Offset(off), DL(dl), Order(O), + Expr(Expr), Var(Var), IsIndirect(false), Offset(off), DL(dl), Order(O), Invalid(false) { kind = CONST; u.Const = C; } // Constructor for frame indices. - SDDbgValue(MDNode *mdP, unsigned FI, uint64_t off, DebugLoc dl, unsigned O) : - mdPtr(mdP), IsIndirect(false), Offset(off), DL(dl), Order(O), + SDDbgValue(MDNode *Expr, MDNode *Var, + unsigned FI, uint64_t off, DebugLoc dl, unsigned O) : + Expr(Expr), Var(Var), IsIndirect(false), Offset(off), DL(dl), Order(O), Invalid(false) { kind = FRAMEIX; u.FrameIx = FI; @@ -82,8 +84,11 @@ // Returns the kind. DbgValueKind getKind() { return kind; } - // Returns the MDNode pointer. - MDNode *getMDPtr() { return mdPtr; } + // Returns the MDNode pointer for the expression. + MDNode *getExpression() { return Expr; } + + // Returns the MDNode pointer for the variable. + MDNode *getVariable() { return Var; } // Returns the SDNode* for a register ref SDNode *getSDNode() { assert (kind==SDNODE); return u.s.Node; } Index: lib/CodeGen/SelectionDAG/SelectionDAG.cpp =================================================================== --- lib/CodeGen/SelectionDAG/SelectionDAG.cpp +++ lib/CodeGen/SelectionDAG/SelectionDAG.cpp @@ -5776,25 +5776,26 @@ /// /// SDNode SDDbgValue * -SelectionDAG::getDbgValue(MDNode *MDPtr, SDNode *N, unsigned R, +SelectionDAG::getDbgValue(MDNode *Expr, MDNode *Var, SDNode *N, unsigned R, bool IsIndirect, uint64_t Off, DebugLoc DL, unsigned O) { - return new (Allocator) SDDbgValue(MDPtr, N, R, IsIndirect, Off, DL, O); + return new (Allocator) SDDbgValue(Expr, Var, N, R, IsIndirect, Off, DL, O); } /// Constant SDDbgValue * -SelectionDAG::getConstantDbgValue(MDNode *MDPtr, const Value *C, +SelectionDAG::getConstantDbgValue(MDNode *Expr, MDNode *Var, const Value *C, uint64_t Off, DebugLoc DL, unsigned O) { - return new (Allocator) SDDbgValue(MDPtr, C, Off, DL, O); + return new (Allocator) SDDbgValue(Expr, Var, C, Off, DL, O); } /// FrameIndex SDDbgValue * -SelectionDAG::getFrameIndexDbgValue(MDNode *MDPtr, unsigned FI, uint64_t Off, +SelectionDAG::getFrameIndexDbgValue(MDNode *Expr, MDNode *Var, + unsigned FI, uint64_t Off, DebugLoc DL, unsigned O) { - return new (Allocator) SDDbgValue(MDPtr, FI, Off, DL, O); + return new (Allocator) SDDbgValue(Expr, Var, FI, Off, DL, O); } namespace { @@ -6200,7 +6201,8 @@ I != E; ++I) { SDDbgValue *Dbg = *I; if (Dbg->getKind() == SDDbgValue::SDNODE) { - SDDbgValue *Clone = getDbgValue(Dbg->getMDPtr(), ToNode, To.getResNo(), + SDDbgValue *Clone = getDbgValue(Dbg->getExpression(), Dbg->getVariable(), + ToNode, To.getResNo(), Dbg->isIndirect(), Dbg->getOffset(), Dbg->getDebugLoc(), Dbg->getOrder()); Index: lib/CodeGen/SelectionDAG/SelectionDAGBuilder.h =================================================================== --- lib/CodeGen/SelectionDAG/SelectionDAGBuilder.h +++ lib/CodeGen/SelectionDAG/SelectionDAGBuilder.h @@ -791,7 +791,8 @@ /// EmitFuncArgumentDbgValue - If V is an function argument then create /// corresponding DBG_VALUE machine instruction for it now. At the end of /// instruction selection, they will be inserted to the entry BB. - bool EmitFuncArgumentDbgValue(const Value *V, MDNode *Variable, + bool EmitFuncArgumentDbgValue(const Value *V, + MDNode *Expr, MDNode *Variable, int64_t Offset, bool IsIndirect, const SDValue &N); }; Index: lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp =================================================================== --- lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp +++ lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp @@ -1012,14 +1012,15 @@ const DbgValueInst *DI = DDI.getDI(); DebugLoc dl = DDI.getdl(); unsigned DbgSDNodeOrder = DDI.getSDNodeOrder(); + MDNode *Expr = DI->getExpression(); MDNode *Variable = DI->getVariable(); uint64_t Offset = DI->getOffset(); // A dbg.value for an alloca is always indirect. bool IsIndirect = isa(V) || Offset != 0; SDDbgValue *SDV; if (Val.getNode()) { - if (!EmitFuncArgumentDbgValue(V, Variable, Offset, IsIndirect, Val)) { - SDV = DAG.getDbgValue(Variable, Val.getNode(), + if (!EmitFuncArgumentDbgValue(V, Expr, Variable, Offset, IsIndirect, Val)) { + SDV = DAG.getDbgValue(Expr, Variable, Val.getNode(), Val.getResNo(), IsIndirect, Offset, dl, DbgSDNodeOrder); DAG.AddDbgValue(SDV, Val.getNode(), false); @@ -4619,7 +4620,8 @@ /// argument, create the corresponding DBG_VALUE machine instruction for it now. /// At the end of instruction selection, they will be inserted to the entry BB. bool -SelectionDAGBuilder::EmitFuncArgumentDbgValue(const Value *V, MDNode *Variable, +SelectionDAGBuilder::EmitFuncArgumentDbgValue(const Value *V, MDNode *Expr, + MDNode *Variable, int64_t Offset, bool IsIndirect, const SDValue &N) { const Argument *Arg = dyn_cast(V); @@ -4676,11 +4678,12 @@ FuncInfo.ArgDbgValues.push_back(BuildMI(MF, getCurDebugLoc(), TII->get(TargetOpcode::DBG_VALUE), IsIndirect, - Op->getReg(), Offset, Variable)); + Op->getReg(), Offset, + Expr, Variable)); else FuncInfo.ArgDbgValues.push_back( BuildMI(MF, getCurDebugLoc(), TII->get(TargetOpcode::DBG_VALUE)) - .addOperand(*Op).addImm(Offset).addMetadata(Variable)); + .addOperand(*Op).addImm(Offset).addMetadata(Expr).addMetadata(Variable)); return true; } @@ -4799,6 +4802,7 @@ } case Intrinsic::dbg_declare: { const DbgDeclareInst &DI = cast(I); + MDNode *Expression = DI.getExpression(); MDNode *Variable = DI.getVariable(); const Value *Address = DI.getAddress(); DIVariable DIVar(Variable); @@ -4835,16 +4839,17 @@ FrameIndexSDNode *FINode = dyn_cast(N.getNode()); if (FINode) // Byval parameter. We have a frame index at this point. - SDV = DAG.getFrameIndexDbgValue(Variable, FINode->getIndex(), + SDV = DAG.getFrameIndexDbgValue(Expression, Variable, + FINode->getIndex(), 0, dl, SDNodeOrder); else { // Address is an argument, so try to emit its dbg value using // virtual register info from the FuncInfo.ValueMap. - EmitFuncArgumentDbgValue(Address, Variable, 0, false, N); + EmitFuncArgumentDbgValue(Address, Expression, Variable, 0, false, N); return nullptr; } } else if (AI) - SDV = DAG.getDbgValue(Variable, N.getNode(), N.getResNo(), + SDV = DAG.getDbgValue(Expression, Variable, N.getNode(), N.getResNo(), true, 0, dl, SDNodeOrder); else { // Can't do anything with other non-AI cases yet. @@ -4857,7 +4862,7 @@ } else { // If Address is an argument then try to emit its dbg value using // virtual register info from the FuncInfo.ValueMap. - if (!EmitFuncArgumentDbgValue(Address, Variable, 0, false, N)) { + if (!EmitFuncArgumentDbgValue(Address, Expression, Variable, 0, false, N)) { // If variable is pinned by a alloca in dominating bb then // use StaticAllocaMap. if (const AllocaInst *AI = dyn_cast(Address)) { @@ -4865,7 +4870,7 @@ DenseMap::iterator SI = FuncInfo.StaticAllocaMap.find(AI); if (SI != FuncInfo.StaticAllocaMap.end()) { - SDV = DAG.getFrameIndexDbgValue(Variable, SI->second, + SDV = DAG.getFrameIndexDbgValue(Expression, Variable, SI->second, 0, dl, SDNodeOrder); DAG.AddDbgValue(SDV, nullptr, false); return nullptr; @@ -4885,6 +4890,7 @@ if (!DIVar) return nullptr; + MDNode *Expression = DI.getExpression(); MDNode *Variable = DI.getVariable(); uint64_t Offset = DI.getOffset(); const Value *V = DI.getValue(); @@ -4893,7 +4899,7 @@ SDDbgValue *SDV; if (isa(V) || isa(V) || isa(V)) { - SDV = DAG.getConstantDbgValue(Variable, V, Offset, dl, SDNodeOrder); + SDV = DAG.getConstantDbgValue(Expression, Variable, V, Offset, dl, SDNodeOrder); DAG.AddDbgValue(SDV, nullptr, false); } else { // Do not use getValue() in here; we don't want to generate code at @@ -4905,8 +4911,8 @@ if (N.getNode()) { // A dbg.value for an alloca is always indirect. bool IsIndirect = isa(V) || Offset != 0; - if (!EmitFuncArgumentDbgValue(V, Variable, Offset, IsIndirect, N)) { - SDV = DAG.getDbgValue(Variable, N.getNode(), + if (!EmitFuncArgumentDbgValue(V, Expression, Variable, Offset, IsIndirect, N)) { + SDV = DAG.getDbgValue(Expression, Variable, N.getNode(), N.getResNo(), IsIndirect, Offset, dl, SDNodeOrder); DAG.AddDbgValue(SDV, N.getNode(), false); Index: lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp =================================================================== --- lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp +++ lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp @@ -489,15 +489,15 @@ "- add if needed"); MachineInstr *Def = RegInfo->getVRegDef(LDI->second); MachineBasicBlock::iterator InsertPos = Def; - const MDNode *Variable = - MI->getOperand(MI->getNumOperands()-1).getMetadata(); + const MDNode *Variable = MI->getDebugVariable(); + const MDNode *Expr = MI->getDebugExpression(); bool IsIndirect = MI->isIndirectDebugValue(); unsigned Offset = IsIndirect ? MI->getOperand(1).getImm() : 0; // Def is never a terminator here, so it is ok to increment InsertPos. BuildMI(*EntryMBB, ++InsertPos, MI->getDebugLoc(), TII.get(TargetOpcode::DBG_VALUE), - IsIndirect, - LDI->second, Offset, Variable); + IsIndirect, LDI->second, Offset, + Expr, Variable); // If this vreg is directly copied into an exported register then // that COPY instructions also need DBG_VALUE, if it is the only @@ -520,7 +520,7 @@ TII.get(TargetOpcode::DBG_VALUE), IsIndirect, CopyUseMI->getOperand(0).getReg(), - Offset, Variable); + Offset, Expr, Variable); MachineBasicBlock::iterator Pos = CopyUseMI; EntryMBB->insertAfter(Pos, NewMI); } Index: lib/IR/DIBuilder.cpp =================================================================== --- lib/IR/DIBuilder.cpp +++ lib/IR/DIBuilder.cpp @@ -1076,35 +1076,22 @@ return RetVar; } -/// createComplexVariable - Create a new descriptor for the specified variable -/// which has a complex address expression for its address. -DIVariable DIBuilder::createComplexVariable(unsigned Tag, DIDescriptor Scope, - StringRef Name, DIFile F, - unsigned LineNo, - DITypeRef Ty, - ArrayRef Addr, - unsigned ArgNo) { - assert(Addr.size() > 0 && "complex address is empty"); - Value *Elts[] = { - GetTagConstant(VMContext, Tag), - getNonCompileUnitScope(Scope), - MDString::get(VMContext, Name), - F, - ConstantInt::get(Type::getInt32Ty(VMContext), - (LineNo | (ArgNo << 24))), - Ty, - Constant::getNullValue(Type::getInt32Ty(VMContext)), - Constant::getNullValue(Type::getInt32Ty(VMContext)), - MDNode::get(VMContext, Addr) - }; - return DIVariable(MDNode::get(VMContext, Elts)); +/// createExpression - Create a new descriptor for the specified +/// variable which has a complex address expression for its address. +/// @param Addr An array of complex address operations. +DIExpression DIBuilder::createExpression(ArrayRef Addr) { + return DIExpression(MDNode::get(VMContext, Addr)); +} + +/// createExpression - Create an empty DIExpression. +DIExpression DIBuilder::createExpression() { + return DIExpression(MDNode::get(VMContext, ArrayRef())); } /// createVariablePiece - Create a descriptor to describe one part /// of aggregate variable that is fragmented across multiple Values. -DIVariable DIBuilder::createVariablePiece(DIVariable Variable, - unsigned OffsetInBytes, - unsigned SizeInBytes) { +DIExpression DIBuilder::createPieceExpression(unsigned OffsetInBytes, + unsigned SizeInBytes) { assert(SizeInBytes > 0 && "zero-size piece"); Value *Addr[] = { ConstantInt::get(Type::getInt32Ty(VMContext), OpPiece), @@ -1112,14 +1099,7 @@ ConstantInt::get(Type::getInt32Ty(VMContext), SizeInBytes) }; - assert((Variable->getNumOperands() == 8 || Variable.isVariablePiece()) && - "variable already has a complex address"); - SmallVector Elts; - for (unsigned i = 0; i < 8; ++i) - Elts.push_back(Variable->getOperand(i)); - - Elts.push_back(MDNode::get(VMContext, Addr)); - return DIVariable(MDNode::get(VMContext, Elts)); + return DIExpression(MDNode::get(VMContext, Addr)); } /// createFunction - Create a new descriptor for the specified function. @@ -1290,7 +1270,8 @@ } /// insertDeclare - Insert a new llvm.dbg.declare intrinsic call. -Instruction *DIBuilder::insertDeclare(Value *Storage, DIVariable VarInfo, +Instruction *DIBuilder::insertDeclare(Value *Storage, + DIExpression Expr, DIVariable VarInfo, Instruction *InsertBefore) { assert(Storage && "no storage passed to dbg.declare"); assert(VarInfo.isVariable() && @@ -1298,12 +1279,14 @@ if (!DeclareFn) DeclareFn = Intrinsic::getDeclaration(&M, Intrinsic::dbg_declare); - Value *Args[] = { MDNode::get(Storage->getContext(), Storage), VarInfo }; + Value *Args[] = { MDNode::get(Storage->getContext(), Storage), + Expr, VarInfo }; return CallInst::Create(DeclareFn, Args, "", InsertBefore); } /// insertDeclare - Insert a new llvm.dbg.declare intrinsic call. -Instruction *DIBuilder::insertDeclare(Value *Storage, DIVariable VarInfo, +Instruction *DIBuilder::insertDeclare(Value *Storage, + DIExpression Expr, DIVariable VarInfo, BasicBlock *InsertAtEnd) { assert(Storage && "no storage passed to dbg.declare"); assert(VarInfo.isVariable() && @@ -1311,7 +1294,8 @@ if (!DeclareFn) DeclareFn = Intrinsic::getDeclaration(&M, Intrinsic::dbg_declare); - Value *Args[] = { MDNode::get(Storage->getContext(), Storage), VarInfo }; + Value *Args[] = { MDNode::get(Storage->getContext(), Storage), + Expr, VarInfo }; // If this block already has a terminator then insert this intrinsic // before the terminator. @@ -1323,6 +1307,7 @@ /// insertDbgValueIntrinsic - Insert a new llvm.dbg.value intrinsic call. Instruction *DIBuilder::insertDbgValueIntrinsic(Value *V, uint64_t Offset, + DIExpression Expr, DIVariable VarInfo, Instruction *InsertBefore) { assert(V && "no value passed to dbg.value"); @@ -1333,12 +1318,13 @@ Value *Args[] = { MDNode::get(V->getContext(), V), ConstantInt::get(Type::getInt64Ty(V->getContext()), Offset), - VarInfo }; + Expr, VarInfo }; return CallInst::Create(ValueFn, Args, "", InsertBefore); } /// insertDbgValueIntrinsic - Insert a new llvm.dbg.value intrinsic call. Instruction *DIBuilder::insertDbgValueIntrinsic(Value *V, uint64_t Offset, + DIExpression Expr, DIVariable VarInfo, BasicBlock *InsertAtEnd) { assert(V && "no value passed to dbg.value"); @@ -1349,6 +1335,6 @@ Value *Args[] = { MDNode::get(V->getContext(), V), ConstantInt::get(Type::getInt64Ty(V->getContext()), Offset), - VarInfo }; + Expr, VarInfo }; return CallInst::Create(ValueFn, Args, "", InsertAtEnd); } Index: lib/IR/DebugInfo.cpp =================================================================== --- lib/IR/DebugInfo.cpp +++ lib/IR/DebugInfo.cpp @@ -138,33 +138,9 @@ } } -uint64_t DIVariable::getAddrElement(unsigned Idx) const { - DIDescriptor ComplexExpr = getDescriptorField(8); - if (Idx < ComplexExpr->getNumOperands()) - if (auto *CI = dyn_cast_or_null(ComplexExpr->getOperand(Idx))) - return CI->getZExtValue(); - - assert(false && "non-existing complex address element requested"); - return 0; -} - /// getInlinedAt - If this variable is inlined then return inline location. MDNode *DIVariable::getInlinedAt() const { return getNodeField(DbgNode, 7); } -bool DIVariable::isVariablePiece() const { - return hasComplexAddress() && getAddrElement(0) == DIBuilder::OpPiece; -} - -uint64_t DIVariable::getPieceOffset() const { - assert(isVariablePiece()); - return getAddrElement(1); -} - -uint64_t DIVariable::getPieceSize() const { - assert(isVariablePiece()); - return getAddrElement(2); -} - /// Return the size reported by the variable's type. unsigned DIVariable::getSizeInBits(const DITypeIdentifierMap &Map) { DIType Ty = getType().resolve(Map); @@ -178,7 +154,28 @@ return Ty.getSizeInBits(); } +uint64_t DIExpression::getElement(unsigned Idx) const { + if (Idx < DbgNode->getNumOperands()) + if (auto *CI = dyn_cast_or_null(DbgNode->getOperand(Idx))) + return CI->getZExtValue(); + assert(false && "non-existing complex address element requested"); + return 0; +} + +bool DIExpression::isVariablePiece() const { + return getNumElements() && getElement(0) == DIBuilder::OpPiece; +} + +uint64_t DIExpression::getPieceOffset() const { + assert(isVariablePiece()); + return getElement(1); +} + +uint64_t DIExpression::getPieceSize() const { + assert(isVariablePiece()); + return getElement(2); +} //===----------------------------------------------------------------------===// @@ -935,19 +932,6 @@ return DIVariable(MDNode::get(VMContext, Elts)); } - -/// getEntireVariable - Remove OpPiece exprs from the variable. -DIVariable llvm::getEntireVariable(DIVariable DV) { - if (!DV.isVariablePiece()) - return DV; - - SmallVector Elts; - for (unsigned i = 0; i < 8; ++i) - Elts.push_back(DV->getOperand(i)); - - return DIVariable(MDNode::get(DV->getContext(), Elts)); -} - /// getDISubprogram - Find subprogram that is enclosing this scope. DISubprogram llvm::getDISubprogram(const MDNode *Scope) { DIDescriptor D(Scope); @@ -1437,6 +1421,10 @@ OS << " [" << Res << ']'; OS << " [line " << getLineNumber() << ']'; +} + +void DIExpression::printInternal(raw_ostream &OS) const { + OS << " [complex location expr]"; if (isVariablePiece()) OS << " [piece, size " << getPieceSize() Index: lib/Target/AArch64/AArch64InstrInfo.h =================================================================== --- lib/Target/AArch64/AArch64InstrInfo.h +++ lib/Target/AArch64/AArch64InstrInfo.h @@ -99,8 +99,8 @@ MachineInstr *Second) const override; MachineInstr *emitFrameIndexDebugValue(MachineFunction &MF, int FrameIx, - uint64_t Offset, const MDNode *MDPtr, - DebugLoc DL) const; + uint64_t Offset, const MDNode *Expr, + const MDNode *Var, DebugLoc DL) const; void copyPhysRegTuple(MachineBasicBlock &MBB, MachineBasicBlock::iterator I, DebugLoc DL, unsigned DestReg, unsigned SrcReg, bool KillSrc, unsigned Opcode, Index: lib/Target/AArch64/AArch64InstrInfo.cpp =================================================================== --- lib/Target/AArch64/AArch64InstrInfo.cpp +++ lib/Target/AArch64/AArch64InstrInfo.cpp @@ -1315,13 +1315,15 @@ MachineInstr *AArch64InstrInfo::emitFrameIndexDebugValue(MachineFunction &MF, int FrameIx, uint64_t Offset, - const MDNode *MDPtr, + const MDNode *Expr, + const MDNode *Var, DebugLoc DL) const { MachineInstrBuilder MIB = BuildMI(MF, DL, get(AArch64::DBG_VALUE)) .addFrameIndex(FrameIx) .addImm(0) .addImm(Offset) - .addMetadata(MDPtr); + .addMetadata(Expr) + .addMetadata(Var); return &*MIB; } Index: lib/Target/X86/X86FastISel.cpp =================================================================== --- lib/Target/X86/X86FastISel.cpp +++ lib/Target/X86/X86FastISel.cpp @@ -2290,7 +2290,7 @@ // FIXME may need to add RegState::Debug to any registers produced, // although ESP/EBP should be the only ones at the moment. addFullAddress(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, II), AM). - addImm(0).addMetadata(DI->getVariable()); + addImm(0).addMetadata(DI->getExpression()).addMetadata(DI->getVariable()); return true; } case Intrinsic::trap: { Index: lib/Transforms/Scalar/SROA.cpp =================================================================== --- lib/Transforms/Scalar/SROA.cpp +++ lib/Transforms/Scalar/SROA.cpp @@ -890,8 +890,10 @@ continue; } Instruction *DbgVal = - DIB.insertDbgValueIntrinsic(Arg, 0, DIVariable(DVI->getVariable()), - Inst); + DIB.insertDbgValueIntrinsic(Arg, 0, + DIExpression(DVI->getExpression()), + DIVariable(DVI->getVariable()), + Inst); DbgVal->setDebugLoc(DVI->getDebugLoc()); } } Index: lib/Transforms/Scalar/ScalarReplAggregates.cpp =================================================================== --- lib/Transforms/Scalar/ScalarReplAggregates.cpp +++ lib/Transforms/Scalar/ScalarReplAggregates.cpp @@ -1120,7 +1120,8 @@ continue; } Instruction *DbgVal = - DIB->insertDbgValueIntrinsic(Arg, 0, DIVariable(DVI->getVariable()), + DIB->insertDbgValueIntrinsic(Arg, 0, DIExpression(DVI->getExpression()), + DIVariable(DVI->getVariable()), Inst); DbgVal->setDebugLoc(DVI->getDebugLoc()); } Index: lib/Transforms/Utils/Local.cpp =================================================================== --- lib/Transforms/Utils/Local.cpp +++ lib/Transforms/Utils/Local.cpp @@ -989,6 +989,7 @@ /// that has an associated llvm.dbg.decl intrinsic. bool llvm::ConvertDebugDeclareToDebugValue(DbgDeclareInst *DDI, StoreInst *SI, DIBuilder &Builder) { + DIExpression DIExpr(DDI->getExpression()); DIVariable DIVar(DDI->getVariable()); assert((!DIVar || DIVar.isVariable()) && "Variable in DbgDeclareInst should be either null or a DIVariable."); @@ -1007,9 +1008,10 @@ if (SExtInst *SExt = dyn_cast(SI->getOperand(0))) ExtendedArg = dyn_cast(SExt->getOperand(0)); if (ExtendedArg) - DbgVal = Builder.insertDbgValueIntrinsic(ExtendedArg, 0, DIVar, SI); + DbgVal = Builder.insertDbgValueIntrinsic(ExtendedArg, 0, DIExpr, DIVar, SI); else - DbgVal = Builder.insertDbgValueIntrinsic(SI->getOperand(0), 0, DIVar, SI); + DbgVal = Builder.insertDbgValueIntrinsic(SI->getOperand(0), 0, DIExpr, + DIVar, SI); DbgVal->setDebugLoc(DDI->getDebugLoc()); return true; } @@ -1018,6 +1020,7 @@ /// that has an associated llvm.dbg.decl intrinsic. bool llvm::ConvertDebugDeclareToDebugValue(DbgDeclareInst *DDI, LoadInst *LI, DIBuilder &Builder) { + DIExpression DIExpr(DDI->getExpression()); DIVariable DIVar(DDI->getVariable()); assert((!DIVar || DIVar.isVariable()) && "Variable in DbgDeclareInst should be either null or a DIVariable."); @@ -1028,7 +1031,7 @@ return true; Instruction *DbgVal = - Builder.insertDbgValueIntrinsic(LI->getOperand(0), 0, + Builder.insertDbgValueIntrinsic(LI->getOperand(0), 0, DIExpr, DIVar, LI); DbgVal->setDebugLoc(DDI->getDebugLoc()); return true; @@ -1074,6 +1077,7 @@ // intrinsic that describes the alloca. auto DbgVal = DIB.insertDbgValueIntrinsic(AI, 0, + DIExpression(DDI->getExpression()), DIVariable(DDI->getVariable()), CI); DbgVal->setDebugLoc(DDI->getDebugLoc()); } @@ -1099,6 +1103,7 @@ DbgDeclareInst *DDI = FindAllocaDbgDeclare(AI); if (!DDI) return false; + DIExpression DIExpr(DDI->getExpression()); DIVariable DIVar(DDI->getVariable()); assert((!DIVar || DIVar.isVariable()) && "Variable in DbgDeclareInst should be either null or a DIVariable."); @@ -1110,23 +1115,20 @@ // will take a value storing address of the memory for variable, not // alloca itself. Type *Int64Ty = Type::getInt64Ty(AI->getContext()); - SmallVector NewDIVarAddress; - if (DIVar.hasComplexAddress()) { - for (unsigned i = 0, n = DIVar.getNumAddrElements(); i < n; ++i) { - NewDIVarAddress.push_back( - ConstantInt::get(Int64Ty, DIVar.getAddrElement(i))); + SmallVector NewDIExpr; + if (DIExpr) { + for (unsigned i = 0, n = DIExpr.getNumElements(); i < n; ++i) { + NewDIExpr.push_back(ConstantInt::get(Int64Ty, DIExpr.getElement(i))); } } - NewDIVarAddress.push_back(ConstantInt::get(Int64Ty, DIBuilder::OpDeref)); - DIVariable NewDIVar = Builder.createComplexVariable( - DIVar.getTag(), DIVar.getContext(), DIVar.getName(), - DIVar.getFile(), DIVar.getLineNumber(), DIVar.getType(), - NewDIVarAddress, DIVar.getArgNumber()); + NewDIExpr.push_back(ConstantInt::get(Int64Ty, DIBuilder::OpDeref)); // Insert llvm.dbg.declare in the same basic block as the original alloca, // and remove old llvm.dbg.declare. BasicBlock *BB = AI->getParent(); - Builder.insertDeclare(NewAllocaAddress, NewDIVar, BB); + Builder.insertDeclare(NewAllocaAddress, + Builder.createExpression(NewDIExpr), + DIVar, BB); DDI->eraseFromParent(); return true; } Index: test/Analysis/GlobalsModRef/pr12351.ll =================================================================== --- test/Analysis/GlobalsModRef/pr12351.ll +++ test/Analysis/GlobalsModRef/pr12351.ll @@ -26,8 +26,8 @@ define void @bar2(i32* %foo) { store i32 0, i32* %foo, align 4 - tail call void @llvm.dbg.value(metadata !{}, i64 0, metadata !{}) + tail call void @llvm.dbg.value(metadata !{}, i64 0, metadata !{}, metadata !{}) ret void } -declare void @llvm.dbg.value(metadata, i64, metadata) nounwind readnone +declare void @llvm.dbg.value(metadata, i64, metadata, metadata) nounwind readnone Index: test/Assembler/2010-02-05-FunctionLocalMetadataBecomesNull.ll =================================================================== --- test/Assembler/2010-02-05-FunctionLocalMetadataBecomesNull.ll +++ test/Assembler/2010-02-05-FunctionLocalMetadataBecomesNull.ll @@ -12,7 +12,7 @@ define i32 @main() nounwind readonly { %diff1 = alloca i64 ; [#uses=2] - call void @llvm.dbg.declare(metadata !{i64* %diff1}, metadata !0) + call void @llvm.dbg.declare(metadata !{i64* %diff1}, metadata !{}, metadata !0) store i64 72, i64* %diff1, align 8 %v1 = load %struct.test** @TestArrayPtr, align 8 ; <%struct.test*> [#uses=1] %v2 = ptrtoint %struct.test* %v1 to i64 ; [#uses=1] @@ -21,7 +21,7 @@ ret i32 4 } -declare void @llvm.dbg.declare(metadata, metadata) nounwind readnone +declare void @llvm.dbg.declare(metadata, metadata, metadata) nounwind readnone !7 = metadata !{metadata !1} !6 = metadata !{i32 786449, metadata !8, i32 12, metadata !"clang version 3.0 (trunk 131941)", i1 true, metadata !"", i32 0, metadata !9, metadata !9, metadata !7, null, null, metadata !""} ; [ DW_TAG_compile_unit ] Index: test/Assembler/functionlocal-metadata.ll =================================================================== --- test/Assembler/functionlocal-metadata.ll +++ test/Assembler/functionlocal-metadata.ll @@ -3,33 +3,33 @@ define void @Foo(i32 %a, i32 %b) { entry: - call void @llvm.dbg.value(metadata !{ i32* %1 }, i64 16, metadata !2) -; CHECK: call void @llvm.dbg.value(metadata !{i32* %1}, i64 16, metadata ![[ID2:[0-9]+]]) + call void @llvm.dbg.value(metadata !{ i32* %1 }, i64 16, metadata !{}, metadata !2) +; CHECK: call void @llvm.dbg.value(metadata !{i32* %1}, i64 16, metadata {{.*}}, metadata ![[ID2:[0-9]+]]) %0 = add i32 %a, 1 ; [#uses=1] %two = add i32 %b, %0 ; [#uses=0] %1 = alloca i32 ; [#uses=1] - call void @llvm.dbg.declare(metadata !{i32* %1}, metadata !{i32* %1}) -; CHECK: metadata !{i32* %1}, metadata !{i32* %1} - call void @llvm.dbg.declare(metadata !{i32 %two}, metadata !{i32 %0}) -; CHECK: metadata !{i32 %two}, metadata !{i32 %0} - call void @llvm.dbg.declare(metadata !{i32 %0}, metadata !{i32* %1, i32 %0}) -; CHECK: metadata !{i32 %0}, metadata !{i32* %1, i32 %0} - call void @llvm.dbg.declare(metadata !{i32* %1}, metadata !{i32 %b, i32 %0}) -; CHECK: metadata !{i32* %1}, metadata !{i32 %b, i32 %0} - call void @llvm.dbg.declare(metadata !{i32 %a}, metadata !{i32 %a, metadata !"foo"}) -; CHECK: metadata !{i32 %a}, metadata !{i32 %a, metadata !"foo"} - call void @llvm.dbg.declare(metadata !{i32 %b}, metadata !{metadata !0, i32 %two}) -; CHECK: metadata !{i32 %b}, metadata !{metadata ![[ID0:[0-9]+]], i32 %two} - - call void @llvm.dbg.value(metadata !{ i32 %a }, i64 0, metadata !1) -; CHECK: metadata !{i32 %a}, i64 0, metadata ![[ID1:[0-9]+]] - call void @llvm.dbg.value(metadata !{ i32 %0 }, i64 25, metadata !0) -; CHECK: metadata !{i32 %0}, i64 25, metadata ![[ID0]] - call void @llvm.dbg.value(metadata !{ i32* %1 }, i64 16, metadata !3) -; CHECK: call void @llvm.dbg.value(metadata !{i32* %1}, i64 16, metadata ![[ID3:[0-9]+]]) - call void @llvm.dbg.value(metadata !3, i64 12, metadata !2) -; CHECK: metadata ![[ID3]], i64 12, metadata ![[ID2]] + call void @llvm.dbg.declare(metadata !{i32* %1}, metadata !{}, metadata !{i32* %1}) +; CHECK: call void @llvm.dbg.declare(metadata !{i32* %1}, metadata {{.*}}, metadata !{i32* %1}) + call void @llvm.dbg.declare(metadata !{i32 %two}, metadata !{}, metadata !{i32 %0}) +; CHECK: call void @llvm.dbg.declare(metadata !{i32 %two}, metadata {{.*}}, metadata !{i32 %0}) + call void @llvm.dbg.declare(metadata !{i32 %0}, metadata !{}, metadata !{i32* %1, i32 %0}) +; CHECK: call void @llvm.dbg.declare(metadata !{i32 %0}, metadata {{.*}}, metadata !{i32* %1, i32 %0}) + call void @llvm.dbg.declare(metadata !{i32* %1}, metadata !{}, metadata !{i32 %b, i32 %0}) +; CHECK: call void @llvm.dbg.declare(metadata !{i32* %1}, metadata {{.*}}, metadata !{i32 %b, i32 %0}) + call void @llvm.dbg.declare(metadata !{i32 %a}, metadata !{}, metadata !{i32 %a, metadata !"foo"}) +; CHECK: call void @llvm.dbg.declare(metadata !{i32 %a}, metadata {{.*}}, metadata !{i32 %a, metadata !"foo"}) + call void @llvm.dbg.declare(metadata !{i32 %b}, metadata !{}, metadata !{metadata !0, i32 %two}) +; CHECK: call void @llvm.dbg.declare(metadata !{i32 %b}, metadata {{.*}}, metadata !{metadata ![[ID0:[0-9]+]], i32 %two}) + + call void @llvm.dbg.value(metadata !{ i32 %a }, i64 0, metadata !{}, metadata !1) +; CHECK: call void @llvm.dbg.value(metadata !{i32 %a}, i64 0, metadata {{.*}}, metadata ![[ID1:[0-9]+]]) + call void @llvm.dbg.value(metadata !{ i32 %0 }, i64 25, metadata !{}, metadata !0) +; CHECK: call void @llvm.dbg.value(metadata !{i32 %0}, i64 25, metadata {{.*}}, metadata ![[ID0]]) + call void @llvm.dbg.value(metadata !{ i32* %1 }, i64 16, metadata !{}, metadata !3) +; CHECK: call void @llvm.dbg.value(metadata !{i32* %1}, i64 16, metadata {{.*}}, metadata ![[ID3:[0-9]+]]) + call void @llvm.dbg.value(metadata !3, i64 12, metadata !{}, metadata !2) +; CHECK: call void @llvm.dbg.value(metadata ![[ID3]], i64 12, metadata {{.*}}, metadata ![[ID2]]) ret void, !foo !0, !bar !1 ; CHECK: ret void, !foo ![[FOO:[0-9]+]], !bar ![[BAR:[0-9]+]] @@ -43,8 +43,8 @@ !3 = metadata !{metadata !"foo"} !4 = metadata !{i32 1, metadata !"Debug Info Version", i32 1} -declare void @llvm.dbg.declare(metadata, metadata) nounwind readnone -declare void @llvm.dbg.value(metadata, i64, metadata) nounwind readnone +declare void @llvm.dbg.declare(metadata, metadata, metadata) nounwind readnone +declare void @llvm.dbg.value(metadata, i64, metadata, metadata) nounwind readnone !foo = !{ !0 } !bar = !{ !1 } Index: test/CodeGen/AArch64/aarch64-2014-08-11-MachineCombinerCrash.ll =================================================================== --- test/CodeGen/AArch64/aarch64-2014-08-11-MachineCombinerCrash.ll +++ test/CodeGen/AArch64/aarch64-2014-08-11-MachineCombinerCrash.ll @@ -16,7 +16,7 @@ %add53 = add nsw i64 %n1, 0, !dbg !52 %add55 = add nsw i64 %n1, 0, !dbg !53 %mul63 = mul nsw i64 %add53, -20995, !dbg !54 - tail call void @llvm.dbg.value(metadata !{i64 %mul63}, i64 0, metadata !30), !dbg !55 + tail call void @llvm.dbg.value(metadata !{i64 %mul63}, i64 0, metadata !{}, metadata !30), !dbg !55 %mul65 = mul nsw i64 %add55, -3196, !dbg !56 %add67 = add nsw i64 0, %mul65, !dbg !57 %add80 = add i64 0, 1024, !dbg !58 @@ -35,7 +35,7 @@ } ; Function Attrs: nounwind readnone -declare void @llvm.dbg.value(metadata, i64, metadata) #1 +declare void @llvm.dbg.value(metadata, i64, metadata, metadata) #1 attributes #0 = { nounwind "less-precise-fpmad"="false" "no-frame-pointer-elim"="true" "no-frame-pointer-elim-non-leaf" "no-infs-fp-math"="false" "no-nans-fp-math"="false" "stack-protector-buffer-size"="8" "unsafe-fp-math"="false" "use-soft-float"="false" } attributes #1 = { nounwind readnone } Index: test/CodeGen/AArch64/arm64-2011-03-17-AsmPrinterCrash.ll =================================================================== --- test/CodeGen/AArch64/arm64-2011-03-17-AsmPrinterCrash.ll +++ test/CodeGen/AArch64/arm64-2011-03-17-AsmPrinterCrash.ll @@ -11,12 +11,12 @@ unreachable if.else295: ; preds = %entry - call void @llvm.dbg.declare(metadata !{i32* %do_tab_convert}, metadata !16), !dbg !18 + call void @llvm.dbg.declare(metadata !{i32* %do_tab_convert}, metadata !{}, metadata !16), !dbg !18 store i32 0, i32* %do_tab_convert, align 4, !dbg !19 unreachable } -declare void @llvm.dbg.declare(metadata, metadata) nounwind readnone +declare void @llvm.dbg.declare(metadata, metadata, metadata) nounwind readnone !llvm.dbg.gv = !{!0} !llvm.dbg.sp = !{!1, !7, !10, !11, !12} Index: test/CodeGen/ARM/2009-10-16-Scope.ll =================================================================== --- test/CodeGen/ARM/2009-10-16-Scope.ll +++ test/CodeGen/ARM/2009-10-16-Scope.ll @@ -9,7 +9,7 @@ br label %do.body, !dbg !0 do.body: ; preds = %entry - call void @llvm.dbg.declare(metadata !{i32* %count_}, metadata !4) + call void @llvm.dbg.declare(metadata !{i32* %count_}, metadata !{}, metadata !4) %conv = ptrtoint i32* %count_ to i32, !dbg !0 ; [#uses=1] %call = call i32 @foo(i32 %conv) ssp, !dbg !0 ; [#uses=0] br label %do.end, !dbg !0 @@ -18,7 +18,7 @@ ret void, !dbg !7 } -declare void @llvm.dbg.declare(metadata, metadata) nounwind readnone +declare void @llvm.dbg.declare(metadata, metadata, metadata) nounwind readnone declare i32 @foo(i32) ssp Index: test/CodeGen/ARM/2010-04-15-ScavengerDebugValue.ll =================================================================== --- test/CodeGen/ARM/2010-04-15-ScavengerDebugValue.ll +++ test/CodeGen/ARM/2010-04-15-ScavengerDebugValue.ll @@ -5,12 +5,12 @@ define hidden i32 @__addvsi3(i32 %a, i32 %b) nounwind { entry: - tail call void @llvm.dbg.value(metadata !{i32 %b}, i64 0, metadata !0) + tail call void @llvm.dbg.value(metadata !{i32 %b}, i64 0, metadata !{}, metadata !0) %0 = add nsw i32 %b, %a, !dbg !9 ; [#uses=1] ret i32 %0, !dbg !11 } -declare void @llvm.dbg.value(metadata, i64, metadata) nounwind readnone +declare void @llvm.dbg.value(metadata, i64, metadata, metadata) nounwind readnone !llvm.dbg.cu = !{!3} !llvm.module.flags = !{!15} Index: test/CodeGen/ARM/2010-06-25-Thumb2ITInvalidIterator.ll =================================================================== --- test/CodeGen/ARM/2010-06-25-Thumb2ITInvalidIterator.ll +++ test/CodeGen/ARM/2010-06-25-Thumb2ITInvalidIterator.ll @@ -7,16 +7,16 @@ define void @x0(i8* nocapture %buf, i32 %nbytes) nounwind optsize { entry: - tail call void @llvm.dbg.value(metadata !{i8* %buf}, i64 0, metadata !0), !dbg !15 - tail call void @llvm.dbg.value(metadata !{i32 %nbytes}, i64 0, metadata !8), !dbg !16 + tail call void @llvm.dbg.value(metadata !{i8* %buf}, i64 0, metadata !{}, metadata !0), !dbg !15 + tail call void @llvm.dbg.value(metadata !{i32 %nbytes}, i64 0, metadata !{}, metadata !8), !dbg !16 %tmp = load i32* @length, !dbg !17 ; [#uses=3] %cmp = icmp eq i32 %tmp, -1, !dbg !17 ; [#uses=1] %cmp.not = xor i1 %cmp, true ; [#uses=1] %cmp3 = icmp ult i32 %tmp, %nbytes, !dbg !17 ; [#uses=1] %or.cond = and i1 %cmp.not, %cmp3 ; [#uses=1] - tail call void @llvm.dbg.value(metadata !{i32 %tmp}, i64 0, metadata !8), !dbg !17 + tail call void @llvm.dbg.value(metadata !{i32 %tmp}, i64 0, metadata !{}, metadata !8), !dbg !17 %nbytes.addr.0 = select i1 %or.cond, i32 %tmp, i32 %nbytes ; [#uses=1] - tail call void @llvm.dbg.value(metadata !18, i64 0, metadata !10), !dbg !19 + tail call void @llvm.dbg.value(metadata !18, i64 0, metadata !{}, metadata !10), !dbg !19 br label %while.cond, !dbg !20 while.cond: ; preds = %while.body, %entry @@ -42,7 +42,7 @@ declare i32 @x1() optsize -declare void @llvm.dbg.value(metadata, i64, metadata) nounwind readnone +declare void @llvm.dbg.value(metadata, i64, metadata, metadata) nounwind readnone !llvm.dbg.lv.fn = !{!0, !8, !10, !12} !llvm.dbg.gv = !{!14} Index: test/CodeGen/ARM/2010-08-04-StackVariable.ll =================================================================== --- test/CodeGen/ARM/2010-08-04-StackVariable.ll +++ test/CodeGen/ARM/2010-08-04-StackVariable.ll @@ -6,8 +6,8 @@ define i32 @_Z3fooi4SVal(i32 %i, %struct.SVal* noalias %location) nounwind ssp { entry: %"alloca point" = bitcast i32 0 to i32 ; [#uses=0] - call void @llvm.dbg.value(metadata !{i32 %i}, i64 0, metadata !23), !dbg !24 - call void @llvm.dbg.value(metadata !{%struct.SVal* %location}, i64 0, metadata !25), !dbg !24 + call void @llvm.dbg.value(metadata !{i32 %i}, i64 0, metadata !{}, metadata !23), !dbg !24 + call void @llvm.dbg.value(metadata !{%struct.SVal* %location}, i64 0, metadata !{}, metadata !25), !dbg !24 %0 = icmp ne i32 %i, 0, !dbg !27 ; [#uses=1] br i1 %0, label %bb, label %bb1, !dbg !27 @@ -34,7 +34,7 @@ define linkonce_odr void @_ZN4SValC1Ev(%struct.SVal* %this) nounwind ssp align 2 { entry: %"alloca point" = bitcast i32 0 to i32 ; [#uses=0] - call void @llvm.dbg.value(metadata !{%struct.SVal* %this}, i64 0, metadata !31), !dbg !34 + call void @llvm.dbg.value(metadata !{%struct.SVal* %this}, i64 0, metadata !{}, metadata !31), !dbg !34 %0 = getelementptr inbounds %struct.SVal* %this, i32 0, i32 0, !dbg !34 ; [#uses=1] store i8* null, i8** %0, align 8, !dbg !34 %1 = getelementptr inbounds %struct.SVal* %this, i32 0, i32 1, !dbg !34 ; [#uses=1] @@ -45,14 +45,14 @@ ret void, !dbg !35 } -declare void @llvm.dbg.declare(metadata, metadata) nounwind readnone +declare void @llvm.dbg.declare(metadata, metadata, metadata) nounwind readnone define i32 @main() nounwind ssp { entry: %0 = alloca %struct.SVal ; <%struct.SVal*> [#uses=3] %v = alloca %struct.SVal ; <%struct.SVal*> [#uses=4] %"alloca point" = bitcast i32 0 to i32 ; [#uses=0] - call void @llvm.dbg.declare(metadata !{%struct.SVal* %v}, metadata !38), !dbg !41 + call void @llvm.dbg.declare(metadata !{%struct.SVal* %v}, metadata !{}, metadata !38), !dbg !41 call void @_ZN4SValC1Ev(%struct.SVal* %v) nounwind, !dbg !41 %1 = getelementptr inbounds %struct.SVal* %v, i32 0, i32 1, !dbg !42 ; [#uses=1] store i32 1, i32* %1, align 8, !dbg !42 @@ -65,14 +65,14 @@ %7 = load i32* %6, align 8, !dbg !43 ; [#uses=1] store i32 %7, i32* %5, align 8, !dbg !43 %8 = call i32 @_Z3fooi4SVal(i32 2, %struct.SVal* noalias %0) nounwind, !dbg !43 ; [#uses=0] - call void @llvm.dbg.value(metadata !{i32 %8}, i64 0, metadata !44), !dbg !43 + call void @llvm.dbg.value(metadata !{i32 %8}, i64 0, metadata !{}, metadata !44), !dbg !43 br label %return, !dbg !45 return: ; preds = %entry ret i32 0, !dbg !45 } -declare void @llvm.dbg.value(metadata, i64, metadata) nounwind readnone +declare void @llvm.dbg.value(metadata, i64, metadata, metadata) nounwind readnone !llvm.dbg.cu = !{!3} !llvm.module.flags = !{!49} Index: test/CodeGen/ARM/2011-01-19-MergedGlobalDbg.ll =================================================================== --- test/CodeGen/ARM/2011-01-19-MergedGlobalDbg.ll +++ test/CodeGen/ARM/2011-01-19-MergedGlobalDbg.ll @@ -30,47 +30,47 @@ define zeroext i8 @get1(i8 zeroext %a) nounwind optsize { entry: - tail call void @llvm.dbg.value(metadata !{i8 %a}, i64 0, metadata !10), !dbg !30 + tail call void @llvm.dbg.value(metadata !{i8 %a}, i64 0, metadata !{}, metadata !10), !dbg !30 %0 = load i8* @x1, align 4, !dbg !30 - tail call void @llvm.dbg.value(metadata !{i8 %0}, i64 0, metadata !11), !dbg !30 + tail call void @llvm.dbg.value(metadata !{i8 %0}, i64 0, metadata !{}, metadata !11), !dbg !30 store i8 %a, i8* @x1, align 4, !dbg !30 ret i8 %0, !dbg !31 } -declare void @llvm.dbg.value(metadata, i64, metadata) nounwind readnone +declare void @llvm.dbg.value(metadata, i64, metadata, metadata) nounwind readnone define zeroext i8 @get2(i8 zeroext %a) nounwind optsize { entry: - tail call void @llvm.dbg.value(metadata !{i8 %a}, i64 0, metadata !18), !dbg !32 + tail call void @llvm.dbg.value(metadata !{i8 %a}, i64 0, metadata !{}, metadata !18), !dbg !32 %0 = load i8* @x2, align 4, !dbg !32 - tail call void @llvm.dbg.value(metadata !{i8 %0}, i64 0, metadata !19), !dbg !32 + tail call void @llvm.dbg.value(metadata !{i8 %0}, i64 0, metadata !{}, metadata !19), !dbg !32 store i8 %a, i8* @x2, align 4, !dbg !32 ret i8 %0, !dbg !33 } define zeroext i8 @get3(i8 zeroext %a) nounwind optsize { entry: - tail call void @llvm.dbg.value(metadata !{i8 %a}, i64 0, metadata !21), !dbg !34 + tail call void @llvm.dbg.value(metadata !{i8 %a}, i64 0, metadata !{}, metadata !21), !dbg !34 %0 = load i8* @x3, align 4, !dbg !34 - tail call void @llvm.dbg.value(metadata !{i8 %0}, i64 0, metadata !22), !dbg !34 + tail call void @llvm.dbg.value(metadata !{i8 %0}, i64 0, metadata !{}, metadata !22), !dbg !34 store i8 %a, i8* @x3, align 4, !dbg !34 ret i8 %0, !dbg !35 } define zeroext i8 @get4(i8 zeroext %a) nounwind optsize { entry: - tail call void @llvm.dbg.value(metadata !{i8 %a}, i64 0, metadata !24), !dbg !36 + tail call void @llvm.dbg.value(metadata !{i8 %a}, i64 0, metadata !{}, metadata !24), !dbg !36 %0 = load i8* @x4, align 4, !dbg !36 - tail call void @llvm.dbg.value(metadata !{i8 %0}, i64 0, metadata !25), !dbg !36 + tail call void @llvm.dbg.value(metadata !{i8 %0}, i64 0, metadata !{}, metadata !25), !dbg !36 store i8 %a, i8* @x4, align 4, !dbg !36 ret i8 %0, !dbg !37 } define zeroext i8 @get5(i8 zeroext %a) nounwind optsize { entry: - tail call void @llvm.dbg.value(metadata !{i8 %a}, i64 0, metadata !27), !dbg !38 + tail call void @llvm.dbg.value(metadata !{i8 %a}, i64 0, metadata !{}, metadata !27), !dbg !38 %0 = load i8* @x5, align 4, !dbg !38 - tail call void @llvm.dbg.value(metadata !{i8 %0}, i64 0, metadata !28), !dbg !38 + tail call void @llvm.dbg.value(metadata !{i8 %0}, i64 0, metadata !{}, metadata !28), !dbg !38 store i8 %a, i8* @x5, align 4, !dbg !38 ret i8 %0, !dbg !39 } Index: test/CodeGen/ARM/2011-08-02-MergedGlobalDbg.ll =================================================================== --- test/CodeGen/ARM/2011-08-02-MergedGlobalDbg.ll +++ test/CodeGen/ARM/2011-08-02-MergedGlobalDbg.ll @@ -29,46 +29,46 @@ @x5 = global i32 0, align 4 define i32 @get1(i32 %a) nounwind optsize ssp { - tail call void @llvm.dbg.value(metadata !{i32 %a}, i64 0, metadata !10), !dbg !30 + tail call void @llvm.dbg.value(metadata !{i32 %a}, i64 0, metadata !{}, metadata !10), !dbg !30 %1 = load i32* @x1, align 4, !dbg !31 - tail call void @llvm.dbg.value(metadata !{i32 %1}, i64 0, metadata !11), !dbg !31 + tail call void @llvm.dbg.value(metadata !{i32 %1}, i64 0, metadata !{}, metadata !11), !dbg !31 store i32 %a, i32* @x1, align 4, !dbg !31 ret i32 %1, !dbg !31 } define i32 @get2(i32 %a) nounwind optsize ssp { - tail call void @llvm.dbg.value(metadata !{i32 %a}, i64 0, metadata !13), !dbg !32 + tail call void @llvm.dbg.value(metadata !{i32 %a}, i64 0, metadata !{}, metadata !13), !dbg !32 %1 = load i32* @x2, align 4, !dbg !33 - tail call void @llvm.dbg.value(metadata !{i32 %1}, i64 0, metadata !14), !dbg !33 + tail call void @llvm.dbg.value(metadata !{i32 %1}, i64 0, metadata !{}, metadata !14), !dbg !33 store i32 %a, i32* @x2, align 4, !dbg !33 ret i32 %1, !dbg !33 } define i32 @get3(i32 %a) nounwind optsize ssp { - tail call void @llvm.dbg.value(metadata !{i32 %a}, i64 0, metadata !16), !dbg !34 + tail call void @llvm.dbg.value(metadata !{i32 %a}, i64 0, metadata !{}, metadata !16), !dbg !34 %1 = load i32* @x3, align 4, !dbg !35 - tail call void @llvm.dbg.value(metadata !{i32 %1}, i64 0, metadata !17), !dbg !35 + tail call void @llvm.dbg.value(metadata !{i32 %1}, i64 0, metadata !{}, metadata !17), !dbg !35 store i32 %a, i32* @x3, align 4, !dbg !35 ret i32 %1, !dbg !35 } define i32 @get4(i32 %a) nounwind optsize ssp { - tail call void @llvm.dbg.value(metadata !{i32 %a}, i64 0, metadata !19), !dbg !36 + tail call void @llvm.dbg.value(metadata !{i32 %a}, i64 0, metadata !{}, metadata !19), !dbg !36 %1 = load i32* @x4, align 4, !dbg !37 - tail call void @llvm.dbg.value(metadata !{i32 %1}, i64 0, metadata !20), !dbg !37 + tail call void @llvm.dbg.value(metadata !{i32 %1}, i64 0, metadata !{}, metadata !20), !dbg !37 store i32 %a, i32* @x4, align 4, !dbg !37 ret i32 %1, !dbg !37 } define i32 @get5(i32 %a) nounwind optsize ssp { - tail call void @llvm.dbg.value(metadata !{i32 %a}, i64 0, metadata !27), !dbg !38 + tail call void @llvm.dbg.value(metadata !{i32 %a}, i64 0, metadata !{}, metadata !27), !dbg !38 %1 = load i32* @x5, align 4, !dbg !39 - tail call void @llvm.dbg.value(metadata !{i32 %1}, i64 0, metadata !28), !dbg !39 + tail call void @llvm.dbg.value(metadata !{i32 %1}, i64 0, metadata !{}, metadata !28), !dbg !39 store i32 %a, i32* @x5, align 4, !dbg !39 ret i32 %1, !dbg !39 } -declare void @llvm.dbg.value(metadata, i64, metadata) nounwind readnone +declare void @llvm.dbg.value(metadata, i64, metadata, metadata) nounwind readnone !llvm.dbg.cu = !{!0} !llvm.module.flags = !{!49} Index: test/CodeGen/ARM/coalesce-dbgvalue.ll =================================================================== --- test/CodeGen/ARM/coalesce-dbgvalue.ll +++ test/CodeGen/ARM/coalesce-dbgvalue.ll @@ -27,11 +27,11 @@ for.body2: ; preds = %for.cond1 store i32 %storemerge11, i32* @b, align 4, !dbg !26 - tail call void @llvm.dbg.value(metadata !27, i64 0, metadata !11), !dbg !28 + tail call void @llvm.dbg.value(metadata !27, i64 0, metadata !{}, metadata !11), !dbg !28 %0 = load i64* @a, align 8, !dbg !29 %xor = xor i64 %0, %e.1.ph, !dbg !29 %conv3 = trunc i64 %xor to i32, !dbg !29 - tail call void @llvm.dbg.value(metadata !{i32 %conv3}, i64 0, metadata !10), !dbg !29 + tail call void @llvm.dbg.value(metadata !{i32 %conv3}, i64 0, metadata !{}, metadata !10), !dbg !29 %tobool4 = icmp eq i32 %conv3, 0, !dbg !29 br i1 %tobool4, label %land.end, label %land.rhs, !dbg !29 @@ -69,7 +69,7 @@ declare i32 @fn3(...) #1 ; Function Attrs: nounwind readnone -declare void @llvm.dbg.value(metadata, i64, metadata) #2 +declare void @llvm.dbg.value(metadata, i64, metadata, metadata) #2 attributes #0 = { nounwind ssp "less-precise-fpmad"="false" "no-frame-pointer-elim"="true" "no-frame-pointer-elim-non-leaf" "no-infs-fp-math"="false" "no-nans-fp-math"="false" "unsafe-fp-math"="false" "use-soft-float"="false" } attributes #1 = { "less-precise-fpmad"="false" "no-frame-pointer-elim"="true" "no-frame-pointer-elim-non-leaf" "no-infs-fp-math"="false" "no-nans-fp-math"="false" "unsafe-fp-math"="false" "use-soft-float"="false" } Index: test/CodeGen/ARM/debug-info-arg.ll =================================================================== --- test/CodeGen/ARM/debug-info-arg.ll +++ test/CodeGen/ARM/debug-info-arg.ll @@ -7,13 +7,13 @@ %struct.tag_s = type { i32, i32, i32 } define void @foo(%struct.tag_s* nocapture %this, %struct.tag_s* %c, i64 %x, i64 %y, %struct.tag_s* nocapture %ptr1, %struct.tag_s* nocapture %ptr2) nounwind ssp { - tail call void @llvm.dbg.value(metadata !{%struct.tag_s* %this}, i64 0, metadata !5), !dbg !20 - tail call void @llvm.dbg.value(metadata !{%struct.tag_s* %c}, i64 0, metadata !13), !dbg !21 - tail call void @llvm.dbg.value(metadata !{i64 %x}, i64 0, metadata !14), !dbg !22 - tail call void @llvm.dbg.value(metadata !{i64 %y}, i64 0, metadata !17), !dbg !23 + tail call void @llvm.dbg.value(metadata !{%struct.tag_s* %this}, i64 0, metadata !{}, metadata !5), !dbg !20 + tail call void @llvm.dbg.value(metadata !{%struct.tag_s* %c}, i64 0, metadata !{}, metadata !13), !dbg !21 + tail call void @llvm.dbg.value(metadata !{i64 %x}, i64 0, metadata !{}, metadata !14), !dbg !22 + tail call void @llvm.dbg.value(metadata !{i64 %y}, i64 0, metadata !{}, metadata !17), !dbg !23 ;CHECK: @DEBUG_VALUE: foo:y <- [R7+8] - tail call void @llvm.dbg.value(metadata !{%struct.tag_s* %ptr1}, i64 0, metadata !18), !dbg !24 - tail call void @llvm.dbg.value(metadata !{%struct.tag_s* %ptr2}, i64 0, metadata !19), !dbg !25 + tail call void @llvm.dbg.value(metadata !{%struct.tag_s* %ptr1}, i64 0, metadata !{}, metadata !18), !dbg !24 + tail call void @llvm.dbg.value(metadata !{%struct.tag_s* %ptr2}, i64 0, metadata !{}, metadata !19), !dbg !25 %1 = icmp eq %struct.tag_s* %c, null, !dbg !26 br i1 %1, label %3, label %2, !dbg !26 @@ -27,7 +27,7 @@ declare void @foobar(i64, i64) -declare void @llvm.dbg.value(metadata, i64, metadata) nounwind readnone +declare void @llvm.dbg.value(metadata, i64, metadata, metadata) nounwind readnone !llvm.dbg.cu = !{!0} !llvm.module.flags = !{!33} Index: test/CodeGen/ARM/debug-info-blocks.ll =================================================================== --- test/CodeGen/ARM/debug-info-blocks.ll +++ test/CodeGen/ARM/debug-info-blocks.ll @@ -19,11 +19,11 @@ @"OBJC_IVAR_$_MyWork._data" = external hidden global i32, section "__DATA, __objc_const", align 4 @"\01L_OBJC_SELECTOR_REFERENCES_222" = external hidden global i8*, section "__DATA, __objc_selrefs, literal_pointers, no_dead_strip" -declare void @llvm.dbg.declare(metadata, metadata) nounwind readnone +declare void @llvm.dbg.declare(metadata, metadata, metadata) nounwind readnone declare i8* @objc_msgSend(i8*, i8*, ...) -declare void @llvm.dbg.value(metadata, i64, metadata) nounwind readnone +declare void @llvm.dbg.value(metadata, i64, metadata, metadata) nounwind readnone declare void @llvm.memcpy.p0i8.p0i8.i32(i8* nocapture, i8* nocapture, i32, i32, i1) nounwind @@ -31,22 +31,22 @@ %1 = alloca %0*, align 4 %bounds = alloca %struct.CR, align 4 %data = alloca %struct.CR, align 4 - call void @llvm.dbg.value(metadata !{i8* %.block_descriptor}, i64 0, metadata !27), !dbg !129 + call void @llvm.dbg.value(metadata !{i8* %.block_descriptor}, i64 0, metadata !{}, metadata !27), !dbg !129 store %0* %loadedMydata, %0** %1, align 4 - call void @llvm.dbg.declare(metadata !{%0** %1}, metadata !130), !dbg !131 + call void @llvm.dbg.declare(metadata !{%0** %1}, metadata !{}, metadata !130), !dbg !131 %2 = bitcast %struct.CR* %bounds to %1* %3 = getelementptr %1* %2, i32 0, i32 0 store [4 x i32] %bounds.coerce0, [4 x i32]* %3 - call void @llvm.dbg.declare(metadata !{%struct.CR* %bounds}, metadata !132), !dbg !133 + call void @llvm.dbg.declare(metadata !{%struct.CR* %bounds}, metadata !{}, metadata !132), !dbg !133 %4 = bitcast %struct.CR* %data to %1* %5 = getelementptr %1* %4, i32 0, i32 0 store [4 x i32] %data.coerce0, [4 x i32]* %5 - call void @llvm.dbg.declare(metadata !{%struct.CR* %data}, metadata !134), !dbg !135 + call void @llvm.dbg.declare(metadata !{%struct.CR* %data}, metadata !{}, metadata !134), !dbg !135 %6 = bitcast i8* %.block_descriptor to %2* %7 = getelementptr inbounds %2* %6, i32 0, i32 6 - call void @llvm.dbg.declare(metadata !{%2* %6}, metadata !136), !dbg !137 - call void @llvm.dbg.declare(metadata !{%2* %6}, metadata !138), !dbg !137 - call void @llvm.dbg.declare(metadata !{%2* %6}, metadata !139), !dbg !140 + call void @llvm.dbg.declare(metadata !{%2* %6}, metadata !163, metadata !136), !dbg !137 + call void @llvm.dbg.declare(metadata !{%2* %6}, metadata !164, metadata !138), !dbg !137 + call void @llvm.dbg.declare(metadata !{%2* %6}, metadata !165, metadata !139), !dbg !140 %8 = load %0** %1, align 4, !dbg !141 %9 = load i8** @"\01L_OBJC_SELECTOR_REFERENCES_13", !dbg !141 %10 = bitcast %0* %8 to i8*, !dbg !141 @@ -231,10 +231,10 @@ !133 = metadata !{i32 609, i32 175, metadata !23, null} !134 = metadata !{i32 786689, metadata !23, metadata !"data", metadata !24, i32 67109473, metadata !108, i32 0, null} ; [ DW_TAG_arg_variable ] !135 = metadata !{i32 609, i32 190, metadata !23, null} -!136 = metadata !{i32 786688, metadata !23, metadata !"mydata", metadata !24, i32 604, metadata !50, i32 0, null, metadata !163} ; [ DW_TAG_auto_variable ] +!136 = metadata !{i32 786688, metadata !23, metadata !"mydata", metadata !24, i32 604, metadata !50, i32 0, null} ;; [ DW_TAG_auto_variable ] !137 = metadata !{i32 604, i32 49, metadata !23, null} -!138 = metadata !{i32 786688, metadata !23, metadata !"self", metadata !40, i32 604, metadata !90, i32 0, null, metadata !164} ; [ DW_TAG_auto_variable ] -!139 = metadata !{i32 786688, metadata !23, metadata !"semi", metadata !24, i32 607, metadata !125, i32 0, null, metadata !165} ; [ DW_TAG_auto_variable ] +!138 = metadata !{i32 786688, metadata !23, metadata !"self", metadata !40, i32 604, metadata !90, i32 0, null} ;; [ DW_TAG_auto_variable ] +!139 = metadata !{i32 786688, metadata !23, metadata !"semi", metadata !24, i32 607, metadata !125, i32 0, null} ;; [ DW_TAG_auto_variable ] !140 = metadata !{i32 607, i32 30, metadata !23, null} !141 = metadata !{i32 610, i32 17, metadata !142, null} !142 = metadata !{i32 786443, metadata !152, metadata !23, i32 609, i32 200, i32 94} ; [ DW_TAG_lexical_block ] Index: test/CodeGen/ARM/debug-info-branch-folding.ll =================================================================== --- test/CodeGen/ARM/debug-info-branch-folding.ll +++ test/CodeGen/ARM/debug-info-branch-folding.ll @@ -20,9 +20,9 @@ for.body9: ; preds = %for.body9, %entry %add19 = fadd <4 x float> undef, , !dbg !39 - tail call void @llvm.dbg.value(metadata !{<4 x float> %add19}, i64 0, metadata !27), !dbg !39 + tail call void @llvm.dbg.value(metadata !{<4 x float> %add19}, i64 0, metadata !{}, metadata !27), !dbg !39 %add20 = fadd <4 x float> undef, , !dbg !39 - tail call void @llvm.dbg.value(metadata !{<4 x float> %add20}, i64 0, metadata !28), !dbg !39 + tail call void @llvm.dbg.value(metadata !{<4 x float> %add20}, i64 0, metadata !{}, metadata !28), !dbg !39 br i1 %cond, label %for.end54, label %for.body9, !dbg !44 for.end54: ; preds = %for.body9 @@ -37,7 +37,7 @@ declare i32 @printf(i8* nocapture, ...) nounwind -declare void @llvm.dbg.value(metadata, i64, metadata) nounwind readnone +declare void @llvm.dbg.value(metadata, i64, metadata, metadata) nounwind readnone !llvm.module.flags = !{!56} !llvm.dbg.cu = !{!2} Index: test/CodeGen/ARM/debug-info-d16-reg.ll =================================================================== --- test/CodeGen/ARM/debug-info-d16-reg.ll +++ test/CodeGen/ARM/debug-info-d16-reg.ll @@ -12,9 +12,9 @@ define i32 @inlineprinter(i8* %ptr, double %val, i8 zeroext %c) nounwind optsize { entry: - tail call void @llvm.dbg.value(metadata !{i8* %ptr}, i64 0, metadata !19), !dbg !26 - tail call void @llvm.dbg.value(metadata !{double %val}, i64 0, metadata !20), !dbg !26 - tail call void @llvm.dbg.value(metadata !{i8 %c}, i64 0, metadata !21), !dbg !26 + tail call void @llvm.dbg.value(metadata !{i8* %ptr}, i64 0, metadata !{}, metadata !19), !dbg !26 + tail call void @llvm.dbg.value(metadata !{double %val}, i64 0, metadata !{}, metadata !20), !dbg !26 + tail call void @llvm.dbg.value(metadata !{i8 %c}, i64 0, metadata !{}, metadata !21), !dbg !26 %0 = zext i8 %c to i32, !dbg !27 %1 = tail call i32 (i8*, ...)* @printf(i8* getelementptr inbounds ([11 x i8]* @.str, i32 0, i32 0), i8* %ptr, double %val, i32 %0) nounwind, !dbg !27 ret i32 0, !dbg !29 @@ -22,9 +22,9 @@ define i32 @printer(i8* %ptr, double %val, i8 zeroext %c) nounwind optsize noinline { entry: - tail call void @llvm.dbg.value(metadata !{i8* %ptr}, i64 0, metadata !16), !dbg !30 - tail call void @llvm.dbg.value(metadata !{double %val}, i64 0, metadata !17), !dbg !30 - tail call void @llvm.dbg.value(metadata !{i8 %c}, i64 0, metadata !18), !dbg !30 + tail call void @llvm.dbg.value(metadata !{i8* %ptr}, i64 0, metadata !{}, metadata !16), !dbg !30 + tail call void @llvm.dbg.value(metadata !{double %val}, i64 0, metadata !{}, metadata !17), !dbg !30 + tail call void @llvm.dbg.value(metadata !{i8 %c}, i64 0, metadata !{}, metadata !18), !dbg !30 %0 = zext i8 %c to i32, !dbg !31 %1 = tail call i32 (i8*, ...)* @printf(i8* getelementptr inbounds ([11 x i8]* @.str, i32 0, i32 0), i8* %ptr, double %val, i32 %0) nounwind, !dbg !31 ret i32 0, !dbg !33 @@ -32,22 +32,22 @@ declare i32 @printf(i8* nocapture, ...) nounwind -declare void @llvm.dbg.value(metadata, i64, metadata) nounwind readnone +declare void @llvm.dbg.value(metadata, i64, metadata, metadata) nounwind readnone define i32 @main(i32 %argc, i8** nocapture %argv) nounwind optsize { entry: - tail call void @llvm.dbg.value(metadata !{i32 %argc}, i64 0, metadata !22), !dbg !34 - tail call void @llvm.dbg.value(metadata !{i8** %argv}, i64 0, metadata !23), !dbg !34 + tail call void @llvm.dbg.value(metadata !{i32 %argc}, i64 0, metadata !{}, metadata !22), !dbg !34 + tail call void @llvm.dbg.value(metadata !{i8** %argv}, i64 0, metadata !{}, metadata !23), !dbg !34 %0 = sitofp i32 %argc to double, !dbg !35 %1 = fadd double %0, 5.555552e+05, !dbg !35 - tail call void @llvm.dbg.value(metadata !{double %1}, i64 0, metadata !24), !dbg !35 + tail call void @llvm.dbg.value(metadata !{double %1}, i64 0, metadata !{}, metadata !24), !dbg !35 %2 = tail call i32 @puts(i8* getelementptr inbounds ([6 x i8]* @.str1, i32 0, i32 0)) nounwind, !dbg !36 %3 = getelementptr inbounds i8* bitcast (i32 (i32, i8**)* @main to i8*), i32 %argc, !dbg !37 %4 = trunc i32 %argc to i8, !dbg !37 %5 = add i8 %4, 97, !dbg !37 - tail call void @llvm.dbg.value(metadata !{i8* %3}, i64 0, metadata !19) nounwind, !dbg !38 - tail call void @llvm.dbg.value(metadata !{double %1}, i64 0, metadata !20) nounwind, !dbg !38 - tail call void @llvm.dbg.value(metadata !{i8 %5}, i64 0, metadata !21) nounwind, !dbg !38 + tail call void @llvm.dbg.value(metadata !{i8* %3}, i64 0, metadata !{}, metadata !19) nounwind, !dbg !38 + tail call void @llvm.dbg.value(metadata !{double %1}, i64 0, metadata !{}, metadata !20) nounwind, !dbg !38 + tail call void @llvm.dbg.value(metadata !{i8 %5}, i64 0, metadata !{}, metadata !21) nounwind, !dbg !38 %6 = zext i8 %5 to i32, !dbg !39 %7 = tail call i32 (i8*, ...)* @printf(i8* getelementptr inbounds ([11 x i8]* @.str, i32 0, i32 0), i8* %3, double %1, i32 %6) nounwind, !dbg !39 %8 = tail call i32 @printer(i8* %3, double %1, i8 zeroext %5) nounwind, !dbg !40 Index: test/CodeGen/ARM/debug-info-qreg.ll =================================================================== --- test/CodeGen/ARM/debug-info-qreg.ll +++ test/CodeGen/ARM/debug-info-qreg.ll @@ -26,7 +26,7 @@ br i1 undef, label %for.end54, label %for.body9, !dbg !44 for.end54: ; preds = %for.body9 - tail call void @llvm.dbg.value(metadata !{<4 x float> %add19}, i64 0, metadata !27), !dbg !39 + tail call void @llvm.dbg.value(metadata !{<4 x float> %add19}, i64 0, metadata !{}, metadata !27), !dbg !39 %tmp115 = extractelement <4 x float> %add19, i32 1 %conv6.i75 = fpext float %tmp115 to double, !dbg !45 %call.i82 = tail call i32 (i8*, ...)* @printf(i8* getelementptr inbounds ([13 x i8]* @.str, i32 0, i32 0), double undef, double %conv6.i75, double undef, double undef) nounwind, !dbg !45 @@ -35,7 +35,7 @@ declare i32 @printf(i8* nocapture, ...) nounwind -declare void @llvm.dbg.value(metadata, i64, metadata) nounwind readnone +declare void @llvm.dbg.value(metadata, i64, metadata, metadata) nounwind readnone !llvm.dbg.cu = !{!2} !llvm.module.flags = !{!56} Index: test/CodeGen/ARM/debug-info-s16-reg.ll =================================================================== --- test/CodeGen/ARM/debug-info-s16-reg.ll +++ test/CodeGen/ARM/debug-info-s16-reg.ll @@ -15,9 +15,9 @@ define i32 @inlineprinter(i8* %ptr, float %val, i8 zeroext %c) nounwind optsize ssp { entry: - tail call void @llvm.dbg.value(metadata !{i8* %ptr}, i64 0, metadata !8), !dbg !24 - tail call void @llvm.dbg.value(metadata !{float %val}, i64 0, metadata !10), !dbg !25 - tail call void @llvm.dbg.value(metadata !{i8 %c}, i64 0, metadata !12), !dbg !26 + tail call void @llvm.dbg.value(metadata !{i8* %ptr}, i64 0, metadata !{}, metadata !8), !dbg !24 + tail call void @llvm.dbg.value(metadata !{float %val}, i64 0, metadata !{}, metadata !10), !dbg !25 + tail call void @llvm.dbg.value(metadata !{i8 %c}, i64 0, metadata !{}, metadata !12), !dbg !26 %conv = fpext float %val to double, !dbg !27 %conv3 = zext i8 %c to i32, !dbg !27 %call = tail call i32 (i8*, ...)* @printf(i8* getelementptr inbounds ([11 x i8]* @.str, i32 0, i32 0), i8* %ptr, double %conv, i32 %conv3) nounwind optsize, !dbg !27 @@ -28,9 +28,9 @@ define i32 @printer(i8* %ptr, float %val, i8 zeroext %c) nounwind optsize noinline ssp { entry: - tail call void @llvm.dbg.value(metadata !{i8* %ptr}, i64 0, metadata !14), !dbg !30 - tail call void @llvm.dbg.value(metadata !{float %val}, i64 0, metadata !15), !dbg !31 - tail call void @llvm.dbg.value(metadata !{i8 %c}, i64 0, metadata !16), !dbg !32 + tail call void @llvm.dbg.value(metadata !{i8* %ptr}, i64 0, metadata !{}, metadata !14), !dbg !30 + tail call void @llvm.dbg.value(metadata !{float %val}, i64 0, metadata !{}, metadata !15), !dbg !31 + tail call void @llvm.dbg.value(metadata !{i8 %c}, i64 0, metadata !{}, metadata !16), !dbg !32 %conv = fpext float %val to double, !dbg !33 %conv3 = zext i8 %c to i32, !dbg !33 %call = tail call i32 (i8*, ...)* @printf(i8* getelementptr inbounds ([11 x i8]* @.str, i32 0, i32 0), i8* %ptr, double %conv, i32 %conv3) nounwind optsize, !dbg !33 @@ -39,19 +39,19 @@ define i32 @main(i32 %argc, i8** nocapture %argv) nounwind optsize ssp { entry: - tail call void @llvm.dbg.value(metadata !{i32 %argc}, i64 0, metadata !17), !dbg !36 - tail call void @llvm.dbg.value(metadata !{i8** %argv}, i64 0, metadata !18), !dbg !37 + tail call void @llvm.dbg.value(metadata !{i32 %argc}, i64 0, metadata !{}, metadata !17), !dbg !36 + tail call void @llvm.dbg.value(metadata !{i8** %argv}, i64 0, metadata !{}, metadata !18), !dbg !37 %conv = sitofp i32 %argc to double, !dbg !38 %add = fadd double %conv, 5.555552e+05, !dbg !38 %conv1 = fptrunc double %add to float, !dbg !38 - tail call void @llvm.dbg.value(metadata !{float %conv1}, i64 0, metadata !22), !dbg !38 + tail call void @llvm.dbg.value(metadata !{float %conv1}, i64 0, metadata !{}, metadata !22), !dbg !38 %call = tail call i32 @puts(i8* getelementptr inbounds ([6 x i8]* @.str1, i32 0, i32 0)) nounwind optsize, !dbg !39 %add.ptr = getelementptr i8* bitcast (i32 (i32, i8**)* @main to i8*), i32 %argc, !dbg !40 %add5 = add nsw i32 %argc, 97, !dbg !40 %conv6 = trunc i32 %add5 to i8, !dbg !40 - tail call void @llvm.dbg.value(metadata !{i8* %add.ptr}, i64 0, metadata !8) nounwind, !dbg !41 - tail call void @llvm.dbg.value(metadata !{float %conv1}, i64 0, metadata !10) nounwind, !dbg !42 - tail call void @llvm.dbg.value(metadata !{i8 %conv6}, i64 0, metadata !12) nounwind, !dbg !43 + tail call void @llvm.dbg.value(metadata !{i8* %add.ptr}, i64 0, metadata !{}, metadata !8) nounwind, !dbg !41 + tail call void @llvm.dbg.value(metadata !{float %conv1}, i64 0, metadata !{}, metadata !10) nounwind, !dbg !42 + tail call void @llvm.dbg.value(metadata !{i8 %conv6}, i64 0, metadata !{}, metadata !12) nounwind, !dbg !43 %conv.i = fpext float %conv1 to double, !dbg !44 %conv3.i = and i32 %add5, 255, !dbg !44 %call.i = tail call i32 (i8*, ...)* @printf(i8* getelementptr inbounds ([11 x i8]* @.str, i32 0, i32 0), i8* %add.ptr, double %conv.i, i32 %conv3.i) nounwind optsize, !dbg !44 @@ -61,7 +61,7 @@ declare i32 @puts(i8* nocapture) nounwind optsize -declare void @llvm.dbg.value(metadata, i64, metadata) nounwind readnone +declare void @llvm.dbg.value(metadata, i64, metadata, metadata) nounwind readnone !llvm.dbg.cu = !{!2} !llvm.module.flags = !{!53} Index: test/CodeGen/ARM/debug-info-sreg2.ll =================================================================== --- test/CodeGen/ARM/debug-info-sreg2.ll +++ test/CodeGen/ARM/debug-info-sreg2.ll @@ -15,7 +15,7 @@ define void @_Z3foov() optsize ssp { entry: %call = tail call float @_Z3barv() optsize, !dbg !11 - tail call void @llvm.dbg.value(metadata !{float %call}, i64 0, metadata !5), !dbg !11 + tail call void @llvm.dbg.value(metadata !{float %call}, i64 0, metadata !{}, metadata !5), !dbg !11 %call16 = tail call float @_Z2f2v() optsize, !dbg !12 %cmp7 = fcmp olt float %call, %call16, !dbg !12 br i1 %cmp7, label %for.body, label %for.end, !dbg !12 @@ -38,7 +38,7 @@ declare float @_Z2f3f(float) optsize -declare void @llvm.dbg.value(metadata, i64, metadata) nounwind readnone +declare void @llvm.dbg.value(metadata, i64, metadata, metadata) nounwind readnone !llvm.dbg.cu = !{!0} !llvm.module.flags = !{!20} Index: test/CodeGen/Generic/dbg_value.ll =================================================================== --- test/CodeGen/Generic/dbg_value.ll +++ test/CodeGen/Generic/dbg_value.ll @@ -4,11 +4,11 @@ %0 = type { i32, i32 } define void @t(%0*, i32, i32, i32, i32) nounwind { - tail call void @llvm.dbg.value(metadata !{%0* %0}, i64 0, metadata !0) + tail call void @llvm.dbg.value(metadata !{%0* %0}, i64 0, metadata !{}, metadata !0) unreachable } -declare void @llvm.dbg.value(metadata, i64, metadata) nounwind readnone +declare void @llvm.dbg.value(metadata, i64, metadata, metadata) nounwind readnone ; !0 should conform to the format of DIVariable. !0 = metadata !{i32 786689, null, metadata !"a", null, i32 0, null, i32 0, i32 0} ; Index: test/CodeGen/Hexagon/hwloop-dbg.ll =================================================================== --- test/CodeGen/Hexagon/hwloop-dbg.ll +++ test/CodeGen/Hexagon/hwloop-dbg.ll @@ -5,9 +5,9 @@ define void @foo(i32* nocapture %a, i32* nocapture %b) nounwind { entry: - tail call void @llvm.dbg.value(metadata !{i32* %a}, i64 0, metadata !13), !dbg !17 - tail call void @llvm.dbg.value(metadata !{i32* %b}, i64 0, metadata !14), !dbg !18 - tail call void @llvm.dbg.value(metadata !30, i64 0, metadata !15), !dbg !19 + tail call void @llvm.dbg.value(metadata !{i32* %a}, i64 0, metadata !{}, metadata !13), !dbg !17 + tail call void @llvm.dbg.value(metadata !{i32* %b}, i64 0, metadata !{}, metadata !14), !dbg !18 + tail call void @llvm.dbg.value(metadata !30, i64 0, metadata !{}, metadata !15), !dbg !19 br label %for.body, !dbg !19 for.body: ; preds = %for.body, %entry @@ -18,11 +18,11 @@ %i.02 = phi i32 [ 0, %entry ], [ %inc, %for.body ] %b.addr.01 = phi i32* [ %b, %entry ], [ %incdec.ptr, %for.body ] %incdec.ptr = getelementptr inbounds i32* %b.addr.01, i32 1, !dbg !21 - tail call void @llvm.dbg.value(metadata !{i32* %incdec.ptr}, i64 0, metadata !14), !dbg !21 + tail call void @llvm.dbg.value(metadata !{i32* %incdec.ptr}, i64 0, metadata !{}, metadata !14), !dbg !21 %0 = load i32* %b.addr.01, align 4, !dbg !21 store i32 %0, i32* %arrayidx.phi, align 4, !dbg !21 %inc = add nsw i32 %i.02, 1, !dbg !26 - tail call void @llvm.dbg.value(metadata !{i32 %inc}, i64 0, metadata !15), !dbg !26 + tail call void @llvm.dbg.value(metadata !{i32 %inc}, i64 0, metadata !{}, metadata !15), !dbg !26 %exitcond = icmp eq i32 %inc, 10, !dbg !19 %arrayidx.inc = getelementptr i32* %arrayidx.phi, i32 1 br i1 %exitcond, label %for.end, label %for.body, !dbg !19 @@ -31,7 +31,7 @@ ret void, !dbg !27 } -declare void @llvm.dbg.value(metadata, i64, metadata) nounwind readnone +declare void @llvm.dbg.value(metadata, i64, metadata, metadata) nounwind readnone !llvm.dbg.cu = !{!0} Index: test/CodeGen/Inputs/DbgValueOtherTargets.ll =================================================================== --- test/CodeGen/Inputs/DbgValueOtherTargets.ll +++ test/CodeGen/Inputs/DbgValueOtherTargets.ll @@ -3,13 +3,13 @@ define i32 @main() nounwind ssp { entry: ; CHECK: DEBUG_VALUE - call void @llvm.dbg.value(metadata !6, i64 0, metadata !7), !dbg !9 + call void @llvm.dbg.value(metadata !6, i64 0, metadata !{}, metadata !7), !dbg !9 ret i32 0, !dbg !10 } -declare void @llvm.dbg.declare(metadata, metadata) nounwind readnone +declare void @llvm.dbg.declare(metadata, metadata, metadata) nounwind readnone -declare void @llvm.dbg.value(metadata, i64, metadata) nounwind readnone +declare void @llvm.dbg.value(metadata, i64, metadata, metadata) nounwind readnone !llvm.dbg.cu = !{!2} !llvm.module.flags = !{!13} Index: test/CodeGen/PowerPC/dbg.ll =================================================================== --- test/CodeGen/PowerPC/dbg.ll +++ test/CodeGen/PowerPC/dbg.ll @@ -6,13 +6,13 @@ define i32 @main(i32 %argc, i8** nocapture %argv) nounwind readnone { entry: - tail call void @llvm.dbg.value(metadata !{i32 %argc}, i64 0, metadata !15), !dbg !17 - tail call void @llvm.dbg.value(metadata !{i8** %argv}, i64 0, metadata !16), !dbg !18 + tail call void @llvm.dbg.value(metadata !{i32 %argc}, i64 0, metadata !{}, metadata !15), !dbg !17 + tail call void @llvm.dbg.value(metadata !{i8** %argv}, i64 0, metadata !{}, metadata !16), !dbg !18 %add = add nsw i32 %argc, 1, !dbg !19 ret i32 %add, !dbg !19 } -declare void @llvm.dbg.value(metadata, i64, metadata) nounwind readnone +declare void @llvm.dbg.value(metadata, i64, metadata, metadata) nounwind readnone !llvm.dbg.cu = !{!0} !llvm.module.flags = !{!22} Index: test/CodeGen/PowerPC/pr17168.ll =================================================================== --- test/CodeGen/PowerPC/pr17168.ll +++ test/CodeGen/PowerPC/pr17168.ll @@ -25,7 +25,7 @@ for.end1042: ; preds = %for.cond968.preheader, %for.cond964.preheader, %entry %0 = phi i32 [ undef, %for.cond964.preheader ], [ undef, %for.cond968.preheader ], [ undef, %entry ] %1 = load i32* getelementptr inbounds ([3 x i32]* @grid_points, i64 0, i64 0), align 4, !dbg !443, !tbaa !444 - tail call void @llvm.dbg.value(metadata !447, i64 0, metadata !119), !dbg !448 + tail call void @llvm.dbg.value(metadata !447, i64 0, metadata !{}, metadata !119), !dbg !448 %sub10454270 = add nsw i32 %0, -1, !dbg !448 %cmp10464271 = icmp sgt i32 %sub10454270, 1, !dbg !448 %sub11134263 = add nsw i32 %1, -1, !dbg !450 @@ -46,7 +46,7 @@ } ; Function Attrs: nounwind readnone -declare void @llvm.dbg.value(metadata, i64, metadata) #1 +declare void @llvm.dbg.value(metadata, i64, metadata, metadata) #1 attributes #0 = { nounwind "less-precise-fpmad"="false" "no-frame-pointer-elim"="true" "no-frame-pointer-elim-non-leaf" "no-infs-fp-math"="false" "no-nans-fp-math"="false" "stack-protector-buffer-size"="8" "unsafe-fp-math"="false" "use-soft-float"="false" } attributes #1 = { nounwind readnone } Index: test/CodeGen/Thumb/2010-07-15-debugOrdering.ll =================================================================== --- test/CodeGen/Thumb/2010-07-15-debugOrdering.ll +++ test/CodeGen/Thumb/2010-07-15-debugOrdering.ll @@ -25,7 +25,7 @@ %storemerge = phi double [ -1.000000e+00, %4 ], [ 1.000000e+00, %3 ], [ 1.000000e+00, %3 ] ; [#uses=1] %v_6 = icmp slt i32 %1, 2 ; [#uses=1] %storemerge1 = select i1 %v_6, double 1.000000e+00, double -1.000000e+00 ; [#uses=3] - call void @llvm.dbg.value(metadata !{double %storemerge}, i64 0, metadata !91), !dbg !0 + call void @llvm.dbg.value(metadata !{double %storemerge}, i64 0, metadata !{}, metadata !91), !dbg !0 %v_7 = icmp eq i32 %2, 1, !dbg !92 ; [#uses=1] %storemerge2 = select i1 %v_7, double 1.000000e+00, double -1.000000e+00 ; [#uses=3] %v_8 = getelementptr inbounds %0* %0, i32 0, i32 0, i32 0 ; [#uses=1] @@ -40,11 +40,11 @@ ret void, !dbg !98 } -declare void @llvm.dbg.declare(metadata, metadata) nounwind readnone +declare void @llvm.dbg.declare(metadata, metadata, metadata) nounwind readnone declare double @sqrt(double) nounwind readonly -declare void @llvm.dbg.value(metadata, i64, metadata) nounwind readnone +declare void @llvm.dbg.value(metadata, i64, metadata, metadata) nounwind readnone !llvm.dbg.cu = !{!5} !llvm.module.flags = !{!104} Index: test/CodeGen/X86/2009-02-12-DebugInfoVLA.ll =================================================================== --- test/CodeGen/X86/2009-02-12-DebugInfoVLA.ll +++ test/CodeGen/X86/2009-02-12-DebugInfoVLA.ll @@ -14,9 +14,9 @@ %2 = alloca i64 ; [#uses=1] %3 = alloca i64 ; [#uses=6] %"alloca point" = bitcast i32 0 to i32 ; [#uses=0] - call void @llvm.dbg.declare(metadata !{i8** %s1_addr}, metadata !0), !dbg !7 + call void @llvm.dbg.declare(metadata !{i8** %s1_addr}, metadata !{}, metadata !0), !dbg !7 store i8* %s1, i8** %s1_addr - call void @llvm.dbg.declare(metadata !{[0 x i8]** %str.0}, metadata !8), !dbg !7 + call void @llvm.dbg.declare(metadata !{[0 x i8]** %str.0}, metadata !{}, metadata !8), !dbg !7 %4 = call i8* @llvm.stacksave(), !dbg !7 ; [#uses=1] store i8* %4, i8** %saved_stack.1, align 8, !dbg !7 %5 = load i8** %s1_addr, align 8, !dbg !13 ; [#uses=1] @@ -58,7 +58,7 @@ ret i8 %retval12, !dbg !16 } -declare void @llvm.dbg.declare(metadata, metadata) nounwind readnone +declare void @llvm.dbg.declare(metadata, metadata, metadata) nounwind readnone declare i8* @llvm.stacksave() nounwind Index: test/CodeGen/X86/2009-10-16-Scope.ll =================================================================== --- test/CodeGen/X86/2009-10-16-Scope.ll +++ test/CodeGen/X86/2009-10-16-Scope.ll @@ -9,7 +9,7 @@ br label %do.body, !dbg !0 do.body: ; preds = %entry - call void @llvm.dbg.declare(metadata !{i32* %count_}, metadata !4) + call void @llvm.dbg.declare(metadata !{i32* %count_}, metadata !{}, metadata !4) %conv = ptrtoint i32* %count_ to i32, !dbg !0 ; [#uses=1] %call = call i32 @foo(i32 %conv) ssp, !dbg !0 ; [#uses=0] br label %do.end, !dbg !0 @@ -18,7 +18,7 @@ ret void, !dbg !7 } -declare void @llvm.dbg.declare(metadata, metadata) nounwind readnone +declare void @llvm.dbg.declare(metadata, metadata, metadata) nounwind readnone declare i32 @foo(i32) ssp Index: test/CodeGen/X86/2010-01-18-DbgValue.ll =================================================================== --- test/CodeGen/X86/2010-01-18-DbgValue.ll +++ test/CodeGen/X86/2010-01-18-DbgValue.ll @@ -12,7 +12,7 @@ %retval = alloca double ; [#uses=2] %0 = alloca double ; [#uses=2] %"alloca point" = bitcast i32 0 to i32 ; [#uses=0] - call void @llvm.dbg.declare(metadata !{%struct.Rect* %my_r0}, metadata !0), !dbg !15 + call void @llvm.dbg.declare(metadata !{%struct.Rect* %my_r0}, metadata !{}, metadata !0), !dbg !15 %1 = getelementptr inbounds %struct.Rect* %my_r0, i32 0, i32 0, !dbg !16 ; <%struct.Pt*> [#uses=1] %2 = getelementptr inbounds %struct.Pt* %1, i32 0, i32 0, !dbg !16 ; [#uses=1] %3 = load double* %2, align 8, !dbg !16 ; [#uses=1] @@ -26,7 +26,7 @@ ret double %retval1, !dbg !16 } -declare void @llvm.dbg.declare(metadata, metadata) nounwind readnone +declare void @llvm.dbg.declare(metadata, metadata, metadata) nounwind readnone !llvm.dbg.cu = !{!3} !llvm.module.flags = !{!21} Index: test/CodeGen/X86/2010-02-01-DbgValueCrash.ll =================================================================== --- test/CodeGen/X86/2010-02-01-DbgValueCrash.ll +++ test/CodeGen/X86/2010-02-01-DbgValueCrash.ll @@ -8,12 +8,12 @@ define i32 @"main(tart.core.String[])->int32"(i32 %args) { entry: - tail call void @llvm.dbg.value(metadata !14, i64 0, metadata !8) + tail call void @llvm.dbg.value(metadata !14, i64 0, metadata !{}, metadata !8) tail call void @"tart.reflect.ComplexType.create->tart.core.Object"(%tart.reflect.ComplexType* @.type.SwitchStmtTest) ; <%tart.core.Object*> [#uses=2] ret i32 3 } -declare void @llvm.dbg.value(metadata, i64, metadata) nounwind readnone +declare void @llvm.dbg.value(metadata, i64, metadata, metadata) nounwind readnone declare void @"tart.reflect.ComplexType.create->tart.core.Object"(%tart.reflect.ComplexType*) nounwind readnone !0 = metadata !{i32 458769, metadata !15, i32 1, metadata !"4.2.1 (Based on Apple Inc. build 5658) (LLVM build)", i1 true, metadata !"", i32 0, metadata !16, metadata !16, null, null, null, i32 0} ; [ DW_TAG_compile_unit ] Index: test/CodeGen/X86/2010-05-25-DotDebugLoc.ll =================================================================== --- test/CodeGen/X86/2010-05-25-DotDebugLoc.ll +++ test/CodeGen/X86/2010-05-25-DotDebugLoc.ll @@ -11,10 +11,10 @@ define hidden %0 @__divsc3(float %a, float %b, float %c, float %d) nounwind readnone { entry: - tail call void @llvm.dbg.value(metadata !{float %a}, i64 0, metadata !0) - tail call void @llvm.dbg.value(metadata !{float %b}, i64 0, metadata !11) - tail call void @llvm.dbg.value(metadata !{float %c}, i64 0, metadata !12) - tail call void @llvm.dbg.value(metadata !{float %d}, i64 0, metadata !13) + tail call void @llvm.dbg.value(metadata !{float %a}, i64 0, metadata !{}, metadata !0) + tail call void @llvm.dbg.value(metadata !{float %b}, i64 0, metadata !{}, metadata !11) + tail call void @llvm.dbg.value(metadata !{float %c}, i64 0, metadata !{}, metadata !12) + tail call void @llvm.dbg.value(metadata !{float %d}, i64 0, metadata !{}, metadata !13) %0 = tail call float @fabsf(float %c) nounwind readnone, !dbg !19 ; [#uses=1] %1 = tail call float @fabsf(float %d) nounwind readnone, !dbg !19 ; [#uses=1] %2 = fcmp olt float %0, %1, !dbg !19 ; [#uses=1] @@ -22,34 +22,34 @@ bb: ; preds = %entry %3 = fdiv float %c, %d, !dbg !20 ; [#uses=3] - tail call void @llvm.dbg.value(metadata !{float %3}, i64 0, metadata !16), !dbg !20 + tail call void @llvm.dbg.value(metadata !{float %3}, i64 0, metadata !{}, metadata !16), !dbg !20 %4 = fmul float %3, %c, !dbg !21 ; [#uses=1] %5 = fadd float %4, %d, !dbg !21 ; [#uses=2] - tail call void @llvm.dbg.value(metadata !{float %5}, i64 0, metadata !14), !dbg !21 + tail call void @llvm.dbg.value(metadata !{float %5}, i64 0, metadata !{}, metadata !14), !dbg !21 %6 = fmul float %3, %a, !dbg !22 ; [#uses=1] %7 = fadd float %6, %b, !dbg !22 ; [#uses=1] %8 = fdiv float %7, %5, !dbg !22 ; [#uses=1] - tail call void @llvm.dbg.value(metadata !{float %8}, i64 0, metadata !17), !dbg !22 + tail call void @llvm.dbg.value(metadata !{float %8}, i64 0, metadata !{}, metadata !17), !dbg !22 %9 = fmul float %3, %b, !dbg !23 ; [#uses=1] %10 = fsub float %9, %a, !dbg !23 ; [#uses=1] %11 = fdiv float %10, %5, !dbg !23 ; [#uses=1] - tail call void @llvm.dbg.value(metadata !{float %11}, i64 0, metadata !18), !dbg !23 + tail call void @llvm.dbg.value(metadata !{float %11}, i64 0, metadata !{}, metadata !18), !dbg !23 br label %bb2, !dbg !23 bb1: ; preds = %entry %12 = fdiv float %d, %c, !dbg !24 ; [#uses=3] - tail call void @llvm.dbg.value(metadata !{float %12}, i64 0, metadata !16), !dbg !24 + tail call void @llvm.dbg.value(metadata !{float %12}, i64 0, metadata !{}, metadata !16), !dbg !24 %13 = fmul float %12, %d, !dbg !25 ; [#uses=1] %14 = fadd float %13, %c, !dbg !25 ; [#uses=2] - tail call void @llvm.dbg.value(metadata !{float %14}, i64 0, metadata !14), !dbg !25 + tail call void @llvm.dbg.value(metadata !{float %14}, i64 0, metadata !{}, metadata !14), !dbg !25 %15 = fmul float %12, %b, !dbg !26 ; [#uses=1] %16 = fadd float %15, %a, !dbg !26 ; [#uses=1] %17 = fdiv float %16, %14, !dbg !26 ; [#uses=1] - tail call void @llvm.dbg.value(metadata !{float %17}, i64 0, metadata !17), !dbg !26 + tail call void @llvm.dbg.value(metadata !{float %17}, i64 0, metadata !{}, metadata !17), !dbg !26 %18 = fmul float %12, %a, !dbg !27 ; [#uses=1] %19 = fsub float %b, %18, !dbg !27 ; [#uses=1] %20 = fdiv float %19, %14, !dbg !27 ; [#uses=1] - tail call void @llvm.dbg.value(metadata !{float %20}, i64 0, metadata !18), !dbg !27 + tail call void @llvm.dbg.value(metadata !{float %20}, i64 0, metadata !{}, metadata !18), !dbg !27 br label %bb2, !dbg !27 bb2: ; preds = %bb1, %bb @@ -75,9 +75,9 @@ bb8: ; preds = %bb6 %27 = tail call float @copysignf(float 0x7FF0000000000000, float %c) nounwind readnone, !dbg !30 ; [#uses=2] %28 = fmul float %27, %a, !dbg !30 ; [#uses=1] - tail call void @llvm.dbg.value(metadata !{float %28}, i64 0, metadata !17), !dbg !30 + tail call void @llvm.dbg.value(metadata !{float %28}, i64 0, metadata !{}, metadata !17), !dbg !30 %29 = fmul float %27, %b, !dbg !31 ; [#uses=1] - tail call void @llvm.dbg.value(metadata !{float %29}, i64 0, metadata !18), !dbg !31 + tail call void @llvm.dbg.value(metadata !{float %29}, i64 0, metadata !{}, metadata !18), !dbg !31 br label %bb46, !dbg !31 bb9: ; preds = %bb6, %bb4 @@ -107,24 +107,24 @@ bb16: ; preds = %bb15 %iftmp.0.0 = select i1 %33, float 1.000000e+00, float 0.000000e+00 ; [#uses=1] %42 = tail call float @copysignf(float %iftmp.0.0, float %a) nounwind readnone, !dbg !33 ; [#uses=2] - tail call void @llvm.dbg.value(metadata !{float %42}, i64 0, metadata !0), !dbg !33 + tail call void @llvm.dbg.value(metadata !{float %42}, i64 0, metadata !{}, metadata !0), !dbg !33 %43 = fcmp ord float %b, 0.000000e+00 ; [#uses=1] %44 = fsub float %b, %b, !dbg !34 ; [#uses=1] %45 = fcmp uno float %44, 0.000000e+00 ; [#uses=1] %46 = and i1 %43, %45, !dbg !34 ; [#uses=1] %iftmp.1.0 = select i1 %46, float 1.000000e+00, float 0.000000e+00 ; [#uses=1] %47 = tail call float @copysignf(float %iftmp.1.0, float %b) nounwind readnone, !dbg !34 ; [#uses=2] - tail call void @llvm.dbg.value(metadata !{float %47}, i64 0, metadata !11), !dbg !34 + tail call void @llvm.dbg.value(metadata !{float %47}, i64 0, metadata !{}, metadata !11), !dbg !34 %48 = fmul float %42, %c, !dbg !35 ; [#uses=1] %49 = fmul float %47, %d, !dbg !35 ; [#uses=1] %50 = fadd float %48, %49, !dbg !35 ; [#uses=1] %51 = fmul float %50, 0x7FF0000000000000, !dbg !35 ; [#uses=1] - tail call void @llvm.dbg.value(metadata !{float %51}, i64 0, metadata !17), !dbg !35 + tail call void @llvm.dbg.value(metadata !{float %51}, i64 0, metadata !{}, metadata !17), !dbg !35 %52 = fmul float %47, %c, !dbg !36 ; [#uses=1] %53 = fmul float %42, %d, !dbg !36 ; [#uses=1] %54 = fsub float %52, %53, !dbg !36 ; [#uses=1] %55 = fmul float %54, 0x7FF0000000000000, !dbg !36 ; [#uses=1] - tail call void @llvm.dbg.value(metadata !{float %55}, i64 0, metadata !18), !dbg !36 + tail call void @llvm.dbg.value(metadata !{float %55}, i64 0, metadata !{}, metadata !18), !dbg !36 br label %bb46, !dbg !36 bb27: ; preds = %bb15, %bb14, %bb11 @@ -155,24 +155,24 @@ bb35: ; preds = %bb34 %iftmp.2.0 = select i1 %59, float 1.000000e+00, float 0.000000e+00 ; [#uses=1] %67 = tail call float @copysignf(float %iftmp.2.0, float %c) nounwind readnone, !dbg !38 ; [#uses=2] - tail call void @llvm.dbg.value(metadata !{float %67}, i64 0, metadata !12), !dbg !38 + tail call void @llvm.dbg.value(metadata !{float %67}, i64 0, metadata !{}, metadata !12), !dbg !38 %68 = fcmp ord float %d, 0.000000e+00 ; [#uses=1] %69 = fsub float %d, %d, !dbg !39 ; [#uses=1] %70 = fcmp uno float %69, 0.000000e+00 ; [#uses=1] %71 = and i1 %68, %70, !dbg !39 ; [#uses=1] %iftmp.3.0 = select i1 %71, float 1.000000e+00, float 0.000000e+00 ; [#uses=1] %72 = tail call float @copysignf(float %iftmp.3.0, float %d) nounwind readnone, !dbg !39 ; [#uses=2] - tail call void @llvm.dbg.value(metadata !{float %72}, i64 0, metadata !13), !dbg !39 + tail call void @llvm.dbg.value(metadata !{float %72}, i64 0, metadata !{}, metadata !13), !dbg !39 %73 = fmul float %67, %a, !dbg !40 ; [#uses=1] %74 = fmul float %72, %b, !dbg !40 ; [#uses=1] %75 = fadd float %73, %74, !dbg !40 ; [#uses=1] %76 = fmul float %75, 0.000000e+00, !dbg !40 ; [#uses=1] - tail call void @llvm.dbg.value(metadata !{float %76}, i64 0, metadata !17), !dbg !40 + tail call void @llvm.dbg.value(metadata !{float %76}, i64 0, metadata !{}, metadata !17), !dbg !40 %77 = fmul float %67, %b, !dbg !41 ; [#uses=1] %78 = fmul float %72, %a, !dbg !41 ; [#uses=1] %79 = fsub float %77, %78, !dbg !41 ; [#uses=1] %80 = fmul float %79, 0.000000e+00, !dbg !41 ; [#uses=1] - tail call void @llvm.dbg.value(metadata !{float %80}, i64 0, metadata !18), !dbg !41 + tail call void @llvm.dbg.value(metadata !{float %80}, i64 0, metadata !{}, metadata !18), !dbg !41 br label %bb46, !dbg !41 bb46: ; preds = %bb35, %bb34, %bb33, %bb30, %bb16, %bb8, %bb2 @@ -196,7 +196,7 @@ declare float @copysignf(float, float) nounwind readnone -declare void @llvm.dbg.value(metadata, i64, metadata) nounwind readnone +declare void @llvm.dbg.value(metadata, i64, metadata, metadata) nounwind readnone !llvm.dbg.cu = !{!3} !llvm.module.flags = !{!48} Index: test/CodeGen/X86/2010-05-26-DotDebugLoc.ll =================================================================== --- test/CodeGen/X86/2010-05-26-DotDebugLoc.ll +++ test/CodeGen/X86/2010-05-26-DotDebugLoc.ll @@ -9,7 +9,7 @@ define i8* @bar(%struct.a* %myvar) nounwind optsize noinline ssp { entry: - tail call void @llvm.dbg.value(metadata !{%struct.a* %myvar}, i64 0, metadata !8) + tail call void @llvm.dbg.value(metadata !{%struct.a* %myvar}, i64 0, metadata !{}, metadata !8) %0 = getelementptr inbounds %struct.a* %myvar, i64 0, i32 0, !dbg !28 ; [#uses=1] %1 = load i32* %0, align 8, !dbg !28 ; [#uses=1] tail call void @foo(i32 %1) nounwind optsize noinline ssp, !dbg !28 @@ -19,7 +19,7 @@ declare void @foo(i32) nounwind optsize noinline ssp -declare void @llvm.dbg.value(metadata, i64, metadata) nounwind readnone +declare void @llvm.dbg.value(metadata, i64, metadata, metadata) nounwind readnone !llvm.dbg.cu = !{!2} !llvm.module.flags = !{!38} Index: test/CodeGen/X86/2010-05-28-Crash.ll =================================================================== --- test/CodeGen/X86/2010-05-28-Crash.ll +++ test/CodeGen/X86/2010-05-28-Crash.ll @@ -4,19 +4,19 @@ define i32 @foo(i32 %y) nounwind optsize ssp { entry: - tail call void @llvm.dbg.value(metadata !{i32 %y}, i64 0, metadata !0) + tail call void @llvm.dbg.value(metadata !{i32 %y}, i64 0, metadata !{}, metadata !0) %0 = tail call i32 (...)* @zoo(i32 %y) nounwind, !dbg !9 ; [#uses=1] ret i32 %0, !dbg !9 } declare i32 @zoo(...) -declare void @llvm.dbg.value(metadata, i64, metadata) nounwind readnone +declare void @llvm.dbg.value(metadata, i64, metadata, metadata) nounwind readnone define i32 @bar(i32 %x) nounwind optsize ssp { entry: - tail call void @llvm.dbg.value(metadata !{i32 %x}, i64 0, metadata !7) - tail call void @llvm.dbg.value(metadata !11, i64 0, metadata !0) nounwind + tail call void @llvm.dbg.value(metadata !{i32 %x}, i64 0, metadata !{}, metadata !7) + tail call void @llvm.dbg.value(metadata !11, i64 0, metadata !{}, metadata !0) nounwind %0 = tail call i32 (...)* @zoo(i32 1) nounwind, !dbg !12 ; [#uses=1] %1 = add nsw i32 %0, %x, !dbg !13 ; [#uses=1] ret i32 %1, !dbg !13 Index: test/CodeGen/X86/2010-06-01-DeadArg-DbgInfo.ll =================================================================== --- test/CodeGen/X86/2010-06-01-DeadArg-DbgInfo.ll +++ test/CodeGen/X86/2010-06-01-DeadArg-DbgInfo.ll @@ -10,14 +10,14 @@ define i32 @_ZN3foo3bazEi(%struct.foo* nocapture %this, i32 %x) nounwind readnone optsize noinline ssp align 2 { ;CHECK: DEBUG_VALUE: baz:this <- RDI{{$}} entry: - tail call void @llvm.dbg.value(metadata !{%struct.foo* %this}, i64 0, metadata !15) - tail call void @llvm.dbg.value(metadata !{i32 %x}, i64 0, metadata !16) + tail call void @llvm.dbg.value(metadata !{%struct.foo* %this}, i64 0, metadata !{}, metadata !15) + tail call void @llvm.dbg.value(metadata !{i32 %x}, i64 0, metadata !{}, metadata !16) %0 = mul nsw i32 %x, 7, !dbg !29 ; [#uses=1] %1 = add nsw i32 %0, 1, !dbg !29 ; [#uses=1] ret i32 %1, !dbg !29 } -declare void @llvm.dbg.value(metadata, i64, metadata) nounwind readnone +declare void @llvm.dbg.value(metadata, i64, metadata, metadata) nounwind readnone !llvm.dbg.cu = !{!4} !llvm.module.flags = !{!34} Index: test/CodeGen/X86/2010-07-06-DbgCrash.ll =================================================================== --- test/CodeGen/X86/2010-07-06-DbgCrash.ll +++ test/CodeGen/X86/2010-07-06-DbgCrash.ll @@ -23,9 +23,9 @@ define i32 @main() nounwind ssp { bb.nph: - tail call void @llvm.dbg.declare(metadata !101, metadata !102), !dbg !107 + tail call void @llvm.dbg.declare(metadata !101, metadata !{}, metadata !102), !dbg !107 ret i32 0, !dbg !107 } -declare void @llvm.dbg.declare(metadata, metadata) nounwind readnone +declare void @llvm.dbg.declare(metadata, metadata, metadata) nounwind readnone Index: test/CodeGen/X86/2010-08-04-StackVariable.ll =================================================================== --- test/CodeGen/X86/2010-08-04-StackVariable.ll +++ test/CodeGen/X86/2010-08-04-StackVariable.ll @@ -6,8 +6,8 @@ define i32 @_Z3fooi4SVal(i32 %i, %struct.SVal* noalias %location) nounwind ssp { entry: %"alloca point" = bitcast i32 0 to i32 ; [#uses=0] - call void @llvm.dbg.value(metadata !{i32 %i}, i64 0, metadata !23), !dbg !24 - call void @llvm.dbg.value(metadata !{%struct.SVal* %location}, i64 0, metadata !25), !dbg !24 + call void @llvm.dbg.value(metadata !{i32 %i}, i64 0, metadata !{}, metadata !23), !dbg !24 + call void @llvm.dbg.value(metadata !{%struct.SVal* %location}, i64 0, metadata !{}, metadata !25), !dbg !24 %0 = icmp ne i32 %i, 0, !dbg !27 ; [#uses=1] br i1 %0, label %bb, label %bb1, !dbg !27 @@ -34,7 +34,7 @@ define linkonce_odr void @_ZN4SValC1Ev(%struct.SVal* %this) nounwind ssp align 2 { entry: %"alloca point" = bitcast i32 0 to i32 ; [#uses=0] - call void @llvm.dbg.value(metadata !{%struct.SVal* %this}, i64 0, metadata !31), !dbg !34 + call void @llvm.dbg.value(metadata !{%struct.SVal* %this}, i64 0, metadata !{}, metadata !31), !dbg !34 %0 = getelementptr inbounds %struct.SVal* %this, i32 0, i32 0, !dbg !34 ; [#uses=1] store i8* null, i8** %0, align 8, !dbg !34 %1 = getelementptr inbounds %struct.SVal* %this, i32 0, i32 1, !dbg !34 ; [#uses=1] @@ -45,14 +45,14 @@ ret void, !dbg !35 } -declare void @llvm.dbg.declare(metadata, metadata) nounwind readnone +declare void @llvm.dbg.declare(metadata, metadata, metadata) nounwind readnone define i32 @main() nounwind ssp { entry: %0 = alloca %struct.SVal ; <%struct.SVal*> [#uses=3] %v = alloca %struct.SVal ; <%struct.SVal*> [#uses=4] %"alloca point" = bitcast i32 0 to i32 ; [#uses=0] - call void @llvm.dbg.declare(metadata !{%struct.SVal* %v}, metadata !38), !dbg !41 + call void @llvm.dbg.declare(metadata !{%struct.SVal* %v}, metadata !{}, metadata !38), !dbg !41 call void @_ZN4SValC1Ev(%struct.SVal* %v) nounwind, !dbg !41 %1 = getelementptr inbounds %struct.SVal* %v, i32 0, i32 1, !dbg !42 ; [#uses=1] store i32 1, i32* %1, align 8, !dbg !42 @@ -65,14 +65,14 @@ %7 = load i32* %6, align 8, !dbg !43 ; [#uses=1] store i32 %7, i32* %5, align 8, !dbg !43 %8 = call i32 @_Z3fooi4SVal(i32 2, %struct.SVal* noalias %0) nounwind, !dbg !43 ; [#uses=0] - call void @llvm.dbg.value(metadata !{i32 %8}, i64 0, metadata !44), !dbg !43 + call void @llvm.dbg.value(metadata !{i32 %8}, i64 0, metadata !{}, metadata !44), !dbg !43 br label %return, !dbg !45 return: ; preds = %entry ret i32 0, !dbg !45 } -declare void @llvm.dbg.value(metadata, i64, metadata) nounwind readnone +declare void @llvm.dbg.value(metadata, i64, metadata, metadata) nounwind readnone !llvm.dbg.cu = !{!3} !llvm.module.flags = !{!49} Index: test/CodeGen/X86/2010-11-02-DbgParameter.ll =================================================================== --- test/CodeGen/X86/2010-11-02-DbgParameter.ll +++ test/CodeGen/X86/2010-11-02-DbgParameter.ll @@ -9,11 +9,11 @@ define i32 @foo(%struct.bar* nocapture %i) nounwind readnone optsize noinline ssp { ; CHECK: TAG_formal_parameter entry: - tail call void @llvm.dbg.value(metadata !{%struct.bar* %i}, i64 0, metadata !6), !dbg !12 + tail call void @llvm.dbg.value(metadata !{%struct.bar* %i}, i64 0, metadata !{}, metadata !6), !dbg !12 ret i32 1, !dbg !13 } -declare void @llvm.dbg.value(metadata, i64, metadata) nounwind readnone +declare void @llvm.dbg.value(metadata, i64, metadata, metadata) nounwind readnone !llvm.dbg.cu = !{!2} !llvm.module.flags = !{!19} Index: test/CodeGen/X86/2011-01-24-DbgValue-Before-Use.ll =================================================================== --- test/CodeGen/X86/2011-01-24-DbgValue-Before-Use.ll +++ test/CodeGen/X86/2011-01-24-DbgValue-Before-Use.ll @@ -22,8 +22,8 @@ define i64 @gcd(i64 %a, i64 %b) nounwind readnone optsize noinline ssp { entry: - tail call void @llvm.dbg.value(metadata !{i64 %a}, i64 0, metadata !10), !dbg !18 - tail call void @llvm.dbg.value(metadata !{i64 %b}, i64 0, metadata !11), !dbg !19 + tail call void @llvm.dbg.value(metadata !{i64 %a}, i64 0, metadata !{}, metadata !10), !dbg !18 + tail call void @llvm.dbg.value(metadata !{i64 %b}, i64 0, metadata !{}, metadata !11), !dbg !19 br label %while.body, !dbg !20 while.body: ; preds = %while.body, %entry @@ -34,14 +34,14 @@ br i1 %cmp, label %if.then, label %while.body, !dbg !23 if.then: ; preds = %while.body - tail call void @llvm.dbg.value(metadata !{i64 %rem}, i64 0, metadata !12), !dbg !21 + tail call void @llvm.dbg.value(metadata !{i64 %rem}, i64 0, metadata !{}, metadata !12), !dbg !21 ret i64 %b.addr.0, !dbg !23 } define i32 @main() nounwind optsize ssp { entry: %call = tail call i32 @rand() nounwind optsize, !dbg !24 - tail call void @llvm.dbg.value(metadata !{i32 %call}, i64 0, metadata !14), !dbg !24 + tail call void @llvm.dbg.value(metadata !{i32 %call}, i64 0, metadata !{}, metadata !14), !dbg !24 %cmp = icmp ugt i32 %call, 21, !dbg !25 br i1 %cmp, label %cond.true, label %cond.end, !dbg !25 @@ -51,7 +51,7 @@ cond.end: ; preds = %entry, %cond.true %cond = phi i32 [ %call1, %cond.true ], [ %call, %entry ], !dbg !25 - tail call void @llvm.dbg.value(metadata !{i32 %cond}, i64 0, metadata !17), !dbg !25 + tail call void @llvm.dbg.value(metadata !{i32 %cond}, i64 0, metadata !{}, metadata !17), !dbg !25 %conv = sext i32 %cond to i64, !dbg !26 %conv5 = zext i32 %call to i64, !dbg !26 %call6 = tail call i64 @gcd(i64 %conv, i64 %conv5) optsize, !dbg !26 @@ -71,7 +71,7 @@ declare i32 @printf(i8* nocapture, ...) nounwind optsize -declare void @llvm.dbg.value(metadata, i64, metadata) nounwind readnone +declare void @llvm.dbg.value(metadata, i64, metadata, metadata) nounwind readnone declare i32 @puts(i8* nocapture) nounwind Index: test/CodeGen/X86/2012-11-30-handlemove-dbg.ll =================================================================== --- test/CodeGen/X86/2012-11-30-handlemove-dbg.ll +++ test/CodeGen/X86/2012-11-30-handlemove-dbg.ll @@ -12,11 +12,11 @@ %struct.hgstruct.2.29 = type { %struct.bnode.1.28*, [3 x double], double, [3 x double] } %struct.bnode.1.28 = type { i16, double, [3 x double], i32, i32, [3 x double], [3 x double], [3 x double], double, %struct.bnode.1.28*, %struct.bnode.1.28* } -declare void @llvm.dbg.declare(metadata, metadata) nounwind readnone +declare void @llvm.dbg.declare(metadata, metadata, metadata) nounwind readnone define signext i16 @subdivp(%struct.node.0.27* nocapture %p, double %dsq, double %tolsq, %struct.hgstruct.2.29* nocapture byval align 8 %hg) nounwind uwtable readonly ssp { entry: - call void @llvm.dbg.declare(metadata !{%struct.hgstruct.2.29* %hg}, metadata !4) + call void @llvm.dbg.declare(metadata !{%struct.hgstruct.2.29* %hg}, metadata !{}, metadata !4) %type = getelementptr inbounds %struct.node.0.27* %p, i64 0, i32 0 %0 = load i16* %type, align 2 %cmp = icmp eq i16 %0, 1 @@ -33,7 +33,7 @@ ret i16 %retval.0 } -declare void @llvm.dbg.value(metadata, i64, metadata) nounwind readnone +declare void @llvm.dbg.value(metadata, i64, metadata, metadata) nounwind readnone !llvm.dbg.cu = !{!0} !llvm.module.flags = !{!12} Index: test/CodeGen/X86/2012-11-30-misched-dbg.ll =================================================================== --- test/CodeGen/X86/2012-11-30-misched-dbg.ll +++ test/CodeGen/X86/2012-11-30-misched-dbg.ll @@ -12,7 +12,7 @@ @.str15 = external hidden unnamed_addr constant [6 x i8], align 1 -declare void @llvm.dbg.declare(metadata, metadata) nounwind readnone +declare void @llvm.dbg.declare(metadata, metadata, metadata) nounwind readnone define i32 @AttachGalley(%union.rec** nocapture %suspend_pt) nounwind uwtable ssp { entry: @@ -43,7 +43,7 @@ br label %if.then4073 if.then4073: ; preds = %if.then3344 - call void @llvm.dbg.declare(metadata !{[20 x i8]* %num14075}, metadata !4) + call void @llvm.dbg.declare(metadata !{[20 x i8]* %num14075}, metadata !{}, metadata !4) %arraydecay4078 = getelementptr inbounds [20 x i8]* %num14075, i64 0, i64 0 %0 = load i32* undef, align 4 %add4093 = add nsw i32 %0, 0 @@ -108,7 +108,7 @@ unreachable cond.end: ; preds = %entry - call void @llvm.dbg.declare(metadata !{%"class.__gnu_cxx::hash_map"* %X}, metadata !31) + call void @llvm.dbg.declare(metadata !{%"class.__gnu_cxx::hash_map"* %X}, metadata !{}, metadata !31) %_M_num_elements.i.i.i.i = getelementptr inbounds %"class.__gnu_cxx::hash_map"* %X, i64 0, i32 0, i32 5 invoke void @_Znwm() to label %exit.i unwind label %lpad2.i.i.i.i Index: test/CodeGen/X86/2012-11-30-regpres-dbg.ll =================================================================== --- test/CodeGen/X86/2012-11-30-regpres-dbg.ll +++ test/CodeGen/X86/2012-11-30-regpres-dbg.ll @@ -9,7 +9,7 @@ %struct.btCompoundLeafCallback = type { i32, i32 } -declare void @llvm.dbg.declare(metadata, metadata) nounwind readnone +declare void @llvm.dbg.declare(metadata, metadata, metadata) nounwind readnone define void @test() unnamed_addr uwtable ssp align 2 { entry: @@ -20,7 +20,7 @@ unreachable if.end: ; preds = %entry - call void @llvm.dbg.declare(metadata !{%struct.btCompoundLeafCallback* %callback}, metadata !3) + call void @llvm.dbg.declare(metadata !{%struct.btCompoundLeafCallback* %callback}, metadata !{}, metadata !3) %m = getelementptr inbounds %struct.btCompoundLeafCallback* %callback, i64 0, i32 1 store i32 0, i32* undef, align 8 %cmp12447 = icmp sgt i32 undef, 0 Index: test/CodeGen/X86/MachineSink-DbgValue.ll =================================================================== --- test/CodeGen/X86/MachineSink-DbgValue.ll +++ test/CodeGen/X86/MachineSink-DbgValue.ll @@ -4,10 +4,10 @@ target triple = "x86_64-apple-macosx10.7.0" define i32 @foo(i32 %i, i32* nocapture %c) nounwind uwtable readonly ssp { - tail call void @llvm.dbg.value(metadata !{i32 %i}, i64 0, metadata !6), !dbg !12 + tail call void @llvm.dbg.value(metadata !{i32 %i}, i64 0, metadata !{}, metadata !6), !dbg !12 %ab = load i32* %c, align 1, !dbg !14 - tail call void @llvm.dbg.value(metadata !{i32* %c}, i64 0, metadata !7), !dbg !13 - tail call void @llvm.dbg.value(metadata !{i32 %ab}, i64 0, metadata !10), !dbg !14 + tail call void @llvm.dbg.value(metadata !{i32* %c}, i64 0, metadata !{}, metadata !7), !dbg !13 + tail call void @llvm.dbg.value(metadata !{i32 %ab}, i64 0, metadata !{}, metadata !10), !dbg !14 %cd = icmp eq i32 %i, 42, !dbg !15 br i1 %cd, label %bb1, label %bb2, !dbg !15 @@ -23,7 +23,7 @@ ret i32 %.0, !dbg !17 } -declare void @llvm.dbg.value(metadata, i64, metadata) nounwind readnone +declare void @llvm.dbg.value(metadata, i64, metadata, metadata) nounwind readnone !llvm.dbg.cu = !{!0} !llvm.module.flags = !{!22} Index: test/CodeGen/X86/StackColoring-dbg.ll =================================================================== --- test/CodeGen/X86/StackColoring-dbg.ll +++ test/CodeGen/X86/StackColoring-dbg.ll @@ -5,7 +5,7 @@ target datalayout = "e-p:64:64:64-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:64:64-f32:32:32-f64:64:64-v64:64:64-v128:128:128-a0:0:64-s0:64:64-f80:128:128-n8:16:32:64-S128" target triple = "x86_64-apple-macosx10.8.0" -declare void @llvm.dbg.declare(metadata, metadata) nounwind readnone +declare void @llvm.dbg.declare(metadata, metadata, metadata) nounwind readnone define void @foo() nounwind uwtable ssp { entry: @@ -17,7 +17,7 @@ for.body: call void @llvm.lifetime.end(i64 -1, i8* %0) nounwind call void @llvm.lifetime.start(i64 -1, i8* %x.i) nounwind - call void @llvm.dbg.declare(metadata !{i8* %x.i}, metadata !22) nounwind + call void @llvm.dbg.declare(metadata !{i8* %x.i}, metadata !{}, metadata !22) nounwind br label %for.body } Index: test/CodeGen/X86/dbg-changes-codegen-branch-folding.ll =================================================================== --- test/CodeGen/X86/dbg-changes-codegen-branch-folding.ll +++ test/CodeGen/X86/dbg-changes-codegen-branch-folding.ll @@ -52,48 +52,48 @@ entry: %var1 = alloca %struct.AAA3, align 1 %var2 = alloca %struct.AAA3, align 1 - tail call void @llvm.dbg.value(metadata !{i32 %param1}, i64 0, metadata !30), !dbg !47 - tail call void @llvm.dbg.value(metadata !{i32 %param2}, i64 0, metadata !31), !dbg !47 - tail call void @llvm.dbg.value(metadata !48, i64 0, metadata !32), !dbg !49 + tail call void @llvm.dbg.value(metadata !{i32 %param1}, i64 0, metadata !{}, metadata !30), !dbg !47 + tail call void @llvm.dbg.value(metadata !{i32 %param2}, i64 0, metadata !{}, metadata !31), !dbg !47 + tail call void @llvm.dbg.value(metadata !48, i64 0, metadata !{}, metadata !32), !dbg !49 %tobool = icmp eq i32 %param2, 0, !dbg !50 br i1 %tobool, label %if.end, label %if.then, !dbg !50 if.then: ; preds = %entry %call = tail call i8* @_Z5i2stri(i32 %param2), !dbg !52 - tail call void @llvm.dbg.value(metadata !{i8* %call}, i64 0, metadata !32), !dbg !49 + tail call void @llvm.dbg.value(metadata !{i8* %call}, i64 0, metadata !{}, metadata !32), !dbg !49 br label %if.end, !dbg !54 if.end: ; preds = %entry, %if.then - tail call void @llvm.dbg.value(metadata !{%struct.AAA3* %var1}, i64 0, metadata !33), !dbg !55 - tail call void @llvm.dbg.value(metadata !{%struct.AAA3* %var1}, i64 0, metadata !56), !dbg !57 - tail call void @llvm.dbg.value(metadata !58, i64 0, metadata !59), !dbg !60 + tail call void @llvm.dbg.value(metadata !{%struct.AAA3* %var1}, i64 0, metadata !{}, metadata !33), !dbg !55 + tail call void @llvm.dbg.value(metadata !{%struct.AAA3* %var1}, i64 0, metadata !{}, metadata !56), !dbg !57 + tail call void @llvm.dbg.value(metadata !58, i64 0, metadata !{}, metadata !59), !dbg !60 %arraydecay.i = getelementptr inbounds %struct.AAA3* %var1, i64 0, i32 0, i64 0, !dbg !61 call void @_Z3fooPcjPKc(i8* %arraydecay.i, i32 4, i8* getelementptr inbounds ([1 x i8]* @.str, i64 0, i64 0)), !dbg !61 - call void @llvm.dbg.value(metadata !{%struct.AAA3* %var2}, i64 0, metadata !34), !dbg !63 - call void @llvm.dbg.value(metadata !{%struct.AAA3* %var2}, i64 0, metadata !64), !dbg !65 - call void @llvm.dbg.value(metadata !58, i64 0, metadata !66), !dbg !67 + call void @llvm.dbg.value(metadata !{%struct.AAA3* %var2}, i64 0, metadata !{}, metadata !34), !dbg !63 + call void @llvm.dbg.value(metadata !{%struct.AAA3* %var2}, i64 0, metadata !{}, metadata !64), !dbg !65 + call void @llvm.dbg.value(metadata !58, i64 0, metadata !{}, metadata !66), !dbg !67 %arraydecay.i5 = getelementptr inbounds %struct.AAA3* %var2, i64 0, i32 0, i64 0, !dbg !68 call void @_Z3fooPcjPKc(i8* %arraydecay.i5, i32 4, i8* getelementptr inbounds ([1 x i8]* @.str, i64 0, i64 0)), !dbg !68 %tobool1 = icmp eq i32 %param1, 0, !dbg !69 - call void @llvm.dbg.value(metadata !{%struct.AAA3* %var2}, i64 0, metadata !34), !dbg !63 + call void @llvm.dbg.value(metadata !{%struct.AAA3* %var2}, i64 0, metadata !{}, metadata !34), !dbg !63 br i1 %tobool1, label %if.else, label %if.then2, !dbg !69 if.then2: ; preds = %if.end - call void @llvm.dbg.value(metadata !{%struct.AAA3* %var2}, i64 0, metadata !71), !dbg !73 - call void @llvm.dbg.value(metadata !74, i64 0, metadata !75), !dbg !76 + call void @llvm.dbg.value(metadata !{%struct.AAA3* %var2}, i64 0, metadata !{}, metadata !71), !dbg !73 + call void @llvm.dbg.value(metadata !74, i64 0, metadata !{}, metadata !75), !dbg !76 call void @_Z3fooPcjPKc(i8* %arraydecay.i5, i32 4, i8* getelementptr inbounds ([2 x i8]* @.str1, i64 0, i64 0)), !dbg !76 br label %if.end3, !dbg !72 if.else: ; preds = %if.end - call void @llvm.dbg.value(metadata !{%struct.AAA3* %var2}, i64 0, metadata !77), !dbg !79 - call void @llvm.dbg.value(metadata !80, i64 0, metadata !81), !dbg !82 + call void @llvm.dbg.value(metadata !{%struct.AAA3* %var2}, i64 0, metadata !{}, metadata !77), !dbg !79 + call void @llvm.dbg.value(metadata !80, i64 0, metadata !{}, metadata !81), !dbg !82 call void @_Z3fooPcjPKc(i8* %arraydecay.i5, i32 4, i8* getelementptr inbounds ([2 x i8]* @.str2, i64 0, i64 0)), !dbg !82 br label %if.end3 if.end3: ; preds = %if.else, %if.then2 - call void @llvm.dbg.value(metadata !{%struct.AAA3* %var1}, i64 0, metadata !33), !dbg !55 - call void @llvm.dbg.value(metadata !{%struct.AAA3* %var1}, i64 0, metadata !83), !dbg !85 - call void @llvm.dbg.value(metadata !58, i64 0, metadata !86), !dbg !87 + call void @llvm.dbg.value(metadata !{%struct.AAA3* %var1}, i64 0, metadata !{}, metadata !33), !dbg !55 + call void @llvm.dbg.value(metadata !{%struct.AAA3* %var1}, i64 0, metadata !{}, metadata !83), !dbg !85 + call void @llvm.dbg.value(metadata !58, i64 0, metadata !{}, metadata !86), !dbg !87 call void @_Z3fooPcjPKc(i8* %arraydecay.i, i32 4, i8* getelementptr inbounds ([1 x i8]* @.str, i64 0, i64 0)), !dbg !87 ret void, !dbg !88 } @@ -103,7 +103,7 @@ declare void @_Z3fooPcjPKc(i8*, i32, i8*) #1 ; Function Attrs: nounwind readnone -declare void @llvm.dbg.value(metadata, i64, metadata) #2 +declare void @llvm.dbg.value(metadata, i64, metadata, metadata) #2 attributes #0 = { uwtable "less-precise-fpmad"="false" "no-frame-pointer-elim"="false" "no-infs-fp-math"="false" "no-nans-fp-math"="false" "stack-protector-buffer-size"="8" "unsafe-fp-math"="false" "use-soft-float"="false" } attributes #1 = { "less-precise-fpmad"="false" "no-frame-pointer-elim"="false" "no-infs-fp-math"="false" "no-nans-fp-math"="false" "stack-protector-buffer-size"="8" "unsafe-fp-math"="false" "use-soft-float"="false" } Index: test/CodeGen/X86/dbg-changes-codegen.ll =================================================================== --- test/CodeGen/X86/dbg-changes-codegen.ll +++ test/CodeGen/X86/dbg-changes-codegen.ll @@ -44,7 +44,7 @@ define zeroext i1 @_ZN3Foo3batEv(%struct.Foo* %this) #0 align 2 { entry: %0 = load %struct.Foo** @pfoo, align 8 - tail call void @llvm.dbg.value(metadata !{%struct.Foo* %0}, i64 0, metadata !62) + tail call void @llvm.dbg.value(metadata !{%struct.Foo* %0}, i64 0, metadata !{}, metadata !62) %cmp.i = icmp eq %struct.Foo* %0, %this ret i1 %cmp.i } @@ -53,7 +53,7 @@ define void @_Z3bazv() #1 { entry: %0 = load %struct.Wibble** @wibble1, align 8 - tail call void @llvm.dbg.value(metadata !64, i64 0, metadata !65) + tail call void @llvm.dbg.value(metadata !64, i64 0, metadata !{}, metadata !65) %1 = load %struct.Wibble** @wibble2, align 8 %cmp.i = icmp ugt %struct.Wibble* %1, %0 br i1 %cmp.i, label %if.then.i, label %_ZN7Flibble3barEP6Wibble.exit @@ -69,7 +69,7 @@ } ; Function Attrs: nounwind readnone -declare void @llvm.dbg.value(metadata, i64, metadata) #2 +declare void @llvm.dbg.value(metadata, i64, metadata, metadata) #2 attributes #0 = { nounwind readonly uwtable "less-precise-fpmad"="false" "no-frame-pointer-elim"="false" "no-frame-pointer-elim-non-leaf"="false" "no-infs-fp-math"="false" "no-nans-fp-math"="false" "unsafe-fp-math"="false" "use-soft-float"="false" } attributes #1 = { nounwind uwtable "less-precise-fpmad"="false" "no-frame-pointer-elim"="false" "no-frame-pointer-elim-non-leaf"="false" "no-infs-fp-math"="false" "no-nans-fp-math"="false" "unsafe-fp-math"="false" "use-soft-float"="false" } Index: test/CodeGen/X86/fpstack-debuginstr-kill.ll =================================================================== --- test/CodeGen/X86/fpstack-debuginstr-kill.ll +++ test/CodeGen/X86/fpstack-debuginstr-kill.ll @@ -32,14 +32,14 @@ unreachable if.end41.i2210: ; preds = %if.end511 - call void @llvm.dbg.value(metadata !{x86_fp80 %src.sroa.0.0.src.sroa.0.0.2280}, i64 0, metadata !20) + call void @llvm.dbg.value(metadata !{x86_fp80 %src.sroa.0.0.src.sroa.0.0.2280}, i64 0, metadata !{}, metadata !20) unreachable sw.bb992: ; preds = %if.end511 ret void } -declare void @llvm.dbg.value(metadata, i64, metadata) +declare void @llvm.dbg.value(metadata, i64, metadata, metadata) !llvm.dbg.cu = !{!0} !llvm.module.flags = !{!24, !25} Index: test/CodeGen/X86/stack-protector-dbginfo.ll =================================================================== --- test/CodeGen/X86/stack-protector-dbginfo.ll +++ test/CodeGen/X86/stack-protector-dbginfo.ll @@ -10,15 +10,15 @@ ; Function Attrs: nounwind sspreq define i32 @_Z18read_response_sizev() #0 { entry: - tail call void @llvm.dbg.value(metadata !22, i64 0, metadata !23), !dbg !39 + tail call void @llvm.dbg.value(metadata !22, i64 0, metadata !{}, metadata !23), !dbg !39 %0 = load i64* getelementptr inbounds ({ i64, [56 x i8] }* @a, i32 0, i32 0), align 8, !dbg !40 - tail call void @llvm.dbg.value(metadata !63, i64 0, metadata !64), !dbg !71 + tail call void @llvm.dbg.value(metadata !63, i64 0, metadata !{}, metadata !64), !dbg !71 %1 = trunc i64 %0 to i32 ret i32 %1 } ; Function Attrs: nounwind readnone -declare void @llvm.dbg.value(metadata, i64, metadata) +declare void @llvm.dbg.value(metadata, i64, metadata, metadata) attributes #0 = { sspreq } Index: test/CodeGen/XCore/dwarf_debug.ll =================================================================== --- test/CodeGen/XCore/dwarf_debug.ll +++ test/CodeGen/XCore/dwarf_debug.ll @@ -13,13 +13,13 @@ entry: %a.addr = alloca i32, align 4 store i32 %a, i32* %a.addr, align 4 - call void @llvm.dbg.declare(metadata !{i32* %a.addr}, metadata !11), !dbg !12 + call void @llvm.dbg.declare(metadata !{i32* %a.addr}, metadata !{}, metadata !11), !dbg !12 %0 = load i32* %a.addr, align 4, !dbg !12 %add = add nsw i32 %0, 1, !dbg !12 ret i32 %add, !dbg !12 } -declare void @llvm.dbg.declare(metadata, metadata) +declare void @llvm.dbg.declare(metadata, metadata, metadata) !llvm.dbg.cu = !{!0} !llvm.module.flags = !{!9, !10} Index: test/DebugInfo/2009-11-10-CurrentFn.ll =================================================================== --- test/DebugInfo/2009-11-10-CurrentFn.ll +++ test/DebugInfo/2009-11-10-CurrentFn.ll @@ -8,7 +8,7 @@ declare void @foo(...) -declare void @llvm.dbg.value(metadata, i64, metadata) nounwind readnone +declare void @llvm.dbg.value(metadata, i64, metadata, metadata) nounwind readnone !llvm.dbg.cu = !{!0} !llvm.module.flags = !{!18} Index: test/DebugInfo/2010-03-12-llc-crash.ll =================================================================== --- test/DebugInfo/2010-03-12-llc-crash.ll +++ test/DebugInfo/2010-03-12-llc-crash.ll @@ -1,11 +1,11 @@ ; RUN: llc -O0 < %s -o /dev/null ; llc should not crash on this invalid input. ; PR6588 -declare void @llvm.dbg.declare(metadata, metadata) nounwind readnone +declare void @llvm.dbg.declare(metadata, metadata, metadata) nounwind readnone define void @foo() { entry: - call void @llvm.dbg.declare(metadata !{i32* undef}, metadata !0) + call void @llvm.dbg.declare(metadata !{i32* undef}, metadata !{}, metadata !0) ret void } Index: test/DebugInfo/2010-03-19-DbgDeclare.ll =================================================================== --- test/DebugInfo/2010-03-19-DbgDeclare.ll +++ test/DebugInfo/2010-03-19-DbgDeclare.ll @@ -4,7 +4,7 @@ define void @Foo(i32 %a, i32 %b) { entry: - call void @llvm.dbg.declare(metadata !{i32* null}, metadata !1) + call void @llvm.dbg.declare(metadata !{i32* null}, metadata !{}, metadata !1) ret void } !llvm.dbg.cu = !{!2} @@ -15,5 +15,5 @@ !1 = metadata !{i32 4, metadata !"foo"} !4 = metadata !{metadata !"scratch.cpp", metadata !"/usr/local/google/home/blaikie/dev/scratch"} -declare void @llvm.dbg.declare(metadata, metadata) nounwind readnone +declare void @llvm.dbg.declare(metadata, metadata, metadata) nounwind readnone !5 = metadata !{i32 1, metadata !"Debug Info Version", i32 1} Index: test/DebugInfo/2010-03-24-MemberFn.ll =================================================================== --- test/DebugInfo/2010-03-24-MemberFn.ll +++ test/DebugInfo/2010-03-24-MemberFn.ll @@ -8,7 +8,7 @@ %0 = alloca i32 ; [#uses=2] %s1 = alloca %struct.S ; <%struct.S*> [#uses=1] %"alloca point" = bitcast i32 0 to i32 ; [#uses=0] - call void @llvm.dbg.declare(metadata !{%struct.S* %s1}, metadata !0), !dbg !16 + call void @llvm.dbg.declare(metadata !{%struct.S* %s1}, metadata !{}, metadata !0), !dbg !16 %1 = call i32 @_ZN1S3fooEv(%struct.S* %s1) nounwind, !dbg !17 ; [#uses=1] store i32 %1, i32* %0, align 4, !dbg !17 %2 = load i32* %0, align 4, !dbg !17 ; [#uses=1] @@ -25,7 +25,7 @@ %this_addr = alloca %struct.S* ; <%struct.S**> [#uses=1] %retval = alloca i32 ; [#uses=1] %"alloca point" = bitcast i32 0 to i32 ; [#uses=0] - call void @llvm.dbg.declare(metadata !{%struct.S** %this_addr}, metadata !18), !dbg !21 + call void @llvm.dbg.declare(metadata !{%struct.S** %this_addr}, metadata !{}, metadata !18), !dbg !21 store %struct.S* %this, %struct.S** %this_addr br label %return, !dbg !21 @@ -34,7 +34,7 @@ ret i32 %retval1, !dbg !22 } -declare void @llvm.dbg.declare(metadata, metadata) nounwind readnone +declare void @llvm.dbg.declare(metadata, metadata, metadata) nounwind readnone !llvm.dbg.cu = !{!5} !llvm.module.flags = !{!28} Index: test/DebugInfo/2010-03-30-InvalidDbgInfoCrash.ll =================================================================== --- test/DebugInfo/2010-03-30-InvalidDbgInfoCrash.ll +++ test/DebugInfo/2010-03-30-InvalidDbgInfoCrash.ll @@ -2,11 +2,11 @@ define void @baz(i32 %i) nounwind ssp { entry: - call void @llvm.dbg.declare(metadata !0, metadata !1), !dbg !0 + call void @llvm.dbg.declare(metadata !0, metadata !{}, metadata !1), !dbg !0 ret void, !dbg !0 } -declare void @llvm.dbg.declare(metadata, metadata) nounwind readnone +declare void @llvm.dbg.declare(metadata, metadata, metadata) nounwind readnone !llvm.dbg.cu = !{!5} !llvm.module.flags = !{!22} Index: test/DebugInfo/2010-04-06-NestedFnDbgInfo.ll =================================================================== --- test/DebugInfo/2010-04-06-NestedFnDbgInfo.ll +++ test/DebugInfo/2010-04-06-NestedFnDbgInfo.ll @@ -26,14 +26,14 @@ %retval = alloca i32, align 4 ; [#uses=3] %b = alloca %class.A, align 1 ; <%class.A*> [#uses=1] store i32 0, i32* %retval - call void @llvm.dbg.declare(metadata !{%class.A* %b}, metadata !0), !dbg !14 + call void @llvm.dbg.declare(metadata !{%class.A* %b}, metadata !{}, metadata !0), !dbg !14 %call = call i32 @_ZN1B2fnEv(%class.A* %b), !dbg !15 ; [#uses=1] store i32 %call, i32* %retval, !dbg !15 %0 = load i32* %retval, !dbg !16 ; [#uses=1] ret i32 %0, !dbg !16 } -declare void @llvm.dbg.declare(metadata, metadata) nounwind readnone +declare void @llvm.dbg.declare(metadata, metadata, metadata) nounwind readnone define linkonce_odr i32 @_ZN1B2fnEv(%class.A* %this) ssp align 2 { entry: @@ -42,10 +42,10 @@ %a = alloca %class.A, align 1 ; <%class.A*> [#uses=1] %i = alloca i32, align 4 ; [#uses=2] store %class.A* %this, %class.A** %this.addr - call void @llvm.dbg.declare(metadata !{%class.A** %this.addr}, metadata !17), !dbg !18 + call void @llvm.dbg.declare(metadata !{%class.A** %this.addr}, metadata !{}, metadata !17), !dbg !18 %this1 = load %class.A** %this.addr ; <%class.A*> [#uses=0] - call void @llvm.dbg.declare(metadata !{%class.A* %a}, metadata !19), !dbg !27 - call void @llvm.dbg.declare(metadata !{i32* %i}, metadata !28), !dbg !29 + call void @llvm.dbg.declare(metadata !{%class.A* %a}, metadata !{}, metadata !19), !dbg !27 + call void @llvm.dbg.declare(metadata !{i32* %i}, metadata !{}, metadata !28), !dbg !29 %call = call i32 @_ZZN1B2fnEvEN1A3fooEv(%class.A* %a), !dbg !30 ; [#uses=1] store i32 %call, i32* %i, !dbg !30 %tmp = load i32* %i, !dbg !31 ; [#uses=1] @@ -59,7 +59,7 @@ %retval = alloca i32, align 4 ; [#uses=2] %this.addr = alloca %class.A*, align 8 ; <%class.A**> [#uses=2] store %class.A* %this, %class.A** %this.addr - call void @llvm.dbg.declare(metadata !{%class.A** %this.addr}, metadata !33), !dbg !34 + call void @llvm.dbg.declare(metadata !{%class.A** %this.addr}, metadata !{}, metadata !33), !dbg !34 %this1 = load %class.A** %this.addr ; <%class.A*> [#uses=0] store i32 42, i32* %retval, !dbg !35 %0 = load i32* %retval, !dbg !35 ; [#uses=1] Index: test/DebugInfo/2010-05-03-DisableFramePtr.ll =================================================================== --- test/DebugInfo/2010-05-03-DisableFramePtr.ll +++ test/DebugInfo/2010-05-03-DisableFramePtr.ll @@ -6,7 +6,7 @@ entry: %userUPP_addr = alloca void (%struct.AppleEvent*)* ; [#uses=1] %"alloca point" = bitcast i32 0 to i32 ; [#uses=0] - call void @llvm.dbg.declare(metadata !{void (%struct.AppleEvent*)** %userUPP_addr}, metadata !0), !dbg !13 + call void @llvm.dbg.declare(metadata !{void (%struct.AppleEvent*)** %userUPP_addr}, metadata !{}, metadata !0), !dbg !13 store void (%struct.AppleEvent*)* %userUPP, void (%struct.AppleEvent*)** %userUPP_addr br label %return, !dbg !14 @@ -14,7 +14,7 @@ ret void, !dbg !14 } -declare void @llvm.dbg.declare(metadata, metadata) nounwind readnone +declare void @llvm.dbg.declare(metadata, metadata, metadata) nounwind readnone !llvm.dbg.cu = !{!3} !llvm.module.flags = !{!19} Index: test/DebugInfo/2010-05-03-OriginDIE.ll =================================================================== --- test/DebugInfo/2010-05-03-OriginDIE.ll +++ test/DebugInfo/2010-05-03-OriginDIE.ll @@ -23,12 +23,12 @@ %a10 = call i64 @llvm.bswap.i64(i64 %a9) nounwind ; [#uses=1] %a11 = getelementptr inbounds %struct.gpt_t* %gpt, i32 0, i32 8, !dbg !7 ; [#uses=1] %a12 = load i64* %a11, align 4, !dbg !7 ; [#uses=1] - call void @llvm.dbg.declare(metadata !{i64* %data_addr.i17}, metadata !8) nounwind, !dbg !14 + call void @llvm.dbg.declare(metadata !{i64* %data_addr.i17}, metadata !{}, metadata !8) nounwind, !dbg !14 store i64 %a12, i64* %data_addr.i17, align 8 - call void @llvm.dbg.value(metadata !6, i64 0, metadata !15) nounwind - call void @llvm.dbg.value(metadata !18, i64 0, metadata !19) nounwind - call void @llvm.dbg.declare(metadata !6, metadata !23) nounwind - call void @llvm.dbg.value(metadata !{i64* %data_addr.i17}, i64 0, metadata !34) nounwind + call void @llvm.dbg.value(metadata !6, i64 0, metadata !{}, metadata !15) nounwind + call void @llvm.dbg.value(metadata !18, i64 0, metadata !{}, metadata !19) nounwind + call void @llvm.dbg.declare(metadata !6, metadata !{}, metadata !23) nounwind + call void @llvm.dbg.value(metadata !{i64* %data_addr.i17}, i64 0, metadata !{}, metadata !34) nounwind %a13 = load volatile i64* %data_addr.i17, align 8 ; [#uses=1] %a14 = call i64 @llvm.bswap.i64(i64 %a13) nounwind ; [#uses=2] %a15 = add i64 %a10, %a14, !dbg !7 ; [#uses=1] @@ -38,9 +38,9 @@ ret void, !dbg !7 } -declare void @llvm.dbg.declare(metadata, metadata) nounwind readnone +declare void @llvm.dbg.declare(metadata, metadata, metadata) nounwind readnone -declare void @llvm.dbg.value(metadata, i64, metadata) nounwind readnone +declare void @llvm.dbg.value(metadata, i64, metadata, metadata) nounwind readnone declare i32 @llvm.bswap.i32(i32) nounwind readnone Index: test/DebugInfo/2010-06-29-InlinedFnLocalVar.ll =================================================================== --- test/DebugInfo/2010-06-29-InlinedFnLocalVar.ll +++ test/DebugInfo/2010-06-29-InlinedFnLocalVar.ll @@ -7,15 +7,15 @@ @i = common global i32 0 ; [#uses=2] -declare void @llvm.dbg.declare(metadata, metadata) nounwind readnone +declare void @llvm.dbg.declare(metadata, metadata, metadata) nounwind readnone -declare void @llvm.dbg.value(metadata, i64, metadata) nounwind readnone +declare void @llvm.dbg.value(metadata, i64, metadata, metadata) nounwind readnone define i32 @bar() nounwind ssp { entry: %0 = load i32* @i, align 4, !dbg !17 ; [#uses=2] - tail call void @llvm.dbg.value(metadata !{i32 %0}, i64 0, metadata !9), !dbg !19 - tail call void @llvm.dbg.declare(metadata !29, metadata !10), !dbg !21 + tail call void @llvm.dbg.value(metadata !{i32 %0}, i64 0, metadata !{}, metadata !9), !dbg !19 + tail call void @llvm.dbg.declare(metadata !29, metadata !{}, metadata !10), !dbg !21 %1 = mul nsw i32 %0, %0, !dbg !22 ; [#uses=2] store i32 %1, i32* @i, align 4, !dbg !17 ret i32 %1, !dbg !23 Index: test/DebugInfo/2010-10-01-crash.ll =================================================================== --- test/DebugInfo/2010-10-01-crash.ll +++ test/DebugInfo/2010-10-01-crash.ll @@ -4,11 +4,11 @@ define void @CGRectStandardize(i32* sret %agg.result, i32* byval %rect) nounwind ssp { entry: - call void @llvm.dbg.declare(metadata !{i32* %rect}, metadata !23), !dbg !24 + call void @llvm.dbg.declare(metadata !{i32* %rect}, metadata !{}, metadata !23), !dbg !24 ret void } -declare void @llvm.dbg.declare(metadata, metadata) nounwind readnone +declare void @llvm.dbg.declare(metadata, metadata, metadata) nounwind readnone declare void @llvm.memcpy.p0i8.p0i8.i32(i8* nocapture, i8* nocapture, i32, i32, i1) nounwind Index: test/DebugInfo/AArch64/struct_by_value.ll =================================================================== --- test/DebugInfo/AArch64/struct_by_value.ll +++ test/DebugInfo/AArch64/struct_by_value.ll @@ -32,14 +32,14 @@ ; Function Attrs: nounwind ssp define i32 @return_five_int(%struct.five* %f) #0 { entry: - call void @llvm.dbg.declare(metadata !{%struct.five* %f}, metadata !17), !dbg !18 + call void @llvm.dbg.declare(metadata !{%struct.five* %f}, metadata !{}, metadata !17), !dbg !18 %a = getelementptr inbounds %struct.five* %f, i32 0, i32 0, !dbg !19 %0 = load i32* %a, align 4, !dbg !19 ret i32 %0, !dbg !19 } ; Function Attrs: nounwind readnone -declare void @llvm.dbg.declare(metadata, metadata) #1 +declare void @llvm.dbg.declare(metadata, metadata, metadata) #1 attributes #0 = { nounwind ssp } attributes #1 = { nounwind readnone } Index: test/DebugInfo/ARM/PR16736.ll =================================================================== --- test/DebugInfo/ARM/PR16736.ll +++ test/DebugInfo/ARM/PR16736.ll @@ -15,14 +15,14 @@ ; Function Attrs: nounwind define arm_aapcscc void @_Z1hiiiif(i32, i32, i32, i32, float %x) #0 { entry: - tail call void @llvm.dbg.value(metadata !{i32 %0}, i64 0, metadata !12), !dbg !18 - tail call void @llvm.dbg.value(metadata !{i32 %1}, i64 0, metadata !13), !dbg !18 - tail call void @llvm.dbg.value(metadata !{i32 %2}, i64 0, metadata !14), !dbg !18 - tail call void @llvm.dbg.value(metadata !{i32 %3}, i64 0, metadata !15), !dbg !18 - tail call void @llvm.dbg.value(metadata !{float %x}, i64 0, metadata !16), !dbg !18 + tail call void @llvm.dbg.value(metadata !{i32 %0}, i64 0, metadata !{}, metadata !12), !dbg !18 + tail call void @llvm.dbg.value(metadata !{i32 %1}, i64 0, metadata !{}, metadata !13), !dbg !18 + tail call void @llvm.dbg.value(metadata !{i32 %2}, i64 0, metadata !{}, metadata !14), !dbg !18 + tail call void @llvm.dbg.value(metadata !{i32 %3}, i64 0, metadata !{}, metadata !15), !dbg !18 + tail call void @llvm.dbg.value(metadata !{float %x}, i64 0, metadata !{}, metadata !16), !dbg !18 %call = tail call arm_aapcscc i32 @_Z1fv() #3, !dbg !19 %conv = sitofp i32 %call to float, !dbg !19 - tail call void @llvm.dbg.value(metadata !{float %conv}, i64 0, metadata !16), !dbg !19 + tail call void @llvm.dbg.value(metadata !{float %conv}, i64 0, metadata !{}, metadata !16), !dbg !19 tail call arm_aapcscc void @_Z1gf(float %conv) #3, !dbg !19 ret void, !dbg !20 } @@ -32,7 +32,7 @@ declare arm_aapcscc i32 @_Z1fv() ; Function Attrs: nounwind readnone -declare void @llvm.dbg.value(metadata, i64, metadata) #2 +declare void @llvm.dbg.value(metadata, i64, metadata, metadata) #2 attributes #0 = { nounwind } attributes #2 = { nounwind readnone } Index: test/DebugInfo/ARM/lowerbdgdeclare_vla.ll =================================================================== --- test/DebugInfo/ARM/lowerbdgdeclare_vla.ll +++ test/DebugInfo/ARM/lowerbdgdeclare_vla.ll @@ -19,18 +19,18 @@ ; Function Attrs: nounwind optsize readnone define void @run(float %r) #0 { entry: - tail call void @llvm.dbg.declare(metadata !{float %r}, metadata !11), !dbg !22 + tail call void @llvm.dbg.declare(metadata !{float %r}, metadata !{}, metadata !11), !dbg !22 %conv = fptosi float %r to i32, !dbg !23 - tail call void @llvm.dbg.declare(metadata !{i32 %conv}, metadata !12), !dbg !23 + tail call void @llvm.dbg.declare(metadata !{i32 %conv}, metadata !{}, metadata !12), !dbg !23 %vla = alloca float, i32 %conv, align 4, !dbg !24 - tail call void @llvm.dbg.declare(metadata !{float* %vla}, metadata !14), !dbg !24 + tail call void @llvm.dbg.declare(metadata !{float* %vla}, metadata !{}, metadata !14), !dbg !24 ; The VLA alloca should be described by a dbg.declare: -; CHECK: call void @llvm.dbg.declare(metadata !{float* %vla}, metadata ![[VLA:.*]]) +; CHECK: call void @llvm.dbg.declare(metadata !{float* %vla}, metadata {{.*}}, metadata ![[VLA:.*]]) ; The VLA alloca and following store into the array should not be lowered to like this: ; CHECK-NOT: call void @llvm.dbg.value(metadata !{float %r}, i64 0, metadata ![[VLA]]) ; the backend interprets this as "vla has the location of %r". store float %r, float* %vla, align 4, !dbg !25, !tbaa !26 - tail call void @llvm.dbg.value(metadata !2, i64 0, metadata !18), !dbg !30 + tail call void @llvm.dbg.value(metadata !2, i64 0, metadata !{}, metadata !18), !dbg !30 %cmp8 = icmp sgt i32 %conv, 0, !dbg !30 br i1 %cmp8, label %for.body, label %for.end, !dbg !30 @@ -41,7 +41,7 @@ %div = fdiv float %0, %r, !dbg !31 store float %div, float* %arrayidx2, align 4, !dbg !31, !tbaa !26 %inc = add nsw i32 %i.09, 1, !dbg !30 - tail call void @llvm.dbg.value(metadata !{i32 %inc}, i64 0, metadata !18), !dbg !30 + tail call void @llvm.dbg.value(metadata !{i32 %inc}, i64 0, metadata !{}, metadata !18), !dbg !30 %exitcond = icmp eq i32 %inc, %conv, !dbg !30 br i1 %exitcond, label %for.end, label %for.body.for.body_crit_edge, !dbg !30 @@ -55,10 +55,10 @@ } ; Function Attrs: nounwind readnone -declare void @llvm.dbg.declare(metadata, metadata) #1 +declare void @llvm.dbg.declare(metadata, metadata, metadata) #1 ; Function Attrs: nounwind readnone -declare void @llvm.dbg.value(metadata, i64, metadata) #1 +declare void @llvm.dbg.value(metadata, i64, metadata, metadata) #1 attributes #0 = { nounwind optsize readnone "less-precise-fpmad"="false" "no-frame-pointer-elim"="false" "no-infs-fp-math"="false" "no-nans-fp-math"="false" "no-realign-stack" "stack-protector-buffer-size"="8" "unsafe-fp-math"="false" "use-soft-float"="false" } attributes #1 = { nounwind readnone } Index: test/DebugInfo/ARM/s-super-register.ll =================================================================== --- test/DebugInfo/ARM/s-super-register.ll +++ test/DebugInfo/ARM/s-super-register.ll @@ -12,7 +12,7 @@ define void @_Z3foov() optsize ssp { entry: %call = tail call float @_Z3barv() optsize, !dbg !11 - tail call void @llvm.dbg.value(metadata !{float %call}, i64 0, metadata !5), !dbg !11 + tail call void @llvm.dbg.value(metadata !{float %call}, i64 0, metadata !{}, metadata !5), !dbg !11 %call16 = tail call float @_Z2f2v() optsize, !dbg !12 %cmp7 = fcmp olt float %call, %call16, !dbg !12 br i1 %cmp7, label %for.body, label %for.end, !dbg !12 @@ -35,7 +35,7 @@ declare float @_Z2f3f(float) optsize -declare void @llvm.dbg.value(metadata, i64, metadata) nounwind readnone +declare void @llvm.dbg.value(metadata, i64, metadata, metadata) nounwind readnone !llvm.dbg.cu = !{!0} !llvm.module.flags = !{!20} Index: test/DebugInfo/ARM/selectiondag-deadcode.ll =================================================================== --- test/DebugInfo/ARM/selectiondag-deadcode.ll +++ test/DebugInfo/ARM/selectiondag-deadcode.ll @@ -13,11 +13,11 @@ ; and SelectionDAGISel crashes. It should definitely not ; crash. Drop the dbg_value instead. ; CHECK-NOT: "matrix" - tail call void @llvm.dbg.declare(metadata !{%class.Matrix3.0.6.10* %agg.result}, metadata !45) + tail call void @llvm.dbg.declare(metadata !{%class.Matrix3.0.6.10* %agg.result}, metadata !{}, metadata !45) %2 = getelementptr inbounds %class.Matrix3.0.6.10* %agg.result, i32 0, i32 0, i32 8 ret void } -declare void @llvm.dbg.declare(metadata, metadata) #1 +declare void @llvm.dbg.declare(metadata, metadata, metadata) #1 declare arm_aapcscc void @_ZL4Sqrtd() #2 !4 = metadata !{i32 786434, metadata !5, null, metadata !"Matrix3", i32 20, i64 288, i64 32, i32 0, i32 0, null, null, i32 0, null, null, metadata !"_ZTS7Matrix3"} ; [ DW_TAG_class_type ] [Matrix3] [line 20, size 288, align 32, offset 0] [def] [from ] !5 = metadata !{metadata !"test.ii", metadata !"/Volumes/Data/radar/15094721"} Index: test/DebugInfo/Mips/delay-slot.ll =================================================================== --- test/DebugInfo/Mips/delay-slot.ll +++ test/DebugInfo/Mips/delay-slot.ll @@ -26,7 +26,7 @@ ; Function Attrs: nounwind define i32 @foo(i32 %x) #0 { entry: - call void @llvm.dbg.value(metadata !{i32 %x}, i64 0, metadata !12), !dbg !13 + call void @llvm.dbg.value(metadata !{i32 %x}, i64 0, metadata !{}, metadata !12), !dbg !13 %tobool = icmp ne i32 %x, 0, !dbg !14 br i1 %tobool, label %if.then, label %if.end, !dbg !14 @@ -42,10 +42,10 @@ } ; Function Attrs: nounwind readnone -declare void @llvm.dbg.declare(metadata, metadata) #1 +declare void @llvm.dbg.declare(metadata, metadata, metadata) #1 ; Function Attrs: nounwind readnone -declare void @llvm.dbg.value(metadata, i64, metadata) #1 +declare void @llvm.dbg.value(metadata, i64, metadata, metadata) #1 attributes #0 = { nounwind } attributes #1 = { nounwind readnone } Index: test/DebugInfo/PR20038.ll =================================================================== --- test/DebugInfo/PR20038.ll +++ test/DebugInfo/PR20038.ll @@ -78,10 +78,10 @@ cleanup.action: ; preds = %land.end store %struct.C* %agg.tmp.ensured, %struct.C** %this.addr.i, align 8, !dbg !22 - call void @llvm.dbg.declare(metadata !{%struct.C** %this.addr.i}, metadata !29), !dbg !31 + call void @llvm.dbg.declare(metadata !{%struct.C** %this.addr.i}, metadata !{}, metadata !29), !dbg !31 %this1.i = load %struct.C** %this.addr.i, !dbg !22 store %struct.C* %this1.i, %struct.C** %this.addr.i.i, align 8, !dbg !21 - call void @llvm.dbg.declare(metadata !{%struct.C** %this.addr.i.i}, metadata !32), !dbg !33 + call void @llvm.dbg.declare(metadata !{%struct.C** %this.addr.i.i}, metadata !{}, metadata !32), !dbg !33 %this1.i.i = load %struct.C** %this.addr.i.i, !dbg !21 br label %cleanup.done, !dbg !22 @@ -95,10 +95,10 @@ %this.addr.i = alloca %struct.C*, align 8, !dbg !37 %this.addr = alloca %struct.C*, align 8 store %struct.C* %this, %struct.C** %this.addr, align 8 - call void @llvm.dbg.declare(metadata !{%struct.C** %this.addr}, metadata !29), !dbg !38 + call void @llvm.dbg.declare(metadata !{%struct.C** %this.addr}, metadata !{}, metadata !29), !dbg !38 %this1 = load %struct.C** %this.addr store %struct.C* %this1, %struct.C** %this.addr.i, align 8, !dbg !37 - call void @llvm.dbg.declare(metadata !{%struct.C** %this.addr.i}, metadata !32), !dbg !39 + call void @llvm.dbg.declare(metadata !{%struct.C** %this.addr.i}, metadata !{}, metadata !32), !dbg !39 %this1.i = load %struct.C** %this.addr.i, !dbg !37 ret void, !dbg !37 } @@ -108,13 +108,13 @@ entry: %this.addr = alloca %struct.C*, align 8 store %struct.C* %this, %struct.C** %this.addr, align 8 - call void @llvm.dbg.declare(metadata !{%struct.C** %this.addr}, metadata !32), !dbg !40 + call void @llvm.dbg.declare(metadata !{%struct.C** %this.addr}, metadata !{}, metadata !32), !dbg !40 %this1 = load %struct.C** %this.addr ret void, !dbg !41 } ; Function Attrs: nounwind readnone -declare void @llvm.dbg.declare(metadata, metadata) #2 +declare void @llvm.dbg.declare(metadata, metadata, metadata) #2 attributes #0 = { nounwind "less-precise-fpmad"="false" "no-frame-pointer-elim"="false" "no-infs-fp-math"="false" "no-nans-fp-math"="false" "no-realign-stack" "stack-protector-buffer-size"="8" "unsafe-fp-math"="false" "use-soft-float"="false" } attributes #1 = { alwaysinline nounwind "less-precise-fpmad"="false" "no-frame-pointer-elim"="false" "no-infs-fp-math"="false" "no-nans-fp-math"="false" "no-realign-stack" "stack-protector-buffer-size"="8" "unsafe-fp-math"="false" "use-soft-float"="false" } Index: test/DebugInfo/SystemZ/variable-loc.ll =================================================================== --- test/DebugInfo/SystemZ/variable-loc.ll +++ test/DebugInfo/SystemZ/variable-loc.ll @@ -25,7 +25,7 @@ declare void @populate_array(i32*, i32) nounwind -declare void @llvm.dbg.declare(metadata, metadata) nounwind readnone +declare void @llvm.dbg.declare(metadata, metadata, metadata) nounwind readnone declare i32 @sum_array(i32*, i32) nounwind @@ -35,8 +35,8 @@ %main_arr = alloca [100 x i32], align 4 %val = alloca i32, align 4 store volatile i32 0, i32* %retval - call void @llvm.dbg.declare(metadata !{[100 x i32]* %main_arr}, metadata !17), !dbg !22 - call void @llvm.dbg.declare(metadata !{i32* %val}, metadata !23), !dbg !24 + call void @llvm.dbg.declare(metadata !{[100 x i32]* %main_arr}, metadata !{}, metadata !17), !dbg !22 + call void @llvm.dbg.declare(metadata !{i32* %val}, metadata !{}, metadata !23), !dbg !24 %arraydecay = getelementptr inbounds [100 x i32]* %main_arr, i32 0, i32 0, !dbg !25 call void @populate_array(i32* %arraydecay, i32 100), !dbg !25 %arraydecay1 = getelementptr inbounds [100 x i32]* %main_arr, i32 0, i32 0, !dbg !26 Index: test/DebugInfo/X86/2010-04-13-PubType.ll =================================================================== --- test/DebugInfo/X86/2010-04-13-PubType.ll +++ test/DebugInfo/X86/2010-04-13-PubType.ll @@ -12,9 +12,9 @@ %retval = alloca i32 ; [#uses=2] %0 = alloca i32 ; [#uses=2] %"alloca point" = bitcast i32 0 to i32 ; [#uses=0] - call void @llvm.dbg.declare(metadata !{%struct.X** %x_addr}, metadata !0), !dbg !13 + call void @llvm.dbg.declare(metadata !{%struct.X** %x_addr}, metadata !{}, metadata !0), !dbg !13 store %struct.X* %x, %struct.X** %x_addr - call void @llvm.dbg.declare(metadata !{%struct.Y** %y_addr}, metadata !14), !dbg !13 + call void @llvm.dbg.declare(metadata !{%struct.Y** %y_addr}, metadata !{}, metadata !14), !dbg !13 store %struct.Y* %y, %struct.Y** %y_addr store i32 0, i32* %0, align 4, !dbg !13 %1 = load i32* %0, align 4, !dbg !13 ; [#uses=1] @@ -26,7 +26,7 @@ ret i32 %retval1, !dbg !15 } -declare void @llvm.dbg.declare(metadata, metadata) nounwind readnone +declare void @llvm.dbg.declare(metadata, metadata, metadata) nounwind readnone !llvm.dbg.cu = !{!3} !llvm.module.flags = !{!20} Index: test/DebugInfo/X86/2011-09-26-GlobalVarContext.ll =================================================================== --- test/DebugInfo/X86/2011-09-26-GlobalVarContext.ll +++ test/DebugInfo/X86/2011-09-26-GlobalVarContext.ll @@ -7,14 +7,14 @@ define i32 @f() nounwind { %LOC = alloca i32, align 4 - call void @llvm.dbg.declare(metadata !{i32* %LOC}, metadata !15), !dbg !17 + call void @llvm.dbg.declare(metadata !{i32* %LOC}, metadata !{}, metadata !15), !dbg !17 %1 = load i32* @GLB, align 4, !dbg !18 store i32 %1, i32* %LOC, align 4, !dbg !18 %2 = load i32* @GLB, align 4, !dbg !19 ret i32 %2, !dbg !19 } -declare void @llvm.dbg.declare(metadata, metadata) nounwind readnone +declare void @llvm.dbg.declare(metadata, metadata, metadata) nounwind readnone !llvm.dbg.cu = !{!0} !llvm.module.flags = !{!21} Index: test/DebugInfo/X86/2011-12-16-BadStructRef.ll =================================================================== --- test/DebugInfo/X86/2011-12-16-BadStructRef.ll +++ test/DebugInfo/X86/2011-12-16-BadStructRef.ll @@ -15,24 +15,24 @@ %myBar = alloca %struct.bar, align 8 store i32 0, i32* %retval store i32 %argc, i32* %argc.addr, align 4 - call void @llvm.dbg.declare(metadata !{i32* %argc.addr}, metadata !49), !dbg !50 + call void @llvm.dbg.declare(metadata !{i32* %argc.addr}, metadata !{}, metadata !49), !dbg !50 store i8** %argv, i8*** %argv.addr, align 8 - call void @llvm.dbg.declare(metadata !{i8*** %argv.addr}, metadata !51), !dbg !52 - call void @llvm.dbg.declare(metadata !{%struct.bar* %myBar}, metadata !53), !dbg !55 + call void @llvm.dbg.declare(metadata !{i8*** %argv.addr}, metadata !{}, metadata !51), !dbg !52 + call void @llvm.dbg.declare(metadata !{%struct.bar* %myBar}, metadata !{}, metadata !53), !dbg !55 call void @_ZN3barC1Ei(%struct.bar* %myBar, i32 1), !dbg !56 ret i32 0, !dbg !57 } -declare void @llvm.dbg.declare(metadata, metadata) nounwind readnone +declare void @llvm.dbg.declare(metadata, metadata, metadata) nounwind readnone define linkonce_odr void @_ZN3barC1Ei(%struct.bar* %this, i32 %x) unnamed_addr uwtable ssp align 2 { entry: %this.addr = alloca %struct.bar*, align 8 %x.addr = alloca i32, align 4 store %struct.bar* %this, %struct.bar** %this.addr, align 8 - call void @llvm.dbg.declare(metadata !{%struct.bar** %this.addr}, metadata !58), !dbg !59 + call void @llvm.dbg.declare(metadata !{%struct.bar** %this.addr}, metadata !{}, metadata !58), !dbg !59 store i32 %x, i32* %x.addr, align 4 - call void @llvm.dbg.declare(metadata !{i32* %x.addr}, metadata !60), !dbg !61 + call void @llvm.dbg.declare(metadata !{i32* %x.addr}, metadata !{}, metadata !60), !dbg !61 %this1 = load %struct.bar** %this.addr %0 = load i32* %x.addr, align 4, !dbg !62 call void @_ZN3barC2Ei(%struct.bar* %this1, i32 %0), !dbg !62 @@ -44,9 +44,9 @@ %this.addr = alloca %struct.bar*, align 8 %x.addr = alloca i32, align 4 store %struct.bar* %this, %struct.bar** %this.addr, align 8 - call void @llvm.dbg.declare(metadata !{%struct.bar** %this.addr}, metadata !63), !dbg !64 + call void @llvm.dbg.declare(metadata !{%struct.bar** %this.addr}, metadata !{}, metadata !63), !dbg !64 store i32 %x, i32* %x.addr, align 4 - call void @llvm.dbg.declare(metadata !{i32* %x.addr}, metadata !65), !dbg !66 + call void @llvm.dbg.declare(metadata !{i32* %x.addr}, metadata !{}, metadata !65), !dbg !66 %this1 = load %struct.bar** %this.addr %b = getelementptr inbounds %struct.bar* %this1, i32 0, i32 0, !dbg !67 %0 = load i32* %x.addr, align 4, !dbg !67 @@ -62,9 +62,9 @@ %this.addr = alloca %struct.baz*, align 8 %a.addr = alloca i32, align 4 store %struct.baz* %this, %struct.baz** %this.addr, align 8 - call void @llvm.dbg.declare(metadata !{%struct.baz** %this.addr}, metadata !70), !dbg !71 + call void @llvm.dbg.declare(metadata !{%struct.baz** %this.addr}, metadata !{}, metadata !70), !dbg !71 store i32 %a, i32* %a.addr, align 4 - call void @llvm.dbg.declare(metadata !{i32* %a.addr}, metadata !72), !dbg !73 + call void @llvm.dbg.declare(metadata !{i32* %a.addr}, metadata !{}, metadata !72), !dbg !73 %this1 = load %struct.baz** %this.addr %0 = load i32* %a.addr, align 4, !dbg !74 call void @_ZN3bazC2Ei(%struct.baz* %this1, i32 %0), !dbg !74 @@ -76,9 +76,9 @@ %this.addr = alloca %struct.baz*, align 8 %a.addr = alloca i32, align 4 store %struct.baz* %this, %struct.baz** %this.addr, align 8 - call void @llvm.dbg.declare(metadata !{%struct.baz** %this.addr}, metadata !75), !dbg !76 + call void @llvm.dbg.declare(metadata !{%struct.baz** %this.addr}, metadata !{}, metadata !75), !dbg !76 store i32 %a, i32* %a.addr, align 4 - call void @llvm.dbg.declare(metadata !{i32* %a.addr}, metadata !77), !dbg !78 + call void @llvm.dbg.declare(metadata !{i32* %a.addr}, metadata !{}, metadata !77), !dbg !78 %this1 = load %struct.baz** %this.addr %h = getelementptr inbounds %struct.baz* %this1, i32 0, i32 0, !dbg !79 %0 = load i32* %a.addr, align 4, !dbg !79 Index: test/DebugInfo/X86/DW_AT_byte_size.ll =================================================================== --- test/DebugInfo/X86/DW_AT_byte_size.ll +++ test/DebugInfo/X86/DW_AT_byte_size.ll @@ -14,14 +14,14 @@ entry: %a.addr = alloca %struct.A*, align 8 store %struct.A* %a, %struct.A** %a.addr, align 8 - call void @llvm.dbg.declare(metadata !{%struct.A** %a.addr}, metadata !16), !dbg !17 + call void @llvm.dbg.declare(metadata !{%struct.A** %a.addr}, metadata !{}, metadata !16), !dbg !17 %0 = load %struct.A** %a.addr, align 8, !dbg !18 %b = getelementptr inbounds %struct.A* %0, i32 0, i32 0, !dbg !18 %1 = load i32* %b, align 4, !dbg !18 ret i32 %1, !dbg !18 } -declare void @llvm.dbg.declare(metadata, metadata) nounwind readnone +declare void @llvm.dbg.declare(metadata, metadata, metadata) nounwind readnone !llvm.dbg.cu = !{!0} !llvm.module.flags = !{!21} Index: test/DebugInfo/X86/DW_AT_linkage_name.ll =================================================================== --- test/DebugInfo/X86/DW_AT_linkage_name.ll +++ test/DebugInfo/X86/DW_AT_linkage_name.ll @@ -38,20 +38,20 @@ entry: %this.addr = alloca %struct.A*, align 8 store %struct.A* %this, %struct.A** %this.addr, align 8 - call void @llvm.dbg.declare(metadata !{%struct.A** %this.addr}, metadata !26), !dbg !28 + call void @llvm.dbg.declare(metadata !{%struct.A** %this.addr}, metadata !{}, metadata !26), !dbg !28 %this1 = load %struct.A** %this.addr ret void, !dbg !29 } ; Function Attrs: nounwind readnone -declare void @llvm.dbg.declare(metadata, metadata) #1 +declare void @llvm.dbg.declare(metadata, metadata, metadata) #1 ; Function Attrs: nounwind ssp uwtable define void @_ZN1AD1Ev(%struct.A* %this) unnamed_addr #0 align 2 { entry: %this.addr = alloca %struct.A*, align 8 store %struct.A* %this, %struct.A** %this.addr, align 8 - call void @llvm.dbg.declare(metadata !{%struct.A** %this.addr}, metadata !30), !dbg !31 + call void @llvm.dbg.declare(metadata !{%struct.A** %this.addr}, metadata !{}, metadata !30), !dbg !31 %this1 = load %struct.A** %this.addr call void @_ZN1AD2Ev(%struct.A* %this1), !dbg !32 ret void, !dbg !33 @@ -61,7 +61,7 @@ define void @_Z3foov() #2 { entry: %a = alloca %struct.A, align 1 - call void @llvm.dbg.declare(metadata !{%struct.A* %a}, metadata !34), !dbg !35 + call void @llvm.dbg.declare(metadata !{%struct.A* %a}, metadata !{}, metadata !34), !dbg !35 call void @_ZN1AC1Ei(%struct.A* %a, i32 1), !dbg !35 call void @_ZN1AD1Ev(%struct.A* %a), !dbg !36 ret void, !dbg !36 Index: test/DebugInfo/X86/DW_AT_location-reference.ll =================================================================== --- test/DebugInfo/X86/DW_AT_location-reference.ll +++ test/DebugInfo/X86/DW_AT_location-reference.ll @@ -64,7 +64,7 @@ entry: %call = tail call i32 @g(i32 0, i32 0) nounwind, !dbg !8 store i32 %call, i32* @a, align 4, !dbg !8 - tail call void @llvm.dbg.value(metadata !12, i64 0, metadata !5), !dbg !13 + tail call void @llvm.dbg.value(metadata !12, i64 0, metadata !{}, metadata !5), !dbg !13 br label %while.body while.body: ; preds = %entry, %while.body @@ -75,10 +75,10 @@ br i1 %tobool, label %while.end, label %while.body, !dbg !14 while.end: ; preds = %while.body - tail call void @llvm.dbg.value(metadata !{i32 %mul}, i64 0, metadata !5), !dbg !14 + tail call void @llvm.dbg.value(metadata !{i32 %mul}, i64 0, metadata !{}, metadata !5), !dbg !14 %call4 = tail call i32 @g(i32 %mul, i32 0) nounwind, !dbg !15 store i32 %call4, i32* @a, align 4, !dbg !15 - tail call void @llvm.dbg.value(metadata !16, i64 0, metadata !5), !dbg !17 + tail call void @llvm.dbg.value(metadata !16, i64 0, metadata !{}, metadata !5), !dbg !17 br label %while.body9 while.body9: ; preds = %while.end, %while.body9 @@ -89,7 +89,7 @@ br i1 %tobool8, label %while.end13, label %while.body9, !dbg !18 while.end13: ; preds = %while.body9 - tail call void @llvm.dbg.value(metadata !{i32 %mul12}, i64 0, metadata !5), !dbg !18 + tail call void @llvm.dbg.value(metadata !{i32 %mul12}, i64 0, metadata !{}, metadata !5), !dbg !18 %call15 = tail call i32 @g(i32 0, i32 %mul12) nounwind, !dbg !19 store i32 %call15, i32* @a, align 4, !dbg !19 ret void, !dbg !20 @@ -97,7 +97,7 @@ declare i32 @g(i32, i32) -declare void @llvm.dbg.value(metadata, i64, metadata) nounwind readnone +declare void @llvm.dbg.value(metadata, i64, metadata, metadata) nounwind readnone !llvm.dbg.cu = !{!2} !llvm.module.flags = !{!24} Index: test/DebugInfo/X86/DW_AT_object_pointer.ll =================================================================== --- test/DebugInfo/X86/DW_AT_object_pointer.ll +++ test/DebugInfo/X86/DW_AT_object_pointer.ll @@ -17,21 +17,21 @@ %.addr = alloca i32, align 4 %a = alloca %class.A, align 4 store i32 %0, i32* %.addr, align 4 - call void @llvm.dbg.declare(metadata !{i32* %.addr}, metadata !36), !dbg !35 - call void @llvm.dbg.declare(metadata !{%class.A* %a}, metadata !21), !dbg !23 + call void @llvm.dbg.declare(metadata !{i32* %.addr}, metadata !{}, metadata !36), !dbg !35 + call void @llvm.dbg.declare(metadata !{%class.A* %a}, metadata !{}, metadata !21), !dbg !23 call void @_ZN1AC1Ev(%class.A* %a), !dbg !24 %m_a = getelementptr inbounds %class.A* %a, i32 0, i32 0, !dbg !25 %1 = load i32* %m_a, align 4, !dbg !25 ret i32 %1, !dbg !25 } -declare void @llvm.dbg.declare(metadata, metadata) nounwind readnone +declare void @llvm.dbg.declare(metadata, metadata, metadata) nounwind readnone define linkonce_odr void @_ZN1AC1Ev(%class.A* %this) unnamed_addr nounwind uwtable ssp align 2 { entry: %this.addr = alloca %class.A*, align 8 store %class.A* %this, %class.A** %this.addr, align 8 - call void @llvm.dbg.declare(metadata !{%class.A** %this.addr}, metadata !26), !dbg !28 + call void @llvm.dbg.declare(metadata !{%class.A** %this.addr}, metadata !{}, metadata !26), !dbg !28 %this1 = load %class.A** %this.addr call void @_ZN1AC2Ev(%class.A* %this1), !dbg !29 ret void, !dbg !29 @@ -41,7 +41,7 @@ entry: %this.addr = alloca %class.A*, align 8 store %class.A* %this, %class.A** %this.addr, align 8 - call void @llvm.dbg.declare(metadata !{%class.A** %this.addr}, metadata !30), !dbg !31 + call void @llvm.dbg.declare(metadata !{%class.A** %this.addr}, metadata !{}, metadata !30), !dbg !31 %this1 = load %class.A** %this.addr %m_a = getelementptr inbounds %class.A* %this1, i32 0, i32 0, !dbg !32 store i32 0, i32* %m_a, align 4, !dbg !32 Index: test/DebugInfo/X86/aligned_stack_var.ll =================================================================== --- test/DebugInfo/X86/aligned_stack_var.ll +++ test/DebugInfo/X86/aligned_stack_var.ll @@ -18,11 +18,11 @@ define void @_Z3runv() nounwind uwtable { entry: %x = alloca i32, align 32 - call void @llvm.dbg.declare(metadata !{i32* %x}, metadata !9), !dbg !12 + call void @llvm.dbg.declare(metadata !{i32* %x}, metadata !{}, metadata !9), !dbg !12 ret void, !dbg !13 } -declare void @llvm.dbg.declare(metadata, metadata) nounwind readnone +declare void @llvm.dbg.declare(metadata, metadata, metadata) nounwind readnone !llvm.dbg.cu = !{!0} !llvm.module.flags = !{!15} Index: test/DebugInfo/X86/arguments.ll =================================================================== --- test/DebugInfo/X86/arguments.ll +++ test/DebugInfo/X86/arguments.ll @@ -31,8 +31,8 @@ ; Function Attrs: nounwind uwtable define void @_Z4func3fooS_(%struct.foo* %f, %struct.foo* %g) #0 { entry: - call void @llvm.dbg.declare(metadata !{%struct.foo* %f}, metadata !19), !dbg !20 - call void @llvm.dbg.declare(metadata !{%struct.foo* %g}, metadata !21), !dbg !20 + call void @llvm.dbg.declare(metadata !{%struct.foo* %f}, metadata !{}, metadata !19), !dbg !20 + call void @llvm.dbg.declare(metadata !{%struct.foo* %g}, metadata !{}, metadata !21), !dbg !20 %i = getelementptr inbounds %struct.foo* %f, i32 0, i32 0, !dbg !22 %0 = load i32* %i, align 4, !dbg !22 %inc = add nsw i32 %0, 1, !dbg !22 @@ -41,7 +41,7 @@ } ; Function Attrs: nounwind readnone -declare void @llvm.dbg.declare(metadata, metadata) #1 +declare void @llvm.dbg.declare(metadata, metadata, metadata) #1 attributes #0 = { nounwind uwtable "less-precise-fpmad"="false" "no-frame-pointer-elim"="true" "no-frame-pointer-elim-non-leaf"="true" "no-infs-fp-math"="false" "no-nans-fp-math"="false" "unsafe-fp-math"="false" "use-soft-float"="false" } attributes #1 = { nounwind readnone } Index: test/DebugInfo/X86/array.ll =================================================================== --- test/DebugInfo/X86/array.ll +++ test/DebugInfo/X86/array.ll @@ -25,7 +25,7 @@ ; Function Attrs: nounwind ssp uwtable define void @f(i32* nocapture %p) #0 { - tail call void @llvm.dbg.value(metadata !{i32* %p}, i64 0, metadata !11), !dbg !28 + tail call void @llvm.dbg.value(metadata !{i32* %p}, i64 0, metadata !{}, metadata !11), !dbg !28 store i32 42, i32* %p, align 4, !dbg !29, !tbaa !30 ret void, !dbg !34 } @@ -33,15 +33,15 @@ ; Function Attrs: nounwind ssp uwtable define i32 @main(i32 %argc, i8** nocapture readnone %argv) #0 { %array = alloca [4 x i32], align 16 - tail call void @llvm.dbg.value(metadata !{i32 %argc}, i64 0, metadata !19), !dbg !35 - tail call void @llvm.dbg.value(metadata !{i8** %argv}, i64 0, metadata !20), !dbg !35 - tail call void @llvm.dbg.value(metadata !{[4 x i32]* %array}, i64 0, metadata !21), !dbg !36 + tail call void @llvm.dbg.value(metadata !{i32 %argc}, i64 0, metadata !{}, metadata !19), !dbg !35 + tail call void @llvm.dbg.value(metadata !{i8** %argv}, i64 0, metadata !{}, metadata !20), !dbg !35 + tail call void @llvm.dbg.value(metadata !{[4 x i32]* %array}, i64 0, metadata !{}, metadata !21), !dbg !36 %1 = bitcast [4 x i32]* %array to i8*, !dbg !36 call void @llvm.memcpy.p0i8.p0i8.i64(i8* %1, i8* bitcast ([4 x i32]* @main.array to i8*), i64 16, i32 16, i1 false), !dbg !36 - tail call void @llvm.dbg.value(metadata !{[4 x i32]* %array}, i64 0, metadata !21), !dbg !36 + tail call void @llvm.dbg.value(metadata !{[4 x i32]* %array}, i64 0, metadata !{}, metadata !21), !dbg !36 %2 = getelementptr inbounds [4 x i32]* %array, i64 0, i64 0, !dbg !37 call void @f(i32* %2), !dbg !37 - tail call void @llvm.dbg.value(metadata !{[4 x i32]* %array}, i64 0, metadata !21), !dbg !36 + tail call void @llvm.dbg.value(metadata !{[4 x i32]* %array}, i64 0, metadata !{}, metadata !21), !dbg !36 %3 = load i32* %2, align 16, !dbg !38, !tbaa !30 ret i32 %3, !dbg !38 } @@ -50,7 +50,7 @@ declare void @llvm.memcpy.p0i8.p0i8.i64(i8* nocapture, i8* nocapture readonly, i64, i32, i1) #1 ; Function Attrs: nounwind readnone -declare void @llvm.dbg.value(metadata, i64, metadata) #2 +declare void @llvm.dbg.value(metadata, i64, metadata, metadata) #2 attributes #0 = { nounwind ssp uwtable } attributes #1 = { nounwind } Index: test/DebugInfo/X86/array2.ll =================================================================== --- test/DebugInfo/X86/array2.ll +++ test/DebugInfo/X86/array2.ll @@ -29,7 +29,7 @@ entry: %p.addr = alloca i32*, align 8 store i32* %p, i32** %p.addr, align 8 - call void @llvm.dbg.declare(metadata !{i32** %p.addr}, metadata !19), !dbg !20 + call void @llvm.dbg.declare(metadata !{i32** %p.addr}, metadata !{}, metadata !19), !dbg !20 %0 = load i32** %p.addr, align 8, !dbg !21 %arrayidx = getelementptr inbounds i32* %0, i64 0, !dbg !21 store i32 42, i32* %arrayidx, align 4, !dbg !21 @@ -37,7 +37,7 @@ } ; Function Attrs: nounwind readnone -declare void @llvm.dbg.declare(metadata, metadata) #1 +declare void @llvm.dbg.declare(metadata, metadata, metadata) #1 ; Function Attrs: nounwind ssp uwtable define i32 @main(i32 %argc, i8** %argv) #0 { @@ -48,10 +48,10 @@ %array = alloca [4 x i32], align 16 store i32 0, i32* %retval store i32 %argc, i32* %argc.addr, align 4 - call void @llvm.dbg.declare(metadata !{i32* %argc.addr}, metadata !23), !dbg !24 + call void @llvm.dbg.declare(metadata !{i32* %argc.addr}, metadata !{}, metadata !23), !dbg !24 store i8** %argv, i8*** %argv.addr, align 8 - call void @llvm.dbg.declare(metadata !{i8*** %argv.addr}, metadata !25), !dbg !24 - call void @llvm.dbg.declare(metadata !{[4 x i32]* %array}, metadata !26), !dbg !30 + call void @llvm.dbg.declare(metadata !{i8*** %argv.addr}, metadata !{}, metadata !25), !dbg !24 + call void @llvm.dbg.declare(metadata !{[4 x i32]* %array}, metadata !{}, metadata !26), !dbg !30 %0 = bitcast [4 x i32]* %array to i8*, !dbg !30 call void @llvm.memcpy.p0i8.p0i8.i64(i8* %0, i8* bitcast ([4 x i32]* @main.array to i8*), i64 16, i32 16, i1 false), !dbg !30 %arraydecay = getelementptr inbounds [4 x i32]* %array, i32 0, i32 0, !dbg !31 Index: test/DebugInfo/X86/block-capture.ll =================================================================== --- test/DebugInfo/X86/block-capture.ll +++ test/DebugInfo/X86/block-capture.ll @@ -17,15 +17,15 @@ %struct.__block_descriptor = type { i64, i64 } %struct.__block_literal_generic = type { i8*, i32, i32, i8*, %struct.__block_descriptor* } -declare void @llvm.dbg.declare(metadata, metadata) nounwind readnone +declare void @llvm.dbg.declare(metadata, metadata, metadata) nounwind readnone define hidden void @__foo_block_invoke_0(i8* %.block_descriptor) uwtable ssp { entry: %exn.slot = alloca i8* %ehselector.slot = alloca i32 - call void @llvm.dbg.value(metadata !{i8* %.block_descriptor}, i64 0, metadata !39), !dbg !51 + call void @llvm.dbg.value(metadata !{i8* %.block_descriptor}, i64 0, metadata !{}, metadata !39), !dbg !51 %block = bitcast i8* %.block_descriptor to <{ i8*, i32, i32, i8*, %struct.__block_descriptor*, void ()* }>*, !dbg !52 - call void @llvm.dbg.declare(metadata !{<{ i8*, i32, i32, i8*, %struct.__block_descriptor*, void ()* }>* %block}, metadata !53), !dbg !54 + call void @llvm.dbg.declare(metadata !{<{ i8*, i32, i32, i8*, %struct.__block_descriptor*, void ()* }>* %block}, metadata !65, metadata !53), !dbg !54 %block.capture.addr = getelementptr inbounds <{ i8*, i32, i32, i8*, %struct.__block_descriptor*, void ()* }>* %block, i32 0, i32 5, !dbg !55 %0 = load void ()** %block.capture.addr, align 8, !dbg !55 %block.literal = bitcast void ()* %0 to %struct.__block_literal_generic*, !dbg !55 @@ -58,7 +58,7 @@ br label %eh.cont, !dbg !58 } -declare void @llvm.dbg.value(metadata, i64, metadata) nounwind readnone +declare void @llvm.dbg.value(metadata, i64, metadata, metadata) nounwind readnone declare i8* @objc_begin_catch(i8*) @@ -118,7 +118,7 @@ !50 = metadata !{i32 786445, metadata !63, metadata !6, metadata !"block", i32 7, i64 64, i64 64, i64 256, i32 0, metadata !9} ; [ DW_TAG_member ] !51 = metadata !{i32 7, i32 18, metadata !28, null} !52 = metadata !{i32 7, i32 19, metadata !28, null} -!53 = metadata !{i32 786688, metadata !28, metadata !"block", metadata !6, i32 5, metadata !9, i32 0, i32 0, metadata !65} ; [ DW_TAG_auto_variable ] +!53 = metadata !{i32 786688, metadata !28, metadata !"block", metadata !6, i32 5, metadata !9, i32 0, i32 0} ;; [ DW_TAG_auto_variable ] !54 = metadata !{i32 5, i32 27, metadata !28, null} !55 = metadata !{i32 8, i32 22, metadata !56, null} !56 = metadata !{i32 786443, metadata !6, metadata !57, i32 7, i32 26, i32 2} ; [ DW_TAG_lexical_block ] Index: test/DebugInfo/X86/byvalstruct.ll =================================================================== --- test/DebugInfo/X86/byvalstruct.ll +++ test/DebugInfo/X86/byvalstruct.ll @@ -66,20 +66,20 @@ %otherBitmap.addr = alloca %0*, align 8 %length.addr = alloca i64, align 8 store %0* %self, %0** %self.addr, align 8 - call void @llvm.dbg.declare(metadata !{%0** %self.addr}, metadata !28), !dbg !29 + call void @llvm.dbg.declare(metadata !{%0** %self.addr}, metadata !{}, metadata !28), !dbg !29 store i8* %_cmd, i8** %_cmd.addr, align 8 - call void @llvm.dbg.declare(metadata !{i8** %_cmd.addr}, metadata !30), !dbg !29 + call void @llvm.dbg.declare(metadata !{i8** %_cmd.addr}, metadata !{}, metadata !30), !dbg !29 store %0* %otherBitmap, %0** %otherBitmap.addr, align 8 - call void @llvm.dbg.declare(metadata !{%0** %otherBitmap.addr}, metadata !32), !dbg !29 - call void @llvm.dbg.declare(metadata !{%struct.ImageInfo* %info}, metadata !33), !dbg !34 + call void @llvm.dbg.declare(metadata !{%0** %otherBitmap.addr}, metadata !{}, metadata !32), !dbg !29 + call void @llvm.dbg.declare(metadata !{%struct.ImageInfo* %info}, metadata !{}, metadata !33), !dbg !34 store i64 %length, i64* %length.addr, align 8 - call void @llvm.dbg.declare(metadata !{i64* %length.addr}, metadata !35), !dbg !36 + call void @llvm.dbg.declare(metadata !{i64* %length.addr}, metadata !{}, metadata !35), !dbg !36 %0 = load i8** %retval, !dbg !37 ret i8* %0, !dbg !37 } ; Function Attrs: nounwind readnone -declare void @llvm.dbg.declare(metadata, metadata) #1 +declare void @llvm.dbg.declare(metadata, metadata, metadata) #1 attributes #0 = { ssp uwtable } attributes #1 = { nounwind readnone } Index: test/DebugInfo/X86/cu-ranges-odr.ll =================================================================== --- test/DebugInfo/X86/cu-ranges-odr.ll +++ test/DebugInfo/X86/cu-ranges-odr.ll @@ -35,9 +35,9 @@ %this.addr = alloca %class.A*, align 8 %i.addr = alloca i32, align 4 store %class.A* %this, %class.A** %this.addr, align 8 - call void @llvm.dbg.declare(metadata !{%class.A** %this.addr}, metadata !27), !dbg !29 + call void @llvm.dbg.declare(metadata !{%class.A** %this.addr}, metadata !{}, metadata !27), !dbg !29 store i32 %i, i32* %i.addr, align 4 - call void @llvm.dbg.declare(metadata !{i32* %i.addr}, metadata !30), !dbg !31 + call void @llvm.dbg.declare(metadata !{i32* %i.addr}, metadata !{}, metadata !30), !dbg !31 %this1 = load %class.A** %this.addr %a = getelementptr inbounds %class.A* %this1, i32 0, i32 0, !dbg !31 %0 = load i32* %i.addr, align 4, !dbg !31 @@ -46,7 +46,7 @@ } ; Function Attrs: nounwind readnone -declare void @llvm.dbg.declare(metadata, metadata) #1 +declare void @llvm.dbg.declare(metadata, metadata, metadata) #1 define internal void @_GLOBAL__I_a() section ".text.startup" { entry: Index: test/DebugInfo/X86/cu-ranges.ll =================================================================== --- test/DebugInfo/X86/cu-ranges.ll +++ test/DebugInfo/X86/cu-ranges.ll @@ -27,21 +27,21 @@ entry: %a.addr = alloca i32, align 4 store i32 %a, i32* %a.addr, align 4 - call void @llvm.dbg.declare(metadata !{i32* %a.addr}, metadata !13), !dbg !14 + call void @llvm.dbg.declare(metadata !{i32* %a.addr}, metadata !{}, metadata !13), !dbg !14 %0 = load i32* %a.addr, align 4, !dbg !14 %add = add nsw i32 %0, 1, !dbg !14 ret i32 %add, !dbg !14 } ; Function Attrs: nounwind readnone -declare void @llvm.dbg.declare(metadata, metadata) #1 +declare void @llvm.dbg.declare(metadata, metadata, metadata) #1 ; Function Attrs: nounwind uwtable define i32 @bar(i32 %b) #0 { entry: %b.addr = alloca i32, align 4 store i32 %b, i32* %b.addr, align 4 - call void @llvm.dbg.declare(metadata !{i32* %b.addr}, metadata !15), !dbg !16 + call void @llvm.dbg.declare(metadata !{i32* %b.addr}, metadata !{}, metadata !15), !dbg !16 %0 = load i32* %b.addr, align 4, !dbg !16 %add = add nsw i32 %0, 2, !dbg !16 ret i32 %add, !dbg !16 Index: test/DebugInfo/X86/dbg-byval-parameter.ll =================================================================== --- test/DebugInfo/X86/dbg-byval-parameter.ll +++ test/DebugInfo/X86/dbg-byval-parameter.ll @@ -9,7 +9,7 @@ %retval = alloca double ; [#uses=2] %0 = alloca double ; [#uses=2] %"alloca point" = bitcast i32 0 to i32 ; [#uses=0] - call void @llvm.dbg.declare(metadata !{%struct.Rect* %my_r0}, metadata !0), !dbg !15 + call void @llvm.dbg.declare(metadata !{%struct.Rect* %my_r0}, metadata !{}, metadata !0), !dbg !15 %1 = getelementptr inbounds %struct.Rect* %my_r0, i32 0, i32 0, !dbg !16 ; <%struct.Pt*> [#uses=1] %2 = getelementptr inbounds %struct.Pt* %1, i32 0, i32 0, !dbg !16 ; [#uses=1] %3 = load double* %2, align 8, !dbg !16 ; [#uses=1] @@ -23,7 +23,7 @@ ret double %retval1, !dbg !16 } -declare void @llvm.dbg.declare(metadata, metadata) nounwind readnone +declare void @llvm.dbg.declare(metadata, metadata, metadata) nounwind readnone !llvm.dbg.cu = !{!3} !llvm.module.flags = !{!21} Index: test/DebugInfo/X86/dbg-const-int.ll =================================================================== --- test/DebugInfo/X86/dbg-const-int.ll +++ test/DebugInfo/X86/dbg-const-int.ll @@ -12,11 +12,11 @@ define i32 @foo() nounwind uwtable readnone optsize ssp { entry: - tail call void @llvm.dbg.value(metadata !8, i64 0, metadata !6), !dbg !9 + tail call void @llvm.dbg.value(metadata !8, i64 0, metadata !{}, metadata !6), !dbg !9 ret i32 42, !dbg !10 } -declare void @llvm.dbg.value(metadata, i64, metadata) nounwind readnone +declare void @llvm.dbg.value(metadata, i64, metadata, metadata) nounwind readnone !llvm.dbg.cu = !{!0} !llvm.module.flags = !{!15} Index: test/DebugInfo/X86/dbg-const.ll =================================================================== --- test/DebugInfo/X86/dbg-const.ll +++ test/DebugInfo/X86/dbg-const.ll @@ -17,15 +17,15 @@ ;CHECK-NEXT: .byte 42 define i32 @foobar() nounwind readonly noinline ssp { entry: - tail call void @llvm.dbg.value(metadata !8, i64 0, metadata !6), !dbg !9 + tail call void @llvm.dbg.value(metadata !8, i64 0, metadata !{}, metadata !6), !dbg !9 %call = tail call i32 @bar(), !dbg !11 - tail call void @llvm.dbg.value(metadata !{i32 %call}, i64 0, metadata !6), !dbg !11 + tail call void @llvm.dbg.value(metadata !{i32 %call}, i64 0, metadata !{}, metadata !6), !dbg !11 %call2 = tail call i32 @bar(), !dbg !11 %add = add nsw i32 %call2, %call, !dbg !12 ret i32 %add, !dbg !10 } -declare void @llvm.dbg.value(metadata, i64, metadata) nounwind readnone +declare void @llvm.dbg.value(metadata, i64, metadata, metadata) nounwind readnone declare i32 @bar() nounwind readnone !llvm.dbg.cu = !{!2} Index: test/DebugInfo/X86/dbg-declare-arg.ll =================================================================== --- test/DebugInfo/X86/dbg-declare-arg.ll +++ test/DebugInfo/X86/dbg-declare-arg.ll @@ -14,8 +14,8 @@ %nrvo = alloca i1 %cleanup.dest.slot = alloca i32 store i32 %i, i32* %i.addr, align 4 - call void @llvm.dbg.declare(metadata !{i32* %i.addr}, metadata !26), !dbg !27 - call void @llvm.dbg.declare(metadata !{i32* %j}, metadata !28), !dbg !30 + call void @llvm.dbg.declare(metadata !{i32* %i.addr}, metadata !{}, metadata !26), !dbg !27 + call void @llvm.dbg.declare(metadata !{i32* %j}, metadata !{}, metadata !28), !dbg !30 store i32 0, i32* %j, align 4, !dbg !31 %tmp = load i32* %i.addr, align 4, !dbg !32 %cmp = icmp eq i32 %tmp, 42, !dbg !32 @@ -29,7 +29,7 @@ if.end: ; preds = %if.then, %entry store i1 false, i1* %nrvo, !dbg !36 - call void @llvm.dbg.declare(metadata !{%class.A* %agg.result}, metadata !37), !dbg !39 + call void @llvm.dbg.declare(metadata !{%class.A* %agg.result}, metadata !{}, metadata !37), !dbg !39 %tmp2 = load i32* %j, align 4, !dbg !40 %x = getelementptr inbounds %class.A* %agg.result, i32 0, i32 0, !dbg !40 store i32 %tmp2, i32* %x, align 4, !dbg !40 @@ -46,13 +46,13 @@ ret void, !dbg !42 } -declare void @llvm.dbg.declare(metadata, metadata) nounwind readnone +declare void @llvm.dbg.declare(metadata, metadata, metadata) nounwind readnone define linkonce_odr void @_ZN1AD1Ev(%class.A* %this) unnamed_addr ssp align 2 { entry: %this.addr = alloca %class.A*, align 8 store %class.A* %this, %class.A** %this.addr, align 8 - call void @llvm.dbg.declare(metadata !{%class.A** %this.addr}, metadata !43), !dbg !44 + call void @llvm.dbg.declare(metadata !{%class.A** %this.addr}, metadata !{}, metadata !43), !dbg !44 %this1 = load %class.A** %this.addr call void @_ZN1AD2Ev(%class.A* %this1) ret void, !dbg !45 @@ -62,7 +62,7 @@ entry: %this.addr = alloca %class.A*, align 8 store %class.A* %this, %class.A** %this.addr, align 8 - call void @llvm.dbg.declare(metadata !{%class.A** %this.addr}, metadata !46), !dbg !47 + call void @llvm.dbg.declare(metadata !{%class.A** %this.addr}, metadata !{}, metadata !46), !dbg !47 %this1 = load %class.A** %this.addr %x = getelementptr inbounds %class.A* %this1, i32 0, i32 0, !dbg !48 store i32 1, i32* %x, align 4, !dbg !48 Index: test/DebugInfo/X86/dbg-declare.ll =================================================================== --- test/DebugInfo/X86/dbg-declare.ll +++ test/DebugInfo/X86/dbg-declare.ll @@ -7,21 +7,21 @@ %saved_stack = alloca i8* %cleanup.dest.slot = alloca i32 store i32* %x, i32** %x.addr, align 8 - call void @llvm.dbg.declare(metadata !{i32** %x.addr}, metadata !14), !dbg !15 + call void @llvm.dbg.declare(metadata !{i32** %x.addr}, metadata !{}, metadata !14), !dbg !15 %0 = load i32** %x.addr, align 8, !dbg !16 %1 = load i32* %0, align 4, !dbg !16 %2 = zext i32 %1 to i64, !dbg !16 %3 = call i8* @llvm.stacksave(), !dbg !16 store i8* %3, i8** %saved_stack, !dbg !16 %vla = alloca i8, i64 %2, align 16, !dbg !16 - call void @llvm.dbg.declare(metadata !{i8* %vla}, metadata !18), !dbg !23 + call void @llvm.dbg.declare(metadata !{i8* %vla}, metadata !{}, metadata !18), !dbg !23 store i32 1, i32* %cleanup.dest.slot %4 = load i8** %saved_stack, !dbg !24 call void @llvm.stackrestore(i8* %4), !dbg !24 ret i32 0, !dbg !25 } -declare void @llvm.dbg.declare(metadata, metadata) nounwind readnone +declare void @llvm.dbg.declare(metadata, metadata, metadata) nounwind readnone declare i8* @llvm.stacksave() nounwind Index: test/DebugInfo/X86/dbg-i128-const.ll =================================================================== --- test/DebugInfo/X86/dbg-i128-const.ll +++ test/DebugInfo/X86/dbg-i128-const.ll @@ -5,12 +5,12 @@ define i128 @__foo(i128 %a, i128 %b) nounwind { entry: - tail call void @llvm.dbg.value(metadata !0, i64 0, metadata !1), !dbg !11 + tail call void @llvm.dbg.value(metadata !0, i64 0, metadata !{}, metadata !1), !dbg !11 %add = add i128 %a, %b, !dbg !11 ret i128 %add, !dbg !11 } -declare void @llvm.dbg.value(metadata, i64, metadata) nounwind readnone +declare void @llvm.dbg.value(metadata, i64, metadata, metadata) nounwind readnone !llvm.dbg.cu = !{!5} !llvm.module.flags = !{!16} Index: test/DebugInfo/X86/dbg-merge-loc-entry.ll =================================================================== --- test/DebugInfo/X86/dbg-merge-loc-entry.ll +++ test/DebugInfo/X86/dbg-merge-loc-entry.ll @@ -14,8 +14,8 @@ define hidden i128 @__divti3(i128 %u, i128 %v) nounwind readnone { entry: - tail call void @llvm.dbg.value(metadata !{i128 %u}, i64 0, metadata !14), !dbg !15 - tail call void @llvm.dbg.value(metadata !16, i64 0, metadata !17), !dbg !21 + tail call void @llvm.dbg.value(metadata !{i128 %u}, i64 0, metadata !{}, metadata !14), !dbg !15 + tail call void @llvm.dbg.value(metadata !16, i64 0, metadata !{}, metadata !17), !dbg !21 br i1 undef, label %bb2, label %bb4, !dbg !22 bb2: ; preds = %entry @@ -31,9 +31,9 @@ ret i128 undef, !dbg !27 } -declare void @llvm.dbg.declare(metadata, metadata) nounwind readnone +declare void @llvm.dbg.declare(metadata, metadata, metadata) nounwind readnone -declare void @llvm.dbg.value(metadata, i64, metadata) nounwind readnone +declare void @llvm.dbg.value(metadata, i64, metadata, metadata) nounwind readnone declare %0 @llvm.uadd.with.overflow.i64(i64, i64) nounwind readnone Index: test/DebugInfo/X86/dbg-prolog-end.ll =================================================================== --- test/DebugInfo/X86/dbg-prolog-end.ll +++ test/DebugInfo/X86/dbg-prolog-end.ll @@ -8,8 +8,8 @@ %i.addr = alloca i32, align 4 %j = alloca i32, align 4 store i32 %i, i32* %i.addr, align 4 - call void @llvm.dbg.declare(metadata !{i32* %i.addr}, metadata !7), !dbg !8 - call void @llvm.dbg.declare(metadata !{i32* %j}, metadata !9), !dbg !11 + call void @llvm.dbg.declare(metadata !{i32* %i.addr}, metadata !{}, metadata !7), !dbg !8 + call void @llvm.dbg.declare(metadata !{i32* %j}, metadata !{}, metadata !9), !dbg !11 store i32 2, i32* %j, align 4, !dbg !12 %tmp = load i32* %j, align 4, !dbg !13 %inc = add nsw i32 %tmp, 1, !dbg !13 @@ -22,7 +22,7 @@ ret i32 %tmp3, !dbg !15 } -declare void @llvm.dbg.declare(metadata, metadata) nounwind readnone +declare void @llvm.dbg.declare(metadata, metadata, metadata) nounwind readnone define i32 @main() nounwind ssp { entry: Index: test/DebugInfo/X86/dbg-value-const-byref.ll =================================================================== --- test/DebugInfo/X86/dbg-value-const-byref.ll +++ test/DebugInfo/X86/dbg-value-const-byref.ll @@ -50,13 +50,13 @@ define i32 @foo() #0 { entry: %i = alloca i32, align 4 - call void @llvm.dbg.value(metadata !14, i64 0, metadata !10), !dbg !15 + call void @llvm.dbg.value(metadata !14, i64 0, metadata !{}, metadata !10), !dbg !15 %call = call i32 @f3(i32 3) #3, !dbg !16 - call void @llvm.dbg.value(metadata !17, i64 0, metadata !10), !dbg !18 + call void @llvm.dbg.value(metadata !17, i64 0, metadata !{}, metadata !10), !dbg !18 %call1 = call i32 (...)* @f1() #3, !dbg !19 - call void @llvm.dbg.value(metadata !{i32 %call1}, i64 0, metadata !10), !dbg !19 + call void @llvm.dbg.value(metadata !{i32 %call1}, i64 0, metadata !{}, metadata !10), !dbg !19 store i32 %call1, i32* %i, align 4, !dbg !19, !tbaa !20 - call void @llvm.dbg.value(metadata !{i32* %i}, i64 0, metadata !10), !dbg !24 + call void @llvm.dbg.value(metadata !{i32* %i}, i64 0, metadata !{}, metadata !10), !dbg !24 call void @f2(i32* %i) #3, !dbg !24 ret i32 0, !dbg !25 } @@ -68,7 +68,7 @@ declare void @f2(i32*) ; Function Attrs: nounwind readnone -declare void @llvm.dbg.value(metadata, i64, metadata) #2 +declare void @llvm.dbg.value(metadata, i64, metadata, metadata) #2 attributes #0 = { nounwind ssp uwtable } attributes #2 = { nounwind readnone } Index: test/DebugInfo/X86/dbg-value-dag-combine.ll =================================================================== --- test/DebugInfo/X86/dbg-value-dag-combine.ll +++ test/DebugInfo/X86/dbg-value-dag-combine.ll @@ -4,21 +4,19 @@ ; PR 9817 -declare <4 x i32> @__amdil_get_global_id_int() -declare void @llvm.dbg.value(metadata , i64 , metadata ) +declare <4 x i32> @__amdil_get_global_id_int() +declare void @llvm.dbg.value(metadata, i64, metadata, metadata) define void @__OpenCL_test_kernel(i32 addrspace(1)* %ip) nounwind { entry: - call void @llvm.dbg.value(metadata !{i32 addrspace(1)* %ip}, i64 0, metadata -!7), !dbg !8 + call void @llvm.dbg.value(metadata !{i32 addrspace(1)* %ip}, i64 0, metadata !{}, metadata !7), !dbg !8 %0 = call <4 x i32> @__amdil_get_global_id_int() nounwind %1 = extractelement <4 x i32> %0, i32 0 - call void @llvm.dbg.value(metadata !{i32 %1}, i64 0, metadata !9), !dbg !11 - call void @llvm.dbg.value(metadata !12, i64 0, metadata !13), !dbg !14 + call void @llvm.dbg.value(metadata !{i32 %1}, i64 0, metadata !{}, metadata !9), !dbg !11 + call void @llvm.dbg.value(metadata !12, i64 0, metadata !{}, metadata !13), !dbg !14 %tmp2 = load i32 addrspace(1)* %ip, align 4, !dbg !15 %tmp3 = add i32 0, %tmp2, !dbg !15 ; CHECK: ##DEBUG_VALUE: idx <- E{{..$}} - call void @llvm.dbg.value(metadata !{i32 %tmp3}, i64 0, metadata !13), !dbg -!15 + call void @llvm.dbg.value(metadata !{i32 %tmp3}, i64 0, metadata !{}, metadata !13), !dbg !15 %arrayidx = getelementptr i32 addrspace(1)* %ip, i32 %1, !dbg !16 store i32 %tmp3, i32 addrspace(1)* %arrayidx, align 4, !dbg !16 ret void, !dbg !17 Index: test/DebugInfo/X86/dbg-value-inlined-parameter.ll =================================================================== --- test/DebugInfo/X86/dbg-value-inlined-parameter.ll +++ test/DebugInfo/X86/dbg-value-inlined-parameter.ll @@ -45,8 +45,8 @@ define i32 @foo(%struct.S1* nocapture %sp, i32 %nums) nounwind optsize ssp { entry: - tail call void @llvm.dbg.value(metadata !{%struct.S1* %sp}, i64 0, metadata !9), !dbg !20 - tail call void @llvm.dbg.value(metadata !{i32 %nums}, i64 0, metadata !18), !dbg !21 + tail call void @llvm.dbg.value(metadata !{%struct.S1* %sp}, i64 0, metadata !{}, metadata !9), !dbg !20 + tail call void @llvm.dbg.value(metadata !{i32 %nums}, i64 0, metadata !{}, metadata !18), !dbg !21 %tmp2 = getelementptr inbounds %struct.S1* %sp, i64 0, i32 1, !dbg !22 store i32 %nums, i32* %tmp2, align 4, !dbg !22 %call = tail call float* @bar(i32 %nums) nounwind optsize, !dbg !27 @@ -61,15 +61,15 @@ define void @foobar() nounwind optsize ssp { entry: - tail call void @llvm.dbg.value(metadata !30, i64 0, metadata !9) nounwind, !dbg !31 - tail call void @llvm.dbg.value(metadata !34, i64 0, metadata !18) nounwind, !dbg !35 + tail call void @llvm.dbg.value(metadata !30, i64 0, metadata !{}, metadata !9) nounwind, !dbg !31 + tail call void @llvm.dbg.value(metadata !34, i64 0, metadata !{}, metadata !18) nounwind, !dbg !35 store i32 1, i32* getelementptr inbounds (%struct.S1* @p, i64 0, i32 1), align 8, !dbg !36 %call.i = tail call float* @bar(i32 1) nounwind optsize, !dbg !37 store float* %call.i, float** getelementptr inbounds (%struct.S1* @p, i64 0, i32 0), align 8, !dbg !37 ret void, !dbg !38 } -declare void @llvm.dbg.value(metadata, i64, metadata) nounwind readnone +declare void @llvm.dbg.value(metadata, i64, metadata, metadata) nounwind readnone !llvm.dbg.cu = !{!2} !llvm.module.flags = !{!43} Index: test/DebugInfo/X86/dbg-value-isel.ll =================================================================== --- test/DebugInfo/X86/dbg-value-isel.ll +++ test/DebugInfo/X86/dbg-value-isel.ll @@ -13,7 +13,7 @@ define void @__OpenCL_nbt02_kernel(i32 addrspace(1)* %ip) nounwind { entry: - call void @llvm.dbg.value(metadata !{i32 addrspace(1)* %ip}, i64 0, metadata !8), !dbg !9 + call void @llvm.dbg.value(metadata !{i32 addrspace(1)* %ip}, i64 0, metadata !{}, metadata !8), !dbg !9 %0 = call <4 x i32> @__amdil_get_local_id_int() nounwind %1 = extractelement <4 x i32> %0, i32 0 br label %2 @@ -28,7 +28,7 @@ get_local_id.exit: ; preds = %4 %6 = phi i32 [ %5, %4 ] - call void @llvm.dbg.value(metadata !{i32 %6}, i64 0, metadata !10), !dbg !12 + call void @llvm.dbg.value(metadata !{i32 %6}, i64 0, metadata !{}, metadata !10), !dbg !12 %7 = call <4 x i32> @__amdil_get_global_id_int() nounwind, !dbg !12 %8 = extractelement <4 x i32> %7, i32 0, !dbg !12 br label %9 @@ -43,7 +43,7 @@ get_global_id.exit: ; preds = %11 %13 = phi i32 [ %12, %11 ] - call void @llvm.dbg.value(metadata !{i32 %13}, i64 0, metadata !13), !dbg !14 + call void @llvm.dbg.value(metadata !{i32 %13}, i64 0, metadata !{}, metadata !13), !dbg !14 %14 = call <4 x i32> @__amdil_get_local_size_int() nounwind %15 = extractelement <4 x i32> %14, i32 0 br label %16 @@ -58,7 +58,7 @@ get_local_size.exit: ; preds = %18 %20 = phi i32 [ %19, %18 ] - call void @llvm.dbg.value(metadata !{i32 %20}, i64 0, metadata !15), !dbg !16 + call void @llvm.dbg.value(metadata !{i32 %20}, i64 0, metadata !{}, metadata !15), !dbg !16 %tmp5 = add i32 %6, %13, !dbg !17 %tmp7 = add i32 %tmp5, %20, !dbg !17 store i32 %tmp7, i32 addrspace(1)* %ip, align 4, !dbg !17 @@ -68,7 +68,7 @@ ret void, !dbg !18 } -declare void @llvm.dbg.declare(metadata, metadata) nounwind readnone +declare void @llvm.dbg.declare(metadata, metadata, metadata) nounwind readnone declare <4 x i32> @__amdil_get_local_size_int() nounwind @@ -76,7 +76,7 @@ declare <4 x i32> @__amdil_get_global_id_int() nounwind -declare void @llvm.dbg.value(metadata, i64, metadata) nounwind readnone +declare void @llvm.dbg.value(metadata, i64, metadata, metadata) nounwind readnone !llvm.dbg.cu = !{!2} !llvm.module.flags = !{!22} Index: test/DebugInfo/X86/dbg-value-location.ll =================================================================== --- test/DebugInfo/X86/dbg-value-location.ll +++ test/DebugInfo/X86/dbg-value-location.ll @@ -14,11 +14,11 @@ @dfm = external global i32, align 4 -declare void @llvm.dbg.declare(metadata, metadata) nounwind readnone +declare void @llvm.dbg.declare(metadata, metadata, metadata) nounwind readnone define i32 @foo(i32 %dev, i64 %cmd, i8* %data, i32 %data2) nounwind optsize ssp { entry: - call void @llvm.dbg.value(metadata !{i32 %dev}, i64 0, metadata !12), !dbg !13 + call void @llvm.dbg.value(metadata !{i32 %dev}, i64 0, metadata !{}, metadata !12), !dbg !13 %tmp.i = load i32* @dfm, align 4, !dbg !14 %cmp.i = icmp eq i32 %tmp.i, 0, !dbg !14 br i1 %cmp.i, label %if.else, label %if.end.i, !dbg !14 @@ -45,7 +45,7 @@ declare hidden fastcc i32 @bar(i32, i32* nocapture) nounwind optsize ssp declare hidden fastcc i32 @bar2(i32) nounwind optsize ssp declare hidden fastcc i32 @bar3(i32) nounwind optsize ssp -declare void @llvm.dbg.value(metadata, i64, metadata) nounwind readnone +declare void @llvm.dbg.value(metadata, i64, metadata, metadata) nounwind readnone !llvm.dbg.cu = !{!2} !llvm.module.flags = !{!29} Index: test/DebugInfo/X86/dbg-value-range.ll =================================================================== --- test/DebugInfo/X86/dbg-value-range.ll +++ test/DebugInfo/X86/dbg-value-range.ll @@ -4,10 +4,10 @@ define i32 @bar(%struct.a* nocapture %b) nounwind ssp { entry: - tail call void @llvm.dbg.value(metadata !{%struct.a* %b}, i64 0, metadata !6), !dbg !13 + tail call void @llvm.dbg.value(metadata !{%struct.a* %b}, i64 0, metadata !{}, metadata !6), !dbg !13 %tmp1 = getelementptr inbounds %struct.a* %b, i64 0, i32 0, !dbg !14 %tmp2 = load i32* %tmp1, align 4, !dbg !14 - tail call void @llvm.dbg.value(metadata !{i32 %tmp2}, i64 0, metadata !11), !dbg !14 + tail call void @llvm.dbg.value(metadata !{i32 %tmp2}, i64 0, metadata !{}, metadata !11), !dbg !14 %call = tail call i32 (...)* @foo(i32 %tmp2) nounwind , !dbg !18 %add = add nsw i32 %tmp2, 1, !dbg !19 ret i32 %add, !dbg !19 @@ -15,7 +15,7 @@ declare i32 @foo(...) -declare void @llvm.dbg.value(metadata, i64, metadata) nounwind readnone +declare void @llvm.dbg.value(metadata, i64, metadata, metadata) nounwind readnone !llvm.dbg.cu = !{!2} !llvm.module.flags = !{!24} Index: test/DebugInfo/X86/dbg-value-terminator.ll =================================================================== --- test/DebugInfo/X86/dbg-value-terminator.ll +++ test/DebugInfo/X86/dbg-value-terminator.ll @@ -87,7 +87,7 @@ "44.i": ; preds = %"42.i" %2 = load %a** undef, align 8, !dbg !12 %3 = bitcast %a* %2 to %a*, !dbg !12 - call void @llvm.dbg.value(metadata !{%a* %3}, i64 0, metadata !6), !dbg !12 + call void @llvm.dbg.value(metadata !{%a* %3}, i64 0, metadata !{}, metadata !6), !dbg !12 br label %may_unswitch_on.exit, !dbg !12 "45.i": ; preds = %"38.i" @@ -108,7 +108,7 @@ attributes #0 = { nounwind readnone } attributes #1 = { nounwind uwtable } -declare void @llvm.dbg.value(metadata, i64, metadata) nounwind readnone +declare void @llvm.dbg.value(metadata, i64, metadata, metadata) nounwind readnone !llvm.dbg.cu = !{!0} !llvm.module.flags = !{!22} Index: test/DebugInfo/X86/dbg_value_direct.ll =================================================================== --- test/DebugInfo/X86/dbg_value_direct.ll +++ test/DebugInfo/X86/dbg_value_direct.ll @@ -53,7 +53,7 @@ %19 = inttoptr i64 %18 to i8* %20 = load i8* %19 %21 = icmp ne i8 %20, 0 - call void @llvm.dbg.declare(metadata !{i32* %3}, metadata !23) + call void @llvm.dbg.declare(metadata !{i32* %3}, metadata !28, metadata !23) br i1 %21, label %22, label %28 ;