Index: llvm/trunk/lib/Target/X86/X86InstructionSelector.cpp =================================================================== --- llvm/trunk/lib/Target/X86/X86InstructionSelector.cpp +++ llvm/trunk/lib/Target/X86/X86InstructionSelector.cpp @@ -118,6 +118,8 @@ MachineFunction &MF) const; bool selectSDiv(MachineInstr &I, MachineRegisterInfo &MRI, MachineFunction &MF) const; + bool selectIntrinsicWSideEffects(MachineInstr &I, MachineRegisterInfo &MRI, + MachineFunction &MF) const; // emit insert subreg instruction and insert it before MachineInstr &I bool emitInsertSubreg(unsigned DstReg, unsigned SrcReg, MachineInstr &I, @@ -387,6 +389,8 @@ return selectShift(I, MRI, MF); case TargetOpcode::G_SDIV: return selectSDiv(I, MRI, MF); + case TargetOpcode::G_INTRINSIC_W_SIDE_EFFECTS: + return selectIntrinsicWSideEffects(I, MRI, MF); } return false; @@ -1661,6 +1665,21 @@ return true; } +bool X86InstructionSelector::selectIntrinsicWSideEffects( + MachineInstr &I, MachineRegisterInfo &MRI, MachineFunction &MF) const { + + assert(I.getOpcode() == TargetOpcode::G_INTRINSIC_W_SIDE_EFFECTS && + "unexpected instruction"); + + if (I.getOperand(0).getIntrinsicID() != Intrinsic::trap) + return false; + + BuildMI(*I.getParent(), I, I.getDebugLoc(), TII.get(X86::TRAP)); + + I.eraseFromParent(); + return true; +} + InstructionSelector * llvm::createX86InstructionSelector(const X86TargetMachine &TM, X86Subtarget &Subtarget, Index: llvm/trunk/test/CodeGen/X86/GlobalISel/x86-select-trap.mir =================================================================== --- llvm/trunk/test/CodeGen/X86/GlobalISel/x86-select-trap.mir +++ llvm/trunk/test/CodeGen/X86/GlobalISel/x86-select-trap.mir @@ -0,0 +1,28 @@ +# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py +# RUN: llc -mtriple=i386-linux-gnu -run-pass=instruction-select -verify-machineinstrs %s -o - | FileCheck %s + +--- | + declare void @llvm.trap() #0 + + define i32 @trap() #0 { + tail call void @llvm.trap() + unreachable + } + + attributes #0 = { noreturn nounwind } + attributes #1 = { nounwind } + +... +--- +name: trap +alignment: 4 +legalized: true +regBankSelected: true +tracksRegLiveness: true +body: | + bb.1 (%ir-block.0): + ; CHECK-LABEL: name: trap + ; CHECK: TRAP + G_INTRINSIC_W_SIDE_EFFECTS intrinsic(@llvm.trap) + +...