Index: include/llvm/Target/Target.td
===================================================================
--- include/llvm/Target/Target.td
+++ include/llvm/Target/Target.td
@@ -581,6 +581,12 @@
   /// instruction selection predicates. FastISel cannot handle such cases, but
   /// SelectionDAG can.
   bit FastISelShouldIgnore = 0;
+
+  /// Normally an unencoded operand (an operand named in InOperandList or
+  /// OutOperandList but not appearing in the instruction encoding) does not
+  /// appear in the MCInst. Setting this to 1 means that the disassembler
+  /// pushes an immediate 0 operand onto the MCInst for such an operand.
+  bit IncludeUnencodedOperands = 0;
 }
 
 /// PseudoInstExpansion - Expansion information for a pseudo-instruction.
Index: utils/TableGen/FixedLenDecoderEmitter.cpp
===================================================================
--- utils/TableGen/FixedLenDecoderEmitter.cpp
+++ utils/TableGen/FixedLenDecoderEmitter.cpp
@@ -2034,7 +2034,9 @@
     if (Base != ~0U)
       OpInfo.addField(Base, Width, Offset);
 
-    if (OpInfo.numFields() > 0)
+    // For an operand with no bits in the instruction encoding, push it only if
+    // IncludeUnencodedOperands is true.
+    if (OpInfo.numFields() > 0 || Def.getValueAsBit("IncludeUnencodedOperands"))
       InsnOperands.push_back(OpInfo);
   }