Index: llvm/trunk/lib/Target/X86/X86InstrShiftRotate.td
===================================================================
--- llvm/trunk/lib/Target/X86/X86InstrShiftRotate.td
+++ llvm/trunk/lib/Target/X86/X86InstrShiftRotate.td
@@ -650,7 +650,7 @@
 // Double shift instructions (generalizations of rotate)
 //===----------------------------------------------------------------------===//
 
-let Constraints = "$src1 = $dst", SchedRW = [WriteShift] in {
+let Constraints = "$src1 = $dst", SchedRW = [WriteShiftDouble] in {
 
 let Uses = [CL] in {
 def SHLD16rrCL : I<0xA5, MRMDestReg, (outs GR16:$dst),
@@ -731,7 +731,7 @@
 }
 } // Constraints = "$src = $dst", SchedRW
 
-let SchedRW = [WriteShiftLd, WriteRMW] in {
+let SchedRW = [WriteShiftDoubleLd, WriteRMW] in {
 let Uses = [CL] in {
 def SHLD16mrCL : I<0xA5, MRMDestMem, (outs), (ins i16mem:$dst, GR16:$src2),
                    "shld{w}\t{%cl, $src2, $dst|$dst, $src2, cl}",
Index: llvm/trunk/lib/Target/X86/X86SchedBroadwell.td
===================================================================
--- llvm/trunk/lib/Target/X86/X86SchedBroadwell.td
+++ llvm/trunk/lib/Target/X86/X86SchedBroadwell.td
@@ -146,6 +146,9 @@
 // Integer shifts and rotates.
 defm : BWWriteResPair<WriteShift, [BWPort06],  1>;
 
+// Double shift instructions.
+defm : BWWriteResPair<WriteShiftDouble, [BWPort06],  1>;
+
 // BMI1 BEXTR, BMI2 BZHI
 defm : BWWriteResPair<WriteBEXTR, [BWPort06,BWPort15], 2, [1,1], 2>;
 defm : BWWriteResPair<WriteBZHI, [BWPort15], 1>;
Index: llvm/trunk/lib/Target/X86/X86SchedHaswell.td
===================================================================
--- llvm/trunk/lib/Target/X86/X86SchedHaswell.td
+++ llvm/trunk/lib/Target/X86/X86SchedHaswell.td
@@ -124,6 +124,7 @@
 defm : HWWriteResPair<WriteIMul64, [HWPort1],   3>;
 def  : WriteRes<WriteIMulH, []> { let Latency = 3; }
 defm : HWWriteResPair<WriteShift,  [HWPort06],  1>;
+defm : HWWriteResPair<WriteShiftDouble,  [HWPort06],  1>;
 defm : HWWriteResPair<WriteJump,   [HWPort06],  1>;
 defm : HWWriteResPair<WriteCRC32,  [HWPort1],   3>;
 
Index: llvm/trunk/lib/Target/X86/X86SchedSandyBridge.td
===================================================================
--- llvm/trunk/lib/Target/X86/X86SchedSandyBridge.td
+++ llvm/trunk/lib/Target/X86/X86SchedSandyBridge.td
@@ -123,6 +123,7 @@
 def  : WriteRes<WriteIMulH, []> { let Latency = 3; }
 
 defm : SBWriteResPair<WriteShift, [SBPort05],  1>;
+defm : SBWriteResPair<WriteShiftDouble, [SBPort05],  1>;
 defm : SBWriteResPair<WriteJump,  [SBPort5],   1>;
 defm : SBWriteResPair<WriteCRC32, [SBPort1],   3, [1], 1, 5>;
 
Index: llvm/trunk/lib/Target/X86/X86SchedSkylakeClient.td
===================================================================
--- llvm/trunk/lib/Target/X86/X86SchedSkylakeClient.td
+++ llvm/trunk/lib/Target/X86/X86SchedSkylakeClient.td
@@ -144,6 +144,9 @@
 // Integer shifts and rotates.
 defm : SKLWriteResPair<WriteShift, [SKLPort06],  1>;
 
+// Double shift instructions.
+defm : SKLWriteResPair<WriteShiftDouble, [SKLPort06],  1>;
+
 // BMI1 BEXTR, BMI2 BZHI
 defm : SKLWriteResPair<WriteBEXTR, [SKLPort06,SKLPort15], 2, [1,1], 2>;
 defm : SKLWriteResPair<WriteBZHI, [SKLPort15], 1>;
Index: llvm/trunk/lib/Target/X86/X86SchedSkylakeServer.td
===================================================================
--- llvm/trunk/lib/Target/X86/X86SchedSkylakeServer.td
+++ llvm/trunk/lib/Target/X86/X86SchedSkylakeServer.td
@@ -137,6 +137,9 @@
 // Integer shifts and rotates.
 defm : SKXWriteResPair<WriteShift, [SKXPort06],  1>;
 
+// Double shift instructions.
+defm : SKXWriteResPair<WriteShiftDouble, [SKXPort06],  1>;
+
 // Bit counts.
 defm : SKXWriteResPair<WriteBSF, [SKXPort1], 3>;
 defm : SKXWriteResPair<WriteBSR, [SKXPort1], 3>;
Index: llvm/trunk/lib/Target/X86/X86Schedule.td
===================================================================
--- llvm/trunk/lib/Target/X86/X86Schedule.td
+++ llvm/trunk/lib/Target/X86/X86Schedule.td
@@ -142,6 +142,8 @@
 
 // Integer shifts and rotates.
 defm WriteShift : X86SchedWritePair;
+// Double shift instructions.
+defm WriteShiftDouble : X86SchedWritePair;
 
 // BMI1 BEXTR, BMI2 BZHI
 defm WriteBEXTR : X86SchedWritePair;
Index: llvm/trunk/lib/Target/X86/X86ScheduleAtom.td
===================================================================
--- llvm/trunk/lib/Target/X86/X86ScheduleAtom.td
+++ llvm/trunk/lib/Target/X86/X86ScheduleAtom.td
@@ -148,6 +148,12 @@
 defm : AtomWriteResPair<WriteShift, [AtomPort0], [AtomPort0]>;
 
 ////////////////////////////////////////////////////////////////////////////////
+// Double shift instructions.
+////////////////////////////////////////////////////////////////////////////////
+
+defm : AtomWriteResPair<WriteShiftDouble, [AtomPort0], [AtomPort0]>;
+
+////////////////////////////////////////////////////////////////////////////////
 // Loads, stores, and moves, not folded with other operations.
 ////////////////////////////////////////////////////////////////////////////////
 
Index: llvm/trunk/lib/Target/X86/X86ScheduleBtVer2.td
===================================================================
--- llvm/trunk/lib/Target/X86/X86ScheduleBtVer2.td
+++ llvm/trunk/lib/Target/X86/X86ScheduleBtVer2.td
@@ -200,6 +200,8 @@
 
 defm : JWriteResIntPair<WriteShift, [JALU01], 1>;
 
+defm : JWriteResIntPair<WriteShiftDouble, [JALU01], 1>;
+
 def JWriteSHLDrri : SchedWriteRes<[JALU01]> {
   let Latency = 3;
   let ResourceCycles = [6];
Index: llvm/trunk/lib/Target/X86/X86ScheduleSLM.td
===================================================================
--- llvm/trunk/lib/Target/X86/X86ScheduleSLM.td
+++ llvm/trunk/lib/Target/X86/X86ScheduleSLM.td
@@ -98,6 +98,7 @@
 defm : SLMWriteResPair<WriteIMul,   [SLM_IEC_RSV1],  3>;
 defm : SLMWriteResPair<WriteIMul64, [SLM_IEC_RSV1],  3>;
 defm : SLMWriteResPair<WriteShift,  [SLM_IEC_RSV0],  1>;
+defm : SLMWriteResPair<WriteShiftDouble,  [SLM_IEC_RSV0],  1>;
 defm : SLMWriteResPair<WriteJump,   [SLM_IEC_RSV1],  1>;
 defm : SLMWriteResPair<WriteCRC32,  [SLM_IEC_RSV1],  3>;
 
Index: llvm/trunk/lib/Target/X86/X86ScheduleZnver1.td
===================================================================
--- llvm/trunk/lib/Target/X86/X86ScheduleZnver1.td
+++ llvm/trunk/lib/Target/X86/X86ScheduleZnver1.td
@@ -180,6 +180,7 @@
 defm : ZnWriteResPair<WriteIMul,   [ZnALU1, ZnMultiplier], 4>;
 defm : ZnWriteResPair<WriteIMul64, [ZnALU1, ZnMultiplier], 4, [1,1], 2>;
 defm : ZnWriteResPair<WriteShift, [ZnALU], 1>;
+defm : ZnWriteResPair<WriteShiftDouble, [ZnALU], 1>;
 defm : ZnWriteResPair<WriteJump,  [ZnALU], 1>;
 defm : ZnWriteResFpuPair<WriteCRC32, [ZnFPU0], 3>;